Lines Matching refs:plat
149 ret = clk_prepare_enable(priv->plat->stmmac_clk); in stmmac_bus_clks_config()
152 ret = clk_prepare_enable(priv->plat->pclk); in stmmac_bus_clks_config()
154 clk_disable_unprepare(priv->plat->stmmac_clk); in stmmac_bus_clks_config()
157 if (priv->plat->clks_config) { in stmmac_bus_clks_config()
158 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); in stmmac_bus_clks_config()
160 clk_disable_unprepare(priv->plat->stmmac_clk); in stmmac_bus_clks_config()
161 clk_disable_unprepare(priv->plat->pclk); in stmmac_bus_clks_config()
166 clk_disable_unprepare(priv->plat->stmmac_clk); in stmmac_bus_clks_config()
167 clk_disable_unprepare(priv->plat->pclk); in stmmac_bus_clks_config()
168 if (priv->plat->clks_config) in stmmac_bus_clks_config()
169 priv->plat->clks_config(priv->plat->bsp_priv, enabled); in stmmac_bus_clks_config()
199 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; in __stmmac_disable_all_queues()
200 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; in __stmmac_disable_all_queues()
226 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; in stmmac_disable_all_queues()
248 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; in stmmac_enable_all_queues()
249 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; in stmmac_enable_all_queues()
299 clk_rate = clk_get_rate(priv->plat->stmmac_clk); in stmmac_clk_csr_set()
323 if (priv->plat->has_sun8i) { in stmmac_clk_csr_set()
334 if (priv->plat->has_xgmac) { in stmmac_clk_csr_set()
405 u32 tx_cnt = priv->plat->tx_queues_to_use; in stmmac_enable_eee_mode()
419 priv->plat->en_tx_lpi_clockgating); in stmmac_enable_eee_mode()
490 priv->plat->mult_fact_100ns, in stmmac_eee_init()
503 priv->plat->mult_fact_100ns, in stmmac_eee_init()
507 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { in stmmac_eee_init()
525 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) in stmmac_cdc_adjust()
526 return (2 * NSEC_PER_SEC) / priv->plat->clk_ptp_rate; in stmmac_cdc_adjust()
591 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) in stmmac_get_rx_hwtstamp()
843 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; in stmmac_init_tstamp_counter()
856 priv->plat->clk_ptp_rate, in stmmac_init_tstamp_counter()
869 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); in stmmac_init_tstamp_counter()
891 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; in stmmac_init_ptp()
894 if (priv->plat->ptp_clk_freq_config) in stmmac_init_ptp()
895 priv->plat->ptp_clk_freq_config(priv); in stmmac_init_ptp()
924 clk_disable_unprepare(priv->plat->clk_ptp_ref); in stmmac_release_ptp()
936 u32 tx_cnt = priv->plat->tx_queues_to_use; in stmmac_mac_flow_ctrl()
949 int tx_cnt = priv->plat->tx_queues_to_use; in stmmac_validate()
950 int max_speed = priv->plat->max_speed; in stmmac_validate()
969 } else if (priv->plat->has_gmac4) { in stmmac_validate()
974 } else if (priv->plat->has_xgmac) { in stmmac_validate()
1051 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; in stmmac_fpe_link_state_handle()
1153 if (priv->plat->fix_mac_speed) in stmmac_mac_link_up()
1154 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); in stmmac_mac_link_up()
1179 phy_init_eee(phy, !priv->plat->rx_clk_runs_in_lpi) >= 0; in stmmac_mac_link_up()
1205 int interface = priv->plat->interface; in stmmac_check_pcs_mode()
1235 node = priv->plat->phylink_node; in stmmac_init_phy()
1244 int addr = priv->plat->phy_addr; in stmmac_init_phy()
1261 if (!priv->plat->pmt) { in stmmac_init_phy()
1274 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; in stmmac_phy_setup()
1275 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); in stmmac_phy_setup()
1276 int mode = priv->plat->phy_interface; in stmmac_phy_setup()
1282 if (priv->plat->mdio_bus_data) in stmmac_phy_setup()
1303 u32 rx_cnt = priv->plat->rx_queues_to_use; in stmmac_display_rx_rings()
1330 u32 tx_cnt = priv->plat->tx_queues_to_use; in stmmac_display_tx_rings()
1446 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; in stmmac_clear_descriptors()
1447 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; in stmmac_clear_descriptors()
1737 u32 rx_count = priv->plat->rx_queues_to_use; in init_dma_rx_desc_rings()
1839 tx_queue_cnt = priv->plat->tx_queues_to_use; in init_dma_tx_desc_rings()
1902 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; in stmmac_free_tx_skbufs()
1947 u32 rx_count = priv->plat->rx_queues_to_use; in free_dma_rx_desc_resources()
1990 u32 tx_count = priv->plat->tx_queues_to_use; in free_dma_tx_desc_resources()
2081 u32 rx_count = priv->plat->rx_queues_to_use; in alloc_dma_rx_desc_resources()
2156 u32 tx_count = priv->plat->tx_queues_to_use; in alloc_dma_tx_desc_resources()
2217 u32 rx_queues_count = priv->plat->rx_queues_to_use; in stmmac_mac_enable_rx_queues()
2222 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; in stmmac_mac_enable_rx_queues()
2281 u32 rx_channels_count = priv->plat->rx_queues_to_use; in stmmac_enable_all_dma_irq()
2282 u32 tx_channels_count = priv->plat->tx_queues_to_use; in stmmac_enable_all_dma_irq()
2304 u32 rx_channels_count = priv->plat->rx_queues_to_use; in stmmac_start_all_dma()
2305 u32 tx_channels_count = priv->plat->tx_queues_to_use; in stmmac_start_all_dma()
2323 u32 rx_channels_count = priv->plat->rx_queues_to_use; in stmmac_stop_all_dma()
2324 u32 tx_channels_count = priv->plat->tx_queues_to_use; in stmmac_stop_all_dma()
2342 u32 rx_channels_count = priv->plat->rx_queues_to_use; in stmmac_dma_operation_mode()
2343 u32 tx_channels_count = priv->plat->tx_queues_to_use; in stmmac_dma_operation_mode()
2344 int rxfifosz = priv->plat->rx_fifo_size; in stmmac_dma_operation_mode()
2345 int txfifosz = priv->plat->tx_fifo_size; in stmmac_dma_operation_mode()
2360 if (priv->plat->force_thresh_dma_mode) { in stmmac_dma_operation_mode()
2363 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { in stmmac_dma_operation_mode()
2384 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; in stmmac_dma_operation_mode()
2402 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; in stmmac_dma_operation_mode()
2702 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, in stmmac_tx_err()
2723 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; in stmmac_set_dma_operation_mode()
2724 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; in stmmac_set_dma_operation_mode()
2725 u32 rx_channels_count = priv->plat->rx_queues_to_use; in stmmac_set_dma_operation_mode()
2726 u32 tx_channels_count = priv->plat->tx_queues_to_use; in stmmac_set_dma_operation_mode()
2727 int rxfifosz = priv->plat->rx_fifo_size; in stmmac_set_dma_operation_mode()
2728 int txfifosz = priv->plat->tx_fifo_size; in stmmac_set_dma_operation_mode()
2771 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { in stmmac_napi_check()
2780 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { in stmmac_napi_check()
2801 u32 tx_channel_count = priv->plat->tx_queues_to_use; in stmmac_dma_interrupt()
2802 u32 rx_channel_count = priv->plat->rx_queues_to_use; in stmmac_dma_interrupt()
2822 if (priv->plat->force_thresh_dma_mode) in stmmac_dma_interrupt()
2901 u32 rx_channels_count = priv->plat->rx_queues_to_use; in stmmac_init_dma_engine()
2902 u32 tx_channels_count = priv->plat->tx_queues_to_use; in stmmac_init_dma_engine()
2910 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { in stmmac_init_dma_engine()
2925 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); in stmmac_init_dma_engine()
2927 if (priv->plat->axi) in stmmac_init_dma_engine()
2928 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); in stmmac_init_dma_engine()
2932 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); in stmmac_init_dma_engine()
2940 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, in stmmac_init_dma_engine()
2954 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, in stmmac_init_dma_engine()
3012 u32 tx_channel_count = priv->plat->tx_queues_to_use; in stmmac_init_coalesce()
3013 u32 rx_channel_count = priv->plat->rx_queues_to_use; in stmmac_init_coalesce()
3032 u32 rx_channels_count = priv->plat->rx_queues_to_use; in stmmac_set_rings_length()
3033 u32 tx_channels_count = priv->plat->tx_queues_to_use; in stmmac_set_rings_length()
3054 u32 tx_queues_count = priv->plat->tx_queues_to_use; in stmmac_set_tx_queue_weight()
3059 weight = priv->plat->tx_queues_cfg[queue].weight; in stmmac_set_tx_queue_weight()
3071 u32 tx_queues_count = priv->plat->tx_queues_to_use; in stmmac_configure_cbs()
3077 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; in stmmac_configure_cbs()
3082 priv->plat->tx_queues_cfg[queue].send_slope, in stmmac_configure_cbs()
3083 priv->plat->tx_queues_cfg[queue].idle_slope, in stmmac_configure_cbs()
3084 priv->plat->tx_queues_cfg[queue].high_credit, in stmmac_configure_cbs()
3085 priv->plat->tx_queues_cfg[queue].low_credit, in stmmac_configure_cbs()
3097 u32 rx_queues_count = priv->plat->rx_queues_to_use; in stmmac_rx_queue_dma_chan_map()
3102 chan = priv->plat->rx_queues_cfg[queue].chan; in stmmac_rx_queue_dma_chan_map()
3114 u32 rx_queues_count = priv->plat->rx_queues_to_use; in stmmac_mac_config_rx_queues_prio()
3119 if (!priv->plat->rx_queues_cfg[queue].use_prio) in stmmac_mac_config_rx_queues_prio()
3122 prio = priv->plat->rx_queues_cfg[queue].prio; in stmmac_mac_config_rx_queues_prio()
3134 u32 tx_queues_count = priv->plat->tx_queues_to_use; in stmmac_mac_config_tx_queues_prio()
3139 if (!priv->plat->tx_queues_cfg[queue].use_prio) in stmmac_mac_config_tx_queues_prio()
3142 prio = priv->plat->tx_queues_cfg[queue].prio; in stmmac_mac_config_tx_queues_prio()
3154 u32 rx_queues_count = priv->plat->rx_queues_to_use; in stmmac_mac_config_rx_queues_routing()
3160 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) in stmmac_mac_config_rx_queues_routing()
3163 packet = priv->plat->rx_queues_cfg[queue].pkt_route; in stmmac_mac_config_rx_queues_routing()
3170 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { in stmmac_mac_config_rss()
3181 priv->plat->rx_queues_to_use); in stmmac_mac_config_rss()
3191 u32 rx_queues_count = priv->plat->rx_queues_to_use; in stmmac_mtl_configuration()
3192 u32 tx_queues_count = priv->plat->tx_queues_to_use; in stmmac_mtl_configuration()
3200 priv->plat->rx_sched_algorithm); in stmmac_mtl_configuration()
3205 priv->plat->tx_sched_algorithm); in stmmac_mtl_configuration()
3239 priv->plat->safety_feat_cfg); in stmmac_safety_feat_configuration()
3282 u32 rx_cnt = priv->plat->rx_queues_to_use; in stmmac_hw_setup()
3283 u32 tx_cnt = priv->plat->tx_queues_to_use; in stmmac_hw_setup()
3301 int speed = priv->plat->mac_port_sel_speed; in stmmac_hw_setup()
3324 priv->plat->rx_coe = STMMAC_RX_COE_NONE; in stmmac_hw_setup()
3337 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); in stmmac_hw_setup()
3408 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); in stmmac_hw_setup()
3409 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); in stmmac_hw_setup()
3417 if (priv->plat->fpe_cfg->enable) in stmmac_hw_setup()
3428 clk_disable_unprepare(priv->plat->clk_ptp_ref); in stmmac_hw_teardown()
3439 irq_idx = priv->plat->tx_queues_to_use; in stmmac_free_irq()
3448 irq_idx = priv->plat->rx_queues_to_use; in stmmac_free_irq()
3580 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { in stmmac_request_irq_multi_msi()
3603 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { in stmmac_request_irq_multi_msi()
3689 if (priv->plat->multi_msi_en) in stmmac_request_irq()
3709 int mode = priv->plat->phy_interface; in stmmac_open()
3755 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { in stmmac_open()
3757 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; in stmmac_open()
3777 if (priv->plat->serdes_powerup) { in stmmac_open()
3778 ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv); in stmmac_open()
3811 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) in stmmac_open()
3857 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) in stmmac_release()
3878 if (priv->plat->serdes_powerdown) in stmmac_release()
3879 priv->plat->serdes_powerdown(dev, priv->plat->bsp_priv); in stmmac_release()
4289 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) in stmmac_xmit()
4326 enh_desc = priv->plat->enh_desc; in stmmac_xmit()
4712 while (index >= priv->plat->tx_queues_to_use) in stmmac_xdp_get_tx_queue()
4713 index -= priv->plat->tx_queues_to_use; in stmmac_xdp_get_tx_queue()
5520 int txfifosz = priv->plat->tx_fifo_size; in stmmac_change_mtu()
5526 txfifosz /= priv->plat->tx_queues_to_use; in stmmac_change_mtu()
5556 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) in stmmac_fix_features()
5559 if (!priv->plat->tx_coe) in stmmac_fix_features()
5567 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) in stmmac_fix_features()
5571 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { in stmmac_fix_features()
5588 priv->hw->rx_csum = priv->plat->rx_coe; in stmmac_set_features()
5600 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) in stmmac_set_features()
5609 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; in stmmac_fpe_event_status()
5652 u32 rx_cnt = priv->plat->rx_queues_to_use; in stmmac_common_interrupt()
5653 u32 tx_cnt = priv->plat->tx_queues_to_use; in stmmac_common_interrupt()
5658 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; in stmmac_common_interrupt()
5676 if ((priv->plat->has_gmac) || xmac) { in stmmac_common_interrupt()
5787 if (priv->plat->force_thresh_dma_mode) in stmmac_msi_intr_tx()
5836 if (priv->plat->multi_msi_en) { in stmmac_poll_controller()
5837 for (i = 0; i < priv->plat->rx_queues_to_use; i++) in stmmac_poll_controller()
5840 for (i = 0; i < priv->plat->tx_queues_to_use; i++) in stmmac_poll_controller()
6014 u32 rx_count = priv->plat->rx_queues_to_use; in stmmac_rings_status_show()
6015 u32 tx_count = priv->plat->tx_queues_to_use; in stmmac_rings_status_show()
6417 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, in stmmac_enable_rx_queue()
6478 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, in stmmac_enable_tx_queue()
6506 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) in stmmac_xdp_release()
6531 u32 rx_cnt = priv->plat->rx_queues_to_use; in stmmac_xdp_open()
6532 u32 tx_cnt = priv->plat->tx_queues_to_use; in stmmac_xdp_open()
6557 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); in stmmac_xdp_open()
6568 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, in stmmac_xdp_open()
6595 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, in stmmac_xdp_open()
6625 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) in stmmac_xdp_open()
6649 if (queue >= priv->plat->rx_queues_to_use || in stmmac_xsk_wakeup()
6650 queue >= priv->plat->tx_queues_to_use) in stmmac_xsk_wakeup()
6738 if (priv->plat->has_sun8i) in stmmac_hw_init()
6757 priv->plat->enh_desc = priv->dma_cap.enh_desc; in stmmac_hw_init()
6758 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && in stmmac_hw_init()
6759 !priv->plat->use_phy_wol; in stmmac_hw_init()
6760 priv->hw->pmt = priv->plat->pmt; in stmmac_hw_init()
6769 if (priv->plat->force_thresh_dma_mode) in stmmac_hw_init()
6770 priv->plat->tx_coe = 0; in stmmac_hw_init()
6772 priv->plat->tx_coe = priv->dma_cap.tx_coe; in stmmac_hw_init()
6775 priv->plat->rx_coe = priv->dma_cap.rx_coe; in stmmac_hw_init()
6778 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; in stmmac_hw_init()
6780 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; in stmmac_hw_init()
6786 if (priv->plat->rx_coe) { in stmmac_hw_init()
6787 priv->hw->rx_csum = priv->plat->rx_coe; in stmmac_hw_init()
6792 if (priv->plat->tx_coe) in stmmac_hw_init()
6795 if (priv->plat->pmt) { in stmmac_hw_init()
6803 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; in stmmac_hw_init()
6804 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; in stmmac_hw_init()
6819 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { in stmmac_hw_init()
6833 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); in stmmac_napi_add()
6842 if (queue < priv->plat->rx_queues_to_use) { in stmmac_napi_add()
6846 if (queue < priv->plat->tx_queues_to_use) { in stmmac_napi_add()
6851 if (queue < priv->plat->rx_queues_to_use && in stmmac_napi_add()
6852 queue < priv->plat->tx_queues_to_use) { in stmmac_napi_add()
6865 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); in stmmac_napi_del()
6870 if (queue < priv->plat->rx_queues_to_use) in stmmac_napi_del()
6872 if (queue < priv->plat->tx_queues_to_use) in stmmac_napi_del()
6874 if (queue < priv->plat->rx_queues_to_use && in stmmac_napi_del()
6875 queue < priv->plat->tx_queues_to_use) { in stmmac_napi_del()
6891 priv->plat->rx_queues_to_use = rx_cnt; in stmmac_reinit_queues()
6892 priv->plat->tx_queues_to_use = tx_cnt; in stmmac_reinit_queues()
6928 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; in stmmac_fpe_lp_task()
6944 priv->plat->tx_queues_to_use, in stmmac_fpe_lp_task()
6945 priv->plat->rx_queues_to_use, in stmmac_fpe_lp_task()
6974 if (priv->plat->fpe_cfg->hs_enable != enable) { in stmmac_fpe_handshake()
6977 priv->plat->fpe_cfg, in stmmac_fpe_handshake()
6980 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; in stmmac_fpe_handshake()
6981 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; in stmmac_fpe_handshake()
6984 priv->plat->fpe_cfg->hs_enable = enable; in stmmac_fpe_handshake()
7020 priv->plat = plat_dat; in stmmac_dvr_probe()
7023 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; in stmmac_dvr_probe()
7064 priv->plat->phy_addr = phyaddr; in stmmac_dvr_probe()
7066 if (priv->plat->stmmac_rst) { in stmmac_dvr_probe()
7067 ret = reset_control_assert(priv->plat->stmmac_rst); in stmmac_dvr_probe()
7068 reset_control_deassert(priv->plat->stmmac_rst); in stmmac_dvr_probe()
7073 reset_control_reset(priv->plat->stmmac_rst); in stmmac_dvr_probe()
7076 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); in stmmac_dvr_probe()
7092 priv->plat->dma_cfg->dche = false; in stmmac_dvr_probe()
7106 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { in stmmac_dvr_probe()
7108 if (priv->plat->has_gmac4) in stmmac_dvr_probe()
7114 if (priv->dma_cap.sphen && !priv->plat->sph_disable) { in stmmac_dvr_probe()
7126 if (priv->plat->addr64) in stmmac_dvr_probe()
7127 priv->dma_cap.addr64 = priv->plat->addr64; in stmmac_dvr_probe()
7141 priv->plat->dma_cfg->eame = true; in stmmac_dvr_probe()
7171 rxq = priv->plat->rx_queues_to_use; in stmmac_dvr_probe()
7176 if (priv->dma_cap.rssen && priv->plat->rss_en) in stmmac_dvr_probe()
7181 if (priv->plat->has_xgmac) in stmmac_dvr_probe()
7183 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) in stmmac_dvr_probe()
7190 if ((priv->plat->maxmtu < ndev->max_mtu) && in stmmac_dvr_probe()
7191 (priv->plat->maxmtu >= ndev->min_mtu)) in stmmac_dvr_probe()
7192 ndev->max_mtu = priv->plat->maxmtu; in stmmac_dvr_probe()
7193 else if (priv->plat->maxmtu < ndev->min_mtu) in stmmac_dvr_probe()
7196 __func__, priv->plat->maxmtu); in stmmac_dvr_probe()
7212 if (priv->plat->clk_csr >= 0) in stmmac_dvr_probe()
7213 priv->clk_csr = priv->plat->clk_csr; in stmmac_dvr_probe()
7230 __func__, priv->plat->bus_id); in stmmac_dvr_probe()
7235 if (priv->plat->speed_mode_2500) in stmmac_dvr_probe()
7236 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); in stmmac_dvr_probe()
7238 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { in stmmac_dvr_probe()
7261 if (priv->plat->dump_debug_regs) in stmmac_dvr_probe()
7262 priv->plat->dump_debug_regs(priv->plat->bsp_priv); in stmmac_dvr_probe()
7313 if (priv->plat->stmmac_rst) in stmmac_dvr_remove()
7314 reset_control_assert(priv->plat->stmmac_rst); in stmmac_dvr_remove()
7315 reset_control_assert(priv->plat->stmmac_ahb_rst); in stmmac_dvr_remove()
7352 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) in stmmac_suspend()
7363 if (priv->plat->serdes_powerdown) in stmmac_suspend()
7364 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); in stmmac_suspend()
7367 if (device_may_wakeup(priv->device) && priv->plat->pmt) { in stmmac_suspend()
7378 if (device_may_wakeup(priv->device) && priv->plat->pmt) { in stmmac_suspend()
7390 priv->plat->fpe_cfg, in stmmac_suspend()
7391 priv->plat->tx_queues_to_use, in stmmac_suspend()
7392 priv->plat->rx_queues_to_use, false); in stmmac_suspend()
7409 u32 rx_cnt = priv->plat->rx_queues_to_use; in stmmac_reset_queues_param()
7410 u32 tx_cnt = priv->plat->tx_queues_to_use; in stmmac_reset_queues_param()
7452 if (device_may_wakeup(priv->device) && priv->plat->pmt) { in stmmac_resume()
7464 if (priv->plat->serdes_powerup) { in stmmac_resume()
7465 ret = priv->plat->serdes_powerup(ndev, in stmmac_resume()
7466 priv->plat->bsp_priv); in stmmac_resume()
7473 if (device_may_wakeup(priv->device) && priv->plat->pmt) { in stmmac_resume()