176 #define XGBE_SET_REG_OFS(p, rb, rn) p->rb##_ofs.rn = \  macro
3095 		XGBE_SET_REG_OFS(slave, port_regs, port_vlan);  in init_slave()
3096 		XGBE_SET_REG_OFS(slave, port_regs, tx_pri_map);  in init_slave()
3097 		XGBE_SET_REG_OFS(slave, port_regs, sa_lo);  in init_slave()
3098 		XGBE_SET_REG_OFS(slave, port_regs, sa_hi);  in init_slave()
3099 		XGBE_SET_REG_OFS(slave, port_regs, ts_ctl);  in init_slave()
3100 		XGBE_SET_REG_OFS(slave, port_regs, ts_seq_ltype);  in init_slave()
3101 		XGBE_SET_REG_OFS(slave, port_regs, ts_vlan);  in init_slave()
3102 		XGBE_SET_REG_OFS(slave, port_regs, ts_ctl_ltype2);  in init_slave()
3103 		XGBE_SET_REG_OFS(slave, port_regs, ts_ctl2);  in init_slave()
3106 		XGBE_SET_REG_OFS(slave, emac_regs, mac_control);  in init_slave()
3107 		XGBE_SET_REG_OFS(slave, emac_regs, soft_reset);  in init_slave()
3108 		XGBE_SET_REG_OFS(slave, emac_regs, rx_maxlen);  in init_slave()
3312 	XGBE_SET_REG_OFS(gbe_dev, ss_regs, id_ver);  in set_xgbe_ethss10_priv()
3313 	XGBE_SET_REG_OFS(gbe_dev, ss_regs, control);  in set_xgbe_ethss10_priv()
3316 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, id_ver);  in set_xgbe_ethss10_priv()
3317 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, control);  in set_xgbe_ethss10_priv()
3318 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, ptype);  in set_xgbe_ethss10_priv()
3319 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, stat_port_en);  in set_xgbe_ethss10_priv()
3320 	XGBE_SET_REG_OFS(gbe_dev, switch_regs, flow_control);  in set_xgbe_ethss10_priv()
3323 	XGBE_SET_REG_OFS(gbe_dev, host_port_regs, port_vlan);  in set_xgbe_ethss10_priv()
3324 	XGBE_SET_REG_OFS(gbe_dev, host_port_regs, tx_pri_map);  in set_xgbe_ethss10_priv()
3325 	XGBE_SET_REG_OFS(gbe_dev, host_port_regs, rx_maxlen);  in set_xgbe_ethss10_priv()