99 	err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);  in vsc824x_add_skew()
108 	err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,  in vsc824x_config_init()
134 	phy_write(phydev, 0x1f, 0x2a30);  in vsc73xx_config_init()
136 	phy_write(phydev, 0x1f, 0x0000);  in vsc73xx_config_init()
150 	phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
152 	phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
153 	phy_write(phydev, 0x10, 0xb68a);  in vsc738x_config_init()
156 	phy_write(phydev, 0x10, 0x968a);  in vsc738x_config_init()
157 	phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
159 	phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
167 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
169 		phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
170 		phy_write(phydev, 0x12, 0x0000);  in vsc738x_config_init()
171 		phy_write(phydev, 0x11, 0x0689);  in vsc738x_config_init()
172 		phy_write(phydev, 0x10, 0x8f92);  in vsc738x_config_init()
173 		phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
174 		phy_write(phydev, 0x12, 0x0000);  in vsc738x_config_init()
175 		phy_write(phydev, 0x11, 0x0e35);  in vsc738x_config_init()
176 		phy_write(phydev, 0x10, 0x9786);  in vsc738x_config_init()
177 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
179 		phy_write(phydev, 0x17, 0xff80);  in vsc738x_config_init()
180 		phy_write(phydev, 0x17, 0x0000);  in vsc738x_config_init()
183 	phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
184 	phy_write(phydev, 0x12, 0x0048);  in vsc738x_config_init()
187 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
188 		phy_write(phydev, 0x14, 0x6600);  in vsc738x_config_init()
189 		phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
190 		phy_write(phydev, 0x18, 0xa24e);  in vsc738x_config_init()
192 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
198 		phy_write(phydev, 0x1f, 0x0001);  in vsc738x_config_init()
200 		phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
215 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
217 	phy_write(phydev, 0x1f, 0x52b5);  in vsc739x_config_init()
218 	phy_write(phydev, 0x10, 0xb68a);  in vsc739x_config_init()
221 	phy_write(phydev, 0x10, 0x968a);  in vsc739x_config_init()
222 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
224 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
226 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
227 	phy_write(phydev, 0x12, 0x0048);  in vsc739x_config_init()
228 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
231 	phy_write(phydev, 0x1f, 0x0001);  in vsc739x_config_init()
233 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
263 	return phy_write(phydev, MII_VSC8601_EPHY_CTL, ret);  in vsc8601_add_skew()
287 		err = phy_write(phydev, MII_VSC8244_IMASK,  in vsc82xx_config_intr()
303 		err = phy_write(phydev, MII_VSC8244_IMASK, 0);  in vsc82xx_config_intr()
338 	err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,  in vsc8221_config_init()
361 	ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);  in vsc82x4_config_autocross_enable()
363 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);  in vsc82x4_config_autocross_enable()
365 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);  in vsc82x4_config_autocross_enable()
367 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);  in vsc82x4_config_autocross_enable()
370 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);  in vsc82x4_config_autocross_enable()
372 		phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);  in vsc82x4_config_autocross_enable()