Lines Matching refs:rt2x00dev
45 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev, in rt2400pci_bbp_write() argument
50 mutex_lock(&rt2x00dev->csr_mutex); in rt2400pci_bbp_write()
56 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_write()
63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_write()
66 mutex_unlock(&rt2x00dev->csr_mutex); in rt2400pci_bbp_write()
69 static u8 rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev, in rt2400pci_bbp_read() argument
75 mutex_lock(&rt2x00dev->csr_mutex); in rt2400pci_bbp_read()
85 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_read()
91 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_read()
93 WAIT_FOR_BBP(rt2x00dev, ®); in rt2400pci_bbp_read()
98 mutex_unlock(&rt2x00dev->csr_mutex); in rt2400pci_bbp_read()
103 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev, in rt2400pci_rf_write() argument
108 mutex_lock(&rt2x00dev->csr_mutex); in rt2400pci_rf_write()
114 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt2400pci_rf_write()
121 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); in rt2400pci_rf_write()
122 rt2x00_rf_write(rt2x00dev, word, value); in rt2400pci_rf_write()
125 mutex_unlock(&rt2x00dev->csr_mutex); in rt2400pci_rf_write()
130 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt2400pci_eepromregister_read() local
133 reg = rt2x00mmio_register_read(rt2x00dev, CSR21); in rt2400pci_eepromregister_read()
145 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt2400pci_eepromregister_write() local
155 rt2x00mmio_register_write(rt2x00dev, CSR21, reg); in rt2400pci_eepromregister_write()
193 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) in rt2400pci_rfkill_poll() argument
197 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); in rt2400pci_rfkill_poll()
210 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); in rt2400pci_brightness_set()
217 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2400pci_brightness_set()
228 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); in rt2400pci_blink_set()
231 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2400pci_blink_set()
236 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev, in rt2400pci_init_led() argument
240 led->rt2x00dev = rt2x00dev; in rt2400pci_init_led()
251 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_filter() argument
261 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); in rt2400pci_config_filter()
269 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); in rt2400pci_config_filter()
271 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) && in rt2400pci_config_filter()
272 !rt2x00dev->intf_ap_count); in rt2400pci_config_filter()
274 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_config_filter()
277 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_intf() argument
290 reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1); in rt2400pci_config_intf()
292 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); in rt2400pci_config_intf()
297 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_config_intf()
299 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_config_intf()
303 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3, in rt2400pci_config_intf()
307 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5, in rt2400pci_config_intf()
312 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_erp() argument
325 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1); in rt2400pci_config_erp()
330 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); in rt2400pci_config_erp()
332 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2); in rt2400pci_config_erp()
337 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); in rt2400pci_config_erp()
339 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3); in rt2400pci_config_erp()
344 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); in rt2400pci_config_erp()
346 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4); in rt2400pci_config_erp()
351 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); in rt2400pci_config_erp()
353 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5); in rt2400pci_config_erp()
358 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); in rt2400pci_config_erp()
362 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates); in rt2400pci_config_erp()
365 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); in rt2400pci_config_erp()
367 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_erp()
369 reg = rt2x00mmio_register_read(rt2x00dev, CSR18); in rt2400pci_config_erp()
372 rt2x00mmio_register_write(rt2x00dev, CSR18, reg); in rt2400pci_config_erp()
374 reg = rt2x00mmio_register_read(rt2x00dev, CSR19); in rt2400pci_config_erp()
377 rt2x00mmio_register_write(rt2x00dev, CSR19, reg); in rt2400pci_config_erp()
381 reg = rt2x00mmio_register_read(rt2x00dev, CSR12); in rt2400pci_config_erp()
386 rt2x00mmio_register_write(rt2x00dev, CSR12, reg); in rt2400pci_config_erp()
390 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_ant() argument
403 r4 = rt2400pci_bbp_read(rt2x00dev, 4); in rt2400pci_config_ant()
404 r1 = rt2400pci_bbp_read(rt2x00dev, 1); in rt2400pci_config_ant()
438 rt2400pci_bbp_write(rt2x00dev, 4, r4); in rt2400pci_config_ant()
439 rt2400pci_bbp_write(rt2x00dev, 1, r1); in rt2400pci_config_ant()
442 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_channel() argument
451 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2400pci_config_channel()
452 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2); in rt2400pci_config_channel()
453 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2400pci_config_channel()
458 if (rt2x00_rf(rt2x00dev, RF2420)) in rt2400pci_config_channel()
466 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2400pci_config_channel()
467 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32); in rt2400pci_config_channel()
468 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2400pci_config_channel()
472 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2400pci_config_channel()
473 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2); in rt2400pci_config_channel()
474 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2400pci_config_channel()
484 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2400pci_config_channel()
485 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2400pci_config_channel()
490 rf->rf1 = rt2x00mmio_register_read(rt2x00dev, CNT0); in rt2400pci_config_channel()
493 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower) in rt2400pci_config_txpower() argument
495 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower)); in rt2400pci_config_txpower()
498 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_retry_limit() argument
503 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); in rt2400pci_config_retry_limit()
508 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_retry_limit()
511 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_ps() argument
520 reg = rt2x00mmio_register_read(rt2x00dev, CSR20); in rt2400pci_config_ps()
522 (rt2x00dev->beacon_int - 20) * 16); in rt2400pci_config_ps()
528 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
531 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
533 reg = rt2x00mmio_register_read(rt2x00dev, CSR20); in rt2400pci_config_ps()
535 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
538 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); in rt2400pci_config_ps()
541 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev, in rt2400pci_config() argument
546 rt2400pci_config_channel(rt2x00dev, &libconf->rf); in rt2400pci_config()
548 rt2400pci_config_txpower(rt2x00dev, in rt2400pci_config()
551 rt2400pci_config_retry_limit(rt2x00dev, libconf); in rt2400pci_config()
553 rt2400pci_config_ps(rt2x00dev, libconf); in rt2400pci_config()
556 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_cw() argument
561 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); in rt2400pci_config_cw()
564 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_cw()
570 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev, in rt2400pci_link_stats() argument
579 reg = rt2x00mmio_register_read(rt2x00dev, CNT0); in rt2400pci_link_stats()
585 bbp = rt2400pci_bbp_read(rt2x00dev, 39); in rt2400pci_link_stats()
589 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev, in rt2400pci_set_vgc() argument
593 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level); in rt2400pci_set_vgc()
599 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev, in rt2400pci_reset_tuner() argument
602 rt2400pci_set_vgc(rt2x00dev, qual, 0x08); in rt2400pci_reset_tuner()
605 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev, in rt2400pci_link_tuner() argument
619 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level); in rt2400pci_link_tuner()
621 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level); in rt2400pci_link_tuner()
629 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2400pci_start_queue() local
634 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); in rt2400pci_start_queue()
636 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_start_queue()
639 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_start_queue()
643 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_start_queue()
652 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2400pci_kick_queue() local
657 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2400pci_kick_queue()
659 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
662 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2400pci_kick_queue()
664 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
667 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2400pci_kick_queue()
669 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
678 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2400pci_stop_queue() local
685 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2400pci_stop_queue()
687 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_stop_queue()
690 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); in rt2400pci_stop_queue()
692 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_stop_queue()
695 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_stop_queue()
699 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_stop_queue()
704 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt2400pci_stop_queue()
757 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) in rt2400pci_init_queues() argument
765 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2); in rt2400pci_init_queues()
766 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); in rt2400pci_init_queues()
767 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); in rt2400pci_init_queues()
768 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); in rt2400pci_init_queues()
769 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); in rt2400pci_init_queues()
770 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); in rt2400pci_init_queues()
772 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; in rt2400pci_init_queues()
773 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3); in rt2400pci_init_queues()
776 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); in rt2400pci_init_queues()
778 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; in rt2400pci_init_queues()
779 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5); in rt2400pci_init_queues()
782 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); in rt2400pci_init_queues()
784 entry_priv = rt2x00dev->atim->entries[0].priv_data; in rt2400pci_init_queues()
785 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4); in rt2400pci_init_queues()
788 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); in rt2400pci_init_queues()
790 entry_priv = rt2x00dev->bcn->entries[0].priv_data; in rt2400pci_init_queues()
791 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6); in rt2400pci_init_queues()
794 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); in rt2400pci_init_queues()
796 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1); in rt2400pci_init_queues()
797 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); in rt2400pci_init_queues()
798 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); in rt2400pci_init_queues()
799 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); in rt2400pci_init_queues()
801 entry_priv = rt2x00dev->rx->entries[0].priv_data; in rt2400pci_init_queues()
802 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2); in rt2400pci_init_queues()
805 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); in rt2400pci_init_queues()
810 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev) in rt2400pci_init_registers() argument
814 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002); in rt2400pci_init_registers()
815 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002); in rt2400pci_init_registers()
816 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20); in rt2400pci_init_registers()
817 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002); in rt2400pci_init_registers()
819 reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR); in rt2400pci_init_registers()
823 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); in rt2400pci_init_registers()
825 reg = rt2x00mmio_register_read(rt2x00dev, CSR9); in rt2400pci_init_registers()
827 (rt2x00dev->rx->data_size / 128)); in rt2400pci_init_registers()
828 rt2x00mmio_register_write(rt2x00dev, CSR9, reg); in rt2400pci_init_registers()
830 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_init_registers()
839 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_init_registers()
841 rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000); in rt2400pci_init_registers()
843 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR0); in rt2400pci_init_registers()
848 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg); in rt2400pci_init_registers()
850 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3); in rt2400pci_init_registers()
857 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); in rt2400pci_init_registers()
859 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); in rt2400pci_init_registers()
861 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) in rt2400pci_init_registers()
864 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223); in rt2400pci_init_registers()
865 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518); in rt2400pci_init_registers()
867 reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2); in rt2400pci_init_registers()
869 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); in rt2400pci_init_registers()
871 reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR); in rt2400pci_init_registers()
876 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); in rt2400pci_init_registers()
878 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); in rt2400pci_init_registers()
882 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
884 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); in rt2400pci_init_registers()
887 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
894 reg = rt2x00mmio_register_read(rt2x00dev, CNT0); in rt2400pci_init_registers()
895 reg = rt2x00mmio_register_read(rt2x00dev, CNT4); in rt2400pci_init_registers()
900 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) in rt2400pci_wait_bbp_ready() argument
906 value = rt2400pci_bbp_read(rt2x00dev, 0); in rt2400pci_wait_bbp_ready()
912 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); in rt2400pci_wait_bbp_ready()
916 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev) in rt2400pci_init_bbp() argument
923 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev))) in rt2400pci_init_bbp()
926 rt2400pci_bbp_write(rt2x00dev, 1, 0x00); in rt2400pci_init_bbp()
927 rt2400pci_bbp_write(rt2x00dev, 3, 0x27); in rt2400pci_init_bbp()
928 rt2400pci_bbp_write(rt2x00dev, 4, 0x08); in rt2400pci_init_bbp()
929 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f); in rt2400pci_init_bbp()
930 rt2400pci_bbp_write(rt2x00dev, 15, 0x72); in rt2400pci_init_bbp()
931 rt2400pci_bbp_write(rt2x00dev, 16, 0x74); in rt2400pci_init_bbp()
932 rt2400pci_bbp_write(rt2x00dev, 17, 0x20); in rt2400pci_init_bbp()
933 rt2400pci_bbp_write(rt2x00dev, 18, 0x72); in rt2400pci_init_bbp()
934 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b); in rt2400pci_init_bbp()
935 rt2400pci_bbp_write(rt2x00dev, 20, 0x00); in rt2400pci_init_bbp()
936 rt2400pci_bbp_write(rt2x00dev, 28, 0x11); in rt2400pci_init_bbp()
937 rt2400pci_bbp_write(rt2x00dev, 29, 0x04); in rt2400pci_init_bbp()
938 rt2400pci_bbp_write(rt2x00dev, 30, 0x21); in rt2400pci_init_bbp()
939 rt2400pci_bbp_write(rt2x00dev, 31, 0x00); in rt2400pci_init_bbp()
942 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i); in rt2400pci_init_bbp()
947 rt2400pci_bbp_write(rt2x00dev, reg_id, value); in rt2400pci_init_bbp()
957 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, in rt2400pci_toggle_irq() argument
969 reg = rt2x00mmio_register_read(rt2x00dev, CSR7); in rt2400pci_toggle_irq()
970 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_toggle_irq()
977 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); in rt2400pci_toggle_irq()
979 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2400pci_toggle_irq()
985 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_toggle_irq()
987 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); in rt2400pci_toggle_irq()
994 tasklet_kill(&rt2x00dev->txstatus_tasklet); in rt2400pci_toggle_irq()
995 tasklet_kill(&rt2x00dev->rxdone_tasklet); in rt2400pci_toggle_irq()
996 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt2400pci_toggle_irq()
1000 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev) in rt2400pci_enable_radio() argument
1005 if (unlikely(rt2400pci_init_queues(rt2x00dev) || in rt2400pci_enable_radio()
1006 rt2400pci_init_registers(rt2x00dev) || in rt2400pci_enable_radio()
1007 rt2400pci_init_bbp(rt2x00dev))) in rt2400pci_enable_radio()
1013 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev) in rt2400pci_disable_radio() argument
1018 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0); in rt2400pci_disable_radio()
1021 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, in rt2400pci_set_state() argument
1032 reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1); in rt2400pci_set_state()
1037 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2400pci_set_state()
1045 reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1); in rt2400pci_set_state()
1050 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2400pci_set_state()
1057 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev, in rt2400pci_set_device_state() argument
1064 retval = rt2400pci_enable_radio(rt2x00dev); in rt2400pci_set_device_state()
1067 rt2400pci_disable_radio(rt2x00dev); in rt2400pci_set_device_state()
1071 rt2400pci_toggle_irq(rt2x00dev, state); in rt2400pci_set_device_state()
1077 retval = rt2400pci_set_state(rt2x00dev, state); in rt2400pci_set_device_state()
1085 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", in rt2400pci_set_device_state()
1168 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt2400pci_write_beacon() local
1175 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_write_beacon()
1177 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_write_beacon()
1180 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n"); in rt2400pci_write_beacon()
1195 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); in rt2400pci_write_beacon()
1201 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_write_beacon()
1210 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt2400pci_fill_rxdone() local
1239 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL); in rt2400pci_fill_rxdone()
1254 entry->queue->rt2x00dev->rssi_offset; in rt2400pci_fill_rxdone()
1265 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, in rt2400pci_txdone() argument
1268 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); in rt2400pci_txdone()
1304 static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, in rt2400pci_enable_interrupt() argument
1313 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt2400pci_enable_interrupt()
1315 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2400pci_enable_interrupt()
1317 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_enable_interrupt()
1319 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt2400pci_enable_interrupt()
1324 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, in rt2400pci_txstatus_tasklet() local
1331 rt2400pci_txdone(rt2x00dev, QID_ATIM); in rt2400pci_txstatus_tasklet()
1332 rt2400pci_txdone(rt2x00dev, QID_AC_VO); in rt2400pci_txstatus_tasklet()
1333 rt2400pci_txdone(rt2x00dev, QID_AC_VI); in rt2400pci_txstatus_tasklet()
1338 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) { in rt2400pci_txstatus_tasklet()
1339 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt2400pci_txstatus_tasklet()
1341 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2400pci_txstatus_tasklet()
1345 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_txstatus_tasklet()
1347 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt2400pci_txstatus_tasklet()
1353 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet); in rt2400pci_tbtt_tasklet() local
1354 rt2x00lib_beacondone(rt2x00dev); in rt2400pci_tbtt_tasklet()
1355 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt2400pci_tbtt_tasklet()
1356 rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE); in rt2400pci_tbtt_tasklet()
1361 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, in rt2400pci_rxdone_tasklet() local
1363 if (rt2x00mmio_rxdone(rt2x00dev)) in rt2400pci_rxdone_tasklet()
1364 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt2400pci_rxdone_tasklet()
1365 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt2400pci_rxdone_tasklet()
1366 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE); in rt2400pci_rxdone_tasklet()
1371 struct rt2x00_dev *rt2x00dev = dev_instance; in rt2400pci_interrupt() local
1378 reg = rt2x00mmio_register_read(rt2x00dev, CSR7); in rt2400pci_interrupt()
1379 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_interrupt()
1384 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt2400pci_interrupt()
1393 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); in rt2400pci_interrupt()
1396 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt2400pci_interrupt()
1401 tasklet_schedule(&rt2x00dev->txstatus_tasklet); in rt2400pci_interrupt()
1414 spin_lock(&rt2x00dev->irqmask_lock); in rt2400pci_interrupt()
1416 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2400pci_interrupt()
1418 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_interrupt()
1420 spin_unlock(&rt2x00dev->irqmask_lock); in rt2400pci_interrupt()
1430 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) in rt2400pci_validate_eeprom() argument
1437 reg = rt2x00mmio_register_read(rt2x00dev, CSR21); in rt2400pci_validate_eeprom()
1439 eeprom.data = rt2x00dev; in rt2400pci_validate_eeprom()
1449 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, in rt2400pci_validate_eeprom()
1455 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); in rt2400pci_validate_eeprom()
1456 rt2x00lib_set_mac_address(rt2x00dev, mac); in rt2400pci_validate_eeprom()
1458 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); in rt2400pci_validate_eeprom()
1460 rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n"); in rt2400pci_validate_eeprom()
1467 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev) in rt2400pci_init_eeprom() argument
1476 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); in rt2400pci_init_eeprom()
1482 reg = rt2x00mmio_register_read(rt2x00dev, CSR0); in rt2400pci_init_eeprom()
1483 rt2x00_set_chip(rt2x00dev, RT2460, value, in rt2400pci_init_eeprom()
1486 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) { in rt2400pci_init_eeprom()
1487 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); in rt2400pci_init_eeprom()
1494 rt2x00dev->default_ant.tx = in rt2400pci_init_eeprom()
1496 rt2x00dev->default_ant.rx = in rt2400pci_init_eeprom()
1505 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY) in rt2400pci_init_eeprom()
1506 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; in rt2400pci_init_eeprom()
1507 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY) in rt2400pci_init_eeprom()
1508 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; in rt2400pci_init_eeprom()
1516 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); in rt2400pci_init_eeprom()
1520 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual, in rt2400pci_init_eeprom()
1528 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); in rt2400pci_init_eeprom()
1534 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); in rt2400pci_init_eeprom()
1560 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) in rt2400pci_probe_hw_mode() argument
1562 struct hw_mode_spec *spec = &rt2x00dev->spec; in rt2400pci_probe_hw_mode()
1570 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); in rt2400pci_probe_hw_mode()
1571 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); in rt2400pci_probe_hw_mode()
1572 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); in rt2400pci_probe_hw_mode()
1573 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); in rt2400pci_probe_hw_mode()
1575 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); in rt2400pci_probe_hw_mode()
1576 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, in rt2400pci_probe_hw_mode()
1577 rt2x00_eeprom_addr(rt2x00dev, in rt2400pci_probe_hw_mode()
1598 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); in rt2400pci_probe_hw_mode()
1607 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev) in rt2400pci_probe_hw() argument
1615 retval = rt2400pci_validate_eeprom(rt2x00dev); in rt2400pci_probe_hw()
1619 retval = rt2400pci_init_eeprom(rt2x00dev); in rt2400pci_probe_hw()
1627 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); in rt2400pci_probe_hw()
1629 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); in rt2400pci_probe_hw()
1634 retval = rt2400pci_probe_hw_mode(rt2x00dev); in rt2400pci_probe_hw()
1641 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags); in rt2400pci_probe_hw()
1642 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); in rt2400pci_probe_hw()
1643 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags); in rt2400pci_probe_hw()
1648 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; in rt2400pci_probe_hw()
1660 struct rt2x00_dev *rt2x00dev = hw->priv; in rt2400pci_conf_tx() local
1676 rt2400pci_config_cw(rt2x00dev, in rt2400pci_conf_tx()
1677 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max); in rt2400pci_conf_tx()
1685 struct rt2x00_dev *rt2x00dev = hw->priv; in rt2400pci_get_tsf() local
1689 reg = rt2x00mmio_register_read(rt2x00dev, CSR17); in rt2400pci_get_tsf()
1691 reg = rt2x00mmio_register_read(rt2x00dev, CSR16); in rt2400pci_get_tsf()
1699 struct rt2x00_dev *rt2x00dev = hw->priv; in rt2400pci_tx_last_beacon() local
1702 reg = rt2x00mmio_register_read(rt2x00dev, CSR15); in rt2400pci_tx_last_beacon()