Lines Matching refs:rtlphy
75 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_rf_serial_read() local
76 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl92c_phy_rf_serial_read()
129 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_rf_serial_write() local
130 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl92c_phy_rf_serial_write()
171 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_bb8192c_config_parafile() local
181 if (rtlphy->rf_type == RF_1T2R) { in _rtl92c_phy_bb8192c_config_parafile()
186 rtlphy->pwrgroup_cnt = 0; in _rtl92c_phy_bb8192c_config_parafile()
200 rtlphy->cck_high_power = in _rtl92c_phy_bb8192c_config_parafile()
213 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_store_pwrindex_diffrate_offset() local
216 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] = in _rtl92c_store_pwrindex_diffrate_offset()
220 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
221 rtlphy->mcs_txpwrlevel_origoffset in _rtl92c_store_pwrindex_diffrate_offset()
222 [rtlphy->pwrgroup_cnt][0]); in _rtl92c_store_pwrindex_diffrate_offset()
225 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] = in _rtl92c_store_pwrindex_diffrate_offset()
229 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
230 rtlphy->mcs_txpwrlevel_origoffset in _rtl92c_store_pwrindex_diffrate_offset()
231 [rtlphy->pwrgroup_cnt][1]); in _rtl92c_store_pwrindex_diffrate_offset()
234 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] = in _rtl92c_store_pwrindex_diffrate_offset()
238 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
239 rtlphy->mcs_txpwrlevel_origoffset in _rtl92c_store_pwrindex_diffrate_offset()
240 [rtlphy->pwrgroup_cnt][6]); in _rtl92c_store_pwrindex_diffrate_offset()
243 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] = in _rtl92c_store_pwrindex_diffrate_offset()
247 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
248 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrindex_diffrate_offset()
252 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] = in _rtl92c_store_pwrindex_diffrate_offset()
256 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
257 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrindex_diffrate_offset()
261 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] = in _rtl92c_store_pwrindex_diffrate_offset()
265 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
266 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrindex_diffrate_offset()
270 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] = in _rtl92c_store_pwrindex_diffrate_offset()
274 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
275 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrindex_diffrate_offset()
279 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] = in _rtl92c_store_pwrindex_diffrate_offset()
283 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
284 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrindex_diffrate_offset()
288 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] = in _rtl92c_store_pwrindex_diffrate_offset()
292 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
293 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrindex_diffrate_offset()
297 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] = in _rtl92c_store_pwrindex_diffrate_offset()
301 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
302 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrindex_diffrate_offset()
306 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] = in _rtl92c_store_pwrindex_diffrate_offset()
310 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
311 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrindex_diffrate_offset()
315 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] = in _rtl92c_store_pwrindex_diffrate_offset()
319 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
320 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrindex_diffrate_offset()
324 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] = in _rtl92c_store_pwrindex_diffrate_offset()
328 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
329 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrindex_diffrate_offset()
333 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] = in _rtl92c_store_pwrindex_diffrate_offset()
337 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
338 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrindex_diffrate_offset()
342 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] = in _rtl92c_store_pwrindex_diffrate_offset()
346 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
347 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrindex_diffrate_offset()
351 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] = in _rtl92c_store_pwrindex_diffrate_offset()
355 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrindex_diffrate_offset()
356 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrindex_diffrate_offset()
359 rtlphy->pwrgroup_cnt++; in _rtl92c_store_pwrindex_diffrate_offset()
367 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_get_hw_reg_originalvalue() local
369 rtlphy->default_initialgain[0] = in rtl92c_phy_get_hw_reg_originalvalue()
371 rtlphy->default_initialgain[1] = in rtl92c_phy_get_hw_reg_originalvalue()
373 rtlphy->default_initialgain[2] = in rtl92c_phy_get_hw_reg_originalvalue()
375 rtlphy->default_initialgain[3] = in rtl92c_phy_get_hw_reg_originalvalue()
380 rtlphy->default_initialgain[0], in rtl92c_phy_get_hw_reg_originalvalue()
381 rtlphy->default_initialgain[1], in rtl92c_phy_get_hw_reg_originalvalue()
382 rtlphy->default_initialgain[2], in rtl92c_phy_get_hw_reg_originalvalue()
383 rtlphy->default_initialgain[3]); in rtl92c_phy_get_hw_reg_originalvalue()
385 rtlphy->framesync = (u8)rtl_get_bbreg(hw, in rtl92c_phy_get_hw_reg_originalvalue()
387 rtlphy->framesync_c34 = rtl_get_bbreg(hw, in rtl92c_phy_get_hw_reg_originalvalue()
392 ROFDM0_RXDETECTOR3, rtlphy->framesync); in rtl92c_phy_get_hw_reg_originalvalue()
398 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_init_bb_rf_register_definition() local
400 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; in _rtl92c_phy_init_bb_rf_register_definition()
401 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; in _rtl92c_phy_init_bb_rf_register_definition()
402 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl92c_phy_init_bb_rf_register_definition()
403 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl92c_phy_init_bb_rf_register_definition()
405 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; in _rtl92c_phy_init_bb_rf_register_definition()
406 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; in _rtl92c_phy_init_bb_rf_register_definition()
407 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl92c_phy_init_bb_rf_register_definition()
408 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl92c_phy_init_bb_rf_register_definition()
410 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; in _rtl92c_phy_init_bb_rf_register_definition()
411 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; in _rtl92c_phy_init_bb_rf_register_definition()
413 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; in _rtl92c_phy_init_bb_rf_register_definition()
414 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; in _rtl92c_phy_init_bb_rf_register_definition()
416 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = in _rtl92c_phy_init_bb_rf_register_definition()
418 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = in _rtl92c_phy_init_bb_rf_register_definition()
421 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; in _rtl92c_phy_init_bb_rf_register_definition()
422 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; in _rtl92c_phy_init_bb_rf_register_definition()
423 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; in _rtl92c_phy_init_bb_rf_register_definition()
424 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; in _rtl92c_phy_init_bb_rf_register_definition()
426 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()
427 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()
428 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()
429 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()
431 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; in _rtl92c_phy_init_bb_rf_register_definition()
432 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; in _rtl92c_phy_init_bb_rf_register_definition()
434 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; in _rtl92c_phy_init_bb_rf_register_definition()
435 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; in _rtl92c_phy_init_bb_rf_register_definition()
437 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; in _rtl92c_phy_init_bb_rf_register_definition()
438 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; in _rtl92c_phy_init_bb_rf_register_definition()
439 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; in _rtl92c_phy_init_bb_rf_register_definition()
440 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; in _rtl92c_phy_init_bb_rf_register_definition()
442 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; in _rtl92c_phy_init_bb_rf_register_definition()
443 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; in _rtl92c_phy_init_bb_rf_register_definition()
444 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; in _rtl92c_phy_init_bb_rf_register_definition()
445 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; in _rtl92c_phy_init_bb_rf_register_definition()
447 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; in _rtl92c_phy_init_bb_rf_register_definition()
448 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; in _rtl92c_phy_init_bb_rf_register_definition()
449 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; in _rtl92c_phy_init_bb_rf_register_definition()
450 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; in _rtl92c_phy_init_bb_rf_register_definition()
452 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
453 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
454 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE; in _rtl92c_phy_init_bb_rf_register_definition()
455 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
457 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
458 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
459 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
460 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
462 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
463 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
464 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
465 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
467 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
468 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
469 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
470 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
472 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; in _rtl92c_phy_init_bb_rf_register_definition()
473 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; in _rtl92c_phy_init_bb_rf_register_definition()
474 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; in _rtl92c_phy_init_bb_rf_register_definition()
475 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; in _rtl92c_phy_init_bb_rf_register_definition()
477 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK; in _rtl92c_phy_init_bb_rf_register_definition()
478 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK; in _rtl92c_phy_init_bb_rf_register_definition()
486 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_get_txpower_level() local
491 txpwr_level = rtlphy->cur_cck_txpwridx; in rtl92c_phy_get_txpower_level()
494 txpwr_level = rtlphy->cur_ofdm24g_txpwridx + in rtl92c_phy_get_txpower_level()
501 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; in rtl92c_phy_get_txpower_level()
514 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_get_txpower_index() local
522 if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) { in _rtl92c_get_txpower_index()
527 } else if (get_rf_type(rtlphy) == RF_2T2R) { in _rtl92c_get_txpower_index()
540 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_ccxpower_index_check() local
542 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; in _rtl92c_ccxpower_index_check()
543 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; in _rtl92c_ccxpower_index_check()
567 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_update_txpower_dbm() local
591 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel); in rtl92c_phy_update_txpower_dbm()
656 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_set_bw_mode() local
658 u8 tmp_bw = rtlphy->current_chan_bw; in rtl92c_phy_set_bw_mode()
660 if (rtlphy->set_bwmode_inprogress) in rtl92c_phy_set_bw_mode()
662 rtlphy->set_bwmode_inprogress = true; in rtl92c_phy_set_bw_mode()
668 rtlphy->set_bwmode_inprogress = false; in rtl92c_phy_set_bw_mode()
669 rtlphy->current_chan_bw = tmp_bw; in rtl92c_phy_set_bw_mode()
678 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_sw_chnl_callback() local
682 "switch to channel%d\n", rtlphy->current_channel); in rtl92c_phy_sw_chnl_callback()
686 if (!rtlphy->sw_chnl_inprogress) in rtl92c_phy_sw_chnl_callback()
689 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, in rtl92c_phy_sw_chnl_callback()
690 &rtlphy->sw_chnl_step, &delay)) { in rtl92c_phy_sw_chnl_callback()
696 rtlphy->sw_chnl_inprogress = false; in rtl92c_phy_sw_chnl_callback()
707 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_sw_chnl() local
710 if (rtlphy->sw_chnl_inprogress) in rtl92c_phy_sw_chnl()
712 if (rtlphy->set_bwmode_inprogress) in rtl92c_phy_sw_chnl()
714 WARN_ONCE((rtlphy->current_channel > 14), in rtl92c_phy_sw_chnl()
716 rtlphy->sw_chnl_inprogress = true; in rtl92c_phy_sw_chnl()
717 rtlphy->sw_chnl_stage = 0; in rtl92c_phy_sw_chnl()
718 rtlphy->sw_chnl_step = 0; in rtl92c_phy_sw_chnl()
723 rtlphy->sw_chnl_inprogress = false; in rtl92c_phy_sw_chnl()
727 rtlphy->sw_chnl_inprogress = false; in rtl92c_phy_sw_chnl()
736 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_sw_rf_seting() local
741 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) { in _rtl92c_phy_sw_rf_seting()
782 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_sw_chnl_step_by_step() local
791 u8 num_total_rfpath = rtlphy->num_total_rfpath; in _rtl92c_phy_sw_chnl_step_by_step()
863 rtlphy->rfreg_chnlval[rfpath] = in _rtl92c_phy_sw_chnl_step_by_step()
864 ((rtlphy->rfreg_chnlval[rfpath] & in _rtl92c_phy_sw_chnl_step_by_step()
870 rtlphy->rfreg_chnlval[rfpath]); in _rtl92c_phy_sw_chnl_step_by_step()
1198 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_iq_calibrate() local
1216 rtlphy->adda_backup, 16); in _rtl92c_phy_iq_calibrate()
1218 rtlphy->iqk_mac_backup); in _rtl92c_phy_iq_calibrate()
1222 rtlphy->rfpi_enable = in _rtl92c_phy_iq_calibrate()
1227 if (!rtlphy->rfpi_enable) in _rtl92c_phy_iq_calibrate()
1230 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1231 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1232 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1242 rtlphy->iqk_mac_backup); in _rtl92c_phy_iq_calibrate()
1301 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04); in _rtl92c_phy_iq_calibrate()
1302 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874); in _rtl92c_phy_iq_calibrate()
1303 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08); in _rtl92c_phy_iq_calibrate()
1309 if (!rtlphy->rfpi_enable) in _rtl92c_phy_iq_calibrate()
1312 rtlphy->adda_backup, 16); in _rtl92c_phy_iq_calibrate()
1314 rtlphy->iqk_mac_backup); in _rtl92c_phy_iq_calibrate()
1353 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_iq_calibrate() local
1378 rtlphy->iqk_bb_backup, 10); in rtl92c_phy_iq_calibrate()
1440 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0]; in rtl92c_phy_iq_calibrate()
1441 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1]; in rtl92c_phy_iq_calibrate()
1443 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4]; in rtl92c_phy_iq_calibrate()
1444 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5]; in rtl92c_phy_iq_calibrate()
1449 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; in rtl92c_phy_iq_calibrate()
1450 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; in rtl92c_phy_iq_calibrate()
1464 rtlphy->iqk_bb_backup, 10); in rtl92c_phy_iq_calibrate()
1483 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_ap_calibrate() local
1486 if (rtlphy->apk_done) in rtl92c_phy_ap_calibrate()
1509 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_set_io_cmd() local
1514 iotype, rtlphy->set_io_inprogress); in rtl92c_phy_set_io_cmd()
1533 if (postprocessing && !rtlphy->set_io_inprogress) { in rtl92c_phy_set_io_cmd()
1534 rtlphy->set_io_inprogress = true; in rtl92c_phy_set_io_cmd()
1535 rtlphy->current_io_type = iotype; in rtl92c_phy_set_io_cmd()
1548 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_set_io() local
1553 rtlphy->current_io_type, rtlphy->set_io_inprogress); in rtl92c_phy_set_io()
1554 switch (rtlphy->current_io_type) { in rtl92c_phy_set_io()
1556 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; in rtl92c_phy_set_io()
1558 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel); in rtl92c_phy_set_io()
1561 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue; in rtl92c_phy_set_io()
1568 rtlphy->current_io_type); in rtl92c_phy_set_io()
1571 rtlphy->set_io_inprogress = false; in rtl92c_phy_set_io()
1573 "(%#x)\n", rtlphy->current_io_type); in rtl92c_phy_set_io()