Lines Matching refs:RF90_PATH_C

388 	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;  in _rtl92d_phy_init_bb_rf_register_definition()
398 	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;  in _rtl92d_phy_init_bb_rf_register_definition()
425 	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;  in _rtl92d_phy_init_bb_rf_register_definition()
434 	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl92d_phy_init_bb_rf_register_definition()
454 	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;  in _rtl92d_phy_init_bb_rf_register_definition()
460 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;  in _rtl92d_phy_init_bb_rf_register_definition()
466 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;  in _rtl92d_phy_init_bb_rf_register_definition()
472 	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
478 	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
484 	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
490 	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
496 	rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;  in _rtl92d_phy_init_bb_rf_register_definition()
807 	case RF90_PATH_C:  in rtl92d_phy_config_rf_with_headerfile()
1136 	case RF90_PATH_C:  in _rtl92d_phy_enable_rf_env()
1172 	case RF90_PATH_C:  in _rtl92d_phy_restore_rf_env()