Lines Matching refs:bar_sz
1300 u8 bar_sz; in xeon_setup_b2b_mw() local
1339 pci_read_config_byte(pdev, XEON_PBAR23SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1340 dev_dbg(&pdev->dev, "PBAR23SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1343 bar_sz -= 1; in xeon_setup_b2b_mw()
1345 bar_sz = 0; in xeon_setup_b2b_mw()
1347 pci_write_config_byte(pdev, XEON_SBAR23SZ_OFFSET, bar_sz); in xeon_setup_b2b_mw()
1348 pci_read_config_byte(pdev, XEON_SBAR23SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1349 dev_dbg(&pdev->dev, "SBAR23SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1352 pci_read_config_byte(pdev, XEON_PBAR45SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1353 dev_dbg(&pdev->dev, "PBAR45SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1356 bar_sz -= 1; in xeon_setup_b2b_mw()
1358 bar_sz = 0; in xeon_setup_b2b_mw()
1360 pci_write_config_byte(pdev, XEON_SBAR45SZ_OFFSET, bar_sz); in xeon_setup_b2b_mw()
1361 pci_read_config_byte(pdev, XEON_SBAR45SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1362 dev_dbg(&pdev->dev, "SBAR45SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1364 pci_read_config_byte(pdev, XEON_PBAR4SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1365 dev_dbg(&pdev->dev, "PBAR4SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1368 bar_sz -= 1; in xeon_setup_b2b_mw()
1370 bar_sz = 0; in xeon_setup_b2b_mw()
1372 pci_write_config_byte(pdev, XEON_SBAR4SZ_OFFSET, bar_sz); in xeon_setup_b2b_mw()
1373 pci_read_config_byte(pdev, XEON_SBAR4SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1374 dev_dbg(&pdev->dev, "SBAR4SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1376 pci_read_config_byte(pdev, XEON_PBAR5SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1377 dev_dbg(&pdev->dev, "PBAR5SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1380 bar_sz -= 1; in xeon_setup_b2b_mw()
1382 bar_sz = 0; in xeon_setup_b2b_mw()
1384 pci_write_config_byte(pdev, XEON_SBAR5SZ_OFFSET, bar_sz); in xeon_setup_b2b_mw()
1385 pci_read_config_byte(pdev, XEON_SBAR5SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1386 dev_dbg(&pdev->dev, "SBAR5SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()