99 				 struct ntb_ctrl_regs __iomem *ctl,  in switchtec_ntb_part_op()  argument
126 	iowrite32(op, &ctl->partition_op);  in switchtec_ntb_part_op()
130 			iowrite32(NTB_CTRL_PART_OP_RESET, &ctl->partition_op);  in switchtec_ntb_part_op()
134 		ps = ioread32(&ctl->partition_status) & 0xFFFF;  in switchtec_ntb_part_op()
147 			ioread32(&ctl->partition_status));  in switchtec_ntb_part_op()
223 	struct ntb_ctrl_regs __iomem *ctl = sndev->mmio_peer_ctrl;  in switchtec_ntb_mw_clr_direct()  local
227 	ctl_val = ioread32(&ctl->bar_entry[bar].ctl);  in switchtec_ntb_mw_clr_direct()
229 	iowrite32(ctl_val, &ctl->bar_entry[bar].ctl);  in switchtec_ntb_mw_clr_direct()
230 	iowrite32(0, &ctl->bar_entry[bar].win_size);  in switchtec_ntb_mw_clr_direct()
231 	iowrite32(0, &ctl->bar_ext_entry[bar].win_size);  in switchtec_ntb_mw_clr_direct()
232 	iowrite64(sndev->self_partition, &ctl->bar_entry[bar].xlate_addr);  in switchtec_ntb_mw_clr_direct()
237 	struct ntb_ctrl_regs __iomem *ctl = sndev->mmio_peer_ctrl;  in switchtec_ntb_mw_clr_lut()  local
239 	iowrite64(0, &ctl->lut_entry[peer_lut_index(sndev, idx)]);  in switchtec_ntb_mw_clr_lut()
247 	struct ntb_ctrl_regs __iomem *ctl = sndev->mmio_peer_ctrl;  in switchtec_ntb_mw_set_direct()  local
250 	ctl_val = ioread32(&ctl->bar_entry[bar].ctl);  in switchtec_ntb_mw_set_direct()
253 	iowrite32(ctl_val, &ctl->bar_entry[bar].ctl);  in switchtec_ntb_mw_set_direct()
255 		  &ctl->bar_entry[bar].win_size);  in switchtec_ntb_mw_set_direct()
256 	iowrite32(upper_32_bits(size), &ctl->bar_ext_entry[bar].win_size);  in switchtec_ntb_mw_set_direct()
258 		  &ctl->bar_entry[bar].xlate_addr);  in switchtec_ntb_mw_set_direct()
264 	struct ntb_ctrl_regs __iomem *ctl = sndev->mmio_peer_ctrl;  in switchtec_ntb_mw_set_lut()  local
267 		  &ctl->lut_entry[peer_lut_index(sndev, idx)]);  in switchtec_ntb_mw_set_lut()
274 	struct ntb_ctrl_regs __iomem *ctl = sndev->mmio_peer_ctrl;  in switchtec_ntb_mw_set_trans()  local
304 	rc = switchtec_ntb_part_op(sndev, ctl, NTB_CTRL_PART_OP_LOCK,  in switchtec_ntb_mw_set_trans()
321 	rc = switchtec_ntb_part_op(sndev, ctl, NTB_CTRL_PART_OP_CFG,  in switchtec_ntb_mw_set_trans()
327 			widx, ioread32(&ctl->bar_error));  in switchtec_ntb_mw_set_trans()
334 		switchtec_ntb_part_op(sndev, ctl, NTB_CTRL_PART_OP_CFG,  in switchtec_ntb_mw_set_trans()
909 			       struct ntb_ctrl_regs __iomem *ctl,  in config_rsvd_lut_win()  argument
916 	rc = switchtec_ntb_part_op(sndev, ctl, NTB_CTRL_PART_OP_LOCK,  in config_rsvd_lut_win()
921 	ctl_val = ioread32(&ctl->bar_entry[peer_bar].ctl);  in config_rsvd_lut_win()
926 	iowrite32(ctl_val, &ctl->bar_entry[peer_bar].ctl);  in config_rsvd_lut_win()
929 		  &ctl->lut_entry[lut_idx]);  in config_rsvd_lut_win()
931 	rc = switchtec_ntb_part_op(sndev, ctl, NTB_CTRL_PART_OP_CFG,  in config_rsvd_lut_win()
936 		bar_error = ioread32(&ctl->bar_error);  in config_rsvd_lut_win()
937 		lut_error = ioread32(&ctl->lut_error);  in config_rsvd_lut_win()
1000 	struct ntb_ctrl_regs __iomem *ctl = sndev->mmio_self_ctrl;  in crosslink_setup_mws()  local
1007 	rc = switchtec_ntb_part_op(sndev, ctl, NTB_CTRL_PART_OP_LOCK,  in crosslink_setup_mws()
1020 			  &ctl->lut_entry[i]);  in crosslink_setup_mws()
1035 		ctl_val = ioread32(&ctl->bar_entry[bar].ctl);  in crosslink_setup_mws()
1038 		iowrite32(ctl_val, &ctl->bar_entry[bar].ctl);  in crosslink_setup_mws()
1040 			  &ctl->bar_entry[bar].win_size);  in crosslink_setup_mws()
1041 		iowrite32(upper_32_bits(size), &ctl->bar_ext_entry[bar].win_size);  in crosslink_setup_mws()
1043 			  &ctl->bar_entry[bar].xlate_addr);  in crosslink_setup_mws()
1046 	rc = switchtec_ntb_part_op(sndev, ctl, NTB_CTRL_PART_OP_CFG,  in crosslink_setup_mws()
1051 		bar_error = ioread32(&ctl->bar_error);  in crosslink_setup_mws()
1052 		lut_error = ioread32(&ctl->lut_error);  in crosslink_setup_mws()
1190 		u32 r = ioread32(&ctrl->bar_entry[i].ctl);  in map_bars()