Lines Matching refs:rw
44 u32 rw; member
54 .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
93 .rw = GENMASK(24, 0),
100 .rw = (GENMASK(15, 12) | GENMASK(7, 4)),
112 .rw = GENMASK(31, 20) | GENMASK(15, 4),
120 .rw = GENMASK(31, 20) | GENMASK(15, 4),
127 .rw = ~0,
131 .rw = ~0,
135 .rw = ~0,
158 .rw = (GENMASK(7, 0) |
200 .rw = GENMASK(14, 0),
227 .rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0),
244 .rw = GENMASK(14, 0),
259 .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
289 .rw = GENMASK(15, 12) | GENMASK(10, 0),
304 .rw = GENMASK(15, 0),
371 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &= in pci_bridge_emul_init()
382 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0; in pci_bridge_emul_init()
449 *value &= behavior[reg / 4].ro | behavior[reg / 4].rw | in pci_bridge_emul_conf_read()
511 new = old & (~mask | ~behavior[reg / 4].rw); in pci_bridge_emul_conf_write()
514 new |= (value << shift) & (behavior[reg / 4].rw & mask); in pci_bridge_emul_conf_write()