Lines Matching refs:fpc
62 static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc) in ftm_clear_write_protection() argument
66 regmap_read(fpc->regmap, FTM_FMS, &val); in ftm_clear_write_protection()
68 regmap_update_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS, in ftm_clear_write_protection()
72 static void ftm_set_write_protection(struct fsl_pwm_chip *fpc) in ftm_set_write_protection() argument
74 regmap_update_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN, FTM_FMS_WPEN); in ftm_set_write_protection()
92 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); in fsl_pwm_request() local
94 ret = clk_prepare_enable(fpc->ipg_clk); in fsl_pwm_request()
95 if (!ret && fpc->soc->has_enable_bits) { in fsl_pwm_request()
96 mutex_lock(&fpc->lock); in fsl_pwm_request()
97 regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), in fsl_pwm_request()
99 mutex_unlock(&fpc->lock); in fsl_pwm_request()
107 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); in fsl_pwm_free() local
109 if (fpc->soc->has_enable_bits) { in fsl_pwm_free()
110 mutex_lock(&fpc->lock); in fsl_pwm_free()
111 regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), in fsl_pwm_free()
113 mutex_unlock(&fpc->lock); in fsl_pwm_free()
116 clk_disable_unprepare(fpc->ipg_clk); in fsl_pwm_free()
119 static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc, in fsl_pwm_ticks_to_ns() argument
125 rate = clk_get_rate(fpc->clk[fpc->period.clk_select]); in fsl_pwm_ticks_to_ns()
128 do_div(exval, rate >> fpc->period.clk_ps); in fsl_pwm_ticks_to_ns()
132 static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc, in fsl_pwm_calculate_period_clk() argument
141 c = clk_get_rate(fpc->clk[index]); in fsl_pwm_calculate_period_clk()
159 static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc, in fsl_pwm_calculate_period() argument
167 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS, in fsl_pwm_calculate_period()
172 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]); in fsl_pwm_calculate_period()
173 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]); in fsl_pwm_calculate_period()
183 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg); in fsl_pwm_calculate_period()
187 return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg); in fsl_pwm_calculate_period()
190 static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc, in fsl_pwm_calculate_duty() argument
195 unsigned int period = fpc->period.mod_period + 1; in fsl_pwm_calculate_duty()
196 unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period); in fsl_pwm_calculate_duty()
204 static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc, in fsl_pwm_is_any_pwm_enabled() argument
209 regmap_read(fpc->regmap, FTM_OUTMASK, &val); in fsl_pwm_is_any_pwm_enabled()
216 static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc, in fsl_pwm_is_other_pwm_enabled() argument
221 regmap_read(fpc->regmap, FTM_OUTMASK, &val); in fsl_pwm_is_other_pwm_enabled()
228 static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc, in fsl_pwm_apply_config() argument
238 if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) { in fsl_pwm_apply_config()
239 dev_err(fpc->chip.dev, "failed to calculate new period\n"); in fsl_pwm_apply_config()
243 if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm)) in fsl_pwm_apply_config()
251 else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) { in fsl_pwm_apply_config()
252 if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) { in fsl_pwm_apply_config()
253 dev_err(fpc->chip.dev, in fsl_pwm_apply_config()
258 if (fpc->period.clk_select != periodcfg.clk_select) { in fsl_pwm_apply_config()
260 enum fsl_pwm_clk oldclk = fpc->period.clk_select; in fsl_pwm_apply_config()
263 ret = clk_prepare_enable(fpc->clk[newclk]); in fsl_pwm_apply_config()
266 clk_disable_unprepare(fpc->clk[oldclk]); in fsl_pwm_apply_config()
271 ftm_clear_write_protection(fpc); in fsl_pwm_apply_config()
274 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, in fsl_pwm_apply_config()
276 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK, in fsl_pwm_apply_config()
278 regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period); in fsl_pwm_apply_config()
280 fpc->period = periodcfg; in fsl_pwm_apply_config()
283 duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle); in fsl_pwm_apply_config()
285 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm), in fsl_pwm_apply_config()
287 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty); in fsl_pwm_apply_config()
293 regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity); in fsl_pwm_apply_config()
295 ftm_set_write_protection(fpc); in fsl_pwm_apply_config()
303 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); in fsl_pwm_apply() local
316 mutex_lock(&fpc->lock); in fsl_pwm_apply()
320 regmap_update_bits(fpc->regmap, FTM_OUTMASK, in fsl_pwm_apply()
322 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); in fsl_pwm_apply()
323 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); in fsl_pwm_apply()
329 ret = fsl_pwm_apply_config(fpc, pwm, newstate); in fsl_pwm_apply()
335 ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]); in fsl_pwm_apply()
339 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); in fsl_pwm_apply()
341 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); in fsl_pwm_apply()
345 regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), in fsl_pwm_apply()
350 mutex_unlock(&fpc->lock); in fsl_pwm_apply()
361 static int fsl_pwm_init(struct fsl_pwm_chip *fpc) in fsl_pwm_init() argument
365 ret = clk_prepare_enable(fpc->ipg_clk); in fsl_pwm_init()
369 regmap_write(fpc->regmap, FTM_CNTIN, 0x00); in fsl_pwm_init()
370 regmap_write(fpc->regmap, FTM_OUTINIT, 0x00); in fsl_pwm_init()
371 regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF); in fsl_pwm_init()
373 clk_disable_unprepare(fpc->ipg_clk); in fsl_pwm_init()
401 struct fsl_pwm_chip *fpc; in fsl_pwm_probe() local
405 fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL); in fsl_pwm_probe()
406 if (!fpc) in fsl_pwm_probe()
409 mutex_init(&fpc->lock); in fsl_pwm_probe()
411 fpc->soc = of_device_get_match_data(&pdev->dev); in fsl_pwm_probe()
412 fpc->chip.dev = &pdev->dev; in fsl_pwm_probe()
418 fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base, in fsl_pwm_probe()
420 if (IS_ERR(fpc->regmap)) { in fsl_pwm_probe()
422 return PTR_ERR(fpc->regmap); in fsl_pwm_probe()
425 fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys"); in fsl_pwm_probe()
426 if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) { in fsl_pwm_probe()
428 return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]); in fsl_pwm_probe()
431 fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix"); in fsl_pwm_probe()
432 if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX])) in fsl_pwm_probe()
433 return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]); in fsl_pwm_probe()
435 fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext"); in fsl_pwm_probe()
436 if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT])) in fsl_pwm_probe()
437 return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]); in fsl_pwm_probe()
439 fpc->clk[FSL_PWM_CLK_CNTEN] = in fsl_pwm_probe()
440 devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en"); in fsl_pwm_probe()
441 if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN])) in fsl_pwm_probe()
442 return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]); in fsl_pwm_probe()
448 fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); in fsl_pwm_probe()
449 if (IS_ERR(fpc->ipg_clk)) in fsl_pwm_probe()
450 fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS]; in fsl_pwm_probe()
453 fpc->chip.ops = &fsl_pwm_ops; in fsl_pwm_probe()
454 fpc->chip.npwm = 8; in fsl_pwm_probe()
456 ret = devm_pwmchip_add(&pdev->dev, &fpc->chip); in fsl_pwm_probe()
462 platform_set_drvdata(pdev, fpc); in fsl_pwm_probe()
464 return fsl_pwm_init(fpc); in fsl_pwm_probe()
470 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev); in fsl_pwm_suspend() local
473 regcache_cache_only(fpc->regmap, true); in fsl_pwm_suspend()
474 regcache_mark_dirty(fpc->regmap); in fsl_pwm_suspend()
476 for (i = 0; i < fpc->chip.npwm; i++) { in fsl_pwm_suspend()
477 struct pwm_device *pwm = &fpc->chip.pwms[i]; in fsl_pwm_suspend()
482 clk_disable_unprepare(fpc->ipg_clk); in fsl_pwm_suspend()
487 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); in fsl_pwm_suspend()
488 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); in fsl_pwm_suspend()
496 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev); in fsl_pwm_resume() local
499 for (i = 0; i < fpc->chip.npwm; i++) { in fsl_pwm_resume()
500 struct pwm_device *pwm = &fpc->chip.pwms[i]; in fsl_pwm_resume()
505 clk_prepare_enable(fpc->ipg_clk); in fsl_pwm_resume()
510 clk_prepare_enable(fpc->clk[fpc->period.clk_select]); in fsl_pwm_resume()
511 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); in fsl_pwm_resume()
515 regcache_cache_only(fpc->regmap, false); in fsl_pwm_resume()
516 regcache_sync(fpc->regmap); in fsl_pwm_resume()