Lines Matching refs:BIT_5
108 #define BIT_5 0x20 macro
401 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
505 #define SRB_LOGIN_FCSP BIT_5
884 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
1197 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1218 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1372 #define MBX_5 BIT_5
1966 #define CF_READ BIT_5
2034 #define PO_DISABLE_INCR_REF_TAG BIT_5
2126 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
2371 #define NOTIFY24XX_FLAGS_FCSP BIT_5
2558 #define NVME_PRLI_SP_INITIATOR BIT_5
2721 #define FCF_ASYNC_ACTIVE BIT_5
4203 #define DT_ISP6312 BIT_5
4492 #define FW_ATTR_EXT0_EDIF BIT_5
4927 #define DFLG_DEV_FAILED BIT_5
5311 #define FC_LL_I BIT_5 /* Intermidiate*/
5321 #define FC_TEC_SL BIT_5 /* short wave with OFC */
5329 #define FC_MED_MI BIT_5 /* Min Coax */
5338 #define FC_SP_16 BIT_5