Lines Matching refs:INPLL
137 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
142 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
154 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
168 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_disable_dynamic_mode()
174 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
185 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_disable_dynamic_mode()
190 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
198 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_disable_dynamic_mode()
204 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_disable_dynamic_mode()
226 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
262 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_disable_dynamic_mode()
270 tmp = INPLL(pllCLK_PIN_CNTL); in radeon_pm_disable_dynamic_mode()
279 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
287 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
295 tmp = INPLL(pllMCLK_MISC); in radeon_pm_disable_dynamic_mode()
305 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_disable_dynamic_mode()
313 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_disable_dynamic_mode()
324 tmp = INPLL( pllVCLK_ECP_CNTL); in radeon_pm_disable_dynamic_mode()
337 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
352 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_enable_dynamic_mode()
361 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
373 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_enable_dynamic_mode()
380 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_enable_dynamic_mode()
385 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_enable_dynamic_mode()
401 tmp = INPLL(pllMCLK_MISC); in radeon_pm_enable_dynamic_mode()
406 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_enable_dynamic_mode()
420 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_enable_dynamic_mode()
437 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
443 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_enable_dynamic_mode()
452 tmp = INPLL( pllCLK_PWRMGT_CNTL); in radeon_pm_enable_dynamic_mode()
461 tmp = INPLL(pllCLK_PIN_CNTL); in radeon_pm_enable_dynamic_mode()
469 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
486 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_enable_dynamic_mode()
504 tmp = INPLL(pllPLL_PWRMGT_CNTL); in radeon_pm_enable_dynamic_mode()
510 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_enable_dynamic_mode()
521 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_enable_dynamic_mode()
529 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_enable_dynamic_mode()
537 tmp = INPLL(pllMCLK_MISC); in radeon_pm_enable_dynamic_mode()
564 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL); in radeon_pm_save_regs()
565 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL); in radeon_pm_save_regs()
566 rinfo->save_regs[2] = INPLL(MCLK_CNTL); in radeon_pm_save_regs()
567 rinfo->save_regs[3] = INPLL(SCLK_CNTL); in radeon_pm_save_regs()
568 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL); in radeon_pm_save_regs()
569 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL); in radeon_pm_save_regs()
570 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL); in radeon_pm_save_regs()
571 rinfo->save_regs[7] = INPLL(MCLK_MISC); in radeon_pm_save_regs()
572 rinfo->save_regs[8] = INPLL(P2PLL_CNTL); in radeon_pm_save_regs()
600 rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL); in radeon_pm_save_regs()
611 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL); in radeon_pm_save_regs()
612 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV); in radeon_pm_save_regs()
613 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0); in radeon_pm_save_regs()
614 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL); in radeon_pm_save_regs()
615 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL); in radeon_pm_save_regs()
661 rinfo->save_regs[73] = INPLL(pllMPLL_CNTL); in radeon_pm_save_regs()
662 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL); in radeon_pm_save_regs()
663 rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL); in radeon_pm_save_regs()
664 rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL); in radeon_pm_save_regs()
665 rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV); in radeon_pm_save_regs()
666 rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL); in radeon_pm_save_regs()
677 rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV); in radeon_pm_save_regs()
678 rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0); in radeon_pm_save_regs()
679 rinfo->save_regs[93] = INPLL(pllPPLL_CNTL); in radeon_pm_save_regs()
683 rinfo->save_regs[97] = INPLL(pllMDLL_CKO); in radeon_pm_save_regs()
684 rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA); in radeon_pm_save_regs()
685 rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB); in radeon_pm_save_regs()
760 INPLL(pllP2PLL_REF_DIV); in radeon_pm_program_v2clk()
766 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP); in radeon_pm_program_v2clk()
769 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET); in radeon_pm_program_v2clk()
773 (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK) in radeon_pm_program_v2clk()
791 reg = INPLL(PLL_PWRMGT_CNTL); in radeon_pm_low_current()
837 sclk_cntl = INPLL( pllSCLK_CNTL); in radeon_pm_setup_for_suspend()
874 sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_setup_for_suspend()
882 mclk_cntl = INPLL( pllMCLK_CNTL); in radeon_pm_setup_for_suspend()
892 vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL); in radeon_pm_setup_for_suspend()
899 pixclks_cntl = INPLL( pllPIXCLKS_CNTL); in radeon_pm_setup_for_suspend()
915 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL); in radeon_pm_setup_for_suspend()
925 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL); in radeon_pm_setup_for_suspend()
947 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL); in radeon_pm_setup_for_suspend()
952 tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND; in radeon_pm_setup_for_suspend()
989 tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL; in radeon_pm_setup_for_suspend()
1032 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL); in radeon_pm_setup_for_suspend()
1033 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ; in radeon_pm_setup_for_suspend()
1034 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL); in radeon_pm_setup_for_suspend()
1152 u32 cko = INPLL(pllMDLL_CKO) | MDLL_CKO__MCKOA_SLEEP in radeon_pm_enable_dll()
1154 u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP in radeon_pm_enable_dll()
1157 u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP in radeon_pm_enable_dll()
1232 dll_value = INPLL(pllMDLL_RDCKA); in radeon_pm_enable_dll_m10()
1464 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_all_ppls_off()
1466 tmp = INPLL(pllP2PLL_CNTL); in radeon_pm_all_ppls_off()
1468 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_all_ppls_off()
1470 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_all_ppls_off()
1479 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_start_mclk_sclk()
1483 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1490 tmp = INPLL(pllM_SPLL_REF_FB_DIV); in radeon_pm_start_mclk_sclk()
1495 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1497 (void)INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1502 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1504 (void)INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1509 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_start_mclk_sclk()
1513 (void)INPLL(pllSCLK_CNTL); in radeon_pm_start_mclk_sclk()
1518 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1525 tmp = INPLL(pllM_SPLL_REF_FB_DIV); in radeon_pm_start_mclk_sclk()
1530 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1532 (void)INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1537 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1539 (void)INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1544 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_start_mclk_sclk()
1547 (void)INPLL(pllMCLK_CNTL); in radeon_pm_start_mclk_sclk()
1599 tmp = INPLL(pllSSPLL_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1602 tmp = INPLL(pllSSPLL_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1631 tmp = INPLL(pllSS_TST_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1645 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_restore_pixel_pll()
1649 tmp = INPLL(pllPPLL_REF_DIV); in radeon_pm_restore_pixel_pll()
1652 INPLL(pllPPLL_REF_DIV); in radeon_pm_restore_pixel_pll()
1657 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_restore_pixel_pll()
1668 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_restore_pixel_pll()
1672 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_restore_pixel_pll()
1676 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_restore_pixel_pll()
1680 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_restore_pixel_pll()
1815 tmp = INPLL(pllSCLK_CNTL); in radeon_reinitialize_M10()
1882 tmp = INPLL(pllSCLK_CNTL2); /* What for ? */ in radeon_reinitialize_M10()
1885 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_reinitialize_M10()
2157 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; in radeon_reinitialize_M9P()
2162 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; in radeon_reinitialize_M9P()
2180 tmp = INPLL(pllSSPLL_CNTL); in radeon_reinitialize_M9P()
2254 tmp = INPLL(pllVCLK_ECP_CNTL);
2256 tmp = INPLL(pllPIXCLKS_CNTL);
2271 tmp = INPLL(M_SPLL_REF_FB_DIV);
2273 tmp = INPLL(M_SPLL_REF_FB_DIV);
2275 INPLL(M_SPLL_REF_FB_DIV);
2277 tmp = INPLL(MPLL_CNTL);
2283 tmp = INPLL(M_SPLL_REF_FB_DIV);
2286 tmp = INPLL(MPLL_CNTL);
2289 tmp = INPLL(MPLL_CNTL);
2296 INPLL(M_SPLL_REF_FB_DIV);
2297 INPLL(MCLK_CNTL);
2298 INPLL(M_SPLL_REF_FB_DIV);
2300 tmp = INPLL(SPLL_CNTL);
2306 tmp = INPLL(M_SPLL_REF_FB_DIV);
2309 tmp = INPLL(SPLL_CNTL);
2312 tmp = INPLL(SPLL_CNTL);
2316 tmp = INPLL(SCLK_CNTL);
2320 cko = INPLL(pllMDLL_CKO);
2321 cka = INPLL(pllMDLL_RDCKA);
2322 ckb = INPLL(pllMDLL_RDCKB);
2391 tmp = INPLL(MCLK_MISC);
2395 tmp = INPLL(SCLK_CNTL);
2403 tmp = INPLL(VCLK_ECP_CNTL);
2406 tmp = INPLL(PPLL_CNTL);
2450 tmp = INPLL(PPLL_REF_DIV);
2453 INPLL(PPLL_REF_DIV);
2468 tmp = INPLL(PPLL_CNTL);
2471 tmp = INPLL(PPLL_CNTL);
2475 tmp = INPLL(VCLK_ECP_CNTL);
2479 tmp = INPLL(VCLK_ECP_CNTL);
2580 tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET in radeon_set_suspend()
2720 return rinfo->save_regs[4] != INPLL(CLK_PIN_CNTL) || in radeon_check_power_loss()
2721 rinfo->save_regs[2] != INPLL(MCLK_CNTL) || in radeon_check_power_loss()
2722 rinfo->save_regs[3] != INPLL(SCLK_CNTL); in radeon_check_power_loss()