Lines Matching refs:rreg
34 {.reg = xreg, .rreg = xreg, .shift = shift_left, \
39 {.reg = xreg, .rreg = xreg, .shift = shift_left, \
49 {.reg = xlreg, .rreg = xrreg, .shift = xshift, .rshift = xshift, \
53 {.reg = xlreg, .rreg = xrreg, .shift = xshift, .rshift = xshift, \
58 {.reg = xlreg, .rreg = xrreg, .shift = xshift, .rshift = xshift, \
70 {.reg = xreg, .rreg = xreg, .shift = xshift, \
90 {.reg = xreg, .rreg = xreg, \
101 {.reg = xreg, .rreg = xreg, .shift = xshift, \
168 {.reg = xreg, .rreg = xrreg, \
188 {.reg = xreg, .rreg = xreg, \
269 {.reg = xreg, .rreg = xreg, .shift = xshift, \
1128 int reg, rreg; member
1166 unsigned int reg, rreg, shift, rshift, invert; member
1188 if (mc->reg == mc->rreg && mc->shift == mc->rshift) in snd_soc_volsw_is_stereo()