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Lines Matching refs:V4L2_DV_VSYNC_POS_POL

87 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
96 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
105 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
115 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
124 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
134 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
144 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
153 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
163 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
173 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
182 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
193 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
203 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
214 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
224 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
235 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
244 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
254 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
265 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
274 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
284 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
293 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
312 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
319 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
352 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
360 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
368 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
376 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
384 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
400 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
408 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
431 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
439 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
456 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
474 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
481 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
488 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
511 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
518 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
525 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
541 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
549 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
566 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
574 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
582 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
598 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
614 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
622 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
638 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
645 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
652 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
676 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
683 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
690 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
706 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
715 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
723 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
731 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
739 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
747 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
771 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
778 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
785 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
800 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
807 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
822 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
829 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
855 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
862 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
869 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
884 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
891 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
907 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
923 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
930 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
937 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \