Lines Matching refs:parent
61 struct clk *parent[2]; member
212 domain->codec.parent[clk_id]); in j721e_configure_refclk()
217 domain->mcasp.parent[clk_id]); in j721e_configure_refclk()
462 struct clk *parent; in j721e_get_clocks() local
477 parent = devm_clk_get(dev, clk_name); in j721e_get_clocks()
479 if (IS_ERR(parent)) { in j721e_get_clocks()
480 ret = PTR_ERR(parent); in j721e_get_clocks()
485 parent = NULL; in j721e_get_clocks()
487 clocks->parent[J721E_CLK_PARENT_48000] = parent; in j721e_get_clocks()
494 parent = devm_clk_get(dev, clk_name); in j721e_get_clocks()
496 if (IS_ERR(parent)) { in j721e_get_clocks()
497 ret = PTR_ERR(parent); in j721e_get_clocks()
502 parent = NULL; in j721e_get_clocks()
504 clocks->parent[J721E_CLK_PARENT_44100] = parent; in j721e_get_clocks()
509 if (!clocks->parent[J721E_CLK_PARENT_44100] && in j721e_get_clocks()
510 !clocks->parent[J721E_CLK_PARENT_48000]) { in j721e_get_clocks()
569 pll = clk_get_parent(domain_clocks->parent[J721E_CLK_PARENT_44100]); in j721e_calculate_rate_range()
578 pll = clk_get_parent(domain_clocks->parent[J721E_CLK_PARENT_48000]); in j721e_calculate_rate_range()