1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #ifndef __INTEL_SSEU_H__
7 #define __INTEL_SSEU_H__
8
9 #include <linux/types.h>
10 #include <linux/kernel.h>
11
12 #include "i915_gem.h"
13
14 struct drm_i915_private;
15 struct intel_gt;
16 struct drm_printer;
17
18 #define GEN_MAX_SLICES (3) /* SKL upper bound */
19 #define GEN_MAX_SUBSLICES (32) /* XEHPSDV upper bound */
20 #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
21 #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
22 #define GEN_MAX_EUS (16) /* TGL upper bound */
23 #define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
24
25 #define GEN_DSS_PER_GSLICE 4
26 #define GEN_DSS_PER_CSLICE 8
27 #define GEN_DSS_PER_MSLICE 8
28
29 struct sseu_dev_info {
30 u8 slice_mask;
31 u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
32 u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
33 u16 eu_total;
34 u8 eu_per_subslice;
35 u8 min_eu_in_pool;
36 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
37 u8 subslice_7eu[3];
38 u8 has_slice_pg:1;
39 u8 has_subslice_pg:1;
40 u8 has_eu_pg:1;
41
42 /* Topology fields */
43 u8 max_slices;
44 u8 max_subslices;
45 u8 max_eus_per_subslice;
46
47 u8 ss_stride;
48 u8 eu_stride;
49 };
50
51 /*
52 * Powergating configuration for a particular (context,engine).
53 */
54 struct intel_sseu {
55 u8 slice_mask;
56 u8 subslice_mask;
57 u8 min_eus_per_subslice;
58 u8 max_eus_per_subslice;
59 };
60
61 static inline struct intel_sseu
intel_sseu_from_device_info(const struct sseu_dev_info * sseu)62 intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
63 {
64 struct intel_sseu value = {
65 .slice_mask = sseu->slice_mask,
66 .subslice_mask = sseu->subslice_mask[0],
67 .min_eus_per_subslice = sseu->max_eus_per_subslice,
68 .max_eus_per_subslice = sseu->max_eus_per_subslice,
69 };
70
71 return value;
72 }
73
74 static inline bool
intel_sseu_has_subslice(const struct sseu_dev_info * sseu,int slice,int subslice)75 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
76 int subslice)
77 {
78 u8 mask;
79 int ss_idx = subslice / BITS_PER_BYTE;
80
81 GEM_BUG_ON(ss_idx >= sseu->ss_stride);
82
83 mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
84
85 return mask & BIT(subslice % BITS_PER_BYTE);
86 }
87
88 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
89 u8 max_subslices, u8 max_eus_per_subslice);
90
91 unsigned int
92 intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
93
94 unsigned int
95 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
96
97 u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
98
99 void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
100 u32 ss_mask);
101
102 void intel_sseu_info_init(struct intel_gt *gt);
103
104 u32 intel_sseu_make_rpcs(struct intel_gt *gt,
105 const struct intel_sseu *req_sseu);
106
107 void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p);
108 void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
109 struct drm_printer *p);
110
111 u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
112
113 #endif /* __INTEL_SSEU_H__ */
114