1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2017 Intel Corporation. All rights reserved.
7 *
8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 */
10
11 #ifndef __SOF_INTEL_HDA_H
12 #define __SOF_INTEL_HDA_H
13
14 #include <linux/soundwire/sdw.h>
15 #include <linux/soundwire/sdw_intel.h>
16 #include <sound/compress_driver.h>
17 #include <sound/hda_codec.h>
18 #include <sound/hdaudio_ext.h>
19 #include "shim.h"
20
21 /* PCI registers */
22 #define PCI_TCSEL 0x44
23 #define PCI_PGCTL PCI_TCSEL
24 #define PCI_CGCTL 0x48
25
26 /* PCI_PGCTL bits */
27 #define PCI_PGCTL_ADSPPGD BIT(2)
28 #define PCI_PGCTL_LSRMD_MASK BIT(4)
29
30 /* PCI_CGCTL bits */
31 #define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
32 #define PCI_CGCTL_ADSPDCGE BIT(1)
33
34 /* Legacy HDA registers and bits used - widths are variable */
35 #define SOF_HDA_GCAP 0x0
36 #define SOF_HDA_GCTL 0x8
37 /* accept unsol. response enable */
38 #define SOF_HDA_GCTL_UNSOL BIT(8)
39 #define SOF_HDA_LLCH 0x14
40 #define SOF_HDA_INTCTL 0x20
41 #define SOF_HDA_INTSTS 0x24
42 #define SOF_HDA_WAKESTS 0x0E
43 #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
44 #define SOF_HDA_RIRBSTS 0x5d
45
46 /* SOF_HDA_GCTL register bist */
47 #define SOF_HDA_GCTL_RESET BIT(0)
48
49 /* SOF_HDA_INCTL regs */
50 #define SOF_HDA_INT_GLOBAL_EN BIT(31)
51 #define SOF_HDA_INT_CTRL_EN BIT(30)
52 #define SOF_HDA_INT_ALL_STREAM 0xff
53
54 /* SOF_HDA_INTSTS regs */
55 #define SOF_HDA_INTSTS_GIS BIT(31)
56
57 #define SOF_HDA_MAX_CAPS 10
58 #define SOF_HDA_CAP_ID_OFF 16
59 #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
60 SOF_HDA_CAP_ID_OFF)
61 #define SOF_HDA_CAP_NEXT_MASK 0xFFFF
62
63 #define SOF_HDA_GTS_CAP_ID 0x1
64 #define SOF_HDA_ML_CAP_ID 0x2
65
66 #define SOF_HDA_PP_CAP_ID 0x3
67 #define SOF_HDA_REG_PP_PPCH 0x10
68 #define SOF_HDA_REG_PP_PPCTL 0x04
69 #define SOF_HDA_REG_PP_PPSTS 0x08
70 #define SOF_HDA_PPCTL_PIE BIT(31)
71 #define SOF_HDA_PPCTL_GPROCEN BIT(30)
72
73 /*Vendor Specific Registers*/
74 #define SOF_HDA_VS_D0I3C 0x104A
75
76 /* D0I3C Register fields */
77 #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */
78 #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */
79
80 /* DPIB entry size: 8 Bytes = 2 DWords */
81 #define SOF_HDA_DPIB_ENTRY_SIZE 0x8
82
83 #define SOF_HDA_SPIB_CAP_ID 0x4
84 #define SOF_HDA_DRSM_CAP_ID 0x5
85
86 #define SOF_HDA_SPIB_BASE 0x08
87 #define SOF_HDA_SPIB_INTERVAL 0x08
88 #define SOF_HDA_SPIB_SPIB 0x00
89 #define SOF_HDA_SPIB_MAXFIFO 0x04
90
91 #define SOF_HDA_PPHC_BASE 0x10
92 #define SOF_HDA_PPHC_INTERVAL 0x10
93
94 #define SOF_HDA_PPLC_BASE 0x10
95 #define SOF_HDA_PPLC_MULTI 0x10
96 #define SOF_HDA_PPLC_INTERVAL 0x10
97
98 #define SOF_HDA_DRSM_BASE 0x08
99 #define SOF_HDA_DRSM_INTERVAL 0x08
100
101 /* Descriptor error interrupt */
102 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
103
104 /* FIFO error interrupt */
105 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
106
107 /* Buffer completion interrupt */
108 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
109
110 #define SOF_HDA_CL_DMA_SD_INT_MASK \
111 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
112 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
113 SOF_HDA_CL_DMA_SD_INT_COMPLETE)
114 #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
115
116 /* Intel HD Audio Code Loader DMA Registers */
117 #define SOF_HDA_ADSP_LOADER_BASE 0x80
118 #define SOF_HDA_ADSP_DPLBASE 0x70
119 #define SOF_HDA_ADSP_DPUBASE 0x74
120 #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
121
122 /* Stream Registers */
123 #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00
124 #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03
125 #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04
126 #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08
127 #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C
128 #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E
129 #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10
130 #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12
131 #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14
132 #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18
133 #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C
134 #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
135
136 /* CL: Software Position Based FIFO Capability Registers */
137 #define SOF_DSP_REG_CL_SPBFIFO \
138 (SOF_HDA_ADSP_LOADER_BASE + 0x20)
139 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
140 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
141 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
142 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
143
144 /* Stream Number */
145 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
146 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
147 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
148 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
149
150 #define HDA_DSP_HDA_BAR 0
151 #define HDA_DSP_PP_BAR 1
152 #define HDA_DSP_SPIB_BAR 2
153 #define HDA_DSP_DRSM_BAR 3
154 #define HDA_DSP_BAR 4
155
156 #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
157
158 #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
159
160 #define HDA_DSP_PANIC_OFFSET(x) \
161 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
162
163 /* SRAM window 0 FW "registers" */
164 #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
165 #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
166 /* FW and ROM share offset 4 */
167 #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
168 #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
169 #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
170
171 #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
172
173 #define HDA_DSP_STREAM_RESET_TIMEOUT 300
174 /*
175 * Timeout in us, for setting the stream RUN bit, during
176 * start/stop the stream. The timeout expires if new RUN bit
177 * value cannot be read back within the specified time.
178 */
179 #define HDA_DSP_STREAM_RUN_TIMEOUT 300
180
181 #define HDA_DSP_SPIB_ENABLE 1
182 #define HDA_DSP_SPIB_DISABLE 0
183
184 #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
185
186 #define HDA_DSP_STACK_DUMP_SIZE 32
187
188 /* ROM status/error values */
189 #define HDA_DSP_ROM_STS_MASK GENMASK(23, 0)
190 #define HDA_DSP_ROM_INIT 0x1
191 #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3
192 #define HDA_DSP_ROM_FW_FW_LOADED 0x4
193 #define HDA_DSP_ROM_FW_ENTERED 0x5
194 #define HDA_DSP_ROM_RFW_START 0xf
195 #define HDA_DSP_ROM_CSE_ERROR 40
196 #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
197 #define HDA_DSP_ROM_IMR_TO_SMALL 42
198 #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
199 #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
200 #define HDA_DSP_ROM_IPC_FATAL_ERROR 45
201 #define HDA_DSP_ROM_L2_CACHE_ERROR 46
202 #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
203 #define HDA_DSP_ROM_API_PTR_INVALID 50
204 #define HDA_DSP_ROM_BASEFW_INCOMPAT 51
205 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
206 #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
207 #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
208 #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
209 #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
210 #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
211 #define HDA_DSP_IPC_PURGE_FW 0x01004000
212
213 /* various timeout values */
214 #define HDA_DSP_PU_TIMEOUT 50
215 #define HDA_DSP_PD_TIMEOUT 50
216 #define HDA_DSP_RESET_TIMEOUT_US 50000
217 #define HDA_DSP_BASEFW_TIMEOUT_US 3000000
218 #define HDA_DSP_INIT_TIMEOUT_US 500000
219 #define HDA_DSP_CTRL_RESET_TIMEOUT 100
220 #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
221 #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
222 #define HDA_DSP_REG_POLL_RETRY_COUNT 50
223
224 #define HDA_DSP_ADSPIC_IPC 1
225 #define HDA_DSP_ADSPIS_IPC 1
226
227 /* Intel HD Audio General DSP Registers */
228 #define HDA_DSP_GEN_BASE 0x0
229 #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
230 #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
231 #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
232 #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
233 #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
234
235 #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5)
236
237 /* Intel HD Audio Inter-Processor Communication Registers */
238 #define HDA_DSP_IPC_BASE 0x40
239 #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
240 #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
241 #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
242 #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
243 #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
244
245 /* Intel Vendor Specific Registers */
246 #define HDA_VS_INTEL_EM2 0x1030
247 #define HDA_VS_INTEL_EM2_L1SEN BIT(13)
248 #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F
249
250 /* HIPCI */
251 #define HDA_DSP_REG_HIPCI_BUSY BIT(31)
252 #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
253
254 /* HIPCIE */
255 #define HDA_DSP_REG_HIPCIE_DONE BIT(30)
256 #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
257
258 /* HIPCCTL */
259 #define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
260 #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
261
262 /* HIPCT */
263 #define HDA_DSP_REG_HIPCT_BUSY BIT(31)
264 #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
265
266 /* HIPCTE */
267 #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
268
269 #define HDA_DSP_ADSPIC_CL_DMA 0x2
270 #define HDA_DSP_ADSPIS_CL_DMA 0x2
271
272 /* Delay before scheduling D0i3 entry */
273 #define BXT_D0I3_DELAY 5000
274
275 #define FW_CL_STREAM_NUMBER 0x1
276 #define HDA_FW_BOOT_ATTEMPTS 3
277
278 /* ADSPCS - Audio DSP Control & Status */
279
280 /*
281 * Core Reset - asserted high
282 * CRST Mask for a given core mask pattern, cm
283 */
284 #define HDA_DSP_ADSPCS_CRST_SHIFT 0
285 #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
286
287 /*
288 * Core run/stall - when set to '1' core is stalled
289 * CSTALL Mask for a given core mask pattern, cm
290 */
291 #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
292 #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
293
294 /*
295 * Set Power Active - when set to '1' turn cores on
296 * SPA Mask for a given core mask pattern, cm
297 */
298 #define HDA_DSP_ADSPCS_SPA_SHIFT 16
299 #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
300
301 /*
302 * Current Power Active - power status of cores, set by hardware
303 * CPA Mask for a given core mask pattern, cm
304 */
305 #define HDA_DSP_ADSPCS_CPA_SHIFT 24
306 #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
307
308 /*
309 * Mask for a given number of cores
310 * nc = number of supported cores
311 */
312 #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
313
314 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
315 #define CNL_DSP_IPC_BASE 0xc0
316 #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
317 #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
318 #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
319 #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
320 #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
321 #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18)
322 #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
323
324 /* HIPCI */
325 #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
326 #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
327
328 /* HIPCIE */
329 #define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
330 #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
331
332 /* HIPCCTL */
333 #define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
334 #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
335
336 /* HIPCT */
337 #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
338 #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
339
340 /* HIPCTDA */
341 #define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
342 #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
343
344 /* HIPCTDD */
345 #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
346
347 /* BDL */
348 #define HDA_DSP_BDL_SIZE 4096
349 #define HDA_DSP_MAX_BDL_ENTRIES \
350 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
351
352 /* Number of DAIs */
353 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
354
355 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
356 #define SOF_SKL_NUM_DAIS 16
357 #else
358 #define SOF_SKL_NUM_DAIS 15
359 #endif
360
361 #else
362 #define SOF_SKL_NUM_DAIS 8
363 #endif
364
365 /* Intel HD Audio SRAM Window 0*/
366 #define HDA_ADSP_SRAM0_BASE_SKL 0x8000
367
368 /* Firmware status window */
369 #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
370 #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
371
372 /* Host Device Memory Space */
373 #define APL_SSP_BASE_OFFSET 0x2000
374 #define CNL_SSP_BASE_OFFSET 0x10000
375
376 /* Host Device Memory Size of a Single SSP */
377 #define SSP_DEV_MEM_SIZE 0x1000
378
379 /* SSP Count of the Platform */
380 #define APL_SSP_COUNT 6
381 #define CNL_SSP_COUNT 3
382 #define ICL_SSP_COUNT 6
383
384 /* SSP Registers */
385 #define SSP_SSC1_OFFSET 0x4
386 #define SSP_SET_SCLK_SLAVE BIT(25)
387 #define SSP_SET_SFRM_SLAVE BIT(24)
388 #define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
389
390 #define HDA_IDISP_ADDR 2
391 #define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR))
392
393 struct sof_intel_dsp_bdl {
394 __le32 addr_l;
395 __le32 addr_h;
396 __le32 size;
397 __le32 ioc;
398 } __attribute((packed));
399
400 #define SOF_HDA_PLAYBACK_STREAMS 16
401 #define SOF_HDA_CAPTURE_STREAMS 16
402 #define SOF_HDA_PLAYBACK 0
403 #define SOF_HDA_CAPTURE 1
404
405 /* stream flags */
406 #define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1
407
408 /*
409 * Time in ms for opportunistic D0I3 entry delay.
410 * This has been deliberately chosen to be long to avoid race conditions.
411 * Could be optimized in future.
412 */
413 #define SOF_HDA_D0I3_WORK_DELAY_MS 5000
414
415 /* HDA DSP D0 substate */
416 enum sof_hda_D0_substate {
417 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */
418 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */
419 };
420
421 /* represents DSP HDA controller frontend - i.e. host facing control */
422 struct sof_intel_hda_dev {
423 int boot_iteration;
424
425 struct hda_bus hbus;
426
427 /* hw config */
428 const struct sof_intel_dsp_desc *desc;
429
430 /* trace */
431 struct hdac_ext_stream *dtrace_stream;
432
433 /* if position update IPC needed */
434 u32 no_ipc_position;
435
436 /* the maximum number of streams (playback + capture) supported */
437 u32 stream_max;
438
439 /* PM related */
440 bool l1_support_changed;/* during suspend, is L1SEN changed or not */
441
442 /* DMIC device */
443 struct platform_device *dmic_dev;
444
445 /* delayed work to enter D0I3 opportunistically */
446 struct delayed_work d0i3_work;
447
448 /* ACPI information stored between scan and probe steps */
449 struct sdw_intel_acpi_info info;
450
451 /* sdw context allocated by SoundWire driver */
452 struct sdw_intel_ctx *sdw;
453
454 /* FW clock config, 0:HPRO, 1:LPRO */
455 bool clk_config_lpro;
456 };
457
sof_to_bus(struct snd_sof_dev * s)458 static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
459 {
460 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
461
462 return &hda->hbus.core;
463 }
464
sof_to_hbus(struct snd_sof_dev * s)465 static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
466 {
467 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
468
469 return &hda->hbus;
470 }
471
472 struct sof_intel_hda_stream {
473 struct snd_sof_dev *sdev;
474 struct hdac_ext_stream hda_stream;
475 struct sof_intel_stream stream;
476 int host_reserved; /* reserve host DMA channel */
477 u32 flags;
478 };
479
480 #define hstream_to_sof_hda_stream(hstream) \
481 container_of(hstream, struct sof_intel_hda_stream, hda_stream)
482
483 #define bus_to_sof_hda(bus) \
484 container_of(bus, struct sof_intel_hda_dev, hbus.core)
485
486 #define SOF_STREAM_SD_OFFSET(s) \
487 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
488 + SOF_HDA_ADSP_LOADER_BASE)
489
490 /*
491 * DSP Core services.
492 */
493 int hda_dsp_probe(struct snd_sof_dev *sdev);
494 int hda_dsp_remove(struct snd_sof_dev *sdev);
495 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
496 unsigned int core_mask);
497 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
498 unsigned int core_mask);
499 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
500 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
501 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
502 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
503 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
504 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
505 unsigned int core_mask);
506 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
507 unsigned int core_mask);
508 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
509 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
510
511 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
512 const struct sof_dsp_power_state *target_state);
513
514 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state);
515 int hda_dsp_resume(struct snd_sof_dev *sdev);
516 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
517 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
518 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
519 int hda_dsp_shutdown(struct snd_sof_dev *sdev);
520 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
521 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
522 void hda_ipc_dump(struct snd_sof_dev *sdev);
523 void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
524 void hda_dsp_d0i3_work(struct work_struct *work);
525
526 /*
527 * DSP PCM Operations.
528 */
529 u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate);
530 u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits);
531 int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
532 struct snd_pcm_substream *substream);
533 int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
534 struct snd_pcm_substream *substream);
535 int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
536 struct snd_pcm_substream *substream,
537 struct snd_pcm_hw_params *params,
538 struct sof_ipc_stream_params *ipc_params);
539 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
540 struct snd_pcm_substream *substream);
541 int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
542 struct snd_pcm_substream *substream, int cmd);
543 snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
544 struct snd_pcm_substream *substream);
545
546 /*
547 * DSP Stream Operations.
548 */
549
550 int hda_dsp_stream_init(struct snd_sof_dev *sdev);
551 void hda_dsp_stream_free(struct snd_sof_dev *sdev);
552 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
553 struct hdac_ext_stream *stream,
554 struct snd_dma_buffer *dmab,
555 struct snd_pcm_hw_params *params);
556 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream,
557 struct snd_dma_buffer *dmab,
558 struct snd_pcm_hw_params *params);
559 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
560 struct hdac_ext_stream *stream, int cmd);
561 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
562 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
563 struct snd_dma_buffer *dmab,
564 struct hdac_stream *stream);
565 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
566 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
567
568 struct hdac_ext_stream *
569 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags);
570 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
571 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
572 struct hdac_ext_stream *stream,
573 int enable, u32 size);
574
575 void hda_ipc_msg_data(struct snd_sof_dev *sdev,
576 struct snd_pcm_substream *substream,
577 void *p, size_t sz);
578 int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
579 struct snd_pcm_substream *substream,
580 const struct sof_ipc_pcm_params_reply *reply);
581
582 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
583 /*
584 * Probe Compress Operations.
585 */
586 int hda_probe_compr_assign(struct snd_sof_dev *sdev,
587 struct snd_compr_stream *cstream,
588 struct snd_soc_dai *dai);
589 int hda_probe_compr_free(struct snd_sof_dev *sdev,
590 struct snd_compr_stream *cstream,
591 struct snd_soc_dai *dai);
592 int hda_probe_compr_set_params(struct snd_sof_dev *sdev,
593 struct snd_compr_stream *cstream,
594 struct snd_compr_params *params,
595 struct snd_soc_dai *dai);
596 int hda_probe_compr_trigger(struct snd_sof_dev *sdev,
597 struct snd_compr_stream *cstream, int cmd,
598 struct snd_soc_dai *dai);
599 int hda_probe_compr_pointer(struct snd_sof_dev *sdev,
600 struct snd_compr_stream *cstream,
601 struct snd_compr_tstamp *tstamp,
602 struct snd_soc_dai *dai);
603 #endif
604
605 /*
606 * DSP IPC Operations.
607 */
608 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
609 struct snd_sof_ipc_msg *msg);
610 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
611 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
612 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
613
614 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
615 int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
616
617 /*
618 * DSP Code loader.
619 */
620 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
621 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev);
622 int hda_dsp_cl_boot_firmware_iccmax_icl(struct snd_sof_dev *sdev);
623 int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
624
625 /* pre and post fw run ops */
626 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
627 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
628 int hda_dsp_post_fw_run_icl(struct snd_sof_dev *sdev);
629 int hda_dsp_core_stall_icl(struct snd_sof_dev *sdev, unsigned int core_mask);
630
631 /* parse platform specific ext manifest ops */
632 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
633 const struct sof_ext_man_elem_header *hdr);
634
635 /*
636 * HDA Controller Operations.
637 */
638 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
639 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
640 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
641 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
642 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
643 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
644 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
645 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
646 /*
647 * HDA bus operations.
648 */
649 void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev);
650
651 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
652 /*
653 * HDA Codec operations.
654 */
655 void hda_codec_probe_bus(struct snd_sof_dev *sdev,
656 bool hda_codec_use_common_hdmi);
657 void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable);
658 void hda_codec_jack_check(struct snd_sof_dev *sdev);
659
660 #endif /* CONFIG_SND_SOC_SOF_HDA */
661
662 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \
663 (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \
664 IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
665
666 void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable);
667 int hda_codec_i915_init(struct snd_sof_dev *sdev);
668 int hda_codec_i915_exit(struct snd_sof_dev *sdev);
669
670 #else
671
hda_codec_i915_display_power(struct snd_sof_dev * sdev,bool enable)672 static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev,
673 bool enable) { }
hda_codec_i915_init(struct snd_sof_dev * sdev)674 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
hda_codec_i915_exit(struct snd_sof_dev * sdev)675 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
676
677 #endif
678
679 /*
680 * Trace Control.
681 */
682 int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
683 int hda_dsp_trace_release(struct snd_sof_dev *sdev);
684 int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
685
686 /*
687 * SoundWire support
688 */
689 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
690
691 int hda_sdw_startup(struct snd_sof_dev *sdev);
692 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
693 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
694 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
695
696 #else
697
hda_sdw_acpi_scan(struct snd_sof_dev * sdev)698 static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
699 {
700 return 0;
701 }
702
hda_sdw_probe(struct snd_sof_dev * sdev)703 static inline int hda_sdw_probe(struct snd_sof_dev *sdev)
704 {
705 return 0;
706 }
707
hda_sdw_startup(struct snd_sof_dev * sdev)708 static inline int hda_sdw_startup(struct snd_sof_dev *sdev)
709 {
710 return 0;
711 }
712
hda_sdw_exit(struct snd_sof_dev * sdev)713 static inline int hda_sdw_exit(struct snd_sof_dev *sdev)
714 {
715 return 0;
716 }
717
hda_sdw_int_enable(struct snd_sof_dev * sdev,bool enable)718 static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
719 {
720 }
721
hda_dsp_check_sdw_irq(struct snd_sof_dev * sdev)722 static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
723 {
724 return false;
725 }
726
hda_dsp_sdw_thread(int irq,void * context)727 static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
728 {
729 return IRQ_HANDLED;
730 }
731
hda_sdw_check_wakeen_irq(struct snd_sof_dev * sdev)732 static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
733 {
734 return false;
735 }
736
hda_sdw_process_wakeen(struct snd_sof_dev * sdev)737 static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
738 {
739 }
740
hda_common_check_sdw_irq(struct snd_sof_dev * sdev)741 static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
742 {
743 return false;
744 }
745
746 #endif
747
748 /* common dai driver */
749 extern struct snd_soc_dai_driver skl_dai[];
750
751 /*
752 * Platform Specific HW abstraction Ops.
753 */
754 extern const struct snd_sof_dsp_ops sof_apl_ops;
755 extern const struct snd_sof_dsp_ops sof_cnl_ops;
756 extern const struct snd_sof_dsp_ops sof_tgl_ops;
757 extern const struct snd_sof_dsp_ops sof_icl_ops;
758
759 extern const struct sof_intel_dsp_desc apl_chip_info;
760 extern const struct sof_intel_dsp_desc cnl_chip_info;
761 extern const struct sof_intel_dsp_desc skl_chip_info;
762 extern const struct sof_intel_dsp_desc icl_chip_info;
763 extern const struct sof_intel_dsp_desc tgl_chip_info;
764 extern const struct sof_intel_dsp_desc tglh_chip_info;
765 extern const struct sof_intel_dsp_desc ehl_chip_info;
766 extern const struct sof_intel_dsp_desc jsl_chip_info;
767 extern const struct sof_intel_dsp_desc adls_chip_info;
768
769 /* machine driver select */
770 void hda_machine_select(struct snd_sof_dev *sdev);
771 void hda_set_mach_params(const struct snd_soc_acpi_mach *mach,
772 struct snd_sof_dev *sdev);
773
774 /* PCI driver selection and probe */
775 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id);
776
777 #endif
778