1 /*
2 * SPDX-License-Identifier: MIT
3 *
4 * Copyright © 2016 Intel Corporation
5 */
6
7 #ifndef __I915_GEM_OBJECT_TYPES_H__
8 #define __I915_GEM_OBJECT_TYPES_H__
9
10 #include <linux/mmu_notifier.h>
11
12 #include <drm/drm_gem.h>
13 #include <drm/ttm/ttm_bo_api.h>
14 #include <uapi/drm/i915_drm.h>
15
16 #include "i915_active.h"
17 #include "i915_selftest.h"
18
19 struct drm_i915_gem_object;
20 struct intel_fronbuffer;
21 struct intel_memory_region;
22
23 /*
24 * struct i915_lut_handle tracks the fast lookups from handle to vma used
25 * for execbuf. Although we use a radixtree for that mapping, in order to
26 * remove them as the object or context is closed, we need a secondary list
27 * and a translation entry (i915_lut_handle).
28 */
29 struct i915_lut_handle {
30 struct list_head obj_link;
31 struct i915_gem_context *ctx;
32 u32 handle;
33 };
34
35 struct drm_i915_gem_object_ops {
36 unsigned int flags;
37 #define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
38 #define I915_GEM_OBJECT_IS_PROXY BIT(2)
39 #define I915_GEM_OBJECT_NO_MMAP BIT(3)
40
41 /* Interface between the GEM object and its backing storage.
42 * get_pages() is called once prior to the use of the associated set
43 * of pages before to binding them into the GTT, and put_pages() is
44 * called after we no longer need them. As we expect there to be
45 * associated cost with migrating pages between the backing storage
46 * and making them available for the GPU (e.g. clflush), we may hold
47 * onto the pages after they are no longer referenced by the GPU
48 * in case they may be used again shortly (for example migrating the
49 * pages to a different memory domain within the GTT). put_pages()
50 * will therefore most likely be called when the object itself is
51 * being released or under memory pressure (where we attempt to
52 * reap pages for the shrinker).
53 */
54 int (*get_pages)(struct drm_i915_gem_object *obj);
55 void (*put_pages)(struct drm_i915_gem_object *obj,
56 struct sg_table *pages);
57 void (*truncate)(struct drm_i915_gem_object *obj);
58 void (*writeback)(struct drm_i915_gem_object *obj);
59
60 int (*pread)(struct drm_i915_gem_object *obj,
61 const struct drm_i915_gem_pread *arg);
62 int (*pwrite)(struct drm_i915_gem_object *obj,
63 const struct drm_i915_gem_pwrite *arg);
64 u64 (*mmap_offset)(struct drm_i915_gem_object *obj);
65
66 int (*dmabuf_export)(struct drm_i915_gem_object *obj);
67
68 /**
69 * adjust_lru - notify that the madvise value was updated
70 * @obj: The gem object
71 *
72 * The madvise value may have been updated, or object was recently
73 * referenced so act accordingly (Perhaps changing an LRU list etc).
74 */
75 void (*adjust_lru)(struct drm_i915_gem_object *obj);
76
77 /**
78 * delayed_free - Override the default delayed free implementation
79 */
80 void (*delayed_free)(struct drm_i915_gem_object *obj);
81
82 /**
83 * migrate - Migrate object to a different region either for
84 * pinning or for as long as the object lock is held.
85 */
86 int (*migrate)(struct drm_i915_gem_object *obj,
87 struct intel_memory_region *mr);
88
89 void (*release)(struct drm_i915_gem_object *obj);
90
91 const struct vm_operations_struct *mmap_ops;
92 const char *name; /* friendly name for debug, e.g. lockdep classes */
93 };
94
95 /**
96 * enum i915_cache_level - The supported GTT caching values for system memory
97 * pages.
98 *
99 * These translate to some special GTT PTE bits when binding pages into some
100 * address space. It also determines whether an object, or rather its pages are
101 * coherent with the GPU, when also reading or writing through the CPU cache
102 * with those pages.
103 *
104 * Userspace can also control this through struct drm_i915_gem_caching.
105 */
106 enum i915_cache_level {
107 /**
108 * @I915_CACHE_NONE:
109 *
110 * GPU access is not coherent with the CPU cache. If the cache is dirty
111 * and we need the underlying pages to be coherent with some later GPU
112 * access then we need to manually flush the pages.
113 *
114 * On shared LLC platforms reads and writes through the CPU cache are
115 * still coherent even with this setting. See also
116 * &drm_i915_gem_object.cache_coherent for more details. Due to this we
117 * should only ever use uncached for scanout surfaces, otherwise we end
118 * up over-flushing in some places.
119 *
120 * This is the default on non-LLC platforms.
121 */
122 I915_CACHE_NONE = 0,
123 /**
124 * @I915_CACHE_LLC:
125 *
126 * GPU access is coherent with the CPU cache. If the cache is dirty,
127 * then the GPU will ensure that access remains coherent, when both
128 * reading and writing through the CPU cache. GPU writes can dirty the
129 * CPU cache.
130 *
131 * Not used for scanout surfaces.
132 *
133 * Applies to both platforms with shared LLC(HAS_LLC), and snooping
134 * based platforms(HAS_SNOOP).
135 *
136 * This is the default on shared LLC platforms. The only exception is
137 * scanout objects, where the display engine is not coherent with the
138 * CPU cache. For such objects I915_CACHE_NONE or I915_CACHE_WT is
139 * automatically applied by the kernel in pin_for_display, if userspace
140 * has not done so already.
141 */
142 I915_CACHE_LLC,
143 /**
144 * @I915_CACHE_L3_LLC:
145 *
146 * Explicitly enable the Gfx L3 cache, with coherent LLC.
147 *
148 * The Gfx L3 sits between the domain specific caches, e.g
149 * sampler/render caches, and the larger LLC. LLC is coherent with the
150 * GPU, but L3 is only visible to the GPU, so likely needs to be flushed
151 * when the workload completes.
152 *
153 * Not used for scanout surfaces.
154 *
155 * Only exposed on some gen7 + GGTT. More recent hardware has dropped
156 * this explicit setting, where it should now be enabled by default.
157 */
158 I915_CACHE_L3_LLC,
159 /**
160 * @I915_CACHE_WT:
161 *
162 * Write-through. Used for scanout surfaces.
163 *
164 * The GPU can utilise the caches, while still having the display engine
165 * be coherent with GPU writes, as a result we don't need to flush the
166 * CPU caches when moving out of the render domain. This is the default
167 * setting chosen by the kernel, if supported by the HW, otherwise we
168 * fallback to I915_CACHE_NONE. On the CPU side writes through the CPU
169 * cache still need to be flushed, to remain coherent with the display
170 * engine.
171 */
172 I915_CACHE_WT,
173 };
174
175 enum i915_map_type {
176 I915_MAP_WB = 0,
177 I915_MAP_WC,
178 #define I915_MAP_OVERRIDE BIT(31)
179 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
180 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
181 };
182
183 enum i915_mmap_type {
184 I915_MMAP_TYPE_GTT = 0,
185 I915_MMAP_TYPE_WC,
186 I915_MMAP_TYPE_WB,
187 I915_MMAP_TYPE_UC,
188 I915_MMAP_TYPE_FIXED,
189 };
190
191 struct i915_mmap_offset {
192 struct drm_vma_offset_node vma_node;
193 struct drm_i915_gem_object *obj;
194 enum i915_mmap_type mmap_type;
195
196 struct rb_node offset;
197 };
198
199 struct i915_gem_object_page_iter {
200 struct scatterlist *sg_pos;
201 unsigned int sg_idx; /* in pages, but 32bit eek! */
202
203 struct radix_tree_root radix;
204 struct mutex lock; /* protects this cache */
205 };
206
207 struct drm_i915_gem_object {
208 /*
209 * We might have reason to revisit the below since it wastes
210 * a lot of space for non-ttm gem objects.
211 * In any case, always use the accessors for the ttm_buffer_object
212 * when accessing it.
213 */
214 union {
215 struct drm_gem_object base;
216 struct ttm_buffer_object __do_not_access;
217 };
218
219 const struct drm_i915_gem_object_ops *ops;
220
221 struct {
222 /**
223 * @vma.lock: protect the list/tree of vmas
224 */
225 spinlock_t lock;
226
227 /**
228 * @vma.list: List of VMAs backed by this object
229 *
230 * The VMA on this list are ordered by type, all GGTT vma are
231 * placed at the head and all ppGTT vma are placed at the tail.
232 * The different types of GGTT vma are unordered between
233 * themselves, use the @vma.tree (which has a defined order
234 * between all VMA) to quickly find an exact match.
235 */
236 struct list_head list;
237
238 /**
239 * @vma.tree: Ordered tree of VMAs backed by this object
240 *
241 * All VMA created for this object are placed in the @vma.tree
242 * for fast retrieval via a binary search in
243 * i915_vma_instance(). They are also added to @vma.list for
244 * easy iteration.
245 */
246 struct rb_root tree;
247 } vma;
248
249 /**
250 * @lut_list: List of vma lookup entries in use for this object.
251 *
252 * If this object is closed, we need to remove all of its VMA from
253 * the fast lookup index in associated contexts; @lut_list provides
254 * this translation from object to context->handles_vma.
255 */
256 struct list_head lut_list;
257 spinlock_t lut_lock; /* guards lut_list */
258
259 /**
260 * @obj_link: Link into @i915_gem_ww_ctx.obj_list
261 *
262 * When we lock this object through i915_gem_object_lock() with a
263 * context, we add it to the list to ensure we can unlock everything
264 * when i915_gem_ww_ctx_backoff() or i915_gem_ww_ctx_fini() are called.
265 */
266 struct list_head obj_link;
267 /**
268 * @shared_resv_from: The object shares the resv from this vm.
269 */
270 struct i915_address_space *shares_resv_from;
271
272 union {
273 struct rcu_head rcu;
274 struct llist_node freed;
275 };
276
277 /**
278 * Whether the object is currently in the GGTT mmap.
279 */
280 unsigned int userfault_count;
281 struct list_head userfault_link;
282
283 struct {
284 spinlock_t lock; /* Protects access to mmo offsets */
285 struct rb_root offsets;
286 } mmo;
287
288 I915_SELFTEST_DECLARE(struct list_head st_link);
289
290 unsigned long flags;
291 #define I915_BO_ALLOC_CONTIGUOUS BIT(0)
292 #define I915_BO_ALLOC_VOLATILE BIT(1)
293 #define I915_BO_ALLOC_CPU_CLEAR BIT(2)
294 #define I915_BO_ALLOC_USER BIT(3)
295 #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
296 I915_BO_ALLOC_VOLATILE | \
297 I915_BO_ALLOC_CPU_CLEAR | \
298 I915_BO_ALLOC_USER)
299 #define I915_BO_READONLY BIT(4)
300 #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
301 #define I915_BO_WAS_BOUND_BIT 6
302
303 /**
304 * @mem_flags - Mutable placement-related flags
305 *
306 * These are flags that indicate specifics of the memory region
307 * the object is currently in. As such they are only stable
308 * either under the object lock or if the object is pinned.
309 */
310 unsigned int mem_flags;
311 #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
312 #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
313 /**
314 * @cache_level: The desired GTT caching level.
315 *
316 * See enum i915_cache_level for possible values, along with what
317 * each does.
318 */
319 unsigned int cache_level:3;
320 /**
321 * @cache_coherent:
322 *
323 * Track whether the pages are coherent with the GPU if reading or
324 * writing through the CPU caches. The largely depends on the
325 * @cache_level setting.
326 *
327 * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom
328 * platforms, coherency must be explicitly requested with some special
329 * GTT caching bits(see enum i915_cache_level). When enabling coherency
330 * it does come at a performance and power cost on such platforms. On
331 * the flip side the kernel does not need to manually flush any buffers
332 * which need to be coherent with the GPU, if the object is not coherent
333 * i.e @cache_coherent is zero.
334 *
335 * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory
336 * access will automatically snoop the CPU caches(even with CACHE_NONE).
337 * The one exception is when dealing with the display engine, like with
338 * scanout surfaces. To handle this the kernel will always flush the
339 * surface out of the CPU caches when preparing it for scanout. Also
340 * note that since scanout surfaces are only ever read by the display
341 * engine we only need to care about flushing any writes through the CPU
342 * cache, reads on the other hand will always be coherent.
343 *
344 * Something strange here is why @cache_coherent is not a simple
345 * boolean, i.e coherent vs non-coherent. The reasoning for this is back
346 * to the display engine not being fully coherent. As a result scanout
347 * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT.
348 * In the case of seeing I915_CACHE_NONE the kernel makes the assumption
349 * that this is likely a scanout surface, and will set @cache_coherent
350 * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared
351 * LLC. The kernel uses this to always flush writes through the CPU
352 * cache as early as possible, where it can, in effect keeping
353 * @cache_dirty clean, so we can potentially avoid stalling when
354 * flushing the surface just before doing the scanout. This does mean
355 * we might unnecessarily flush non-scanout objects in some places, but
356 * the default assumption is that all normal objects should be using
357 * I915_CACHE_LLC, at least on platforms with the shared LLC.
358 *
359 * Supported values:
360 *
361 * I915_BO_CACHE_COHERENT_FOR_READ:
362 *
363 * On shared LLC platforms, we use this for special scanout surfaces,
364 * where the display engine is not coherent with the CPU cache. As such
365 * we need to ensure we flush any writes before doing the scanout. As an
366 * optimisation we try to flush any writes as early as possible to avoid
367 * stalling later.
368 *
369 * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC
370 * platforms, we use:
371 *
372 * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ
373 *
374 * While for normal objects that are fully coherent, including special
375 * scanout surfaces marked as I915_CACHE_WT, we use:
376 *
377 * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ |
378 * I915_BO_CACHE_COHERENT_FOR_WRITE
379 *
380 * And then for objects that are not coherent at all we use:
381 *
382 * cache_coherent = 0
383 *
384 * I915_BO_CACHE_COHERENT_FOR_WRITE:
385 *
386 * When writing through the CPU cache, the GPU is still coherent. Note
387 * that this also implies I915_BO_CACHE_COHERENT_FOR_READ.
388 */
389 #define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
390 #define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
391 unsigned int cache_coherent:2;
392
393 /**
394 * @cache_dirty:
395 *
396 * Track if we are we dirty with writes through the CPU cache for this
397 * object. As a result reading directly from main memory might yield
398 * stale data.
399 *
400 * This also ties into whether the kernel is tracking the object as
401 * coherent with the GPU, as per @cache_coherent, as it determines if
402 * flushing might be needed at various points.
403 *
404 * Another part of @cache_dirty is managing flushing when first
405 * acquiring the pages for system memory, at this point the pages are
406 * considered foreign, so the default assumption is that the cache is
407 * dirty, for example the page zeroing done by the kernel might leave
408 * writes though the CPU cache, or swapping-in, while the actual data in
409 * main memory is potentially stale. Note that this is a potential
410 * security issue when dealing with userspace objects and zeroing. Now,
411 * whether we actually need apply the big sledgehammer of flushing all
412 * the pages on acquire depends on if @cache_coherent is marked as
413 * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent
414 * for both reads and writes though the CPU cache.
415 *
416 * Note that on shared LLC platforms we still apply the heavy flush for
417 * I915_CACHE_NONE objects, under the assumption that this is going to
418 * be used for scanout.
419 *
420 * Update: On some hardware there is now also the 'Bypass LLC' MOCS
421 * entry, which defeats our @cache_coherent tracking, since userspace
422 * can freely bypass the CPU cache when touching the pages with the GPU,
423 * where the kernel is completely unaware. On such platform we need
424 * apply the sledgehammer-on-acquire regardless of the @cache_coherent.
425 */
426 unsigned int cache_dirty:1;
427
428 /**
429 * @read_domains: Read memory domains.
430 *
431 * These monitor which caches contain read/write data related to the
432 * object. When transitioning from one set of domains to another,
433 * the driver is called to ensure that caches are suitably flushed and
434 * invalidated.
435 */
436 u16 read_domains;
437
438 /**
439 * @write_domain: Corresponding unique write memory domain.
440 */
441 u16 write_domain;
442
443 struct intel_frontbuffer __rcu *frontbuffer;
444
445 /** Current tiling stride for the object, if it's tiled. */
446 unsigned int tiling_and_stride;
447 #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
448 #define TILING_MASK (FENCE_MINIMUM_STRIDE - 1)
449 #define STRIDE_MASK (~TILING_MASK)
450
451 struct {
452 /*
453 * Protects the pages and their use. Do not use directly, but
454 * instead go through the pin/unpin interfaces.
455 */
456 atomic_t pages_pin_count;
457 atomic_t shrink_pin;
458
459 /**
460 * Priority list of potential placements for this object.
461 */
462 struct intel_memory_region **placements;
463 int n_placements;
464
465 /**
466 * Memory region for this object.
467 */
468 struct intel_memory_region *region;
469
470 /**
471 * Memory manager resource allocated for this object. Only
472 * needed for the mock region.
473 */
474 struct ttm_resource *res;
475
476 /**
477 * Element within memory_region->objects or region->purgeable
478 * if the object is marked as DONTNEED. Access is protected by
479 * region->obj_lock.
480 */
481 struct list_head region_link;
482
483 struct sg_table *pages;
484 void *mapping;
485
486 struct i915_page_sizes {
487 /**
488 * The sg mask of the pages sg_table. i.e the mask of
489 * of the lengths for each sg entry.
490 */
491 unsigned int phys;
492
493 /**
494 * The gtt page sizes we are allowed to use given the
495 * sg mask and the supported page sizes. This will
496 * express the smallest unit we can use for the whole
497 * object, as well as the larger sizes we may be able
498 * to use opportunistically.
499 */
500 unsigned int sg;
501
502 /**
503 * The actual gtt page size usage. Since we can have
504 * multiple vma associated with this object we need to
505 * prevent any trampling of state, hence a copy of this
506 * struct also lives in each vma, therefore the gtt
507 * value here should only be read/write through the vma.
508 */
509 unsigned int gtt;
510 } page_sizes;
511
512 I915_SELFTEST_DECLARE(unsigned int page_mask);
513
514 struct i915_gem_object_page_iter get_page;
515 struct i915_gem_object_page_iter get_dma_page;
516
517 /**
518 * Element within i915->mm.unbound_list or i915->mm.bound_list,
519 * locked by i915->mm.obj_lock.
520 */
521 struct list_head link;
522
523 /**
524 * Advice: are the backing pages purgeable?
525 */
526 unsigned int madv:2;
527
528 /**
529 * This is set if the object has been written to since the
530 * pages were last acquired.
531 */
532 bool dirty:1;
533 } mm;
534
535 struct {
536 struct sg_table *cached_io_st;
537 struct i915_gem_object_page_iter get_io_page;
538 bool created:1;
539 } ttm;
540
541 /** Record of address bit 17 of each page at last unbind. */
542 unsigned long *bit_17;
543
544 union {
545 #ifdef CONFIG_MMU_NOTIFIER
546 struct i915_gem_userptr {
547 uintptr_t ptr;
548 unsigned long notifier_seq;
549
550 struct mmu_interval_notifier notifier;
551 struct page **pvec;
552 int page_ref;
553 } userptr;
554 #endif
555
556 struct drm_mm_node *stolen;
557
558 unsigned long scratch;
559 u64 encode;
560
561 void *gvt_info;
562 };
563 };
564
565 static inline struct drm_i915_gem_object *
to_intel_bo(struct drm_gem_object * gem)566 to_intel_bo(struct drm_gem_object *gem)
567 {
568 /* Assert that to_intel_bo(NULL) == NULL */
569 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
570
571 return container_of(gem, struct drm_i915_gem_object, base);
572 }
573
574 #endif
575