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1  /* SPDX-License-Identifier: GPL-2.0+ */
2  /*
3   * TI OMAP4 ISS V4L2 Driver - Register defines
4   *
5   * Copyright (C) 2012 Texas Instruments.
6   *
7   * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>
8   */
9  
10  #ifndef _OMAP4_ISS_REGS_H_
11  #define _OMAP4_ISS_REGS_H_
12  
13  /* ISS */
14  #define ISS_HL_REVISION					0x0
15  
16  #define ISS_HL_SYSCONFIG				0x10
17  #define ISS_HL_SYSCONFIG_IDLEMODE_SHIFT			2
18  #define ISS_HL_SYSCONFIG_IDLEMODE_FORCEIDLE		0x0
19  #define ISS_HL_SYSCONFIG_IDLEMODE_NOIDLE		0x1
20  #define ISS_HL_SYSCONFIG_IDLEMODE_SMARTIDLE		0x2
21  #define ISS_HL_SYSCONFIG_SOFTRESET			BIT(0)
22  
23  #define ISS_HL_IRQSTATUS_RAW(i)				(0x20 + (0x10 * (i)))
24  #define ISS_HL_IRQSTATUS(i)				(0x24 + (0x10 * (i)))
25  #define ISS_HL_IRQENABLE_SET(i)				(0x28 + (0x10 * (i)))
26  #define ISS_HL_IRQENABLE_CLR(i)				(0x2c + (0x10 * (i)))
27  
28  #define ISS_HL_IRQ_HS_VS			BIT(17)
29  #define ISS_HL_IRQ_SIMCOP(i)			BIT(12 + (i))
30  #define ISS_HL_IRQ_BTE				BIT(11)
31  #define ISS_HL_IRQ_CBUFF			BIT(10)
32  #define ISS_HL_IRQ_CCP2(i)			BIT((i) > 3 ? 16 : 14 + (i))
33  #define ISS_HL_IRQ_CSIB				BIT(5)
34  #define ISS_HL_IRQ_CSIA				BIT(4)
35  #define ISS_HL_IRQ_ISP(i)			BIT(i)
36  
37  #define ISS_CTRL					0x80
38  #define ISS_CTRL_CLK_DIV_MASK				(3 << 4)
39  #define ISS_CTRL_INPUT_SEL_MASK				(3 << 2)
40  #define ISS_CTRL_INPUT_SEL_CSI2A			(0 << 2)
41  #define ISS_CTRL_INPUT_SEL_CSI2B			(1 << 2)
42  #define ISS_CTRL_SYNC_DETECT_VS_RAISING			(3 << 0)
43  
44  #define ISS_CLKCTRL					0x84
45  #define ISS_CLKCTRL_VPORT2_CLK				BIT(30)
46  #define ISS_CLKCTRL_VPORT1_CLK				BIT(29)
47  #define ISS_CLKCTRL_VPORT0_CLK				BIT(28)
48  #define ISS_CLKCTRL_CCP2				BIT(4)
49  #define ISS_CLKCTRL_CSI2_B				BIT(3)
50  #define ISS_CLKCTRL_CSI2_A				BIT(2)
51  #define ISS_CLKCTRL_ISP					BIT(1)
52  #define ISS_CLKCTRL_SIMCOP				BIT(0)
53  
54  #define ISS_CLKSTAT					0x88
55  #define ISS_CLKSTAT_VPORT2_CLK				BIT(30)
56  #define ISS_CLKSTAT_VPORT1_CLK				BIT(29)
57  #define ISS_CLKSTAT_VPORT0_CLK				BIT(28)
58  #define ISS_CLKSTAT_CCP2				BIT(4)
59  #define ISS_CLKSTAT_CSI2_B				BIT(3)
60  #define ISS_CLKSTAT_CSI2_A				BIT(2)
61  #define ISS_CLKSTAT_ISP					BIT(1)
62  #define ISS_CLKSTAT_SIMCOP				BIT(0)
63  
64  #define ISS_PM_STATUS					0x8c
65  #define ISS_PM_STATUS_CBUFF_PM_MASK			(3 << 12)
66  #define ISS_PM_STATUS_BTE_PM_MASK			(3 << 10)
67  #define ISS_PM_STATUS_SIMCOP_PM_MASK			(3 << 8)
68  #define ISS_PM_STATUS_ISP_PM_MASK			(3 << 6)
69  #define ISS_PM_STATUS_CCP2_PM_MASK			(3 << 4)
70  #define ISS_PM_STATUS_CSI2_B_PM_MASK			(3 << 2)
71  #define ISS_PM_STATUS_CSI2_A_PM_MASK			(3 << 0)
72  
73  #define REGISTER0					0x0
74  #define REGISTER0_HSCLOCKCONFIG				BIT(24)
75  #define REGISTER0_THS_TERM_MASK				(0xff << 8)
76  #define REGISTER0_THS_TERM_SHIFT			8
77  #define REGISTER0_THS_SETTLE_MASK			(0xff << 0)
78  #define REGISTER0_THS_SETTLE_SHIFT			0
79  
80  #define REGISTER1					0x4
81  #define REGISTER1_RESET_DONE_CTRLCLK			BIT(29)
82  #define REGISTER1_CLOCK_MISS_DETECTOR_STATUS		BIT(25)
83  #define REGISTER1_TCLK_TERM_MASK			(0x3f << 18)
84  #define REGISTER1_TCLK_TERM_SHIFT			18
85  #define REGISTER1_DPHY_HS_SYNC_PATTERN_SHIFT		10
86  #define REGISTER1_CTRLCLK_DIV_FACTOR_MASK		(0x3 << 8)
87  #define REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT		8
88  #define REGISTER1_TCLK_SETTLE_MASK			(0xff << 0)
89  #define REGISTER1_TCLK_SETTLE_SHIFT			0
90  
91  #define REGISTER2					0x8
92  
93  #define CSI2_SYSCONFIG					0x10
94  #define CSI2_SYSCONFIG_MSTANDBY_MODE_MASK		(3 << 12)
95  #define CSI2_SYSCONFIG_MSTANDBY_MODE_FORCE		(0 << 12)
96  #define CSI2_SYSCONFIG_MSTANDBY_MODE_NO			(1 << 12)
97  #define CSI2_SYSCONFIG_MSTANDBY_MODE_SMART		(2 << 12)
98  #define CSI2_SYSCONFIG_SOFT_RESET			(1 << 1)
99  #define CSI2_SYSCONFIG_AUTO_IDLE			(1 << 0)
100  
101  #define CSI2_SYSSTATUS					0x14
102  #define CSI2_SYSSTATUS_RESET_DONE			BIT(0)
103  
104  #define CSI2_IRQSTATUS					0x18
105  #define CSI2_IRQENABLE					0x1c
106  
107  /* Shared bits across CSI2_IRQENABLE and IRQSTATUS */
108  
109  #define CSI2_IRQ_OCP_ERR				BIT(14)
110  #define CSI2_IRQ_SHORT_PACKET				BIT(13)
111  #define CSI2_IRQ_ECC_CORRECTION				BIT(12)
112  #define CSI2_IRQ_ECC_NO_CORRECTION			BIT(11)
113  #define CSI2_IRQ_COMPLEXIO_ERR				BIT(9)
114  #define CSI2_IRQ_FIFO_OVF				BIT(8)
115  #define CSI2_IRQ_CONTEXT0				BIT(0)
116  
117  #define CSI2_CTRL					0x40
118  #define CSI2_CTRL_MFLAG_LEVH_MASK			(7 << 20)
119  #define CSI2_CTRL_MFLAG_LEVH_SHIFT			20
120  #define CSI2_CTRL_MFLAG_LEVL_MASK			(7 << 17)
121  #define CSI2_CTRL_MFLAG_LEVL_SHIFT			17
122  #define CSI2_CTRL_BURST_SIZE_EXPAND			(1 << 16)
123  #define CSI2_CTRL_VP_CLK_EN				(1 << 15)
124  #define CSI2_CTRL_NON_POSTED_WRITE			(1 << 13)
125  #define CSI2_CTRL_VP_ONLY_EN				(1 << 11)
126  #define CSI2_CTRL_VP_OUT_CTRL_MASK			(3 << 8)
127  #define CSI2_CTRL_VP_OUT_CTRL_SHIFT			8
128  #define CSI2_CTRL_DBG_EN				(1 << 7)
129  #define CSI2_CTRL_BURST_SIZE_MASK			(3 << 5)
130  #define CSI2_CTRL_ENDIANNESS				(1 << 4)
131  #define CSI2_CTRL_FRAME					(1 << 3)
132  #define CSI2_CTRL_ECC_EN				(1 << 2)
133  #define CSI2_CTRL_IF_EN					(1 << 0)
134  
135  #define CSI2_DBG_H					0x44
136  
137  #define CSI2_COMPLEXIO_CFG				0x50
138  #define CSI2_COMPLEXIO_CFG_RESET_CTRL			(1 << 30)
139  #define CSI2_COMPLEXIO_CFG_RESET_DONE			(1 << 29)
140  #define CSI2_COMPLEXIO_CFG_PWD_CMD_MASK			(3 << 27)
141  #define CSI2_COMPLEXIO_CFG_PWD_CMD_OFF			(0 << 27)
142  #define CSI2_COMPLEXIO_CFG_PWD_CMD_ON			(1 << 27)
143  #define CSI2_COMPLEXIO_CFG_PWD_CMD_ULP			(2 << 27)
144  #define CSI2_COMPLEXIO_CFG_PWD_STATUS_MASK		(3 << 25)
145  #define CSI2_COMPLEXIO_CFG_PWD_STATUS_OFF		(0 << 25)
146  #define CSI2_COMPLEXIO_CFG_PWD_STATUS_ON		(1 << 25)
147  #define CSI2_COMPLEXIO_CFG_PWD_STATUS_ULP		(2 << 25)
148  #define CSI2_COMPLEXIO_CFG_PWR_AUTO			(1 << 24)
149  #define CSI2_COMPLEXIO_CFG_DATA_POL(i)			(1 << (((i) * 4) + 3))
150  #define CSI2_COMPLEXIO_CFG_DATA_POSITION_MASK(i)	(7 << ((i) * 4))
151  #define CSI2_COMPLEXIO_CFG_DATA_POSITION_SHIFT(i)	((i) * 4)
152  #define CSI2_COMPLEXIO_CFG_CLOCK_POL			(1 << 3)
153  #define CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK		(7 << 0)
154  #define CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT		0
155  
156  #define CSI2_COMPLEXIO_IRQSTATUS			0x54
157  
158  #define CSI2_SHORT_PACKET				0x5c
159  
160  #define CSI2_COMPLEXIO_IRQENABLE			0x60
161  
162  /* Shared bits across CSI2_COMPLEXIO_IRQENABLE and IRQSTATUS */
163  #define CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT		BIT(26)
164  #define CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER		BIT(25)
165  #define CSI2_COMPLEXIO_IRQ_STATEULPM5			BIT(24)
166  #define CSI2_COMPLEXIO_IRQ_STATEULPM4			BIT(23)
167  #define CSI2_COMPLEXIO_IRQ_STATEULPM3			BIT(22)
168  #define CSI2_COMPLEXIO_IRQ_STATEULPM2			BIT(21)
169  #define CSI2_COMPLEXIO_IRQ_STATEULPM1			BIT(20)
170  #define CSI2_COMPLEXIO_IRQ_ERRCONTROL5			BIT(19)
171  #define CSI2_COMPLEXIO_IRQ_ERRCONTROL4			BIT(18)
172  #define CSI2_COMPLEXIO_IRQ_ERRCONTROL3			BIT(17)
173  #define CSI2_COMPLEXIO_IRQ_ERRCONTROL2			BIT(16)
174  #define CSI2_COMPLEXIO_IRQ_ERRCONTROL1			BIT(15)
175  #define CSI2_COMPLEXIO_IRQ_ERRESC5			BIT(14)
176  #define CSI2_COMPLEXIO_IRQ_ERRESC4			BIT(13)
177  #define CSI2_COMPLEXIO_IRQ_ERRESC3			BIT(12)
178  #define CSI2_COMPLEXIO_IRQ_ERRESC2			BIT(11)
179  #define CSI2_COMPLEXIO_IRQ_ERRESC1			BIT(10)
180  #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5		BIT(9)
181  #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4		BIT(8)
182  #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3		BIT(7)
183  #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2		BIT(6)
184  #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1		BIT(5)
185  #define CSI2_COMPLEXIO_IRQ_ERRSOTHS5			BIT(4)
186  #define CSI2_COMPLEXIO_IRQ_ERRSOTHS4			BIT(3)
187  #define CSI2_COMPLEXIO_IRQ_ERRSOTHS3			BIT(2)
188  #define CSI2_COMPLEXIO_IRQ_ERRSOTHS2			BIT(1)
189  #define CSI2_COMPLEXIO_IRQ_ERRSOTHS1			BIT(0)
190  
191  #define CSI2_DBG_P					0x68
192  
193  #define CSI2_TIMING					0x6c
194  #define CSI2_TIMING_FORCE_RX_MODE_IO1			BIT(15)
195  #define CSI2_TIMING_STOP_STATE_X16_IO1			BIT(14)
196  #define CSI2_TIMING_STOP_STATE_X4_IO1			BIT(13)
197  #define CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK		(0x1fff << 0)
198  #define CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT	0
199  
200  #define CSI2_CTX_CTRL1(i)				(0x70 + (0x20 * (i)))
201  #define CSI2_CTX_CTRL1_GENERIC				BIT(30)
202  #define CSI2_CTX_CTRL1_TRANSCODE			(0xf << 24)
203  #define CSI2_CTX_CTRL1_FEC_NUMBER_MASK			(0xff << 16)
204  #define CSI2_CTX_CTRL1_COUNT_MASK			(0xff << 8)
205  #define CSI2_CTX_CTRL1_COUNT_SHIFT			8
206  #define CSI2_CTX_CTRL1_EOF_EN				BIT(7)
207  #define CSI2_CTX_CTRL1_EOL_EN				BIT(6)
208  #define CSI2_CTX_CTRL1_CS_EN				BIT(5)
209  #define CSI2_CTX_CTRL1_COUNT_UNLOCK			BIT(4)
210  #define CSI2_CTX_CTRL1_PING_PONG			BIT(3)
211  #define CSI2_CTX_CTRL1_CTX_EN				BIT(0)
212  
213  #define CSI2_CTX_CTRL2(i)				(0x74 + (0x20 * (i)))
214  #define CSI2_CTX_CTRL2_FRAME_MASK			(0xffff << 16)
215  #define CSI2_CTX_CTRL2_FRAME_SHIFT			16
216  #define CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT		13
217  #define CSI2_CTX_CTRL2_USER_DEF_MAP_MASK		\
218  		(0x3 << CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT)
219  #define CSI2_CTX_CTRL2_VIRTUAL_ID_MASK			(3 << 11)
220  #define CSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT			11
221  #define CSI2_CTX_CTRL2_DPCM_PRED			(1 << 10)
222  #define CSI2_CTX_CTRL2_FORMAT_MASK			(0x3ff << 0)
223  #define CSI2_CTX_CTRL2_FORMAT_SHIFT			0
224  
225  #define CSI2_CTX_DAT_OFST(i)				(0x78 + (0x20 * (i)))
226  #define CSI2_CTX_DAT_OFST_MASK				(0xfff << 5)
227  
228  #define CSI2_CTX_PING_ADDR(i)				(0x7c + (0x20 * (i)))
229  #define CSI2_CTX_PING_ADDR_MASK				0xffffffe0
230  
231  #define CSI2_CTX_PONG_ADDR(i)				(0x80 + (0x20 * (i)))
232  #define CSI2_CTX_PONG_ADDR_MASK				CSI2_CTX_PING_ADDR_MASK
233  
234  #define CSI2_CTX_IRQENABLE(i)				(0x84 + (0x20 * (i)))
235  #define CSI2_CTX_IRQSTATUS(i)				(0x88 + (0x20 * (i)))
236  
237  #define CSI2_CTX_CTRL3(i)				(0x8c + (0x20 * (i)))
238  #define CSI2_CTX_CTRL3_ALPHA_SHIFT			5
239  #define CSI2_CTX_CTRL3_ALPHA_MASK			\
240  		(0x3fff << CSI2_CTX_CTRL3_ALPHA_SHIFT)
241  
242  /* Shared bits across CSI2_CTX_IRQENABLE and IRQSTATUS */
243  #define CSI2_CTX_IRQ_ECC_CORRECTION			BIT(8)
244  #define CSI2_CTX_IRQ_LINE_NUMBER			BIT(7)
245  #define CSI2_CTX_IRQ_FRAME_NUMBER			BIT(6)
246  #define CSI2_CTX_IRQ_CS					BIT(5)
247  #define CSI2_CTX_IRQ_LE					BIT(3)
248  #define CSI2_CTX_IRQ_LS					BIT(2)
249  #define CSI2_CTX_IRQ_FE					BIT(1)
250  #define CSI2_CTX_IRQ_FS					BIT(0)
251  
252  /* ISS BTE */
253  #define BTE_CTRL					(0x0030)
254  #define BTE_CTRL_BW_LIMITER_MASK			(0x3ff << 22)
255  #define BTE_CTRL_BW_LIMITER_SHIFT			22
256  
257  /* ISS ISP_SYS1 */
258  #define ISP5_REVISION					(0x0000)
259  #define ISP5_SYSCONFIG					(0x0010)
260  #define ISP5_SYSCONFIG_STANDBYMODE_MASK			(3 << 4)
261  #define ISP5_SYSCONFIG_STANDBYMODE_FORCE		(0 << 4)
262  #define ISP5_SYSCONFIG_STANDBYMODE_NO			(1 << 4)
263  #define ISP5_SYSCONFIG_STANDBYMODE_SMART		(2 << 4)
264  #define ISP5_SYSCONFIG_SOFTRESET			(1 << 1)
265  
266  #define ISP5_IRQSTATUS(i)				(0x0028 + (0x10 * (i)))
267  #define ISP5_IRQENABLE_SET(i)				(0x002c + (0x10 * (i)))
268  #define ISP5_IRQENABLE_CLR(i)				(0x0030 + (0x10 * (i)))
269  
270  /* Bits shared for ISP5_IRQ* registers */
271  #define ISP5_IRQ_OCP_ERR				BIT(31)
272  #define ISP5_IRQ_IPIPE_INT_DPC_RNEW1			BIT(29)
273  #define ISP5_IRQ_IPIPE_INT_DPC_RNEW0			BIT(28)
274  #define ISP5_IRQ_IPIPE_INT_DPC_INIT			BIT(27)
275  #define ISP5_IRQ_IPIPE_INT_EOF				BIT(25)
276  #define ISP5_IRQ_H3A_INT_EOF				BIT(24)
277  #define ISP5_IRQ_RSZ_INT_EOF1				BIT(23)
278  #define ISP5_IRQ_RSZ_INT_EOF0				BIT(22)
279  #define ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR			BIT(19)
280  #define ISP5_IRQ_RSZ_FIFO_OVF				BIT(18)
281  #define ISP5_IRQ_RSZ_INT_CYC_RSZB			BIT(17)
282  #define ISP5_IRQ_RSZ_INT_CYC_RSZA			BIT(16)
283  #define ISP5_IRQ_RSZ_INT_DMA				BIT(15)
284  #define ISP5_IRQ_RSZ_INT_LAST_PIX			BIT(14)
285  #define ISP5_IRQ_RSZ_INT_REG				BIT(13)
286  #define ISP5_IRQ_H3A_INT				BIT(12)
287  #define ISP5_IRQ_AF_INT					BIT(11)
288  #define ISP5_IRQ_AEW_INT				BIT(10)
289  #define ISP5_IRQ_IPIPEIF_IRQ				BIT(9)
290  #define ISP5_IRQ_IPIPE_INT_HST				BIT(8)
291  #define ISP5_IRQ_IPIPE_INT_BSC				BIT(7)
292  #define ISP5_IRQ_IPIPE_INT_DMA				BIT(6)
293  #define ISP5_IRQ_IPIPE_INT_LAST_PIX			BIT(5)
294  #define ISP5_IRQ_IPIPE_INT_REG				BIT(4)
295  #define ISP5_IRQ_ISIF_INT(i)				BIT(i)
296  
297  #define ISP5_CTRL					(0x006c)
298  #define ISP5_CTRL_MSTANDBY				BIT(24)
299  #define ISP5_CTRL_VD_PULSE_EXT				BIT(23)
300  #define ISP5_CTRL_MSTANDBY_WAIT				BIT(20)
301  #define ISP5_CTRL_BL_CLK_ENABLE				BIT(15)
302  #define ISP5_CTRL_ISIF_CLK_ENABLE			BIT(14)
303  #define ISP5_CTRL_H3A_CLK_ENABLE			BIT(13)
304  #define ISP5_CTRL_RSZ_CLK_ENABLE			BIT(12)
305  #define ISP5_CTRL_IPIPE_CLK_ENABLE			BIT(11)
306  #define ISP5_CTRL_IPIPEIF_CLK_ENABLE			BIT(10)
307  #define ISP5_CTRL_SYNC_ENABLE				BIT(9)
308  #define ISP5_CTRL_PSYNC_CLK_SEL				BIT(8)
309  
310  /* ISS ISP ISIF register offsets */
311  #define ISIF_SYNCEN					(0x0000)
312  #define ISIF_SYNCEN_DWEN				BIT(1)
313  #define ISIF_SYNCEN_SYEN				BIT(0)
314  
315  #define ISIF_MODESET					(0x0004)
316  #define ISIF_MODESET_INPMOD_MASK			(3 << 12)
317  #define ISIF_MODESET_INPMOD_RAW				(0 << 12)
318  #define ISIF_MODESET_INPMOD_YCBCR16			(1 << 12)
319  #define ISIF_MODESET_INPMOD_YCBCR8			(2 << 12)
320  #define ISIF_MODESET_CCDW_MASK				(7 << 8)
321  #define ISIF_MODESET_CCDW_2BIT				(2 << 8)
322  #define ISIF_MODESET_CCDMD				(1 << 7)
323  #define ISIF_MODESET_SWEN				(1 << 5)
324  #define ISIF_MODESET_HDPOL				(1 << 3)
325  #define ISIF_MODESET_VDPOL				(1 << 2)
326  
327  #define ISIF_SPH					(0x0018)
328  #define ISIF_SPH_MASK					(0x7fff)
329  
330  #define ISIF_LNH					(0x001c)
331  #define ISIF_LNH_MASK					(0x7fff)
332  
333  #define ISIF_LNV					(0x0028)
334  #define ISIF_LNV_MASK					(0x7fff)
335  
336  #define ISIF_HSIZE					(0x0034)
337  #define ISIF_HSIZE_ADCR					BIT(12)
338  #define ISIF_HSIZE_HSIZE_MASK				(0xfff)
339  
340  #define ISIF_CADU					(0x003c)
341  #define ISIF_CADU_MASK					(0x7ff)
342  
343  #define ISIF_CADL					(0x0040)
344  #define ISIF_CADL_MASK					(0xffff)
345  
346  #define ISIF_CCOLP					(0x004c)
347  #define ISIF_CCOLP_CP0_F0_R				(0 << 6)
348  #define ISIF_CCOLP_CP0_F0_GR				(1 << 6)
349  #define ISIF_CCOLP_CP0_F0_B				(3 << 6)
350  #define ISIF_CCOLP_CP0_F0_GB				(2 << 6)
351  #define ISIF_CCOLP_CP1_F0_R				(0 << 4)
352  #define ISIF_CCOLP_CP1_F0_GR				(1 << 4)
353  #define ISIF_CCOLP_CP1_F0_B				(3 << 4)
354  #define ISIF_CCOLP_CP1_F0_GB				(2 << 4)
355  #define ISIF_CCOLP_CP2_F0_R				(0 << 2)
356  #define ISIF_CCOLP_CP2_F0_GR				(1 << 2)
357  #define ISIF_CCOLP_CP2_F0_B				(3 << 2)
358  #define ISIF_CCOLP_CP2_F0_GB				(2 << 2)
359  #define ISIF_CCOLP_CP3_F0_R				(0 << 0)
360  #define ISIF_CCOLP_CP3_F0_GR				(1 << 0)
361  #define ISIF_CCOLP_CP3_F0_B				(3 << 0)
362  #define ISIF_CCOLP_CP3_F0_GB				(2 << 0)
363  
364  #define ISIF_VDINT(i)					(0x0070 + (i) * 4)
365  #define ISIF_VDINT_MASK					(0x7fff)
366  
367  #define ISIF_CGAMMAWD					(0x0080)
368  #define ISIF_CGAMMAWD_GWDI_MASK				(0xf << 1)
369  #define ISIF_CGAMMAWD_GWDI(bpp)				((16 - (bpp)) << 1)
370  
371  #define ISIF_CCDCFG					(0x0088)
372  #define ISIF_CCDCFG_Y8POS				BIT(11)
373  
374  /* ISS ISP IPIPEIF register offsets */
375  #define IPIPEIF_ENABLE					(0x0000)
376  
377  #define IPIPEIF_CFG1					(0x0004)
378  #define IPIPEIF_CFG1_INPSRC1_MASK			(3 << 14)
379  #define IPIPEIF_CFG1_INPSRC1_VPORT_RAW			(0 << 14)
380  #define IPIPEIF_CFG1_INPSRC1_SDRAM_RAW			(1 << 14)
381  #define IPIPEIF_CFG1_INPSRC1_ISIF_DARKFM		(2 << 14)
382  #define IPIPEIF_CFG1_INPSRC1_SDRAM_YUV			(3 << 14)
383  #define IPIPEIF_CFG1_INPSRC2_MASK			(3 << 2)
384  #define IPIPEIF_CFG1_INPSRC2_ISIF			(0 << 2)
385  #define IPIPEIF_CFG1_INPSRC2_SDRAM_RAW			(1 << 2)
386  #define IPIPEIF_CFG1_INPSRC2_ISIF_DARKFM		(2 << 2)
387  #define IPIPEIF_CFG1_INPSRC2_SDRAM_YUV			(3 << 2)
388  
389  #define IPIPEIF_CFG2					(0x0030)
390  #define IPIPEIF_CFG2_YUV8P				BIT(7)
391  #define IPIPEIF_CFG2_YUV8				BIT(6)
392  #define IPIPEIF_CFG2_YUV16				BIT(3)
393  #define IPIPEIF_CFG2_VDPOL				BIT(2)
394  #define IPIPEIF_CFG2_HDPOL				BIT(1)
395  #define IPIPEIF_CFG2_INTSW				BIT(0)
396  
397  #define IPIPEIF_CLKDIV					(0x0040)
398  
399  /* ISS ISP IPIPE register offsets */
400  #define IPIPE_SRC_EN					(0x0000)
401  #define IPIPE_SRC_EN_EN					BIT(0)
402  
403  #define IPIPE_SRC_MODE					(0x0004)
404  #define IPIPE_SRC_MODE_WRT				BIT(1)
405  #define IPIPE_SRC_MODE_OST				BIT(0)
406  
407  #define IPIPE_SRC_FMT					(0x0008)
408  #define IPIPE_SRC_FMT_RAW2YUV				(0 << 0)
409  #define IPIPE_SRC_FMT_RAW2RAW				(1 << 0)
410  #define IPIPE_SRC_FMT_RAW2STATS				(2 << 0)
411  #define IPIPE_SRC_FMT_YUV2YUV				(3 << 0)
412  
413  #define IPIPE_SRC_COL					(0x000c)
414  #define IPIPE_SRC_COL_OO_R				(0 << 6)
415  #define IPIPE_SRC_COL_OO_GR				(1 << 6)
416  #define IPIPE_SRC_COL_OO_B				(3 << 6)
417  #define IPIPE_SRC_COL_OO_GB				(2 << 6)
418  #define IPIPE_SRC_COL_OE_R				(0 << 4)
419  #define IPIPE_SRC_COL_OE_GR				(1 << 4)
420  #define IPIPE_SRC_COL_OE_B				(3 << 4)
421  #define IPIPE_SRC_COL_OE_GB				(2 << 4)
422  #define IPIPE_SRC_COL_EO_R				(0 << 2)
423  #define IPIPE_SRC_COL_EO_GR				(1 << 2)
424  #define IPIPE_SRC_COL_EO_B				(3 << 2)
425  #define IPIPE_SRC_COL_EO_GB				(2 << 2)
426  #define IPIPE_SRC_COL_EE_R				(0 << 0)
427  #define IPIPE_SRC_COL_EE_GR				(1 << 0)
428  #define IPIPE_SRC_COL_EE_B				(3 << 0)
429  #define IPIPE_SRC_COL_EE_GB				(2 << 0)
430  
431  #define IPIPE_SRC_VPS					(0x0010)
432  #define IPIPE_SRC_VPS_MASK				(0xffff)
433  
434  #define IPIPE_SRC_VSZ					(0x0014)
435  #define IPIPE_SRC_VSZ_MASK				(0x1fff)
436  
437  #define IPIPE_SRC_HPS					(0x0018)
438  #define IPIPE_SRC_HPS_MASK				(0xffff)
439  
440  #define IPIPE_SRC_HSZ					(0x001c)
441  #define IPIPE_SRC_HSZ_MASK				(0x1ffe)
442  
443  #define IPIPE_SEL_SBU					(0x0020)
444  
445  #define IPIPE_SRC_STA					(0x0024)
446  
447  #define IPIPE_GCK_MMR					(0x0028)
448  #define IPIPE_GCK_MMR_REG				BIT(0)
449  
450  #define IPIPE_GCK_PIX					(0x002c)
451  #define IPIPE_GCK_PIX_G3				BIT(3)
452  #define IPIPE_GCK_PIX_G2				BIT(2)
453  #define IPIPE_GCK_PIX_G1				BIT(1)
454  #define IPIPE_GCK_PIX_G0				BIT(0)
455  
456  #define IPIPE_DPC_LUT_EN				(0x0034)
457  #define IPIPE_DPC_LUT_SEL				(0x0038)
458  #define IPIPE_DPC_LUT_ADR				(0x003c)
459  #define IPIPE_DPC_LUT_SIZ				(0x0040)
460  
461  #define IPIPE_DPC_OTF_EN				(0x0044)
462  #define IPIPE_DPC_OTF_TYP				(0x0048)
463  #define IPIPE_DPC_OTF_2_D_THR_R				(0x004c)
464  #define IPIPE_DPC_OTF_2_D_THR_GR			(0x0050)
465  #define IPIPE_DPC_OTF_2_D_THR_GB			(0x0054)
466  #define IPIPE_DPC_OTF_2_D_THR_B				(0x0058)
467  #define IPIPE_DPC_OTF_2_C_THR_R				(0x005c)
468  #define IPIPE_DPC_OTF_2_C_THR_GR			(0x0060)
469  #define IPIPE_DPC_OTF_2_C_THR_GB			(0x0064)
470  #define IPIPE_DPC_OTF_2_C_THR_B				(0x0068)
471  #define IPIPE_DPC_OTF_3_SHF				(0x006c)
472  #define IPIPE_DPC_OTF_3_D_THR				(0x0070)
473  #define IPIPE_DPC_OTF_3_D_SPL				(0x0074)
474  #define IPIPE_DPC_OTF_3_D_MIN				(0x0078)
475  #define IPIPE_DPC_OTF_3_D_MAX				(0x007c)
476  #define IPIPE_DPC_OTF_3_C_THR				(0x0080)
477  #define IPIPE_DPC_OTF_3_C_SLP				(0x0084)
478  #define IPIPE_DPC_OTF_3_C_MIN				(0x0088)
479  #define IPIPE_DPC_OTF_3_C_MAX				(0x008c)
480  
481  #define IPIPE_LSC_VOFT					(0x0090)
482  #define IPIPE_LSC_VA2					(0x0094)
483  #define IPIPE_LSC_VA1					(0x0098)
484  #define IPIPE_LSC_VS					(0x009c)
485  #define IPIPE_LSC_HOFT					(0x00a0)
486  #define IPIPE_LSC_HA2					(0x00a4)
487  #define IPIPE_LSC_HA1					(0x00a8)
488  #define IPIPE_LSC_HS					(0x00ac)
489  #define IPIPE_LSC_GAN_R					(0x00b0)
490  #define IPIPE_LSC_GAN_GR				(0x00b4)
491  #define IPIPE_LSC_GAN_GB				(0x00b8)
492  #define IPIPE_LSC_GAN_B					(0x00bc)
493  #define IPIPE_LSC_OFT_R					(0x00c0)
494  #define IPIPE_LSC_OFT_GR				(0x00c4)
495  #define IPIPE_LSC_OFT_GB				(0x00c8)
496  #define IPIPE_LSC_OFT_B					(0x00cc)
497  #define IPIPE_LSC_SHF					(0x00d0)
498  #define IPIPE_LSC_MAX					(0x00d4)
499  
500  #define IPIPE_D2F_1ST_EN				(0x00d8)
501  #define IPIPE_D2F_1ST_TYP				(0x00dc)
502  #define IPIPE_D2F_1ST_THR_00				(0x00e0)
503  #define IPIPE_D2F_1ST_THR_01				(0x00e4)
504  #define IPIPE_D2F_1ST_THR_02				(0x00e8)
505  #define IPIPE_D2F_1ST_THR_03				(0x00ec)
506  #define IPIPE_D2F_1ST_THR_04				(0x00f0)
507  #define IPIPE_D2F_1ST_THR_05				(0x00f4)
508  #define IPIPE_D2F_1ST_THR_06				(0x00f8)
509  #define IPIPE_D2F_1ST_THR_07				(0x00fc)
510  #define IPIPE_D2F_1ST_STR_00				(0x0100)
511  #define IPIPE_D2F_1ST_STR_01				(0x0104)
512  #define IPIPE_D2F_1ST_STR_02				(0x0108)
513  #define IPIPE_D2F_1ST_STR_03				(0x010c)
514  #define IPIPE_D2F_1ST_STR_04				(0x0110)
515  #define IPIPE_D2F_1ST_STR_05				(0x0114)
516  #define IPIPE_D2F_1ST_STR_06				(0x0118)
517  #define IPIPE_D2F_1ST_STR_07				(0x011c)
518  #define IPIPE_D2F_1ST_SPR_00				(0x0120)
519  #define IPIPE_D2F_1ST_SPR_01				(0x0124)
520  #define IPIPE_D2F_1ST_SPR_02				(0x0128)
521  #define IPIPE_D2F_1ST_SPR_03				(0x012c)
522  #define IPIPE_D2F_1ST_SPR_04				(0x0130)
523  #define IPIPE_D2F_1ST_SPR_05				(0x0134)
524  #define IPIPE_D2F_1ST_SPR_06				(0x0138)
525  #define IPIPE_D2F_1ST_SPR_07				(0x013c)
526  #define IPIPE_D2F_1ST_EDG_MIN				(0x0140)
527  #define IPIPE_D2F_1ST_EDG_MAX				(0x0144)
528  #define IPIPE_D2F_2ND_EN				(0x0148)
529  #define IPIPE_D2F_2ND_TYP				(0x014c)
530  #define IPIPE_D2F_2ND_THR00				(0x0150)
531  #define IPIPE_D2F_2ND_THR01				(0x0154)
532  #define IPIPE_D2F_2ND_THR02				(0x0158)
533  #define IPIPE_D2F_2ND_THR03				(0x015c)
534  #define IPIPE_D2F_2ND_THR04				(0x0160)
535  #define IPIPE_D2F_2ND_THR05				(0x0164)
536  #define IPIPE_D2F_2ND_THR06				(0x0168)
537  #define IPIPE_D2F_2ND_THR07				(0x016c)
538  #define IPIPE_D2F_2ND_STR_00				(0x0170)
539  #define IPIPE_D2F_2ND_STR_01				(0x0174)
540  #define IPIPE_D2F_2ND_STR_02				(0x0178)
541  #define IPIPE_D2F_2ND_STR_03				(0x017c)
542  #define IPIPE_D2F_2ND_STR_04				(0x0180)
543  #define IPIPE_D2F_2ND_STR_05				(0x0184)
544  #define IPIPE_D2F_2ND_STR_06				(0x0188)
545  #define IPIPE_D2F_2ND_STR_07				(0x018c)
546  #define IPIPE_D2F_2ND_SPR_00				(0x0190)
547  #define IPIPE_D2F_2ND_SPR_01				(0x0194)
548  #define IPIPE_D2F_2ND_SPR_02				(0x0198)
549  #define IPIPE_D2F_2ND_SPR_03				(0x019c)
550  #define IPIPE_D2F_2ND_SPR_04				(0x01a0)
551  #define IPIPE_D2F_2ND_SPR_05				(0x01a4)
552  #define IPIPE_D2F_2ND_SPR_06				(0x01a8)
553  #define IPIPE_D2F_2ND_SPR_07				(0x01ac)
554  #define IPIPE_D2F_2ND_EDG_MIN				(0x01b0)
555  #define IPIPE_D2F_2ND_EDG_MAX				(0x01b4)
556  
557  #define IPIPE_GIC_EN					(0x01b8)
558  #define IPIPE_GIC_TYP					(0x01bc)
559  #define IPIPE_GIC_GAN					(0x01c0)
560  #define IPIPE_GIC_NFGAIN				(0x01c4)
561  #define IPIPE_GIC_THR					(0x01c8)
562  #define IPIPE_GIC_SLP					(0x01cc)
563  
564  #define IPIPE_WB2_OFT_R					(0x01d0)
565  #define IPIPE_WB2_OFT_GR				(0x01d4)
566  #define IPIPE_WB2_OFT_GB				(0x01d8)
567  #define IPIPE_WB2_OFT_B					(0x01dc)
568  
569  #define IPIPE_WB2_WGN_R					(0x01e0)
570  #define IPIPE_WB2_WGN_GR				(0x01e4)
571  #define IPIPE_WB2_WGN_GB				(0x01e8)
572  #define IPIPE_WB2_WGN_B					(0x01ec)
573  
574  #define IPIPE_CFA_MODE					(0x01f0)
575  #define IPIPE_CFA_2DIR_HPF_THR				(0x01f4)
576  #define IPIPE_CFA_2DIR_HPF_SLP				(0x01f8)
577  #define IPIPE_CFA_2DIR_MIX_THR				(0x01fc)
578  #define IPIPE_CFA_2DIR_MIX_SLP				(0x0200)
579  #define IPIPE_CFA_2DIR_DIR_TRH				(0x0204)
580  #define IPIPE_CFA_2DIR_DIR_SLP				(0x0208)
581  #define IPIPE_CFA_2DIR_NDWT				(0x020c)
582  #define IPIPE_CFA_MONO_HUE_FRA				(0x0210)
583  #define IPIPE_CFA_MONO_EDG_THR				(0x0214)
584  #define IPIPE_CFA_MONO_THR_MIN				(0x0218)
585  
586  #define IPIPE_CFA_MONO_THR_SLP				(0x021c)
587  #define IPIPE_CFA_MONO_SLP_MIN				(0x0220)
588  #define IPIPE_CFA_MONO_SLP_SLP				(0x0224)
589  #define IPIPE_CFA_MONO_LPWT				(0x0228)
590  
591  #define IPIPE_RGB1_MUL_RR				(0x022c)
592  #define IPIPE_RGB1_MUL_GR				(0x0230)
593  #define IPIPE_RGB1_MUL_BR				(0x0234)
594  #define IPIPE_RGB1_MUL_RG				(0x0238)
595  #define IPIPE_RGB1_MUL_GG				(0x023c)
596  #define IPIPE_RGB1_MUL_BG				(0x0240)
597  #define IPIPE_RGB1_MUL_RB				(0x0244)
598  #define IPIPE_RGB1_MUL_GB				(0x0248)
599  #define IPIPE_RGB1_MUL_BB				(0x024c)
600  #define IPIPE_RGB1_OFT_OR				(0x0250)
601  #define IPIPE_RGB1_OFT_OG				(0x0254)
602  #define IPIPE_RGB1_OFT_OB				(0x0258)
603  #define IPIPE_GMM_CFG					(0x025c)
604  #define IPIPE_RGB2_MUL_RR				(0x0260)
605  #define IPIPE_RGB2_MUL_GR				(0x0264)
606  #define IPIPE_RGB2_MUL_BR				(0x0268)
607  #define IPIPE_RGB2_MUL_RG				(0x026c)
608  #define IPIPE_RGB2_MUL_GG				(0x0270)
609  #define IPIPE_RGB2_MUL_BG				(0x0274)
610  #define IPIPE_RGB2_MUL_RB				(0x0278)
611  #define IPIPE_RGB2_MUL_GB				(0x027c)
612  #define IPIPE_RGB2_MUL_BB				(0x0280)
613  #define IPIPE_RGB2_OFT_OR				(0x0284)
614  #define IPIPE_RGB2_OFT_OG				(0x0288)
615  #define IPIPE_RGB2_OFT_OB				(0x028c)
616  
617  #define IPIPE_YUV_ADJ					(0x0294)
618  #define IPIPE_YUV_MUL_RY				(0x0298)
619  #define IPIPE_YUV_MUL_GY				(0x029c)
620  #define IPIPE_YUV_MUL_BY				(0x02a0)
621  #define IPIPE_YUV_MUL_RCB				(0x02a4)
622  #define IPIPE_YUV_MUL_GCB				(0x02a8)
623  #define IPIPE_YUV_MUL_BCB				(0x02ac)
624  #define IPIPE_YUV_MUL_RCR				(0x02b0)
625  #define IPIPE_YUV_MUL_GCR				(0x02b4)
626  #define IPIPE_YUV_MUL_BCR				(0x02b8)
627  #define IPIPE_YUV_OFT_Y					(0x02bc)
628  #define IPIPE_YUV_OFT_CB				(0x02c0)
629  #define IPIPE_YUV_OFT_CR				(0x02c4)
630  
631  #define IPIPE_YUV_PHS					(0x02c8)
632  #define IPIPE_YUV_PHS_LPF				BIT(1)
633  #define IPIPE_YUV_PHS_POS				BIT(0)
634  
635  #define IPIPE_YEE_EN					(0x02d4)
636  #define IPIPE_YEE_TYP					(0x02d8)
637  #define IPIPE_YEE_SHF					(0x02dc)
638  #define IPIPE_YEE_MUL_00				(0x02e0)
639  #define IPIPE_YEE_MUL_01				(0x02e4)
640  #define IPIPE_YEE_MUL_02				(0x02e8)
641  #define IPIPE_YEE_MUL_10				(0x02ec)
642  #define IPIPE_YEE_MUL_11				(0x02f0)
643  #define IPIPE_YEE_MUL_12				(0x02f4)
644  #define IPIPE_YEE_MUL_20				(0x02f8)
645  #define IPIPE_YEE_MUL_21				(0x02fc)
646  #define IPIPE_YEE_MUL_22				(0x0300)
647  #define IPIPE_YEE_THR					(0x0304)
648  #define IPIPE_YEE_E_GAN					(0x0308)
649  #define IPIPE_YEE_E_THR_1				(0x030c)
650  #define IPIPE_YEE_E_THR_2				(0x0310)
651  #define IPIPE_YEE_G_GAN					(0x0314)
652  #define IPIPE_YEE_G_OFT					(0x0318)
653  
654  #define IPIPE_CAR_EN					(0x031c)
655  #define IPIPE_CAR_TYP					(0x0320)
656  #define IPIPE_CAR_SW					(0x0324)
657  #define IPIPE_CAR_HPF_TYP				(0x0328)
658  #define IPIPE_CAR_HPF_SHF				(0x032c)
659  #define IPIPE_CAR_HPF_THR				(0x0330)
660  #define IPIPE_CAR_GN1_GAN				(0x0334)
661  #define IPIPE_CAR_GN1_SHF				(0x0338)
662  #define IPIPE_CAR_GN1_MIN				(0x033c)
663  #define IPIPE_CAR_GN2_GAN				(0x0340)
664  #define IPIPE_CAR_GN2_SHF				(0x0344)
665  #define IPIPE_CAR_GN2_MIN				(0x0348)
666  #define IPIPE_CGS_EN					(0x034c)
667  #define IPIPE_CGS_GN1_L_THR				(0x0350)
668  #define IPIPE_CGS_GN1_L_GAIN				(0x0354)
669  #define IPIPE_CGS_GN1_L_SHF				(0x0358)
670  #define IPIPE_CGS_GN1_L_MIN				(0x035c)
671  #define IPIPE_CGS_GN1_H_THR				(0x0360)
672  #define IPIPE_CGS_GN1_H_GAIN				(0x0364)
673  #define IPIPE_CGS_GN1_H_SHF				(0x0368)
674  #define IPIPE_CGS_GN1_H_MIN				(0x036c)
675  #define IPIPE_CGS_GN2_L_THR				(0x0370)
676  #define IPIPE_CGS_GN2_L_GAIN				(0x0374)
677  #define IPIPE_CGS_GN2_L_SHF				(0x0378)
678  #define IPIPE_CGS_GN2_L_MIN				(0x037c)
679  
680  #define IPIPE_BOX_EN					(0x0380)
681  #define IPIPE_BOX_MODE					(0x0384)
682  #define IPIPE_BOX_TYP					(0x0388)
683  #define IPIPE_BOX_SHF					(0x038c)
684  #define IPIPE_BOX_SDR_SAD_H				(0x0390)
685  #define IPIPE_BOX_SDR_SAD_L				(0x0394)
686  
687  #define IPIPE_HST_EN					(0x039c)
688  #define IPIPE_HST_MODE					(0x03a0)
689  #define IPIPE_HST_SEL					(0x03a4)
690  #define IPIPE_HST_PARA					(0x03a8)
691  #define IPIPE_HST_0_VPS					(0x03ac)
692  #define IPIPE_HST_0_VSZ					(0x03b0)
693  #define IPIPE_HST_0_HPS					(0x03b4)
694  #define IPIPE_HST_0_HSZ					(0x03b8)
695  #define IPIPE_HST_1_VPS					(0x03bc)
696  #define IPIPE_HST_1_VSZ					(0x03c0)
697  #define IPIPE_HST_1_HPS					(0x03c4)
698  #define IPIPE_HST_1_HSZ					(0x03c8)
699  #define IPIPE_HST_2_VPS					(0x03cc)
700  #define IPIPE_HST_2_VSZ					(0x03d0)
701  #define IPIPE_HST_2_HPS					(0x03d4)
702  #define IPIPE_HST_2_HSZ					(0x03d8)
703  #define IPIPE_HST_3_VPS					(0x03dc)
704  #define IPIPE_HST_3_VSZ					(0x03e0)
705  #define IPIPE_HST_3_HPS					(0x03e4)
706  #define IPIPE_HST_3_HSZ					(0x03e8)
707  #define IPIPE_HST_TBL					(0x03ec)
708  #define IPIPE_HST_MUL_R					(0x03f0)
709  #define IPIPE_HST_MUL_GR				(0x03f4)
710  #define IPIPE_HST_MUL_GB				(0x03f8)
711  #define IPIPE_HST_MUL_B					(0x03fc)
712  
713  #define IPIPE_BSC_EN					(0x0400)
714  #define IPIPE_BSC_MODE					(0x0404)
715  #define IPIPE_BSC_TYP					(0x0408)
716  #define IPIPE_BSC_ROW_VCT				(0x040c)
717  #define IPIPE_BSC_ROW_SHF				(0x0410)
718  #define IPIPE_BSC_ROW_VPO				(0x0414)
719  #define IPIPE_BSC_ROW_VNU				(0x0418)
720  #define IPIPE_BSC_ROW_VSKIP				(0x041c)
721  #define IPIPE_BSC_ROW_HPO				(0x0420)
722  #define IPIPE_BSC_ROW_HNU				(0x0424)
723  #define IPIPE_BSC_ROW_HSKIP				(0x0428)
724  #define IPIPE_BSC_COL_VCT				(0x042c)
725  #define IPIPE_BSC_COL_SHF				(0x0430)
726  #define IPIPE_BSC_COL_VPO				(0x0434)
727  #define IPIPE_BSC_COL_VNU				(0x0438)
728  #define IPIPE_BSC_COL_VSKIP				(0x043c)
729  #define IPIPE_BSC_COL_HPO				(0x0440)
730  #define IPIPE_BSC_COL_HNU				(0x0444)
731  #define IPIPE_BSC_COL_HSKIP				(0x0448)
732  
733  #define IPIPE_BSC_EN					(0x0400)
734  
735  /* ISS ISP Resizer register offsets */
736  #define RSZ_REVISION					(0x0000)
737  #define RSZ_SYSCONFIG					(0x0004)
738  #define RSZ_SYSCONFIG_RSZB_CLK_EN			BIT(9)
739  #define RSZ_SYSCONFIG_RSZA_CLK_EN			BIT(8)
740  
741  #define RSZ_IN_FIFO_CTRL				(0x000c)
742  #define RSZ_IN_FIFO_CTRL_THRLD_LOW_MASK			(0x1ff << 16)
743  #define RSZ_IN_FIFO_CTRL_THRLD_LOW_SHIFT		16
744  #define RSZ_IN_FIFO_CTRL_THRLD_HIGH_MASK		(0x1ff << 0)
745  #define RSZ_IN_FIFO_CTRL_THRLD_HIGH_SHIFT		0
746  
747  #define RSZ_FRACDIV					(0x0008)
748  #define RSZ_FRACDIV_MASK				(0xffff)
749  
750  #define RSZ_SRC_EN					(0x0020)
751  #define RSZ_SRC_EN_SRC_EN				BIT(0)
752  
753  #define RSZ_SRC_MODE					(0x0024)
754  #define RSZ_SRC_MODE_OST				BIT(0)
755  #define RSZ_SRC_MODE_WRT				BIT(1)
756  
757  #define RSZ_SRC_FMT0					(0x0028)
758  #define RSZ_SRC_FMT0_BYPASS				BIT(1)
759  #define RSZ_SRC_FMT0_SEL				BIT(0)
760  
761  #define RSZ_SRC_FMT1					(0x002c)
762  #define RSZ_SRC_FMT1_IN420				BIT(1)
763  
764  #define RSZ_SRC_VPS					(0x0030)
765  #define RSZ_SRC_VSZ					(0x0034)
766  #define RSZ_SRC_HPS					(0x0038)
767  #define RSZ_SRC_HSZ					(0x003c)
768  #define RSZ_DMA_RZA					(0x0040)
769  #define RSZ_DMA_RZB					(0x0044)
770  #define RSZ_DMA_STA					(0x0048)
771  #define RSZ_GCK_MMR					(0x004c)
772  #define RSZ_GCK_MMR_MMR					BIT(0)
773  
774  #define RSZ_GCK_SDR					(0x0054)
775  #define RSZ_GCK_SDR_CORE				BIT(0)
776  
777  #define RSZ_IRQ_RZA					(0x0058)
778  #define RSZ_IRQ_RZA_MASK				(0x1fff)
779  
780  #define RSZ_IRQ_RZB					(0x005c)
781  #define RSZ_IRQ_RZB_MASK				(0x1fff)
782  
783  #define RSZ_YUV_Y_MIN					(0x0060)
784  #define RSZ_YUV_Y_MAX					(0x0064)
785  #define RSZ_YUV_C_MIN					(0x0068)
786  #define RSZ_YUV_C_MAX					(0x006c)
787  
788  #define RSZ_SEQ						(0x0074)
789  #define RSZ_SEQ_HRVB					BIT(2)
790  #define RSZ_SEQ_HRVA					BIT(0)
791  
792  #define RZA_EN						(0x0078)
793  #define RZA_MODE					(0x007c)
794  #define RZA_MODE_ONE_SHOT				BIT(0)
795  
796  #define RZA_420						(0x0080)
797  #define RZA_I_VPS					(0x0084)
798  #define RZA_I_HPS					(0x0088)
799  #define RZA_O_VSZ					(0x008c)
800  #define RZA_O_HSZ					(0x0090)
801  #define RZA_V_PHS_Y					(0x0094)
802  #define RZA_V_PHS_C					(0x0098)
803  #define RZA_V_DIF					(0x009c)
804  #define RZA_V_TYP					(0x00a0)
805  #define RZA_V_LPF					(0x00a4)
806  #define RZA_H_PHS					(0x00a8)
807  #define RZA_H_DIF					(0x00b0)
808  #define RZA_H_TYP					(0x00b4)
809  #define RZA_H_LPF					(0x00b8)
810  #define RZA_DWN_EN					(0x00bc)
811  #define RZA_SDR_Y_BAD_H					(0x00d0)
812  #define RZA_SDR_Y_BAD_L					(0x00d4)
813  #define RZA_SDR_Y_SAD_H					(0x00d8)
814  #define RZA_SDR_Y_SAD_L					(0x00dc)
815  #define RZA_SDR_Y_OFT					(0x00e0)
816  #define RZA_SDR_Y_PTR_S					(0x00e4)
817  #define RZA_SDR_Y_PTR_E					(0x00e8)
818  #define RZA_SDR_C_BAD_H					(0x00ec)
819  #define RZA_SDR_C_BAD_L					(0x00f0)
820  #define RZA_SDR_C_SAD_H					(0x00f4)
821  #define RZA_SDR_C_SAD_L					(0x00f8)
822  #define RZA_SDR_C_OFT					(0x00fc)
823  #define RZA_SDR_C_PTR_S					(0x0100)
824  #define RZA_SDR_C_PTR_E					(0x0104)
825  
826  #define RZB_EN						(0x0108)
827  #define RZB_MODE					(0x010c)
828  #define RZB_420						(0x0110)
829  #define RZB_I_VPS					(0x0114)
830  #define RZB_I_HPS					(0x0118)
831  #define RZB_O_VSZ					(0x011c)
832  #define RZB_O_HSZ					(0x0120)
833  
834  #define RZB_V_DIF					(0x012c)
835  #define RZB_V_TYP					(0x0130)
836  #define RZB_V_LPF					(0x0134)
837  
838  #define RZB_H_DIF					(0x0140)
839  #define RZB_H_TYP					(0x0144)
840  #define RZB_H_LPF					(0x0148)
841  
842  #define RZB_SDR_Y_BAD_H					(0x0160)
843  #define RZB_SDR_Y_BAD_L					(0x0164)
844  #define RZB_SDR_Y_SAD_H					(0x0168)
845  #define RZB_SDR_Y_SAD_L					(0x016c)
846  #define RZB_SDR_Y_OFT					(0x0170)
847  #define RZB_SDR_Y_PTR_S					(0x0174)
848  #define RZB_SDR_Y_PTR_E					(0x0178)
849  #define RZB_SDR_C_BAD_H					(0x017c)
850  #define RZB_SDR_C_BAD_L					(0x0180)
851  #define RZB_SDR_C_SAD_H					(0x0184)
852  #define RZB_SDR_C_SAD_L					(0x0188)
853  
854  #define RZB_SDR_C_PTR_S					(0x0190)
855  #define RZB_SDR_C_PTR_E					(0x0194)
856  
857  /* Shared Bitmasks between RZA & RZB */
858  #define RSZ_EN_EN					BIT(0)
859  
860  #define RSZ_420_CEN					BIT(1)
861  #define RSZ_420_YEN					BIT(0)
862  
863  #define RSZ_I_VPS_MASK					(0x1fff)
864  
865  #define RSZ_I_HPS_MASK					(0x1fff)
866  
867  #define RSZ_O_VSZ_MASK					(0x1fff)
868  
869  #define RSZ_O_HSZ_MASK					(0x1ffe)
870  
871  #define RSZ_V_PHS_Y_MASK				(0x3fff)
872  
873  #define RSZ_V_PHS_C_MASK				(0x3fff)
874  
875  #define RSZ_V_DIF_MASK					(0x3fff)
876  
877  #define RSZ_V_TYP_C					BIT(1)
878  #define RSZ_V_TYP_Y					BIT(0)
879  
880  #define RSZ_V_LPF_C_MASK				(0x3f << 6)
881  #define RSZ_V_LPF_C_SHIFT				6
882  #define RSZ_V_LPF_Y_MASK				(0x3f << 0)
883  #define RSZ_V_LPF_Y_SHIFT				0
884  
885  #define RSZ_H_PHS_MASK					(0x3fff)
886  
887  #define RSZ_H_DIF_MASK					(0x3fff)
888  
889  #define RSZ_H_TYP_C					BIT(1)
890  #define RSZ_H_TYP_Y					BIT(0)
891  
892  #define RSZ_H_LPF_C_MASK				(0x3f << 6)
893  #define RSZ_H_LPF_C_SHIFT				6
894  #define RSZ_H_LPF_Y_MASK				(0x3f << 0)
895  #define RSZ_H_LPF_Y_SHIFT				0
896  
897  #define RSZ_DWN_EN_DWN_EN				BIT(0)
898  
899  #endif /* _OMAP4_ISS_REGS_H_ */
900