1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_DP_TYPES_H 27 #define DC_DP_TYPES_H 28 29 #include "os_types.h" 30 31 enum dc_lane_count { 32 LANE_COUNT_UNKNOWN = 0, 33 LANE_COUNT_ONE = 1, 34 LANE_COUNT_TWO = 2, 35 LANE_COUNT_FOUR = 4, 36 LANE_COUNT_EIGHT = 8, 37 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR 38 }; 39 40 /* This is actually a reference clock (27MHz) multiplier 41 * 162MBps bandwidth for 1.62GHz like rate, 42 * 270MBps for 2.70GHz, 43 * 324MBps for 3.24Ghz, 44 * 540MBps for 5.40GHz 45 * 810MBps for 8.10GHz 46 */ 47 enum dc_link_rate { 48 LINK_RATE_UNKNOWN = 0, 49 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane 50 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 51 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 52 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane 53 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane 54 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 55 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane 56 LINK_RATE_HIGH3 = 0x1E // Rate_8 (HBR3)- 8.10 Gbps/Lane 57 }; 58 59 enum dc_link_spread { 60 LINK_SPREAD_DISABLED = 0x00, 61 /* 0.5 % downspread 30 kHz */ 62 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, 63 /* 0.5 % downspread 33 kHz */ 64 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 65 }; 66 67 enum dc_voltage_swing { 68 VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ 69 VOLTAGE_SWING_LEVEL1, 70 VOLTAGE_SWING_LEVEL2, 71 VOLTAGE_SWING_LEVEL3, 72 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 73 }; 74 75 enum dc_pre_emphasis { 76 PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ 77 PRE_EMPHASIS_LEVEL1, 78 PRE_EMPHASIS_LEVEL2, 79 PRE_EMPHASIS_LEVEL3, 80 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 81 }; 82 /* Post Cursor 2 is optional for transmitter 83 * and it applies only to the main link operating at HBR2 84 */ 85 enum dc_post_cursor2 { 86 POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ 87 POST_CURSOR2_LEVEL1, 88 POST_CURSOR2_LEVEL2, 89 POST_CURSOR2_LEVEL3, 90 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, 91 }; 92 93 enum dc_dp_training_pattern { 94 DP_TRAINING_PATTERN_SEQUENCE_1 = 0, 95 DP_TRAINING_PATTERN_SEQUENCE_2, 96 DP_TRAINING_PATTERN_SEQUENCE_3, 97 DP_TRAINING_PATTERN_SEQUENCE_4, 98 DP_TRAINING_PATTERN_VIDEOIDLE, 99 }; 100 101 enum dp_link_encoding { 102 DP_UNKNOWN_ENCODING = 0, 103 DP_8b_10b_ENCODING = 1, 104 }; 105 106 struct dc_link_settings { 107 enum dc_lane_count lane_count; 108 enum dc_link_rate link_rate; 109 enum dc_link_spread link_spread; 110 bool use_link_rate_set; 111 uint8_t link_rate_set; 112 }; 113 114 struct dc_lane_settings { 115 enum dc_voltage_swing VOLTAGE_SWING; 116 enum dc_pre_emphasis PRE_EMPHASIS; 117 enum dc_post_cursor2 POST_CURSOR2; 118 }; 119 120 struct dc_link_training_settings { 121 struct dc_link_settings link; 122 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; 123 }; 124 125 struct dc_link_training_overrides { 126 enum dc_voltage_swing *voltage_swing; 127 enum dc_pre_emphasis *pre_emphasis; 128 enum dc_post_cursor2 *post_cursor2; 129 130 uint16_t *cr_pattern_time; 131 uint16_t *eq_pattern_time; 132 enum dc_dp_training_pattern *pattern_for_cr; 133 enum dc_dp_training_pattern *pattern_for_eq; 134 135 enum dc_link_spread *downspread; 136 bool *alternate_scrambler_reset; 137 bool *enhanced_framing; 138 bool *mst_enable; 139 bool *fec_enable; 140 }; 141 142 union dpcd_rev { 143 struct { 144 uint8_t MINOR:4; 145 uint8_t MAJOR:4; 146 } bits; 147 uint8_t raw; 148 }; 149 150 union max_lane_count { 151 struct { 152 uint8_t MAX_LANE_COUNT:5; 153 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; 154 uint8_t TPS3_SUPPORTED:1; 155 uint8_t ENHANCED_FRAME_CAP:1; 156 } bits; 157 uint8_t raw; 158 }; 159 160 union max_down_spread { 161 struct { 162 uint8_t MAX_DOWN_SPREAD:1; 163 uint8_t RESERVED:5; 164 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; 165 uint8_t TPS4_SUPPORTED:1; 166 } bits; 167 uint8_t raw; 168 }; 169 170 union mstm_cap { 171 struct { 172 uint8_t MST_CAP:1; 173 uint8_t RESERVED:7; 174 } bits; 175 uint8_t raw; 176 }; 177 178 union lane_count_set { 179 struct { 180 uint8_t LANE_COUNT_SET:5; 181 uint8_t POST_LT_ADJ_REQ_GRANTED:1; 182 uint8_t RESERVED:1; 183 uint8_t ENHANCED_FRAMING:1; 184 } bits; 185 uint8_t raw; 186 }; 187 188 union lane_status { 189 struct { 190 uint8_t CR_DONE_0:1; 191 uint8_t CHANNEL_EQ_DONE_0:1; 192 uint8_t SYMBOL_LOCKED_0:1; 193 uint8_t RESERVED0:1; 194 uint8_t CR_DONE_1:1; 195 uint8_t CHANNEL_EQ_DONE_1:1; 196 uint8_t SYMBOL_LOCKED_1:1; 197 uint8_t RESERVED_1:1; 198 } bits; 199 uint8_t raw; 200 }; 201 202 union device_service_irq { 203 struct { 204 uint8_t REMOTE_CONTROL_CMD_PENDING:1; 205 uint8_t AUTOMATED_TEST:1; 206 uint8_t CP_IRQ:1; 207 uint8_t MCCS_IRQ:1; 208 uint8_t DOWN_REP_MSG_RDY:1; 209 uint8_t UP_REQ_MSG_RDY:1; 210 uint8_t SINK_SPECIFIC:1; 211 uint8_t reserved:1; 212 } bits; 213 uint8_t raw; 214 }; 215 216 union sink_count { 217 struct { 218 uint8_t SINK_COUNT:6; 219 uint8_t CPREADY:1; 220 uint8_t RESERVED:1; 221 } bits; 222 uint8_t raw; 223 }; 224 225 union lane_align_status_updated { 226 struct { 227 uint8_t INTERLANE_ALIGN_DONE:1; 228 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; 229 uint8_t RESERVED:4; 230 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; 231 uint8_t LINK_STATUS_UPDATED:1; 232 } bits; 233 uint8_t raw; 234 }; 235 236 union lane_adjust { 237 struct { 238 uint8_t VOLTAGE_SWING_LANE:2; 239 uint8_t PRE_EMPHASIS_LANE:2; 240 uint8_t RESERVED:4; 241 } bits; 242 uint8_t raw; 243 }; 244 245 union dpcd_training_pattern { 246 struct { 247 uint8_t TRAINING_PATTERN_SET:4; 248 uint8_t RECOVERED_CLOCK_OUT_EN:1; 249 uint8_t SCRAMBLING_DISABLE:1; 250 uint8_t SYMBOL_ERROR_COUNT_SEL:2; 251 } v1_4; 252 struct { 253 uint8_t TRAINING_PATTERN_SET:2; 254 uint8_t LINK_QUAL_PATTERN_SET:2; 255 uint8_t RESERVED:4; 256 } v1_3; 257 uint8_t raw; 258 }; 259 260 /* Training Lane is used to configure downstream DP device's voltage swing 261 and pre-emphasis levels*/ 262 /* The DPCD addresses are from 0x103 to 0x106*/ 263 union dpcd_training_lane { 264 struct { 265 uint8_t VOLTAGE_SWING_SET:2; 266 uint8_t MAX_SWING_REACHED:1; 267 uint8_t PRE_EMPHASIS_SET:2; 268 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 269 uint8_t RESERVED:2; 270 } bits; 271 uint8_t raw; 272 }; 273 274 /* TMDS-converter related */ 275 union dwnstream_port_caps_byte0 { 276 struct { 277 uint8_t DWN_STRM_PORTX_TYPE:3; 278 uint8_t DWN_STRM_PORTX_HPD:1; 279 uint8_t RESERVERD:4; 280 } bits; 281 uint8_t raw; 282 }; 283 284 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ 285 enum dpcd_downstream_port_detailed_type { 286 DOWN_STREAM_DETAILED_DP = 0, 287 DOWN_STREAM_DETAILED_VGA, 288 DOWN_STREAM_DETAILED_DVI, 289 DOWN_STREAM_DETAILED_HDMI, 290 DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ 291 DOWN_STREAM_DETAILED_DP_PLUS_PLUS 292 }; 293 294 union dwnstream_port_caps_byte2 { 295 struct { 296 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; 297 uint8_t RESERVED:6; 298 } bits; 299 uint8_t raw; 300 }; 301 302 union dp_downstream_port_present { 303 uint8_t byte; 304 struct { 305 uint8_t PORT_PRESENT:1; 306 uint8_t PORT_TYPE:2; 307 uint8_t FMT_CONVERSION:1; 308 uint8_t DETAILED_CAPS:1; 309 uint8_t RESERVED:3; 310 } fields; 311 }; 312 313 union dwnstream_port_caps_byte3_dvi { 314 struct { 315 uint8_t RESERVED1:1; 316 uint8_t DUAL_LINK:1; 317 uint8_t HIGH_COLOR_DEPTH:1; 318 uint8_t RESERVED2:5; 319 } bits; 320 uint8_t raw; 321 }; 322 323 union dwnstream_port_caps_byte3_hdmi { 324 struct { 325 uint8_t FRAME_SEQ_TO_FRAME_PACK:1; 326 uint8_t YCrCr422_PASS_THROUGH:1; 327 uint8_t YCrCr420_PASS_THROUGH:1; 328 uint8_t YCrCr422_CONVERSION:1; 329 uint8_t YCrCr420_CONVERSION:1; 330 uint8_t RESERVED:3; 331 } bits; 332 uint8_t raw; 333 }; 334 335 /*4-byte structure for detailed capabilities of a down-stream port 336 (DP-to-TMDS converter).*/ 337 union dwnstream_portxcaps { 338 struct { 339 union dwnstream_port_caps_byte0 byte0; 340 unsigned char max_TMDS_clock; //byte1 341 union dwnstream_port_caps_byte2 byte2; 342 343 union { 344 union dwnstream_port_caps_byte3_dvi byteDVI; 345 union dwnstream_port_caps_byte3_hdmi byteHDMI; 346 } byte3; 347 } bytes; 348 349 unsigned char raw[4]; 350 }; 351 352 union downstream_port { 353 struct { 354 unsigned char present:1; 355 unsigned char type:2; 356 unsigned char format_conv:1; 357 unsigned char detailed_caps:1; 358 unsigned char reserved:3; 359 } bits; 360 unsigned char raw; 361 }; 362 363 364 union sink_status { 365 struct { 366 uint8_t RX_PORT0_STATUS:1; 367 uint8_t RX_PORT1_STATUS:1; 368 uint8_t RESERVED:6; 369 } bits; 370 uint8_t raw; 371 }; 372 373 /*6-byte structure corresponding to 6 registers (200h-205h) 374 read during handling of HPD-IRQ*/ 375 union hpd_irq_data { 376 struct { 377 union sink_count sink_cnt;/* 200h */ 378 union device_service_irq device_service_irq;/* 201h */ 379 union lane_status lane01_status;/* 202h */ 380 union lane_status lane23_status;/* 203h */ 381 union lane_align_status_updated lane_status_updated;/* 204h */ 382 union sink_status sink_status; 383 } bytes; 384 uint8_t raw[6]; 385 }; 386 387 union down_stream_port_count { 388 struct { 389 uint8_t DOWN_STR_PORT_COUNT:4; 390 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ 391 /*Bit 6 = MSA_TIMING_PAR_IGNORED 392 0 = Sink device requires the MSA timing parameters 393 1 = Sink device is capable of rendering incoming video 394 stream without MSA timing parameters*/ 395 uint8_t IGNORE_MSA_TIMING_PARAM:1; 396 /*Bit 7 = OUI Support 397 0 = OUI not supported 398 1 = OUI supported 399 (OUI and Device Identification mandatory for DP 1.2)*/ 400 uint8_t OUI_SUPPORT:1; 401 } bits; 402 uint8_t raw; 403 }; 404 405 union down_spread_ctrl { 406 struct { 407 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ 408 /* Bits 4 = SPREAD_AMP. Spreading amplitude 409 0 = Main link signal is not downspread 410 1 = Main link signal is downspread <= 0.5% 411 with frequency in the range of 30kHz ~ 33kHz*/ 412 uint8_t SPREAD_AMP:1; 413 uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/ 414 /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN 415 0 = Source device will send valid data for the MSA Timing Params 416 1 = Source device may send invalid data for these MSA Timing Params*/ 417 uint8_t IGNORE_MSA_TIMING_PARAM:1; 418 } bits; 419 uint8_t raw; 420 }; 421 422 union dpcd_edp_config { 423 struct { 424 uint8_t PANEL_MODE_EDP:1; 425 uint8_t FRAMING_CHANGE_ENABLE:1; 426 uint8_t RESERVED:5; 427 uint8_t PANEL_SELF_TEST_ENABLE:1; 428 } bits; 429 uint8_t raw; 430 }; 431 432 struct dp_device_vendor_id { 433 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 434 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 435 }; 436 437 struct dp_sink_hw_fw_revision { 438 uint8_t ieee_hw_rev; 439 uint8_t ieee_fw_rev[2]; 440 }; 441 442 struct dpcd_vendor_signature { 443 bool is_valid; 444 445 union dpcd_ieee_vendor_signature { 446 struct { 447 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 448 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 449 uint8_t ieee_hw_rev; 450 uint8_t ieee_fw_rev[2]; 451 }; 452 uint8_t raw[12]; 453 } data; 454 }; 455 456 struct dpcd_amd_signature { 457 uint8_t AMD_IEEE_TxSignature_byte1; 458 uint8_t AMD_IEEE_TxSignature_byte2; 459 uint8_t AMD_IEEE_TxSignature_byte3; 460 }; 461 462 struct dpcd_amd_device_id { 463 uint8_t device_id_byte1; 464 uint8_t device_id_byte2; 465 uint8_t zero[4]; 466 uint8_t dce_version; 467 uint8_t dal_version_byte1; 468 uint8_t dal_version_byte2; 469 }; 470 471 struct dpcd_source_backlight_set { 472 struct { 473 uint8_t byte0; 474 uint8_t byte1; 475 uint8_t byte2; 476 uint8_t byte3; 477 } backlight_level_millinits; 478 479 struct { 480 uint8_t byte0; 481 uint8_t byte1; 482 } backlight_transition_time_ms; 483 }; 484 485 union dpcd_source_backlight_get { 486 struct { 487 uint32_t backlight_millinits_peak; /* 326h */ 488 uint32_t backlight_millinits_avg; /* 32Ah */ 489 } bytes; 490 uint8_t raw[8]; 491 }; 492 493 /*DPCD register of DP receiver capability field bits-*/ 494 union edp_configuration_cap { 495 struct { 496 uint8_t ALT_SCRAMBLER_RESET:1; 497 uint8_t FRAMING_CHANGE:1; 498 uint8_t RESERVED:1; 499 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; 500 uint8_t RESERVED2:4; 501 } bits; 502 uint8_t raw; 503 }; 504 505 union dprx_feature { 506 struct { 507 uint8_t GTC_CAP:1; // bit 0: DP 1.3+ 508 uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4 509 uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+ 510 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+ 511 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4 512 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4 513 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4 514 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4 515 } bits; 516 uint8_t raw; 517 }; 518 519 union training_aux_rd_interval { 520 struct { 521 uint8_t TRAINIG_AUX_RD_INTERVAL:7; 522 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1; 523 } bits; 524 uint8_t raw; 525 }; 526 527 /* Automated test structures */ 528 union test_request { 529 struct { 530 uint8_t LINK_TRAINING :1; 531 uint8_t LINK_TEST_PATTRN :1; 532 uint8_t EDID_READ :1; 533 uint8_t PHY_TEST_PATTERN :1; 534 uint8_t RESERVED :1; 535 uint8_t AUDIO_TEST_PATTERN :1; 536 uint8_t TEST_AUDIO_DISABLED_VIDEO :1; 537 } bits; 538 uint8_t raw; 539 }; 540 541 union test_response { 542 struct { 543 uint8_t ACK :1; 544 uint8_t NO_ACK :1; 545 uint8_t EDID_CHECKSUM_WRITE:1; 546 uint8_t RESERVED :5; 547 } bits; 548 uint8_t raw; 549 }; 550 551 union phy_test_pattern { 552 struct { 553 /* DpcdPhyTestPatterns. This field is 2 bits for DP1.1 554 * and 3 bits for DP1.2. 555 */ 556 uint8_t PATTERN :3; 557 /* BY speci, bit7:2 is 0 for DP1.1. */ 558 uint8_t RESERVED :5; 559 } bits; 560 uint8_t raw; 561 }; 562 563 /* States of Compliance Test Specification (CTS DP1.2). */ 564 union compliance_test_state { 565 struct { 566 unsigned char STEREO_3D_RUNNING : 1; 567 unsigned char RESERVED : 7; 568 } bits; 569 unsigned char raw; 570 }; 571 572 union link_test_pattern { 573 struct { 574 /* dpcd_link_test_patterns */ 575 unsigned char PATTERN :2; 576 unsigned char RESERVED:6; 577 } bits; 578 unsigned char raw; 579 }; 580 581 union test_misc { 582 struct dpcd_test_misc_bits { 583 unsigned char SYNC_CLOCK :1; 584 /* dpcd_test_color_format */ 585 unsigned char CLR_FORMAT :2; 586 /* dpcd_test_dyn_range */ 587 unsigned char DYN_RANGE :1; 588 unsigned char YCBCR_COEFS :1; 589 /* dpcd_test_bit_depth */ 590 unsigned char BPC :3; 591 } bits; 592 unsigned char raw; 593 }; 594 595 union audio_test_mode { 596 struct { 597 unsigned char sampling_rate :4; 598 unsigned char channel_count :4; 599 } bits; 600 unsigned char raw; 601 }; 602 603 union audio_test_pattern_period { 604 struct { 605 unsigned char pattern_period :4; 606 unsigned char reserved :4; 607 } bits; 608 unsigned char raw; 609 }; 610 611 struct audio_test_pattern_type { 612 unsigned char value; 613 }; 614 615 struct dp_audio_test_data_flags { 616 uint8_t test_requested :1; 617 uint8_t disable_video :1; 618 }; 619 620 struct dp_audio_test_data { 621 622 struct dp_audio_test_data_flags flags; 623 uint8_t sampling_rate; 624 uint8_t channel_count; 625 uint8_t pattern_type; 626 uint8_t pattern_period[8]; 627 }; 628 629 /* FEC capability DPCD register field bits-*/ 630 union dpcd_fec_capability { 631 struct { 632 uint8_t FEC_CAPABLE:1; 633 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 634 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 635 uint8_t BIT_ERROR_COUNT_CAPABLE:1; 636 uint8_t RESERVED:4; 637 } bits; 638 uint8_t raw; 639 }; 640 641 /* DSC capability DPCD register field bits-*/ 642 struct dpcd_dsc_support { 643 uint8_t DSC_SUPPORT :1; 644 uint8_t DSC_PASSTHROUGH_SUPPORT :1; 645 uint8_t RESERVED :6; 646 }; 647 648 struct dpcd_dsc_algorithm_revision { 649 uint8_t DSC_VERSION_MAJOR :4; 650 uint8_t DSC_VERSION_MINOR :4; 651 }; 652 653 struct dpcd_dsc_rc_buffer_block_size { 654 uint8_t RC_BLOCK_BUFFER_SIZE :2; 655 uint8_t RESERVED :6; 656 }; 657 658 struct dpcd_dsc_slice_capability1 { 659 uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1; 660 uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1; 661 uint8_t RESERVED :1; 662 uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1; 663 uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1; 664 uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1; 665 uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1; 666 uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1; 667 }; 668 669 struct dpcd_dsc_line_buffer_bit_depth { 670 uint8_t LINE_BUFFER_BIT_DEPTH :4; 671 uint8_t RESERVED :4; 672 }; 673 674 struct dpcd_dsc_block_prediction_support { 675 uint8_t BLOCK_PREDICTION_SUPPORT:1; 676 uint8_t RESERVED :7; 677 }; 678 679 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor { 680 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7; 681 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7; 682 uint8_t RESERVED :2; 683 }; 684 685 struct dpcd_dsc_decoder_color_format_capabilities { 686 uint8_t RGB_SUPPORT :1; 687 uint8_t Y_CB_CR_444_SUPPORT :1; 688 uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1; 689 uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1; 690 uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1; 691 uint8_t RESERVED :3; 692 }; 693 694 struct dpcd_dsc_decoder_color_depth_capabilities { 695 uint8_t RESERVED0 :1; 696 uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1; 697 uint8_t TEN_BITS_PER_COLOR_SUPPORT :1; 698 uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1; 699 uint8_t RESERVED1 :4; 700 }; 701 702 struct dpcd_peak_dsc_throughput_dsc_sink { 703 uint8_t THROUGHPUT_MODE_0:4; 704 uint8_t THROUGHPUT_MODE_1:4; 705 }; 706 707 struct dpcd_dsc_slice_capabilities_2 { 708 uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1; 709 uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1; 710 uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1; 711 uint8_t RESERVED :5; 712 }; 713 714 struct dpcd_bits_per_pixel_increment{ 715 uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3; 716 uint8_t RESERVED :5; 717 }; 718 union dpcd_dsc_basic_capabilities { 719 struct { 720 struct dpcd_dsc_support dsc_support; 721 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision; 722 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size; 723 uint8_t dsc_rc_buffer_size; 724 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1; 725 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth; 726 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support; 727 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor; 728 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities; 729 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities; 730 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink; 731 uint8_t dsc_maximum_slice_width; 732 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2; 733 uint8_t reserved; 734 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment; 735 } fields; 736 uint8_t raw[16]; 737 }; 738 739 union dpcd_dsc_branch_decoder_capabilities { 740 struct { 741 uint8_t BRANCH_OVERALL_THROUGHPUT_0; 742 uint8_t BRANCH_OVERALL_THROUGHPUT_1; 743 uint8_t BRANCH_MAX_LINE_WIDTH; 744 } fields; 745 uint8_t raw[3]; 746 }; 747 748 struct dpcd_dsc_capabilities { 749 union dpcd_dsc_basic_capabilities dsc_basic_caps; 750 union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps; 751 }; 752 753 /* These parameters are from PSR capabilities reported by Sink DPCD */ 754 struct psr_caps { 755 unsigned char psr_version; 756 unsigned int psr_rfb_setup_time; 757 bool psr_exit_link_training_required; 758 }; 759 760 #endif /* DC_DP_TYPES_H */ 761