1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2020 Intel Corporation. */
3
4 #include <linux/clk.h>
5 #include <linux/completion.h>
6 #include <linux/dmaengine.h>
7 #include <linux/dma-direction.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/err.h>
10 #include <linux/init.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/rawnand.h>
17 #include <linux/mtd/nand.h>
18
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/sched.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
24 #include <linux/units.h>
25 #include <asm/unaligned.h>
26
27 #define EBU_CLC 0x000
28 #define EBU_CLC_RST 0x00000000u
29
30 #define EBU_ADDR_SEL(n) (0x020 + (n) * 4)
31 /* 5 bits 26:22 included for comparison in the ADDR_SELx */
32 #define EBU_ADDR_MASK(x) ((x) << 4)
33 #define EBU_ADDR_SEL_REGEN 0x1
34
35 #define EBU_BUSCON(n) (0x060 + (n) * 4)
36 #define EBU_BUSCON_CMULT_V4 0x1
37 #define EBU_BUSCON_RECOVC(n) ((n) << 2)
38 #define EBU_BUSCON_HOLDC(n) ((n) << 4)
39 #define EBU_BUSCON_WAITRDC(n) ((n) << 6)
40 #define EBU_BUSCON_WAITWRC(n) ((n) << 8)
41 #define EBU_BUSCON_BCGEN_CS 0x0
42 #define EBU_BUSCON_SETUP_EN BIT(22)
43 #define EBU_BUSCON_ALEC 0xC000
44
45 #define EBU_CON 0x0B0
46 #define EBU_CON_NANDM_EN BIT(0)
47 #define EBU_CON_NANDM_DIS 0x0
48 #define EBU_CON_CSMUX_E_EN BIT(1)
49 #define EBU_CON_ALE_P_LOW BIT(2)
50 #define EBU_CON_CLE_P_LOW BIT(3)
51 #define EBU_CON_CS_P_LOW BIT(4)
52 #define EBU_CON_SE_P_LOW BIT(5)
53 #define EBU_CON_WP_P_LOW BIT(6)
54 #define EBU_CON_PRE_P_LOW BIT(7)
55 #define EBU_CON_IN_CS_S(n) ((n) << 8)
56 #define EBU_CON_OUT_CS_S(n) ((n) << 10)
57 #define EBU_CON_LAT_EN_CS_P ((0x3D) << 18)
58
59 #define EBU_WAIT 0x0B4
60 #define EBU_WAIT_RDBY BIT(0)
61 #define EBU_WAIT_WR_C BIT(3)
62
63 #define HSNAND_CTL1 0x110
64 #define HSNAND_CTL1_ADDR_SHIFT 24
65
66 #define HSNAND_CTL2 0x114
67 #define HSNAND_CTL2_ADDR_SHIFT 8
68 #define HSNAND_CTL2_CYC_N_V5 (0x2 << 16)
69
70 #define HSNAND_INT_MSK_CTL 0x124
71 #define HSNAND_INT_MSK_CTL_WR_C BIT(4)
72
73 #define HSNAND_INT_STA 0x128
74 #define HSNAND_INT_STA_WR_C BIT(4)
75
76 #define HSNAND_CTL 0x130
77 #define HSNAND_CTL_ENABLE_ECC BIT(0)
78 #define HSNAND_CTL_GO BIT(2)
79 #define HSNAND_CTL_CE_SEL_CS(n) BIT(3 + (n))
80 #define HSNAND_CTL_RW_READ 0x0
81 #define HSNAND_CTL_RW_WRITE BIT(10)
82 #define HSNAND_CTL_ECC_OFF_V8TH BIT(11)
83 #define HSNAND_CTL_CKFF_EN 0x0
84 #define HSNAND_CTL_MSG_EN BIT(17)
85
86 #define HSNAND_PARA0 0x13c
87 #define HSNAND_PARA0_PAGE_V8192 0x3
88 #define HSNAND_PARA0_PIB_V256 (0x3 << 4)
89 #define HSNAND_PARA0_BYP_EN_NP 0x0
90 #define HSNAND_PARA0_BYP_DEC_NP 0x0
91 #define HSNAND_PARA0_TYPE_ONFI BIT(18)
92 #define HSNAND_PARA0_ADEP_EN BIT(21)
93
94 #define HSNAND_CMSG_0 0x150
95 #define HSNAND_CMSG_1 0x154
96
97 #define HSNAND_ALE_OFFS BIT(2)
98 #define HSNAND_CLE_OFFS BIT(3)
99 #define HSNAND_CS_OFFS BIT(4)
100
101 #define HSNAND_ECC_OFFSET 0x008
102
103 #define NAND_DATA_IFACE_CHECK_ONLY -1
104
105 #define MAX_CS 2
106
107 #define USEC_PER_SEC 1000000L
108
109 struct ebu_nand_cs {
110 void __iomem *chipaddr;
111 dma_addr_t nand_pa;
112 u32 addr_sel;
113 };
114
115 struct ebu_nand_controller {
116 struct nand_controller controller;
117 struct nand_chip chip;
118 struct device *dev;
119 void __iomem *ebu;
120 void __iomem *hsnand;
121 struct dma_chan *dma_tx;
122 struct dma_chan *dma_rx;
123 struct completion dma_access_complete;
124 unsigned long clk_rate;
125 struct clk *clk;
126 u32 nd_para0;
127 u8 cs_num;
128 struct ebu_nand_cs cs[MAX_CS];
129 };
130
nand_to_ebu(struct nand_chip * chip)131 static inline struct ebu_nand_controller *nand_to_ebu(struct nand_chip *chip)
132 {
133 return container_of(chip, struct ebu_nand_controller, chip);
134 }
135
ebu_nand_waitrdy(struct nand_chip * chip,int timeout_ms)136 static int ebu_nand_waitrdy(struct nand_chip *chip, int timeout_ms)
137 {
138 struct ebu_nand_controller *ctrl = nand_to_ebu(chip);
139 u32 status;
140
141 return readl_poll_timeout(ctrl->ebu + EBU_WAIT, status,
142 (status & EBU_WAIT_RDBY) ||
143 (status & EBU_WAIT_WR_C), 20, timeout_ms);
144 }
145
ebu_nand_readb(struct nand_chip * chip)146 static u8 ebu_nand_readb(struct nand_chip *chip)
147 {
148 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
149 u8 cs_num = ebu_host->cs_num;
150 u8 val;
151
152 val = readb(ebu_host->cs[cs_num].chipaddr + HSNAND_CS_OFFS);
153 ebu_nand_waitrdy(chip, 1000);
154 return val;
155 }
156
ebu_nand_writeb(struct nand_chip * chip,u32 offset,u8 value)157 static void ebu_nand_writeb(struct nand_chip *chip, u32 offset, u8 value)
158 {
159 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
160 u8 cs_num = ebu_host->cs_num;
161
162 writeb(value, ebu_host->cs[cs_num].chipaddr + offset);
163 ebu_nand_waitrdy(chip, 1000);
164 }
165
ebu_read_buf(struct nand_chip * chip,u_char * buf,unsigned int len)166 static void ebu_read_buf(struct nand_chip *chip, u_char *buf, unsigned int len)
167 {
168 int i;
169
170 for (i = 0; i < len; i++)
171 buf[i] = ebu_nand_readb(chip);
172 }
173
ebu_write_buf(struct nand_chip * chip,const u_char * buf,int len)174 static void ebu_write_buf(struct nand_chip *chip, const u_char *buf, int len)
175 {
176 int i;
177
178 for (i = 0; i < len; i++)
179 ebu_nand_writeb(chip, HSNAND_CS_OFFS, buf[i]);
180 }
181
ebu_nand_disable(struct nand_chip * chip)182 static void ebu_nand_disable(struct nand_chip *chip)
183 {
184 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
185
186 writel(0, ebu_host->ebu + EBU_CON);
187 }
188
ebu_select_chip(struct nand_chip * chip)189 static void ebu_select_chip(struct nand_chip *chip)
190 {
191 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
192 void __iomem *nand_con = ebu_host->ebu + EBU_CON;
193 u32 cs = ebu_host->cs_num;
194
195 writel(EBU_CON_NANDM_EN | EBU_CON_CSMUX_E_EN | EBU_CON_CS_P_LOW |
196 EBU_CON_SE_P_LOW | EBU_CON_WP_P_LOW | EBU_CON_PRE_P_LOW |
197 EBU_CON_IN_CS_S(cs) | EBU_CON_OUT_CS_S(cs) |
198 EBU_CON_LAT_EN_CS_P, nand_con);
199 }
200
ebu_nand_set_timings(struct nand_chip * chip,int csline,const struct nand_interface_config * conf)201 static int ebu_nand_set_timings(struct nand_chip *chip, int csline,
202 const struct nand_interface_config *conf)
203 {
204 struct ebu_nand_controller *ctrl = nand_to_ebu(chip);
205 unsigned int rate = clk_get_rate(ctrl->clk) / HZ_PER_MHZ;
206 unsigned int period = DIV_ROUND_UP(USEC_PER_SEC, rate);
207 const struct nand_sdr_timings *timings;
208 u32 trecov, thold, twrwait, trdwait;
209 u32 reg = 0;
210
211 timings = nand_get_sdr_timings(conf);
212 if (IS_ERR(timings))
213 return PTR_ERR(timings);
214
215 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
216 return 0;
217
218 trecov = DIV_ROUND_UP(max(timings->tREA_max, timings->tREH_min),
219 period);
220 reg |= EBU_BUSCON_RECOVC(trecov);
221
222 thold = DIV_ROUND_UP(max(timings->tDH_min, timings->tDS_min), period);
223 reg |= EBU_BUSCON_HOLDC(thold);
224
225 trdwait = DIV_ROUND_UP(max(timings->tRC_min, timings->tREH_min),
226 period);
227 reg |= EBU_BUSCON_WAITRDC(trdwait);
228
229 twrwait = DIV_ROUND_UP(max(timings->tWC_min, timings->tWH_min), period);
230 reg |= EBU_BUSCON_WAITWRC(twrwait);
231
232 reg |= EBU_BUSCON_CMULT_V4 | EBU_BUSCON_BCGEN_CS | EBU_BUSCON_ALEC |
233 EBU_BUSCON_SETUP_EN;
234
235 writel(reg, ctrl->ebu + EBU_BUSCON(ctrl->cs_num));
236
237 return 0;
238 }
239
ebu_nand_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)240 static int ebu_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
241 struct mtd_oob_region *oobregion)
242 {
243 struct nand_chip *chip = mtd_to_nand(mtd);
244
245 if (section)
246 return -ERANGE;
247
248 oobregion->offset = HSNAND_ECC_OFFSET;
249 oobregion->length = chip->ecc.total;
250
251 return 0;
252 }
253
ebu_nand_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)254 static int ebu_nand_ooblayout_free(struct mtd_info *mtd, int section,
255 struct mtd_oob_region *oobregion)
256 {
257 struct nand_chip *chip = mtd_to_nand(mtd);
258
259 if (section)
260 return -ERANGE;
261
262 oobregion->offset = chip->ecc.total + HSNAND_ECC_OFFSET;
263 oobregion->length = mtd->oobsize - oobregion->offset;
264
265 return 0;
266 }
267
268 static const struct mtd_ooblayout_ops ebu_nand_ooblayout_ops = {
269 .ecc = ebu_nand_ooblayout_ecc,
270 .free = ebu_nand_ooblayout_free,
271 };
272
ebu_dma_rx_callback(void * cookie)273 static void ebu_dma_rx_callback(void *cookie)
274 {
275 struct ebu_nand_controller *ebu_host = cookie;
276
277 dmaengine_terminate_async(ebu_host->dma_rx);
278
279 complete(&ebu_host->dma_access_complete);
280 }
281
ebu_dma_tx_callback(void * cookie)282 static void ebu_dma_tx_callback(void *cookie)
283 {
284 struct ebu_nand_controller *ebu_host = cookie;
285
286 dmaengine_terminate_async(ebu_host->dma_tx);
287
288 complete(&ebu_host->dma_access_complete);
289 }
290
ebu_dma_start(struct ebu_nand_controller * ebu_host,u32 dir,const u8 * buf,u32 len)291 static int ebu_dma_start(struct ebu_nand_controller *ebu_host, u32 dir,
292 const u8 *buf, u32 len)
293 {
294 struct dma_async_tx_descriptor *tx;
295 struct completion *dma_completion;
296 dma_async_tx_callback callback;
297 struct dma_chan *chan;
298 dma_cookie_t cookie;
299 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
300 dma_addr_t buf_dma;
301 int ret;
302 u32 timeout;
303
304 if (dir == DMA_DEV_TO_MEM) {
305 chan = ebu_host->dma_rx;
306 dma_completion = &ebu_host->dma_access_complete;
307 callback = ebu_dma_rx_callback;
308 } else {
309 chan = ebu_host->dma_tx;
310 dma_completion = &ebu_host->dma_access_complete;
311 callback = ebu_dma_tx_callback;
312 }
313
314 buf_dma = dma_map_single(chan->device->dev, (void *)buf, len, dir);
315 if (dma_mapping_error(chan->device->dev, buf_dma)) {
316 dev_err(ebu_host->dev, "Failed to map DMA buffer\n");
317 ret = -EIO;
318 goto err_unmap;
319 }
320
321 tx = dmaengine_prep_slave_single(chan, buf_dma, len, dir, flags);
322 if (!tx) {
323 ret = -ENXIO;
324 goto err_unmap;
325 }
326
327 tx->callback = callback;
328 tx->callback_param = ebu_host;
329 cookie = tx->tx_submit(tx);
330
331 ret = dma_submit_error(cookie);
332 if (ret) {
333 dev_err(ebu_host->dev, "dma_submit_error %d\n", cookie);
334 ret = -EIO;
335 goto err_unmap;
336 }
337
338 init_completion(dma_completion);
339 dma_async_issue_pending(chan);
340
341 /* Wait DMA to finish the data transfer.*/
342 timeout = wait_for_completion_timeout(dma_completion, msecs_to_jiffies(1000));
343 if (!timeout) {
344 dev_err(ebu_host->dev, "I/O Error in DMA RX (status %d)\n",
345 dmaengine_tx_status(chan, cookie, NULL));
346 dmaengine_terminate_sync(chan);
347 ret = -ETIMEDOUT;
348 goto err_unmap;
349 }
350
351 return 0;
352
353 err_unmap:
354 dma_unmap_single(ebu_host->dev, buf_dma, len, dir);
355
356 return ret;
357 }
358
ebu_nand_trigger(struct ebu_nand_controller * ebu_host,int page,u32 cmd)359 static void ebu_nand_trigger(struct ebu_nand_controller *ebu_host,
360 int page, u32 cmd)
361 {
362 unsigned int val;
363
364 val = cmd | (page & 0xFF) << HSNAND_CTL1_ADDR_SHIFT;
365 writel(val, ebu_host->hsnand + HSNAND_CTL1);
366 val = (page & 0xFFFF00) >> 8 | HSNAND_CTL2_CYC_N_V5;
367 writel(val, ebu_host->hsnand + HSNAND_CTL2);
368
369 writel(ebu_host->nd_para0, ebu_host->hsnand + HSNAND_PARA0);
370
371 /* clear first, will update later */
372 writel(0xFFFFFFFF, ebu_host->hsnand + HSNAND_CMSG_0);
373 writel(0xFFFFFFFF, ebu_host->hsnand + HSNAND_CMSG_1);
374
375 writel(HSNAND_INT_MSK_CTL_WR_C,
376 ebu_host->hsnand + HSNAND_INT_MSK_CTL);
377
378 if (!cmd)
379 val = HSNAND_CTL_RW_READ;
380 else
381 val = HSNAND_CTL_RW_WRITE;
382
383 writel(HSNAND_CTL_MSG_EN | HSNAND_CTL_CKFF_EN |
384 HSNAND_CTL_ECC_OFF_V8TH | HSNAND_CTL_CE_SEL_CS(ebu_host->cs_num) |
385 HSNAND_CTL_ENABLE_ECC | HSNAND_CTL_GO | val,
386 ebu_host->hsnand + HSNAND_CTL);
387 }
388
ebu_nand_read_page_hwecc(struct nand_chip * chip,u8 * buf,int oob_required,int page)389 static int ebu_nand_read_page_hwecc(struct nand_chip *chip, u8 *buf,
390 int oob_required, int page)
391 {
392 struct mtd_info *mtd = nand_to_mtd(chip);
393 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
394 int ret, reg_data;
395
396 ebu_nand_trigger(ebu_host, page, NAND_CMD_READ0);
397
398 ret = ebu_dma_start(ebu_host, DMA_DEV_TO_MEM, buf, mtd->writesize);
399 if (ret)
400 return ret;
401
402 if (oob_required)
403 chip->ecc.read_oob(chip, page);
404
405 reg_data = readl(ebu_host->hsnand + HSNAND_CTL);
406 reg_data &= ~HSNAND_CTL_GO;
407 writel(reg_data, ebu_host->hsnand + HSNAND_CTL);
408
409 return 0;
410 }
411
ebu_nand_write_page_hwecc(struct nand_chip * chip,const u8 * buf,int oob_required,int page)412 static int ebu_nand_write_page_hwecc(struct nand_chip *chip, const u8 *buf,
413 int oob_required, int page)
414 {
415 struct mtd_info *mtd = nand_to_mtd(chip);
416 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
417 void __iomem *int_sta = ebu_host->hsnand + HSNAND_INT_STA;
418 int reg_data, ret, val;
419 u32 reg;
420
421 ebu_nand_trigger(ebu_host, page, NAND_CMD_SEQIN);
422
423 ret = ebu_dma_start(ebu_host, DMA_MEM_TO_DEV, buf, mtd->writesize);
424 if (ret)
425 return ret;
426
427 if (oob_required) {
428 reg = get_unaligned_le32(chip->oob_poi);
429 writel(reg, ebu_host->hsnand + HSNAND_CMSG_0);
430
431 reg = get_unaligned_le32(chip->oob_poi + 4);
432 writel(reg, ebu_host->hsnand + HSNAND_CMSG_1);
433 }
434
435 ret = readl_poll_timeout_atomic(int_sta, val, !(val & HSNAND_INT_STA_WR_C),
436 10, 1000);
437 if (ret)
438 return ret;
439
440 reg_data = readl(ebu_host->hsnand + HSNAND_CTL);
441 reg_data &= ~HSNAND_CTL_GO;
442 writel(reg_data, ebu_host->hsnand + HSNAND_CTL);
443
444 return 0;
445 }
446
447 static const u8 ecc_strength[] = { 1, 1, 4, 8, 24, 32, 40, 60, };
448
ebu_nand_attach_chip(struct nand_chip * chip)449 static int ebu_nand_attach_chip(struct nand_chip *chip)
450 {
451 struct mtd_info *mtd = nand_to_mtd(chip);
452 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
453 u32 ecc_steps, ecc_bytes, ecc_total, pagesize, pg_per_blk;
454 u32 ecc_strength_ds = chip->ecc.strength;
455 u32 ecc_size = chip->ecc.size;
456 u32 writesize = mtd->writesize;
457 u32 blocksize = mtd->erasesize;
458 int bch_algo, start, val;
459
460 /* Default to an ECC size of 512 */
461 if (!chip->ecc.size)
462 chip->ecc.size = 512;
463
464 switch (ecc_size) {
465 case 512:
466 start = 1;
467 if (!ecc_strength_ds)
468 ecc_strength_ds = 4;
469 break;
470 case 1024:
471 start = 4;
472 if (!ecc_strength_ds)
473 ecc_strength_ds = 32;
474 break;
475 default:
476 return -EINVAL;
477 }
478
479 /* BCH ECC algorithm Settings for number of bits per 512B/1024B */
480 bch_algo = round_up(start + 1, 4);
481 for (val = start; val < bch_algo; val++) {
482 if (ecc_strength_ds == ecc_strength[val])
483 break;
484 }
485 if (val == bch_algo)
486 return -EINVAL;
487
488 if (ecc_strength_ds == 8)
489 ecc_bytes = 14;
490 else
491 ecc_bytes = DIV_ROUND_UP(ecc_strength_ds * fls(8 * ecc_size), 8);
492
493 ecc_steps = writesize / ecc_size;
494 ecc_total = ecc_steps * ecc_bytes;
495 if ((ecc_total + 8) > mtd->oobsize)
496 return -ERANGE;
497
498 chip->ecc.total = ecc_total;
499 pagesize = fls(writesize >> 11);
500 if (pagesize > HSNAND_PARA0_PAGE_V8192)
501 return -ERANGE;
502
503 pg_per_blk = fls((blocksize / writesize) >> 6) / 8;
504 if (pg_per_blk > HSNAND_PARA0_PIB_V256)
505 return -ERANGE;
506
507 ebu_host->nd_para0 = pagesize | pg_per_blk | HSNAND_PARA0_BYP_EN_NP |
508 HSNAND_PARA0_BYP_DEC_NP | HSNAND_PARA0_ADEP_EN |
509 HSNAND_PARA0_TYPE_ONFI | (val << 29);
510
511 mtd_set_ooblayout(mtd, &ebu_nand_ooblayout_ops);
512 chip->ecc.read_page = ebu_nand_read_page_hwecc;
513 chip->ecc.write_page = ebu_nand_write_page_hwecc;
514
515 return 0;
516 }
517
ebu_nand_exec_op(struct nand_chip * chip,const struct nand_operation * op,bool check_only)518 static int ebu_nand_exec_op(struct nand_chip *chip,
519 const struct nand_operation *op, bool check_only)
520 {
521 const struct nand_op_instr *instr = NULL;
522 unsigned int op_id;
523 int i, timeout_ms, ret = 0;
524
525 if (check_only)
526 return 0;
527
528 ebu_select_chip(chip);
529 for (op_id = 0; op_id < op->ninstrs; op_id++) {
530 instr = &op->instrs[op_id];
531
532 switch (instr->type) {
533 case NAND_OP_CMD_INSTR:
534 ebu_nand_writeb(chip, HSNAND_CLE_OFFS | HSNAND_CS_OFFS,
535 instr->ctx.cmd.opcode);
536 break;
537
538 case NAND_OP_ADDR_INSTR:
539 for (i = 0; i < instr->ctx.addr.naddrs; i++)
540 ebu_nand_writeb(chip,
541 HSNAND_ALE_OFFS | HSNAND_CS_OFFS,
542 instr->ctx.addr.addrs[i]);
543 break;
544
545 case NAND_OP_DATA_IN_INSTR:
546 ebu_read_buf(chip, instr->ctx.data.buf.in,
547 instr->ctx.data.len);
548 break;
549
550 case NAND_OP_DATA_OUT_INSTR:
551 ebu_write_buf(chip, instr->ctx.data.buf.out,
552 instr->ctx.data.len);
553 break;
554
555 case NAND_OP_WAITRDY_INSTR:
556 timeout_ms = instr->ctx.waitrdy.timeout_ms * 1000;
557 ret = ebu_nand_waitrdy(chip, timeout_ms);
558 break;
559 }
560 }
561
562 return ret;
563 }
564
565 static const struct nand_controller_ops ebu_nand_controller_ops = {
566 .attach_chip = ebu_nand_attach_chip,
567 .setup_interface = ebu_nand_set_timings,
568 .exec_op = ebu_nand_exec_op,
569 };
570
ebu_dma_cleanup(struct ebu_nand_controller * ebu_host)571 static void ebu_dma_cleanup(struct ebu_nand_controller *ebu_host)
572 {
573 if (ebu_host->dma_rx)
574 dma_release_channel(ebu_host->dma_rx);
575
576 if (ebu_host->dma_tx)
577 dma_release_channel(ebu_host->dma_tx);
578 }
579
ebu_nand_probe(struct platform_device * pdev)580 static int ebu_nand_probe(struct platform_device *pdev)
581 {
582 struct device *dev = &pdev->dev;
583 struct ebu_nand_controller *ebu_host;
584 struct device_node *chip_np;
585 struct nand_chip *nand;
586 struct mtd_info *mtd;
587 struct resource *res;
588 char *resname;
589 int ret;
590 u32 cs;
591
592 ebu_host = devm_kzalloc(dev, sizeof(*ebu_host), GFP_KERNEL);
593 if (!ebu_host)
594 return -ENOMEM;
595
596 ebu_host->dev = dev;
597 nand_controller_init(&ebu_host->controller);
598
599 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ebunand");
600 ebu_host->ebu = devm_ioremap_resource(&pdev->dev, res);
601 if (IS_ERR(ebu_host->ebu))
602 return PTR_ERR(ebu_host->ebu);
603
604 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsnand");
605 ebu_host->hsnand = devm_ioremap_resource(&pdev->dev, res);
606 if (IS_ERR(ebu_host->hsnand))
607 return PTR_ERR(ebu_host->hsnand);
608
609 chip_np = of_get_next_child(dev->of_node, NULL);
610 if (!chip_np)
611 return dev_err_probe(dev, -EINVAL,
612 "Could not find child node for the NAND chip\n");
613
614 ret = of_property_read_u32(chip_np, "reg", &cs);
615 if (ret) {
616 dev_err(dev, "failed to get chip select: %d\n", ret);
617 goto err_of_node_put;
618 }
619 if (cs >= MAX_CS) {
620 dev_err(dev, "got invalid chip select: %d\n", cs);
621 ret = -EINVAL;
622 goto err_of_node_put;
623 }
624
625 ebu_host->cs_num = cs;
626
627 resname = devm_kasprintf(dev, GFP_KERNEL, "nand_cs%d", cs);
628 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, resname);
629 ebu_host->cs[cs].chipaddr = devm_ioremap_resource(dev, res);
630 if (IS_ERR(ebu_host->cs[cs].chipaddr))
631 goto err_of_node_put;
632 ebu_host->cs[cs].nand_pa = res->start;
633
634 ebu_host->clk = devm_clk_get(dev, NULL);
635 if (IS_ERR(ebu_host->clk)) {
636 ret = dev_err_probe(dev, PTR_ERR(ebu_host->clk),
637 "failed to get clock\n");
638 goto err_of_node_put;
639 }
640
641 ret = clk_prepare_enable(ebu_host->clk);
642 if (ret) {
643 dev_err(dev, "failed to enable clock: %d\n", ret);
644 goto err_of_node_put;
645 }
646 ebu_host->clk_rate = clk_get_rate(ebu_host->clk);
647
648 ebu_host->dma_tx = dma_request_chan(dev, "tx");
649 if (IS_ERR(ebu_host->dma_tx)) {
650 ret = dev_err_probe(dev, PTR_ERR(ebu_host->dma_tx),
651 "failed to request DMA tx chan!.\n");
652 goto err_disable_unprepare_clk;
653 }
654
655 ebu_host->dma_rx = dma_request_chan(dev, "rx");
656 if (IS_ERR(ebu_host->dma_rx)) {
657 ret = dev_err_probe(dev, PTR_ERR(ebu_host->dma_rx),
658 "failed to request DMA rx chan!.\n");
659 ebu_host->dma_rx = NULL;
660 goto err_cleanup_dma;
661 }
662
663 resname = devm_kasprintf(dev, GFP_KERNEL, "addr_sel%d", cs);
664 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, resname);
665 if (!res) {
666 ret = -EINVAL;
667 goto err_cleanup_dma;
668 }
669 ebu_host->cs[cs].addr_sel = res->start;
670 writel(ebu_host->cs[cs].addr_sel | EBU_ADDR_MASK(5) | EBU_ADDR_SEL_REGEN,
671 ebu_host->ebu + EBU_ADDR_SEL(cs));
672
673 nand_set_flash_node(&ebu_host->chip, chip_np);
674
675 mtd = nand_to_mtd(&ebu_host->chip);
676 if (!mtd->name) {
677 dev_err(ebu_host->dev, "NAND label property is mandatory\n");
678 ret = -EINVAL;
679 goto err_cleanup_dma;
680 }
681
682 mtd->dev.parent = dev;
683 ebu_host->dev = dev;
684
685 platform_set_drvdata(pdev, ebu_host);
686 nand_set_controller_data(&ebu_host->chip, ebu_host);
687
688 nand = &ebu_host->chip;
689 nand->controller = &ebu_host->controller;
690 nand->controller->ops = &ebu_nand_controller_ops;
691
692 /* Scan to find existence of the device */
693 ret = nand_scan(&ebu_host->chip, 1);
694 if (ret)
695 goto err_cleanup_dma;
696
697 ret = mtd_device_register(mtd, NULL, 0);
698 if (ret)
699 goto err_clean_nand;
700
701 return 0;
702
703 err_clean_nand:
704 nand_cleanup(&ebu_host->chip);
705 err_cleanup_dma:
706 ebu_dma_cleanup(ebu_host);
707 err_disable_unprepare_clk:
708 clk_disable_unprepare(ebu_host->clk);
709 err_of_node_put:
710 of_node_put(chip_np);
711
712 return ret;
713 }
714
ebu_nand_remove(struct platform_device * pdev)715 static int ebu_nand_remove(struct platform_device *pdev)
716 {
717 struct ebu_nand_controller *ebu_host = platform_get_drvdata(pdev);
718 int ret;
719
720 ret = mtd_device_unregister(nand_to_mtd(&ebu_host->chip));
721 WARN_ON(ret);
722 nand_cleanup(&ebu_host->chip);
723 ebu_nand_disable(&ebu_host->chip);
724 ebu_dma_cleanup(ebu_host);
725 clk_disable_unprepare(ebu_host->clk);
726
727 return 0;
728 }
729
730 static const struct of_device_id ebu_nand_match[] = {
731 { .compatible = "intel,lgm-ebunand" },
732 {}
733 };
734 MODULE_DEVICE_TABLE(of, ebu_nand_match);
735
736 static struct platform_driver ebu_nand_driver = {
737 .probe = ebu_nand_probe,
738 .remove = ebu_nand_remove,
739 .driver = {
740 .name = "intel-nand-controller",
741 .of_match_table = ebu_nand_match,
742 },
743
744 };
745 module_platform_driver(ebu_nand_driver);
746
747 MODULE_LICENSE("GPL v2");
748 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
749 MODULE_DESCRIPTION("Intel's LGM External Bus NAND Controller driver");
750