1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S 4 * 5 * Copyright (C) 1996-2000 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASSEMBLY__ 9 #error "Only include this from assembly code" 10 #endif 11 12 #ifndef __ASM_ASSEMBLER_H 13 #define __ASM_ASSEMBLER_H 14 15 #include <asm-generic/export.h> 16 17 #include <asm/asm-offsets.h> 18 #include <asm/alternative.h> 19 #include <asm/asm-bug.h> 20 #include <asm/cpufeature.h> 21 #include <asm/cputype.h> 22 #include <asm/debug-monitors.h> 23 #include <asm/page.h> 24 #include <asm/pgtable-hwdef.h> 25 #include <asm/ptrace.h> 26 #include <asm/thread_info.h> 27 28 /* 29 * Provide a wxN alias for each wN register so what we can paste a xN 30 * reference after a 'w' to obtain the 32-bit version. 31 */ 32 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 33 wx\n .req w\n 34 .endr 35 36 .macro save_and_disable_daif, flags 37 mrs \flags, daif 38 msr daifset, #0xf 39 .endm 40 41 .macro disable_daif 42 msr daifset, #0xf 43 .endm 44 45 .macro enable_daif 46 msr daifclr, #0xf 47 .endm 48 49 .macro restore_daif, flags:req 50 msr daif, \flags 51 .endm 52 53 /* IRQ/FIQ are the lowest priority flags, unconditionally unmask the rest. */ 54 .macro enable_da 55 msr daifclr, #(8 | 4) 56 .endm 57 58 /* 59 * Save/restore interrupts. 60 */ 61 .macro save_and_disable_irq, flags 62 mrs \flags, daif 63 msr daifset, #3 64 .endm 65 66 .macro restore_irq, flags 67 msr daif, \flags 68 .endm 69 70 .macro enable_dbg 71 msr daifclr, #8 72 .endm 73 74 .macro disable_step_tsk, flgs, tmp 75 tbz \flgs, #TIF_SINGLESTEP, 9990f 76 mrs \tmp, mdscr_el1 77 bic \tmp, \tmp, #DBG_MDSCR_SS 78 msr mdscr_el1, \tmp 79 isb // Synchronise with enable_dbg 80 9990: 81 .endm 82 83 /* call with daif masked */ 84 .macro enable_step_tsk, flgs, tmp 85 tbz \flgs, #TIF_SINGLESTEP, 9990f 86 mrs \tmp, mdscr_el1 87 orr \tmp, \tmp, #DBG_MDSCR_SS 88 msr mdscr_el1, \tmp 89 9990: 90 .endm 91 92 /* 93 * RAS Error Synchronization barrier 94 */ 95 .macro esb 96 #ifdef CONFIG_ARM64_RAS_EXTN 97 hint #16 98 #else 99 nop 100 #endif 101 .endm 102 103 /* 104 * Value prediction barrier 105 */ 106 .macro csdb 107 hint #20 108 .endm 109 110 /* 111 * Clear Branch History instruction 112 */ 113 .macro clearbhb 114 hint #22 115 .endm 116 117 /* 118 * Speculation barrier 119 */ 120 .macro sb 121 alternative_if_not ARM64_HAS_SB 122 dsb nsh 123 isb 124 alternative_else 125 SB_BARRIER_INSN 126 nop 127 alternative_endif 128 .endm 129 130 /* 131 * NOP sequence 132 */ 133 .macro nops, num 134 .rept \num 135 nop 136 .endr 137 .endm 138 139 /* 140 * Create an exception table entry for `insn`, which will branch to `fixup` 141 * when an unhandled fault is taken. 142 */ 143 .macro _asm_extable, insn, fixup 144 .pushsection __ex_table, "a" 145 .align 3 146 .long (\insn - .), (\fixup - .) 147 .popsection 148 .endm 149 150 /* 151 * Create an exception table entry for `insn` if `fixup` is provided. Otherwise 152 * do nothing. 153 */ 154 .macro _cond_extable, insn, fixup 155 .ifnc \fixup, 156 _asm_extable \insn, \fixup 157 .endif 158 .endm 159 160 161 #define USER(l, x...) \ 162 9999: x; \ 163 _asm_extable 9999b, l 164 165 /* 166 * Register aliases. 167 */ 168 lr .req x30 // link register 169 170 /* 171 * Vector entry 172 */ 173 .macro ventry label 174 .align 7 175 b \label 176 .endm 177 178 /* 179 * Select code when configured for BE. 180 */ 181 #ifdef CONFIG_CPU_BIG_ENDIAN 182 #define CPU_BE(code...) code 183 #else 184 #define CPU_BE(code...) 185 #endif 186 187 /* 188 * Select code when configured for LE. 189 */ 190 #ifdef CONFIG_CPU_BIG_ENDIAN 191 #define CPU_LE(code...) 192 #else 193 #define CPU_LE(code...) code 194 #endif 195 196 /* 197 * Define a macro that constructs a 64-bit value by concatenating two 198 * 32-bit registers. Note that on big endian systems the order of the 199 * registers is swapped. 200 */ 201 #ifndef CONFIG_CPU_BIG_ENDIAN 202 .macro regs_to_64, rd, lbits, hbits 203 #else 204 .macro regs_to_64, rd, hbits, lbits 205 #endif 206 orr \rd, \lbits, \hbits, lsl #32 207 .endm 208 209 /* 210 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where 211 * <symbol> is within the range +/- 4 GB of the PC. 212 */ 213 /* 214 * @dst: destination register (64 bit wide) 215 * @sym: name of the symbol 216 */ 217 .macro adr_l, dst, sym 218 adrp \dst, \sym 219 add \dst, \dst, :lo12:\sym 220 .endm 221 222 /* 223 * @dst: destination register (32 or 64 bit wide) 224 * @sym: name of the symbol 225 * @tmp: optional 64-bit scratch register to be used if <dst> is a 226 * 32-bit wide register, in which case it cannot be used to hold 227 * the address 228 */ 229 .macro ldr_l, dst, sym, tmp= 230 .ifb \tmp 231 adrp \dst, \sym 232 ldr \dst, [\dst, :lo12:\sym] 233 .else 234 adrp \tmp, \sym 235 ldr \dst, [\tmp, :lo12:\sym] 236 .endif 237 .endm 238 239 /* 240 * @src: source register (32 or 64 bit wide) 241 * @sym: name of the symbol 242 * @tmp: mandatory 64-bit scratch register to calculate the address 243 * while <src> needs to be preserved. 244 */ 245 .macro str_l, src, sym, tmp 246 adrp \tmp, \sym 247 str \src, [\tmp, :lo12:\sym] 248 .endm 249 250 /* 251 * @dst: destination register 252 */ 253 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 254 .macro get_this_cpu_offset, dst 255 mrs \dst, tpidr_el2 256 .endm 257 #else 258 .macro get_this_cpu_offset, dst 259 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN 260 mrs \dst, tpidr_el1 261 alternative_else 262 mrs \dst, tpidr_el2 263 alternative_endif 264 .endm 265 266 .macro set_this_cpu_offset, src 267 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN 268 msr tpidr_el1, \src 269 alternative_else 270 msr tpidr_el2, \src 271 alternative_endif 272 .endm 273 #endif 274 275 /* 276 * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP) 277 * @sym: The name of the per-cpu variable 278 * @tmp: scratch register 279 */ 280 .macro adr_this_cpu, dst, sym, tmp 281 adrp \tmp, \sym 282 add \dst, \tmp, #:lo12:\sym 283 get_this_cpu_offset \tmp 284 add \dst, \dst, \tmp 285 .endm 286 287 /* 288 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id())) 289 * @sym: The name of the per-cpu variable 290 * @tmp: scratch register 291 */ 292 .macro ldr_this_cpu dst, sym, tmp 293 adr_l \dst, \sym 294 get_this_cpu_offset \tmp 295 ldr \dst, [\dst, \tmp] 296 .endm 297 298 /* 299 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm) 300 */ 301 .macro vma_vm_mm, rd, rn 302 ldr \rd, [\rn, #VMA_VM_MM] 303 .endm 304 305 /* 306 * read_ctr - read CTR_EL0. If the system has mismatched register fields, 307 * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val 308 */ 309 .macro read_ctr, reg 310 #ifndef __KVM_NVHE_HYPERVISOR__ 311 alternative_if_not ARM64_MISMATCHED_CACHE_TYPE 312 mrs \reg, ctr_el0 // read CTR 313 nop 314 alternative_else 315 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL 316 alternative_endif 317 #else 318 alternative_if_not ARM64_KVM_PROTECTED_MODE 319 ASM_BUG() 320 alternative_else_nop_endif 321 alternative_cb kvm_compute_final_ctr_el0 322 movz \reg, #0 323 movk \reg, #0, lsl #16 324 movk \reg, #0, lsl #32 325 movk \reg, #0, lsl #48 326 alternative_cb_end 327 #endif 328 .endm 329 330 331 /* 332 * raw_dcache_line_size - get the minimum D-cache line size on this CPU 333 * from the CTR register. 334 */ 335 .macro raw_dcache_line_size, reg, tmp 336 mrs \tmp, ctr_el0 // read CTR 337 ubfm \tmp, \tmp, #16, #19 // cache line size encoding 338 mov \reg, #4 // bytes per word 339 lsl \reg, \reg, \tmp // actual cache line size 340 .endm 341 342 /* 343 * dcache_line_size - get the safe D-cache line size across all CPUs 344 */ 345 .macro dcache_line_size, reg, tmp 346 read_ctr \tmp 347 ubfm \tmp, \tmp, #16, #19 // cache line size encoding 348 mov \reg, #4 // bytes per word 349 lsl \reg, \reg, \tmp // actual cache line size 350 .endm 351 352 /* 353 * raw_icache_line_size - get the minimum I-cache line size on this CPU 354 * from the CTR register. 355 */ 356 .macro raw_icache_line_size, reg, tmp 357 mrs \tmp, ctr_el0 // read CTR 358 and \tmp, \tmp, #0xf // cache line size encoding 359 mov \reg, #4 // bytes per word 360 lsl \reg, \reg, \tmp // actual cache line size 361 .endm 362 363 /* 364 * icache_line_size - get the safe I-cache line size across all CPUs 365 */ 366 .macro icache_line_size, reg, tmp 367 read_ctr \tmp 368 and \tmp, \tmp, #0xf // cache line size encoding 369 mov \reg, #4 // bytes per word 370 lsl \reg, \reg, \tmp // actual cache line size 371 .endm 372 373 /* 374 * tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map 375 */ 376 .macro tcr_set_t0sz, valreg, t0sz 377 bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH 378 .endm 379 380 /* 381 * tcr_set_t1sz - update TCR.T1SZ 382 */ 383 .macro tcr_set_t1sz, valreg, t1sz 384 bfi \valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH 385 .endm 386 387 /* 388 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported 389 * ID_AA64MMFR0_EL1.PARange value 390 * 391 * tcr: register with the TCR_ELx value to be updated 392 * pos: IPS or PS bitfield position 393 * tmp{0,1}: temporary registers 394 */ 395 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1 396 mrs \tmp0, ID_AA64MMFR0_EL1 397 // Narrow PARange to fit the PS field in TCR_ELx 398 ubfx \tmp0, \tmp0, #ID_AA64MMFR0_EL1_PARANGE_SHIFT, #3 399 mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_MAX 400 cmp \tmp0, \tmp1 401 csel \tmp0, \tmp1, \tmp0, hi 402 bfi \tcr, \tmp0, \pos, #3 403 .endm 404 405 .macro __dcache_op_workaround_clean_cache, op, addr 406 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE 407 dc \op, \addr 408 alternative_else 409 dc civac, \addr 410 alternative_endif 411 .endm 412 413 /* 414 * Macro to perform a data cache maintenance for the interval 415 * [start, end) 416 * 417 * op: operation passed to dc instruction 418 * domain: domain used in dsb instruciton 419 * start: starting virtual address of the region 420 * end: end virtual address of the region 421 * fixup: optional label to branch to on user fault 422 * Corrupts: start, end, tmp1, tmp2 423 */ 424 .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup 425 dcache_line_size \tmp1, \tmp2 426 sub \tmp2, \tmp1, #1 427 bic \start, \start, \tmp2 428 .Ldcache_op\@: 429 .ifc \op, cvau 430 __dcache_op_workaround_clean_cache \op, \start 431 .else 432 .ifc \op, cvac 433 __dcache_op_workaround_clean_cache \op, \start 434 .else 435 .ifc \op, cvap 436 sys 3, c7, c12, 1, \start // dc cvap 437 .else 438 .ifc \op, cvadp 439 sys 3, c7, c13, 1, \start // dc cvadp 440 .else 441 dc \op, \start 442 .endif 443 .endif 444 .endif 445 .endif 446 add \start, \start, \tmp1 447 cmp \start, \end 448 b.lo .Ldcache_op\@ 449 dsb \domain 450 451 _cond_extable .Ldcache_op\@, \fixup 452 .endm 453 454 /* 455 * Macro to perform an instruction cache maintenance for the interval 456 * [start, end) 457 * 458 * start, end: virtual addresses describing the region 459 * fixup: optional label to branch to on user fault 460 * Corrupts: tmp1, tmp2 461 */ 462 .macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup 463 icache_line_size \tmp1, \tmp2 464 sub \tmp2, \tmp1, #1 465 bic \tmp2, \start, \tmp2 466 .Licache_op\@: 467 ic ivau, \tmp2 // invalidate I line PoU 468 add \tmp2, \tmp2, \tmp1 469 cmp \tmp2, \end 470 b.lo .Licache_op\@ 471 dsb ish 472 isb 473 474 _cond_extable .Licache_op\@, \fixup 475 .endm 476 477 /* 478 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present 479 */ 480 .macro reset_pmuserenr_el0, tmpreg 481 mrs \tmpreg, id_aa64dfr0_el1 482 sbfx \tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 483 cmp \tmpreg, #1 // Skip if no PMU present 484 b.lt 9000f 485 msr pmuserenr_el0, xzr // Disable PMU access from EL0 486 9000: 487 .endm 488 489 /* 490 * reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present 491 */ 492 .macro reset_amuserenr_el0, tmpreg 493 mrs \tmpreg, id_aa64pfr0_el1 // Check ID_AA64PFR0_EL1 494 ubfx \tmpreg, \tmpreg, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 495 cbz \tmpreg, .Lskip_\@ // Skip if no AMU present 496 msr_s SYS_AMUSERENR_EL0, xzr // Disable AMU access from EL0 497 .Lskip_\@: 498 .endm 499 /* 500 * copy_page - copy src to dest using temp registers t1-t8 501 */ 502 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req 503 9998: ldp \t1, \t2, [\src] 504 ldp \t3, \t4, [\src, #16] 505 ldp \t5, \t6, [\src, #32] 506 ldp \t7, \t8, [\src, #48] 507 add \src, \src, #64 508 stnp \t1, \t2, [\dest] 509 stnp \t3, \t4, [\dest, #16] 510 stnp \t5, \t6, [\dest, #32] 511 stnp \t7, \t8, [\dest, #48] 512 add \dest, \dest, #64 513 tst \src, #(PAGE_SIZE - 1) 514 b.ne 9998b 515 .endm 516 517 /* 518 * Annotate a function as being unsuitable for kprobes. 519 */ 520 #ifdef CONFIG_KPROBES 521 #define NOKPROBE(x) \ 522 .pushsection "_kprobe_blacklist", "aw"; \ 523 .quad x; \ 524 .popsection; 525 #else 526 #define NOKPROBE(x) 527 #endif 528 529 #if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS) 530 #define EXPORT_SYMBOL_NOKASAN(name) 531 #else 532 #define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name) 533 #endif 534 535 #ifdef CONFIG_KASAN_HW_TAGS 536 #define EXPORT_SYMBOL_NOHWKASAN(name) 537 #else 538 #define EXPORT_SYMBOL_NOHWKASAN(name) EXPORT_SYMBOL_NOKASAN(name) 539 #endif 540 /* 541 * Emit a 64-bit absolute little endian symbol reference in a way that 542 * ensures that it will be resolved at build time, even when building a 543 * PIE binary. This requires cooperation from the linker script, which 544 * must emit the lo32/hi32 halves individually. 545 */ 546 .macro le64sym, sym 547 .long \sym\()_lo32 548 .long \sym\()_hi32 549 .endm 550 551 /* 552 * mov_q - move an immediate constant into a 64-bit register using 553 * between 2 and 4 movz/movk instructions (depending on the 554 * magnitude and sign of the operand) 555 */ 556 .macro mov_q, reg, val 557 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff) 558 movz \reg, :abs_g1_s:\val 559 .else 560 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff) 561 movz \reg, :abs_g2_s:\val 562 .else 563 movz \reg, :abs_g3:\val 564 movk \reg, :abs_g2_nc:\val 565 .endif 566 movk \reg, :abs_g1_nc:\val 567 .endif 568 movk \reg, :abs_g0_nc:\val 569 .endm 570 571 /* 572 * Return the current task_struct. 573 */ 574 .macro get_current_task, rd 575 mrs \rd, sp_el0 576 .endm 577 578 /* 579 * Offset ttbr1 to allow for 48-bit kernel VAs set with 52-bit PTRS_PER_PGD. 580 * orr is used as it can cover the immediate value (and is idempotent). 581 * In future this may be nop'ed out when dealing with 52-bit kernel VAs. 582 * ttbr: Value of ttbr to set, modified. 583 */ 584 .macro offset_ttbr1, ttbr, tmp 585 #ifdef CONFIG_ARM64_VA_BITS_52 586 mrs_s \tmp, SYS_ID_AA64MMFR2_EL1 587 and \tmp, \tmp, #(0xf << ID_AA64MMFR2_EL1_VARange_SHIFT) 588 cbnz \tmp, .Lskipoffs_\@ 589 orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET 590 .Lskipoffs_\@ : 591 #endif 592 .endm 593 594 /* 595 * Perform the reverse of offset_ttbr1. 596 * bic is used as it can cover the immediate value and, in future, won't need 597 * to be nop'ed out when dealing with 52-bit kernel VAs. 598 */ 599 .macro restore_ttbr1, ttbr 600 #ifdef CONFIG_ARM64_VA_BITS_52 601 bic \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET 602 #endif 603 .endm 604 605 /* 606 * Arrange a physical address in a TTBR register, taking care of 52-bit 607 * addresses. 608 * 609 * phys: physical address, preserved 610 * ttbr: returns the TTBR value 611 */ 612 .macro phys_to_ttbr, ttbr, phys 613 #ifdef CONFIG_ARM64_PA_BITS_52 614 orr \ttbr, \phys, \phys, lsr #46 615 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52 616 #else 617 mov \ttbr, \phys 618 #endif 619 .endm 620 621 .macro phys_to_pte, pte, phys 622 #ifdef CONFIG_ARM64_PA_BITS_52 623 /* 624 * We assume \phys is 64K aligned and this is guaranteed by only 625 * supporting this configuration with 64K pages. 626 */ 627 orr \pte, \phys, \phys, lsr #36 628 and \pte, \pte, #PTE_ADDR_MASK 629 #else 630 mov \pte, \phys 631 #endif 632 .endm 633 634 .macro pte_to_phys, phys, pte 635 #ifdef CONFIG_ARM64_PA_BITS_52 636 ubfiz \phys, \pte, #(48 - 16 - 12), #16 637 bfxil \phys, \pte, #16, #32 638 lsl \phys, \phys, #16 639 #else 640 and \phys, \pte, #PTE_ADDR_MASK 641 #endif 642 .endm 643 644 /* 645 * tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU. 646 */ 647 .macro tcr_clear_errata_bits, tcr, tmp1, tmp2 648 #ifdef CONFIG_FUJITSU_ERRATUM_010001 649 mrs \tmp1, midr_el1 650 651 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK 652 and \tmp1, \tmp1, \tmp2 653 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001 654 cmp \tmp1, \tmp2 655 b.ne 10f 656 657 mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001 658 bic \tcr, \tcr, \tmp2 659 10: 660 #endif /* CONFIG_FUJITSU_ERRATUM_010001 */ 661 .endm 662 663 /** 664 * Errata workaround prior to disable MMU. Insert an ISB immediately prior 665 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0. 666 */ 667 .macro pre_disable_mmu_workaround 668 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041 669 isb 670 #endif 671 .endm 672 673 /* 674 * frame_push - Push @regcount callee saved registers to the stack, 675 * starting at x19, as well as x29/x30, and set x29 to 676 * the new value of sp. Add @extra bytes of stack space 677 * for locals. 678 */ 679 .macro frame_push, regcount:req, extra 680 __frame st, \regcount, \extra 681 .endm 682 683 /* 684 * frame_pop - Pop the callee saved registers from the stack that were 685 * pushed in the most recent call to frame_push, as well 686 * as x29/x30 and any extra stack space that may have been 687 * allocated. 688 */ 689 .macro frame_pop 690 __frame ld 691 .endm 692 693 .macro __frame_regs, reg1, reg2, op, num 694 .if .Lframe_regcount == \num 695 \op\()r \reg1, [sp, #(\num + 1) * 8] 696 .elseif .Lframe_regcount > \num 697 \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8] 698 .endif 699 .endm 700 701 .macro __frame, op, regcount, extra=0 702 .ifc \op, st 703 .if (\regcount) < 0 || (\regcount) > 10 704 .error "regcount should be in the range [0 ... 10]" 705 .endif 706 .if ((\extra) % 16) != 0 707 .error "extra should be a multiple of 16 bytes" 708 .endif 709 .ifdef .Lframe_regcount 710 .if .Lframe_regcount != -1 711 .error "frame_push/frame_pop may not be nested" 712 .endif 713 .endif 714 .set .Lframe_regcount, \regcount 715 .set .Lframe_extra, \extra 716 .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16 717 stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]! 718 mov x29, sp 719 .endif 720 721 __frame_regs x19, x20, \op, 1 722 __frame_regs x21, x22, \op, 3 723 __frame_regs x23, x24, \op, 5 724 __frame_regs x25, x26, \op, 7 725 __frame_regs x27, x28, \op, 9 726 727 .ifc \op, ld 728 .if .Lframe_regcount == -1 729 .error "frame_push/frame_pop may not be nested" 730 .endif 731 ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra 732 .set .Lframe_regcount, -1 733 .endif 734 .endm 735 736 /* 737 * Set SCTLR_ELx to the @reg value, and invalidate the local icache 738 * in the process. This is called when setting the MMU on. 739 */ 740 .macro set_sctlr, sreg, reg 741 msr \sreg, \reg 742 isb 743 /* 744 * Invalidate the local I-cache so that any instructions fetched 745 * speculatively from the PoC are discarded, since they may have 746 * been dynamically patched at the PoU. 747 */ 748 ic iallu 749 dsb nsh 750 isb 751 .endm 752 753 .macro set_sctlr_el1, reg 754 set_sctlr sctlr_el1, \reg 755 .endm 756 757 .macro set_sctlr_el2, reg 758 set_sctlr sctlr_el2, \reg 759 .endm 760 761 /* 762 * Check whether preempt/bh-disabled asm code should yield as soon as 763 * it is able. This is the case if we are currently running in task 764 * context, and either a softirq is pending, or the TIF_NEED_RESCHED 765 * flag is set and re-enabling preemption a single time would result in 766 * a preempt count of zero. (Note that the TIF_NEED_RESCHED flag is 767 * stored negated in the top word of the thread_info::preempt_count 768 * field) 769 */ 770 .macro cond_yield, lbl:req, tmp:req, tmp2:req 771 get_current_task \tmp 772 ldr \tmp, [\tmp, #TSK_TI_PREEMPT] 773 /* 774 * If we are serving a softirq, there is no point in yielding: the 775 * softirq will not be preempted no matter what we do, so we should 776 * run to completion as quickly as we can. 777 */ 778 tbnz \tmp, #SOFTIRQ_SHIFT, .Lnoyield_\@ 779 #ifdef CONFIG_PREEMPTION 780 sub \tmp, \tmp, #PREEMPT_DISABLE_OFFSET 781 cbz \tmp, \lbl 782 #endif 783 adr_l \tmp, irq_stat + IRQ_CPUSTAT_SOFTIRQ_PENDING 784 get_this_cpu_offset \tmp2 785 ldr w\tmp, [\tmp, \tmp2] 786 cbnz w\tmp, \lbl // yield on pending softirq in task context 787 .Lnoyield_\@: 788 .endm 789 790 /* 791 * Branch Target Identifier (BTI) 792 */ 793 .macro bti, targets 794 .equ .L__bti_targets_c, 34 795 .equ .L__bti_targets_j, 36 796 .equ .L__bti_targets_jc,38 797 hint #.L__bti_targets_\targets 798 .endm 799 800 /* 801 * This macro emits a program property note section identifying 802 * architecture features which require special handling, mainly for 803 * use in assembly files included in the VDSO. 804 */ 805 806 #define NT_GNU_PROPERTY_TYPE_0 5 807 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000 808 809 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0) 810 #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1) 811 812 #ifdef CONFIG_ARM64_BTI_KERNEL 813 #define GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT \ 814 ((GNU_PROPERTY_AARCH64_FEATURE_1_BTI | \ 815 GNU_PROPERTY_AARCH64_FEATURE_1_PAC)) 816 #endif 817 818 #ifdef GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT 819 .macro emit_aarch64_feature_1_and, feat=GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT 820 .pushsection .note.gnu.property, "a" 821 .align 3 822 .long 2f - 1f 823 .long 6f - 3f 824 .long NT_GNU_PROPERTY_TYPE_0 825 1: .string "GNU" 826 2: 827 .align 3 828 3: .long GNU_PROPERTY_AARCH64_FEATURE_1_AND 829 .long 5f - 4f 830 4: 831 /* 832 * This is described with an array of char in the Linux API 833 * spec but the text and all other usage (including binutils, 834 * clang and GCC) treat this as a 32 bit value so no swizzling 835 * is required for big endian. 836 */ 837 .long \feat 838 5: 839 .align 3 840 6: 841 .popsection 842 .endm 843 844 #else 845 .macro emit_aarch64_feature_1_and, feat=0 846 .endm 847 848 #endif /* GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT */ 849 850 .macro __mitigate_spectre_bhb_loop tmp 851 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 852 alternative_cb spectre_bhb_patch_loop_iter 853 mov \tmp, #32 // Patched to correct the immediate 854 alternative_cb_end 855 .Lspectre_bhb_loop\@: 856 b . + 4 857 subs \tmp, \tmp, #1 858 b.ne .Lspectre_bhb_loop\@ 859 sb 860 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 861 .endm 862 863 .macro mitigate_spectre_bhb_loop tmp 864 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 865 alternative_cb spectre_bhb_patch_loop_mitigation_enable 866 b .L_spectre_bhb_loop_done\@ // Patched to NOP 867 alternative_cb_end 868 __mitigate_spectre_bhb_loop \tmp 869 .L_spectre_bhb_loop_done\@: 870 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 871 .endm 872 873 /* Save/restores x0-x3 to the stack */ 874 .macro __mitigate_spectre_bhb_fw 875 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 876 stp x0, x1, [sp, #-16]! 877 stp x2, x3, [sp, #-16]! 878 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3 879 alternative_cb smccc_patch_fw_mitigation_conduit 880 nop // Patched to SMC/HVC #0 881 alternative_cb_end 882 ldp x2, x3, [sp], #16 883 ldp x0, x1, [sp], #16 884 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 885 .endm 886 887 .macro mitigate_spectre_bhb_clear_insn 888 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 889 alternative_cb spectre_bhb_patch_clearbhb 890 /* Patched to NOP when not supported */ 891 clearbhb 892 isb 893 alternative_cb_end 894 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 895 .endm 896 897 #if defined(__KVM_NVHE_HYPERVISOR__) 898 /* 899 * pKVM uses the module_ops struct to expose services to modules but 900 * doesn't allow fine-grained definition of the license for each export, 901 * and doesn't have a way to check the license of the loaded module. 902 * Given that said module may be proprietary, let's seek GPL compliance 903 * by preventing the accidental export of GPL symbols to hyp modules via 904 * pKVM's module_ops struct. 905 */ 906 #ifdef EXPORT_SYMBOL_GPL 907 #undef EXPORT_SYMBOL_GPL 908 #endif 909 #define EXPORT_SYMBOL_GPL(sym) ASM_BUILD_BUG() 910 #endif 911 #endif /* __ASM_ASSEMBLER_H */ 912