1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
3
4 /* include files */
5
6 #include "../include/odm_precomp.h"
7
8 static const u16 dB_Invert_Table[8][12] = {
9 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
10 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
11 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
12 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
13 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
14 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
15 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
16 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
17 };
18
19 /* avoid to warn in FreeBSD ==> To DO modify */
20 static u32 EDCAParam[HT_IOT_PEER_MAX][3] = {
21 /* UL DL */
22 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
23 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */
24 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */
25 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */
26 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */
27 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */
28 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */
29 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */
30 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */
31 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */
32 };
33
34 /* Global var */
35 u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
36 0x7f8001fe, /* 0, +6.0dB */
37 0x788001e2, /* 1, +5.5dB */
38 0x71c001c7, /* 2, +5.0dB */
39 0x6b8001ae, /* 3, +4.5dB */
40 0x65400195, /* 4, +4.0dB */
41 0x5fc0017f, /* 5, +3.5dB */
42 0x5a400169, /* 6, +3.0dB */
43 0x55400155, /* 7, +2.5dB */
44 0x50800142, /* 8, +2.0dB */
45 0x4c000130, /* 9, +1.5dB */
46 0x47c0011f, /* 10, +1.0dB */
47 0x43c0010f, /* 11, +0.5dB */
48 0x40000100, /* 12, +0dB */
49 0x3c8000f2, /* 13, -0.5dB */
50 0x390000e4, /* 14, -1.0dB */
51 0x35c000d7, /* 15, -1.5dB */
52 0x32c000cb, /* 16, -2.0dB */
53 0x300000c0, /* 17, -2.5dB */
54 0x2d4000b5, /* 18, -3.0dB */
55 0x2ac000ab, /* 19, -3.5dB */
56 0x288000a2, /* 20, -4.0dB */
57 0x26000098, /* 21, -4.5dB */
58 0x24000090, /* 22, -5.0dB */
59 0x22000088, /* 23, -5.5dB */
60 0x20000080, /* 24, -6.0dB */
61 0x1e400079, /* 25, -6.5dB */
62 0x1c800072, /* 26, -7.0dB */
63 0x1b00006c, /* 27. -7.5dB */
64 0x19800066, /* 28, -8.0dB */
65 0x18000060, /* 29, -8.5dB */
66 0x16c0005b, /* 30, -9.0dB */
67 0x15800056, /* 31, -9.5dB */
68 0x14400051, /* 32, -10.0dB */
69 0x1300004c, /* 33, -10.5dB */
70 0x12000048, /* 34, -11.0dB */
71 0x11000044, /* 35, -11.5dB */
72 0x10000040, /* 36, -12.0dB */
73 0x0f00003c,/* 37, -12.5dB */
74 0x0e400039,/* 38, -13.0dB */
75 0x0d800036,/* 39, -13.5dB */
76 0x0cc00033,/* 40, -14.0dB */
77 0x0c000030,/* 41, -14.5dB */
78 0x0b40002d,/* 42, -15.0dB */
79 };
80
81 u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
82 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
83 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
84 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
85 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
86 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
87 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
88 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
89 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
90 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
91 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
92 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
93 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
94 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
95 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
96 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
97 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
98 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
99 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
100 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
101 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
102 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
103 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
104 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
105 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
106 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
107 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
108 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
109 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
110 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
111 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
112 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
113 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
114 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
115 };
116
117 u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = {
118 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
119 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
120 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
121 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
122 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
123 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
124 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
125 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
126 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
127 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
128 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
129 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
130 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
131 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
132 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
133 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
134 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
135 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
136 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
137 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
138 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
139 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
140 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
141 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
142 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
143 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
144 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
145 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
146 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
147 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
148 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
149 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
150 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
151 };
152
153 #define RxDefaultAnt1 0x65a9
154 #define RxDefaultAnt2 0x569a
155
156 /* 3 Export Interface */
157
158 /* 2011/09/21 MH Add to describe different team necessary resource allocate?? */
ODM_DMInit(struct odm_dm_struct * pDM_Odm)159 void ODM_DMInit(struct odm_dm_struct *pDM_Odm)
160 {
161 /* 2012.05.03 Luke: For all IC series */
162 odm_CommonInfoSelfInit(pDM_Odm);
163 odm_DIGInit(pDM_Odm);
164 odm_RateAdaptiveMaskInit(pDM_Odm);
165
166 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
167 ;
168 } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
169 odm_PrimaryCCA_Init(pDM_Odm); /* Gary */
170 odm_DynamicBBPowerSavingInit(pDM_Odm);
171 odm_DynamicTxPowerInit(pDM_Odm);
172 odm_TXPowerTrackingInit(pDM_Odm);
173 ODM_EdcaTurboInit(pDM_Odm);
174 ODM_RAInfo_Init_all(pDM_Odm);
175 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
176 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
177 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
178 odm_InitHybridAntDiv(pDM_Odm);
179 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
180 odm_SwAntDivInit(pDM_Odm);
181 }
182 }
183
184 /* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
185 /* You can not add any dummy function here, be care, you can only use DM structure */
186 /* to perform any new ODM_DM. */
ODM_DMWatchdog(struct odm_dm_struct * pDM_Odm)187 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm)
188 {
189 /* 2012.05.03 Luke: For all IC series */
190 odm_GlobalAdapterCheck();
191 odm_CommonInfoSelfUpdate(pDM_Odm);
192 odm_FalseAlarmCounterStatistics(pDM_Odm);
193 odm_RSSIMonitorCheck(pDM_Odm);
194
195 /* For CE Platform(SPRD or Tablet) */
196 /* 8723A or 8189ES platform */
197 /* NeilChen--2012--08--24-- */
198 /* Fix Leave LPS issue */
199 if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/* in LPS mode */
200 ((pDM_Odm->SupportICType & (ODM_RTL8723A)) ||
201 (pDM_Odm->SupportICType & (ODM_RTL8188E) &&
202 ((pDM_Odm->SupportInterface == ODM_ITRF_SDIO)))))
203 odm_DIGbyRSSI_LPS(pDM_Odm);
204 else
205 odm_DIG(pDM_Odm);
206 odm_CCKPacketDetectionThresh(pDM_Odm);
207
208 if (*pDM_Odm->pbPowerSaving)
209 return;
210
211 odm_RefreshRateAdaptiveMask(pDM_Odm);
212
213 odm_DynamicBBPowerSaving(pDM_Odm);
214 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
215 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
216 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
217 odm_HwAntDiv(pDM_Odm);
218 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
219 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK);
220
221 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
222 ;
223 } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
224 ODM_TXPowerTrackingCheck(pDM_Odm);
225 odm_EdcaTurboCheck(pDM_Odm);
226 odm_DynamicTxPower(pDM_Odm);
227 }
228 odm_dtc(pDM_Odm);
229 }
230
231 /* Init /.. Fixed HW value. Only init time. */
ODM_CmnInfoInit(struct odm_dm_struct * pDM_Odm,enum odm_common_info_def CmnInfo,u32 Value)232 void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value)
233 {
234 /* This section is used for init value */
235 switch (CmnInfo) {
236 /* Fixed ODM value. */
237 case ODM_CMNINFO_ABILITY:
238 pDM_Odm->SupportAbility = (u32)Value;
239 break;
240 case ODM_CMNINFO_PLATFORM:
241 pDM_Odm->SupportPlatform = (u8)Value;
242 break;
243 case ODM_CMNINFO_INTERFACE:
244 pDM_Odm->SupportInterface = (u8)Value;
245 break;
246 case ODM_CMNINFO_MP_TEST_CHIP:
247 pDM_Odm->bIsMPChip = (u8)Value;
248 break;
249 case ODM_CMNINFO_IC_TYPE:
250 pDM_Odm->SupportICType = Value;
251 break;
252 case ODM_CMNINFO_CUT_VER:
253 pDM_Odm->CutVersion = (u8)Value;
254 break;
255 case ODM_CMNINFO_FAB_VER:
256 pDM_Odm->FabVersion = (u8)Value;
257 break;
258 case ODM_CMNINFO_RF_TYPE:
259 pDM_Odm->RFType = (u8)Value;
260 break;
261 case ODM_CMNINFO_RF_ANTENNA_TYPE:
262 pDM_Odm->AntDivType = (u8)Value;
263 break;
264 case ODM_CMNINFO_BOARD_TYPE:
265 pDM_Odm->BoardType = (u8)Value;
266 break;
267 case ODM_CMNINFO_EXT_LNA:
268 pDM_Odm->ExtLNA = (u8)Value;
269 break;
270 case ODM_CMNINFO_EXT_PA:
271 pDM_Odm->ExtPA = (u8)Value;
272 break;
273 case ODM_CMNINFO_EXT_TRSW:
274 pDM_Odm->ExtTRSW = (u8)Value;
275 break;
276 case ODM_CMNINFO_PATCH_ID:
277 pDM_Odm->PatchID = (u8)Value;
278 break;
279 case ODM_CMNINFO_BINHCT_TEST:
280 pDM_Odm->bInHctTest = (bool)Value;
281 break;
282 case ODM_CMNINFO_BWIFI_TEST:
283 pDM_Odm->bWIFITest = (bool)Value;
284 break;
285 case ODM_CMNINFO_SMART_CONCURRENT:
286 pDM_Odm->bDualMacSmartConcurrent = (bool)Value;
287 break;
288 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
289 default:
290 /* do nothing */
291 break;
292 }
293
294 /* Tx power tracking BB swing table. */
295 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
296 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */
297 pDM_Odm->BbSwingIdxOfdmCurrent = 12;
298 pDM_Odm->BbSwingFlagOfdm = false;
299 }
300
ODM_CmnInfoHook(struct odm_dm_struct * pDM_Odm,enum odm_common_info_def CmnInfo,void * pValue)301 void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, void *pValue)
302 {
303 /* */
304 /* Hook call by reference pointer. */
305 /* */
306 switch (CmnInfo) {
307 /* Dynamic call by reference pointer. */
308 case ODM_CMNINFO_MAC_PHY_MODE:
309 pDM_Odm->pMacPhyMode = (u8 *)pValue;
310 break;
311 case ODM_CMNINFO_TX_UNI:
312 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue;
313 break;
314 case ODM_CMNINFO_RX_UNI:
315 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue;
316 break;
317 case ODM_CMNINFO_WM_MODE:
318 pDM_Odm->pWirelessMode = (u8 *)pValue;
319 break;
320 case ODM_CMNINFO_BAND:
321 pDM_Odm->pBandType = (u8 *)pValue;
322 break;
323 case ODM_CMNINFO_SEC_CHNL_OFFSET:
324 pDM_Odm->pSecChOffset = (u8 *)pValue;
325 break;
326 case ODM_CMNINFO_SEC_MODE:
327 pDM_Odm->pSecurity = (u8 *)pValue;
328 break;
329 case ODM_CMNINFO_BW:
330 pDM_Odm->pBandWidth = (u8 *)pValue;
331 break;
332 case ODM_CMNINFO_CHNL:
333 pDM_Odm->pChannel = (u8 *)pValue;
334 break;
335 case ODM_CMNINFO_DMSP_GET_VALUE:
336 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue;
337 break;
338 case ODM_CMNINFO_BUDDY_ADAPTOR:
339 pDM_Odm->pBuddyAdapter = (struct adapter **)pValue;
340 break;
341 case ODM_CMNINFO_DMSP_IS_MASTER:
342 pDM_Odm->pbMasterOfDMSP = (bool *)pValue;
343 break;
344 case ODM_CMNINFO_SCAN:
345 pDM_Odm->pbScanInProcess = (bool *)pValue;
346 break;
347 case ODM_CMNINFO_POWER_SAVING:
348 pDM_Odm->pbPowerSaving = (bool *)pValue;
349 break;
350 case ODM_CMNINFO_ONE_PATH_CCA:
351 pDM_Odm->pOnePathCCA = (u8 *)pValue;
352 break;
353 case ODM_CMNINFO_DRV_STOP:
354 pDM_Odm->pbDriverStopped = (bool *)pValue;
355 break;
356 case ODM_CMNINFO_PNP_IN:
357 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (bool *)pValue;
358 break;
359 case ODM_CMNINFO_INIT_ON:
360 pDM_Odm->pinit_adpt_in_progress = (bool *)pValue;
361 break;
362 case ODM_CMNINFO_ANT_TEST:
363 pDM_Odm->pAntennaTest = (u8 *)pValue;
364 break;
365 case ODM_CMNINFO_NET_CLOSED:
366 pDM_Odm->pbNet_closed = (bool *)pValue;
367 break;
368 case ODM_CMNINFO_MP_MODE:
369 pDM_Odm->mp_mode = (u8 *)pValue;
370 break;
371 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
372 default:
373 /* do nothing */
374 break;
375 }
376 }
377
ODM_CmnInfoPtrArrayHook(struct odm_dm_struct * pDM_Odm,enum odm_common_info_def CmnInfo,u16 Index,void * pValue)378 void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue)
379 {
380 /* Hook call by reference pointer. */
381 switch (CmnInfo) {
382 /* Dynamic call by reference pointer. */
383 case ODM_CMNINFO_STA_STATUS:
384 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
385 break;
386 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
387 default:
388 /* do nothing */
389 break;
390 }
391 }
392
393 /* Update Band/CHannel/.. The values are dynamic but non-per-packet. */
ODM_CmnInfoUpdate(struct odm_dm_struct * pDM_Odm,u32 CmnInfo,u64 Value)394 void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value)
395 {
396 /* */
397 /* This init variable may be changed in run time. */
398 /* */
399 switch (CmnInfo) {
400 case ODM_CMNINFO_ABILITY:
401 pDM_Odm->SupportAbility = (u32)Value;
402 break;
403 case ODM_CMNINFO_RF_TYPE:
404 pDM_Odm->RFType = (u8)Value;
405 break;
406 case ODM_CMNINFO_WIFI_DIRECT:
407 pDM_Odm->bWIFI_Direct = (bool)Value;
408 break;
409 case ODM_CMNINFO_WIFI_DISPLAY:
410 pDM_Odm->bWIFI_Display = (bool)Value;
411 break;
412 case ODM_CMNINFO_LINK:
413 pDM_Odm->bLinked = (bool)Value;
414 break;
415 case ODM_CMNINFO_RSSI_MIN:
416 pDM_Odm->RSSI_Min = (u8)Value;
417 break;
418 case ODM_CMNINFO_RA_THRESHOLD_HIGH:
419 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
420 break;
421 case ODM_CMNINFO_RA_THRESHOLD_LOW:
422 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
423 break;
424 }
425 }
426
odm_CommonInfoSelfInit(struct odm_dm_struct * pDM_Odm)427 void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm)
428 {
429 pDM_Odm->bCckHighPower = (bool)ODM_GetBBReg(pDM_Odm, 0x824, BIT(9));
430 pDM_Odm->RFPathRxEnable = (u8)ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);
431 if (pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D))
432 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
433 if (pDM_Odm->SupportICType & (ODM_RTL8723A))
434 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
435 }
436
odm_CommonInfoSelfUpdate(struct odm_dm_struct * pDM_Odm)437 void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm)
438 {
439 u8 EntryCnt = 0;
440 u8 i;
441 struct sta_info *pEntry;
442
443 if (*pDM_Odm->pBandWidth == ODM_BW40M) {
444 if (*pDM_Odm->pSecChOffset == 1)
445 pDM_Odm->ControlChannel = *pDM_Odm->pChannel - 2;
446 else if (*pDM_Odm->pSecChOffset == 2)
447 pDM_Odm->ControlChannel = *pDM_Odm->pChannel + 2;
448 } else {
449 pDM_Odm->ControlChannel = *pDM_Odm->pChannel;
450 }
451
452 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
453 pEntry = pDM_Odm->pODM_StaInfo[i];
454 if (IS_STA_VALID(pEntry))
455 EntryCnt++;
456 }
457 if (EntryCnt == 1)
458 pDM_Odm->bOneEntryOnly = true;
459 else
460 pDM_Odm->bOneEntryOnly = false;
461 }
462
getIGIForDiff(int value_IGI)463 static int getIGIForDiff(int value_IGI)
464 {
465 #define ONERCCA_LOW_TH 0x30
466 #define ONERCCA_LOW_DIFF 8
467
468 if (value_IGI < ONERCCA_LOW_TH) {
469 if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF)
470 return ONERCCA_LOW_TH;
471 else
472 return value_IGI + ONERCCA_LOW_DIFF;
473 } else {
474 return value_IGI;
475 }
476 }
477
ODM_Write_DIG(struct odm_dm_struct * pDM_Odm,u8 CurrentIGI)478 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI)
479 {
480 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
481
482 if (pDM_DigTable->CurIGValue != CurrentIGI) {
483 if (pDM_Odm->SupportPlatform & (ODM_CE | ODM_MP)) {
484 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
485 if (pDM_Odm->SupportICType != ODM_RTL8188E)
486 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
487 } else if (pDM_Odm->SupportPlatform & (ODM_AP | ODM_ADSL)) {
488 switch (*pDM_Odm->pOnePathCCA) {
489 case ODM_CCA_2R:
490 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
491 if (pDM_Odm->SupportICType != ODM_RTL8188E)
492 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
493 break;
494 case ODM_CCA_1R_A:
495 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
496 if (pDM_Odm->SupportICType != ODM_RTL8188E)
497 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), getIGIForDiff(CurrentIGI));
498 break;
499 case ODM_CCA_1R_B:
500 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), getIGIForDiff(CurrentIGI));
501 if (pDM_Odm->SupportICType != ODM_RTL8188E)
502 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
503 break;
504 }
505 }
506 /* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */
507 pDM_DigTable->CurIGValue = CurrentIGI;
508 }
509 /* Add by Neil Chen to enable edcca to MP Platform */
510 }
511
512 /* Need LPS mode for CE platform --2012--08--24--- */
513 /* 8723AS/8189ES */
odm_DIGbyRSSI_LPS(struct odm_dm_struct * pDM_Odm)514 void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm)
515 {
516 struct adapter *pAdapter = pDM_Odm->Adapter;
517 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
518
519 u8 RSSI_Lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */
520 u8 bFwCurrentInPSMode = false;
521 u8 CurrentIGI = pDM_Odm->RSSI_Min;
522
523 if (!(pDM_Odm->SupportICType & (ODM_RTL8723A | ODM_RTL8188E)))
524 return;
525
526 CurrentIGI = CurrentIGI + RSSI_OFFSET_DIG;
527 bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
528
529 /* Using FW PS mode to make IGI */
530 if (bFwCurrentInPSMode) {
531 /* Adjust by FA in LPS MODE */
532 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS)
533 CurrentIGI = CurrentIGI + 2;
534 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
535 CurrentIGI = CurrentIGI + 1;
536 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
537 CurrentIGI = CurrentIGI - 1;
538 } else {
539 CurrentIGI = RSSI_Lower;
540 }
541
542 /* Lower bound checking */
543
544 /* RSSI Lower bound check */
545 if ((pDM_Odm->RSSI_Min - 10) > DM_DIG_MIN_NIC)
546 RSSI_Lower = (pDM_Odm->RSSI_Min - 10);
547 else
548 RSSI_Lower = DM_DIG_MIN_NIC;
549
550 /* Upper and Lower Bound checking */
551 if (CurrentIGI > DM_DIG_MAX_NIC)
552 CurrentIGI = DM_DIG_MAX_NIC;
553 else if (CurrentIGI < RSSI_Lower)
554 CurrentIGI = RSSI_Lower;
555
556 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */
557 }
558
odm_DIGInit(struct odm_dm_struct * pDM_Odm)559 void odm_DIGInit(struct odm_dm_struct *pDM_Odm)
560 {
561 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
562
563 pDM_DigTable->CurIGValue = (u8)ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
564 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW;
565 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH;
566 pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW;
567 pDM_DigTable->FAHighThresh = DM_false_ALARM_THRESH_HIGH;
568 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
569 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
570 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
571 } else {
572 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
573 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
574 }
575 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
576 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
577 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
578 pDM_DigTable->PreCCK_CCAThres = 0xFF;
579 pDM_DigTable->CurCCK_CCAThres = 0x83;
580 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
581 pDM_DigTable->LargeFAHit = 0;
582 pDM_DigTable->Recover_cnt = 0;
583 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
584 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
585 pDM_DigTable->bMediaConnect_0 = false;
586 pDM_DigTable->bMediaConnect_1 = false;
587
588 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */
589 pDM_Odm->bDMInitialGainEnable = true;
590 }
591
odm_DIG(struct odm_dm_struct * pDM_Odm)592 void odm_DIG(struct odm_dm_struct *pDM_Odm)
593 {
594 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
595 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
596 u8 DIG_Dynamic_MIN;
597 u8 DIG_MaxOfMin;
598 bool FirstConnect, FirstDisConnect;
599 u8 dm_dig_max, dm_dig_min;
600 u8 CurrentIGI = pDM_DigTable->CurIGValue;
601
602 if ((!(pDM_Odm->SupportAbility & ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)))
603 return;
604
605 if (*pDM_Odm->pbScanInProcess)
606 return;
607
608 /* add by Neil Chen to avoid PSD is processing */
609 if (!pDM_Odm->bDMInitialGainEnable)
610 return;
611
612 if (pDM_Odm->SupportICType == ODM_RTL8192D) {
613 if (*pDM_Odm->pMacPhyMode == ODM_DMSP) {
614 if (*pDM_Odm->pbMasterOfDMSP) {
615 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
616 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
617 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
618 } else {
619 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
620 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1);
621 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1);
622 }
623 } else {
624 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
625 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1);
626 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1);
627 }
628 } else {
629 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
630 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
631 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
632 }
633
634 /* 1 Boundary Decision */
635 if ((pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8723A)) &&
636 ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) {
637 if (pDM_Odm->SupportPlatform & (ODM_AP | ODM_ADSL)) {
638 dm_dig_max = DM_DIG_MAX_AP_HP;
639 dm_dig_min = DM_DIG_MIN_AP_HP;
640 } else {
641 dm_dig_max = DM_DIG_MAX_NIC_HP;
642 dm_dig_min = DM_DIG_MIN_NIC_HP;
643 }
644 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
645 } else {
646 if (pDM_Odm->SupportPlatform & (ODM_AP | ODM_ADSL)) {
647 dm_dig_max = DM_DIG_MAX_AP;
648 dm_dig_min = DM_DIG_MIN_AP;
649 DIG_MaxOfMin = dm_dig_max;
650 } else {
651 dm_dig_max = DM_DIG_MAX_NIC;
652 dm_dig_min = DM_DIG_MIN_NIC;
653 DIG_MaxOfMin = DM_DIG_MAX_AP;
654 }
655 }
656 if (pDM_Odm->bLinked) {
657 /* 2 8723A Series, offset need to be 10 */
658 if (pDM_Odm->SupportICType == (ODM_RTL8723A)) {
659 /* 2 Upper Bound */
660 if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC)
661 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
662 else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC)
663 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
664 else
665 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
666 /* 2 If BT is Concurrent, need to set Lower Bound */
667 DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
668 } else {
669 /* 2 Modify DIG upper bound */
670 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
671 pDM_DigTable->rx_gain_range_max = dm_dig_max;
672 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
673 pDM_DigTable->rx_gain_range_max = dm_dig_min;
674 else
675 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
676 /* 2 Modify DIG lower bound */
677 if (pDM_Odm->bOneEntryOnly) {
678 if (pDM_Odm->RSSI_Min < dm_dig_min)
679 DIG_Dynamic_MIN = dm_dig_min;
680 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
681 DIG_Dynamic_MIN = DIG_MaxOfMin;
682 else
683 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
684 } else if ((pDM_Odm->SupportICType == ODM_RTL8188E) &&
685 (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
686 /* 1 Lower Bound for 88E AntDiv */
687 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
688 DIG_Dynamic_MIN = (u8)pDM_DigTable->AntDiv_RSSI_max;
689 } else {
690 DIG_Dynamic_MIN = dm_dig_min;
691 }
692 }
693 } else {
694 pDM_DigTable->rx_gain_range_max = dm_dig_max;
695 DIG_Dynamic_MIN = dm_dig_min;
696 }
697
698 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
699 if (pFalseAlmCnt->Cnt_all > 10000) {
700 if (pDM_DigTable->LargeFAHit != 3)
701 pDM_DigTable->LargeFAHit++;
702 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
703 pDM_DigTable->ForbiddenIGI = CurrentIGI;
704 pDM_DigTable->LargeFAHit = 1;
705 }
706
707 if (pDM_DigTable->LargeFAHit >= 3) {
708 if ((pDM_DigTable->ForbiddenIGI + 1) > pDM_DigTable->rx_gain_range_max)
709 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
710 else
711 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
712 pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */
713 }
714
715 } else {
716 /* Recovery mechanism for IGI lower bound */
717 if (pDM_DigTable->Recover_cnt != 0) {
718 pDM_DigTable->Recover_cnt--;
719 } else {
720 if (pDM_DigTable->LargeFAHit < 3) {
721 if ((pDM_DigTable->ForbiddenIGI - 1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */
722 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
723 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
724 } else {
725 pDM_DigTable->ForbiddenIGI--;
726 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
727 }
728 } else {
729 pDM_DigTable->LargeFAHit = 0;
730 }
731 }
732 }
733
734 /* 1 Adjust initial gain by false alarm */
735 if (pDM_Odm->bLinked) {
736 if (FirstConnect) {
737 CurrentIGI = pDM_Odm->RSSI_Min;
738 } else {
739 if (pDM_Odm->SupportICType == ODM_RTL8192D) {
740 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D)
741 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
742 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D)
743 CurrentIGI = CurrentIGI + 1; /* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
744 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D)
745 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
746 } else {
747 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
748 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
749 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
750 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
751 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
752 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
753 }
754 }
755 } else {
756 if (FirstDisConnect) {
757 CurrentIGI = pDM_DigTable->rx_gain_range_min;
758 } else {
759 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
760 if (pFalseAlmCnt->Cnt_all > 10000)
761 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
762 else if (pFalseAlmCnt->Cnt_all > 8000)
763 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
764 else if (pFalseAlmCnt->Cnt_all < 500)
765 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
766 }
767 }
768 /* 1 Check initial gain by upper/lower bound */
769 if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
770 CurrentIGI = pDM_DigTable->rx_gain_range_max;
771 if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
772 CurrentIGI = pDM_DigTable->rx_gain_range_min;
773
774 /* 2 High power RSSI threshold */
775
776 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */
777 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
778 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
779 }
780
781 /* 3============================================================ */
782 /* 3 FASLE ALARM CHECK */
783 /* 3============================================================ */
784
odm_FalseAlarmCounterStatistics(struct odm_dm_struct * pDM_Odm)785 void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
786 {
787 u32 ret_value;
788 struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
789
790 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
791 return;
792
793 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
794 /* hold ofdm counter */
795 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */
796 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */
797
798 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
799 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value & 0xffff);
800 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value & 0xffff0000) >> 16);
801 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
802 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value & 0xffff);
803 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value & 0xffff0000) >> 16);
804 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
805 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value & 0xffff);
806 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value & 0xffff0000) >> 16);
807 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
808 FalseAlmCnt->Cnt_Mcs_fail = (ret_value & 0xffff);
809
810 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
811 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
812 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
813
814 if (pDM_Odm->SupportICType == ODM_RTL8188E) {
815 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord);
816 FalseAlmCnt->Cnt_BW_LSC = (ret_value & 0xffff);
817 FalseAlmCnt->Cnt_BW_USC = ((ret_value & 0xffff0000) >> 16);
818 }
819
820 /* hold cck counter */
821 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
822 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
823
824 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
825 FalseAlmCnt->Cnt_Cck_fail = ret_value;
826 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
827 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff) << 8;
828
829 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
830 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value & 0xFF) << 8) | ((ret_value & 0xFF00) >> 8);
831
832 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
833 FalseAlmCnt->Cnt_SB_Search_fail +
834 FalseAlmCnt->Cnt_Parity_Fail +
835 FalseAlmCnt->Cnt_Rate_Illegal +
836 FalseAlmCnt->Cnt_Crc8_fail +
837 FalseAlmCnt->Cnt_Mcs_fail +
838 FalseAlmCnt->Cnt_Cck_fail);
839
840 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
841
842 if (pDM_Odm->SupportICType >= ODM_RTL8723A) {
843 /* reset false alarm counter registers */
844 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
845 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
846 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
847 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
848 /* update ofdm counter */
849 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0); /* update page C counter */
850 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0); /* update page D counter */
851
852 /* reset CCK CCA counter */
853 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 0);
854 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 2);
855 /* reset CCK FA counter */
856 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 0);
857 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2);
858 }
859 } else { /* FOR ODM_IC_11AC_SERIES */
860 /* read OFDM FA counter */
861 FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord);
862 FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord);
863 FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail;
864
865 /* reset OFDM FA coutner */
866 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 1);
867 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 0);
868 /* reset CCK FA counter */
869 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 0);
870 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 1);
871 }
872 }
873
874 /* 3============================================================ */
875 /* 3 CCK Packet Detect Threshold */
876 /* 3============================================================ */
877
odm_CCKPacketDetectionThresh(struct odm_dm_struct * pDM_Odm)878 void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm)
879 {
880 u8 CurCCK_CCAThres;
881 struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
882
883 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD | ODM_BB_FA_CNT)))
884 return;
885 if (pDM_Odm->ExtLNA)
886 return;
887 if (pDM_Odm->bLinked) {
888 if (pDM_Odm->RSSI_Min > 25) {
889 CurCCK_CCAThres = 0xcd;
890 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
891 CurCCK_CCAThres = 0x83;
892 } else {
893 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
894 CurCCK_CCAThres = 0x83;
895 else
896 CurCCK_CCAThres = 0x40;
897 }
898 } else {
899 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
900 CurCCK_CCAThres = 0x83;
901 else
902 CurCCK_CCAThres = 0x40;
903 }
904 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres);
905 }
906
ODM_Write_CCK_CCA_Thres(struct odm_dm_struct * pDM_Odm,u8 CurCCK_CCAThres)907 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres)
908 {
909 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
910
911 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */
912 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);
913 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
914 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
915 }
916
917 /* 3============================================================ */
918 /* 3 BB Power Save */
919 /* 3============================================================ */
odm_DynamicBBPowerSavingInit(struct odm_dm_struct * pDM_Odm)920 void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm)
921 {
922 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
923
924 pDM_PSTable->pre_cca_state = CCA_MAX;
925 pDM_PSTable->cur_cca_state = CCA_MAX;
926 pDM_PSTable->pre_rf_state = RF_MAX;
927 pDM_PSTable->cur_rf_state = RF_MAX;
928 pDM_PSTable->rssi_val_min = 0;
929 pDM_PSTable->initialize = 0;
930 }
931
odm_DynamicBBPowerSaving(struct odm_dm_struct * pDM_Odm)932 void odm_DynamicBBPowerSaving(struct odm_dm_struct *pDM_Odm)
933 {
934 if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8723A))
935 return;
936 if (!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE))
937 return;
938 if (!(pDM_Odm->SupportPlatform & (ODM_MP | ODM_CE)))
939 return;
940
941 /* 1 2.Power Saving for 92C */
942 if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->RFType == ODM_2T2R)) {
943 odm_1R_CCA(pDM_Odm);
944 } else {
945 /* 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable. */
946 /* 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns. */
947 /* 1 3.Power Saving for 88C */
948 ODM_RF_Saving(pDM_Odm, false);
949 }
950 }
951
odm_1R_CCA(struct odm_dm_struct * pDM_Odm)952 void odm_1R_CCA(struct odm_dm_struct *pDM_Odm)
953 {
954 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
955
956 if (pDM_Odm->RSSI_Min != 0xFF) {
957 if (pDM_PSTable->pre_cca_state == CCA_2R) {
958 if (pDM_Odm->RSSI_Min >= 35)
959 pDM_PSTable->cur_cca_state = CCA_1R;
960 else
961 pDM_PSTable->cur_cca_state = CCA_2R;
962 } else {
963 if (pDM_Odm->RSSI_Min <= 30)
964 pDM_PSTable->cur_cca_state = CCA_2R;
965 else
966 pDM_PSTable->cur_cca_state = CCA_1R;
967 }
968 } else {
969 pDM_PSTable->cur_cca_state = CCA_MAX;
970 }
971
972 if (pDM_PSTable->pre_cca_state != pDM_PSTable->cur_cca_state) {
973 if (pDM_PSTable->cur_cca_state == CCA_1R) {
974 if (pDM_Odm->RFType == ODM_2T2R)
975 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x13);
976 else
977 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x23);
978 } else {
979 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x33);
980 }
981 pDM_PSTable->pre_cca_state = pDM_PSTable->cur_cca_state;
982 }
983 }
984
ODM_RF_Saving(struct odm_dm_struct * pDM_Odm,u8 bForceInNormal)985 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal)
986 {
987 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
988 u8 Rssi_Up_bound = 30;
989 u8 Rssi_Low_bound = 25;
990
991 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
992 Rssi_Up_bound = 50;
993 Rssi_Low_bound = 45;
994 }
995 if (pDM_PSTable->initialize == 0) {
996 pDM_PSTable->reg_874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord) & 0x1CC000) >> 14;
997 pDM_PSTable->reg_c70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord) & BIT(3)) >> 3;
998 pDM_PSTable->reg_85c = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord) & 0xFF000000) >> 24;
999 pDM_PSTable->reg_a74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord) & 0xF000) >> 12;
1000 pDM_PSTable->initialize = 1;
1001 }
1002
1003 if (!bForceInNormal) {
1004 if (pDM_Odm->RSSI_Min != 0xFF) {
1005 if (pDM_PSTable->pre_rf_state == RF_Normal) {
1006 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
1007 pDM_PSTable->cur_rf_state = RF_Save;
1008 else
1009 pDM_PSTable->cur_rf_state = RF_Normal;
1010 } else {
1011 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
1012 pDM_PSTable->cur_rf_state = RF_Normal;
1013 else
1014 pDM_PSTable->cur_rf_state = RF_Save;
1015 }
1016 } else {
1017 pDM_PSTable->cur_rf_state = RF_MAX;
1018 }
1019 } else {
1020 pDM_PSTable->cur_rf_state = RF_Normal;
1021 }
1022
1023 if (pDM_PSTable->pre_rf_state != pDM_PSTable->cur_rf_state) {
1024 if (pDM_PSTable->cur_rf_state == RF_Save) {
1025 /* <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode. */
1026 /* Suggested by SD3 Yu-Nan. 2011.01.20. */
1027 if (pDM_Odm->SupportICType == ODM_RTL8723A)
1028 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x1); /* Reg874[5]=1b'1 */
1029 ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */
1030 ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */
1031 ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */
1032 ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */
1033 ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */
1034 ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */
1035 ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */
1036 } else {
1037 ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, pDM_PSTable->reg_874);
1038 ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), pDM_PSTable->reg_c70);
1039 ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->reg_85c);
1040 ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->reg_a74);
1041 ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0);
1042
1043 if (pDM_Odm->SupportICType == ODM_RTL8723A)
1044 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x0); /* Reg874[5]=1b'0 */
1045 }
1046 pDM_PSTable->pre_rf_state = pDM_PSTable->cur_rf_state;
1047 }
1048 }
1049
1050 /* 3============================================================ */
1051 /* 3 RATR MASK */
1052 /* 3============================================================ */
1053 /* 3============================================================ */
1054 /* 3 Rate Adaptive */
1055 /* 3============================================================ */
1056
odm_RateAdaptiveMaskInit(struct odm_dm_struct * pDM_Odm)1057 void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm)
1058 {
1059 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
1060
1061 pOdmRA->Type = DM_Type_ByDriver;
1062 if (pOdmRA->Type == DM_Type_ByDriver)
1063 pDM_Odm->bUseRAMask = true;
1064 else
1065 pDM_Odm->bUseRAMask = false;
1066
1067 pOdmRA->RATRState = DM_RATR_STA_INIT;
1068 pOdmRA->HighRSSIThresh = 50;
1069 pOdmRA->LowRSSIThresh = 20;
1070 }
1071
ODM_Get_Rate_Bitmap(struct odm_dm_struct * pDM_Odm,u32 macid,u32 ra_mask,u8 rssi_level)1072 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level)
1073 {
1074 struct sta_info *pEntry;
1075 u32 rate_bitmap = 0x0fffffff;
1076 u8 WirelessMode;
1077
1078 pEntry = pDM_Odm->pODM_StaInfo[macid];
1079 if (!IS_STA_VALID(pEntry))
1080 return ra_mask;
1081
1082 WirelessMode = pEntry->wireless_mode;
1083
1084 switch (WirelessMode) {
1085 case ODM_WM_B:
1086 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */
1087 rate_bitmap = 0x0000000d;
1088 else
1089 rate_bitmap = 0x0000000f;
1090 break;
1091 case (ODM_WM_B | ODM_WM_G):
1092 if (rssi_level == DM_RATR_STA_HIGH)
1093 rate_bitmap = 0x00000f00;
1094 else if (rssi_level == DM_RATR_STA_MIDDLE)
1095 rate_bitmap = 0x00000ff0;
1096 else
1097 rate_bitmap = 0x00000ff5;
1098 break;
1099 case (ODM_WM_B | ODM_WM_G | ODM_WM_N24G):
1100 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) {
1101 if (rssi_level == DM_RATR_STA_HIGH) {
1102 rate_bitmap = 0x000f0000;
1103 } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1104 rate_bitmap = 0x000ff000;
1105 } else {
1106 if (*pDM_Odm->pBandWidth == ODM_BW40M)
1107 rate_bitmap = 0x000ff015;
1108 else
1109 rate_bitmap = 0x000ff005;
1110 }
1111 } else {
1112 if (rssi_level == DM_RATR_STA_HIGH) {
1113 rate_bitmap = 0x0f8f0000;
1114 } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1115 rate_bitmap = 0x0f8ff000;
1116 } else {
1117 if (*pDM_Odm->pBandWidth == ODM_BW40M)
1118 rate_bitmap = 0x0f8ff015;
1119 else
1120 rate_bitmap = 0x0f8ff005;
1121 }
1122 }
1123 break;
1124 default:
1125 /* case WIRELESS_11_24N: */
1126 if (pDM_Odm->RFType == RF_1T2R)
1127 rate_bitmap = 0x000fffff;
1128 else
1129 rate_bitmap = 0x0fffffff;
1130 break;
1131 }
1132
1133 return rate_bitmap;
1134 }
1135
1136 /*-----------------------------------------------------------------------------
1137 * Function: odm_RefreshRateAdaptiveMask()
1138 *
1139 * Overview: Update rate table mask according to rssi
1140 *
1141 * Input: NONE
1142 *
1143 * Output: NONE
1144 *
1145 * Return: NONE
1146 *
1147 * Revised History:
1148 * When Who Remark
1149 * 05/27/2009 hpfan Create Version 0.
1150 *
1151 *---------------------------------------------------------------------------*/
odm_RefreshRateAdaptiveMask(struct odm_dm_struct * pDM_Odm)1152 void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm)
1153 {
1154 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
1155 return;
1156 /* */
1157 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1158 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1159 /* HW dynamic mechanism. */
1160 /* */
1161 switch (pDM_Odm->SupportPlatform) {
1162 case ODM_MP:
1163 odm_RefreshRateAdaptiveMaskMP(pDM_Odm);
1164 break;
1165 case ODM_CE:
1166 odm_RefreshRateAdaptiveMaskCE(pDM_Odm);
1167 break;
1168 case ODM_AP:
1169 case ODM_ADSL:
1170 odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm);
1171 break;
1172 }
1173 }
1174
odm_RefreshRateAdaptiveMaskMP(struct odm_dm_struct * pDM_Odm)1175 void odm_RefreshRateAdaptiveMaskMP(struct odm_dm_struct *pDM_Odm)
1176 {
1177 }
1178
odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct * pDM_Odm)1179 void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm)
1180 {
1181 u8 i;
1182 struct adapter *pAdapter = pDM_Odm->Adapter;
1183
1184 if (pAdapter->bDriverStopped)
1185 return;
1186
1187 if (!pDM_Odm->bUseRAMask)
1188 return;
1189
1190 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1191 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
1192 if (IS_STA_VALID(pstat)) {
1193 if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level))
1194 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level);
1195 }
1196 }
1197 }
1198
odm_RefreshRateAdaptiveMaskAPADSL(struct odm_dm_struct * pDM_Odm)1199 void odm_RefreshRateAdaptiveMaskAPADSL(struct odm_dm_struct *pDM_Odm)
1200 {
1201 }
1202
1203 /* Return Value: bool */
1204 /* - true: RATRState is changed. */
ODM_RAStateCheck(struct odm_dm_struct * pDM_Odm,s32 RSSI,bool bForceUpdate,u8 * pRATRState)1205 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState)
1206 {
1207 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
1208 const u8 GoUpGap = 5;
1209 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
1210 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
1211 u8 RATRState;
1212
1213 /* Threshold Adjustment: */
1214 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
1215 /* Here GoUpGap is added to solve the boundary's level alternation issue. */
1216 switch (*pRATRState) {
1217 case DM_RATR_STA_INIT:
1218 case DM_RATR_STA_HIGH:
1219 break;
1220 case DM_RATR_STA_MIDDLE:
1221 HighRSSIThreshForRA += GoUpGap;
1222 break;
1223 case DM_RATR_STA_LOW:
1224 HighRSSIThreshForRA += GoUpGap;
1225 LowRSSIThreshForRA += GoUpGap;
1226 break;
1227 default:
1228 break;
1229 }
1230
1231 /* Decide RATRState by RSSI. */
1232 if (RSSI > HighRSSIThreshForRA)
1233 RATRState = DM_RATR_STA_HIGH;
1234 else if (RSSI > LowRSSIThreshForRA)
1235 RATRState = DM_RATR_STA_MIDDLE;
1236 else
1237 RATRState = DM_RATR_STA_LOW;
1238
1239 if (*pRATRState != RATRState || bForceUpdate) {
1240 *pRATRState = RATRState;
1241 return true;
1242 }
1243 return false;
1244 }
1245
1246 /* 3============================================================ */
1247 /* 3 Dynamic Tx Power */
1248 /* 3============================================================ */
1249
odm_DynamicTxPowerInit(struct odm_dm_struct * pDM_Odm)1250 void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm)
1251 {
1252 struct adapter *Adapter = pDM_Odm->Adapter;
1253 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
1254 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1255 pdmpriv->bDynamicTxPowerEnable = false;
1256 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
1257 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
1258 }
1259
odm_DynamicTxPower(struct odm_dm_struct * pDM_Odm)1260 void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm)
1261 {
1262 /* For AP/ADSL use struct rtl8192cd_priv * */
1263 /* For CE/NIC use struct adapter * */
1264
1265 if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
1266 return;
1267
1268 /* 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. */
1269 if (!pDM_Odm->ExtPA)
1270 return;
1271
1272 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1273 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1274 /* HW dynamic mechanism. */
1275 switch (pDM_Odm->SupportPlatform) {
1276 case ODM_MP:
1277 case ODM_CE:
1278 odm_DynamicTxPowerNIC(pDM_Odm);
1279 break;
1280 case ODM_AP:
1281 odm_DynamicTxPowerAP(pDM_Odm);
1282 break;
1283 case ODM_ADSL:
1284 break;
1285 }
1286 }
1287
odm_DynamicTxPowerNIC(struct odm_dm_struct * pDM_Odm)1288 void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm)
1289 {
1290 if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
1291 return;
1292
1293 if (pDM_Odm->SupportICType == ODM_RTL8188E) {
1294 /* ??? */
1295 /* This part need to be redefined. */
1296 }
1297 }
1298
odm_DynamicTxPowerAP(struct odm_dm_struct * pDM_Odm)1299 void odm_DynamicTxPowerAP(struct odm_dm_struct *pDM_Odm)
1300 {
1301 }
1302
1303 /* 3============================================================ */
1304 /* 3 RSSI Monitor */
1305 /* 3============================================================ */
1306
odm_RSSIMonitorCheck(struct odm_dm_struct * pDM_Odm)1307 void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm)
1308 {
1309 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
1310 return;
1311
1312 /* */
1313 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1314 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1315 /* HW dynamic mechanism. */
1316 /* */
1317 switch (pDM_Odm->SupportPlatform) {
1318 case ODM_MP:
1319 odm_RSSIMonitorCheckMP(pDM_Odm);
1320 break;
1321 case ODM_CE:
1322 odm_RSSIMonitorCheckCE(pDM_Odm);
1323 break;
1324 case ODM_AP:
1325 odm_RSSIMonitorCheckAP(pDM_Odm);
1326 break;
1327 case ODM_ADSL:
1328 /* odm_DIGAP(pDM_Odm); */
1329 break;
1330 }
1331
1332 } /* odm_RSSIMonitorCheck */
1333
odm_RSSIMonitorCheckMP(struct odm_dm_struct * pDM_Odm)1334 void odm_RSSIMonitorCheckMP(struct odm_dm_struct *pDM_Odm)
1335 {
1336 }
1337
FindMinimumRSSI(struct adapter * pAdapter)1338 static void FindMinimumRSSI(struct adapter *pAdapter)
1339 {
1340 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
1341 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1342 struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv;
1343
1344 /* 1 1.Determine the minimum RSSI */
1345 if (!check_fwstate(pmlmepriv, _FW_LINKED) &&
1346 pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)
1347 pdmpriv->MinUndecoratedPWDBForDM = 0;
1348 if (check_fwstate(pmlmepriv, _FW_LINKED)) /* Default port */
1349 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1350 else /* associated entry pwdb */
1351 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1352 }
1353
odm_RSSIMonitorCheckCE(struct odm_dm_struct * pDM_Odm)1354 void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm)
1355 {
1356 struct adapter *Adapter = pDM_Odm->Adapter;
1357 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
1358 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1359 int i;
1360 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
1361 u8 sta_cnt = 0;
1362 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
1363 struct sta_info *psta;
1364 u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
1365
1366 if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED))
1367 return;
1368
1369 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1370 psta = pDM_Odm->pODM_StaInfo[i];
1371 if (IS_STA_VALID(psta) &&
1372 (psta->state & WIFI_ASOC_STATE) &&
1373 memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) &&
1374 memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) {
1375 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
1376 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1377
1378 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
1379 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1380 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
1381 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB << 16));
1382 }
1383 }
1384
1385 for (i = 0; i < sta_cnt; i++) {
1386 if (PWDB_rssi[i] != (0)) {
1387 if (pHalData->fw_ractrl) {
1388 /* Report every sta's RSSI to FW */
1389 } else {
1390 ODM_RA_SetRSSI_8188E(
1391 &pHalData->odmpriv, (PWDB_rssi[i] & 0xFF), (u8)((PWDB_rssi[i] >> 16) & 0xFF));
1392 }
1393 }
1394 }
1395
1396 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */
1397 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
1398 else
1399 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
1400
1401 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */
1402 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
1403 else
1404 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
1405
1406 FindMinimumRSSI(Adapter);
1407 ODM_CmnInfoUpdate(&pHalData->odmpriv, ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
1408 }
1409
odm_RSSIMonitorCheckAP(struct odm_dm_struct * pDM_Odm)1410 void odm_RSSIMonitorCheckAP(struct odm_dm_struct *pDM_Odm)
1411 {
1412 }
1413
ODM_InitAllTimers(struct odm_dm_struct * pDM_Odm)1414 void ODM_InitAllTimers(struct odm_dm_struct *pDM_Odm)
1415 {
1416 timer_setup(&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer, odm_SwAntDivChkAntSwitchCallback, 0);
1417 }
1418
ODM_CancelAllTimers(struct odm_dm_struct * pDM_Odm)1419 void ODM_CancelAllTimers(struct odm_dm_struct *pDM_Odm)
1420 {
1421 ODM_CancelTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
1422 }
1423
ODM_ReleaseAllTimers(struct odm_dm_struct * pDM_Odm)1424 void ODM_ReleaseAllTimers(struct odm_dm_struct *pDM_Odm)
1425 {
1426 ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
1427
1428 ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->FastAntTrainingTimer);
1429 }
1430
1431 /* 3============================================================ */
1432 /* 3 Tx Power Tracking */
1433 /* 3============================================================ */
1434
odm_TXPowerTrackingInit(struct odm_dm_struct * pDM_Odm)1435 void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm)
1436 {
1437 odm_TXPowerTrackingThermalMeterInit(pDM_Odm);
1438 }
1439
odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct * pDM_Odm)1440 void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm)
1441 {
1442 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true;
1443 pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
1444 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false;
1445 if (*pDM_Odm->mp_mode != 1)
1446 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1447 MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl);
1448
1449 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1450 }
1451
ODM_TXPowerTrackingCheck(struct odm_dm_struct * pDM_Odm)1452 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm)
1453 {
1454 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1455 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1456 /* HW dynamic mechanism. */
1457 switch (pDM_Odm->SupportPlatform) {
1458 case ODM_MP:
1459 odm_TXPowerTrackingCheckMP(pDM_Odm);
1460 break;
1461 case ODM_CE:
1462 odm_TXPowerTrackingCheckCE(pDM_Odm);
1463 break;
1464 case ODM_AP:
1465 odm_TXPowerTrackingCheckAP(pDM_Odm);
1466 break;
1467 case ODM_ADSL:
1468 break;
1469 }
1470 }
1471
odm_TXPowerTrackingCheckCE(struct odm_dm_struct * pDM_Odm)1472 void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm)
1473 {
1474 struct adapter *Adapter = pDM_Odm->Adapter;
1475
1476 if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
1477 return;
1478
1479 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */
1480 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
1481
1482 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
1483 return;
1484 } else {
1485 odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter);
1486 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0;
1487 }
1488 }
1489
odm_TXPowerTrackingCheckMP(struct odm_dm_struct * pDM_Odm)1490 void odm_TXPowerTrackingCheckMP(struct odm_dm_struct *pDM_Odm)
1491 {
1492 }
1493
odm_TXPowerTrackingCheckAP(struct odm_dm_struct * pDM_Odm)1494 void odm_TXPowerTrackingCheckAP(struct odm_dm_struct *pDM_Odm)
1495 {
1496 }
1497
1498 /* antenna mapping info */
1499 /* 1: right-side antenna */
1500 /* 2/0: left-side antenna */
1501 /* PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 */
1502 /* PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 */
1503 /* We select left antenna as default antenna in initial process, modify it as needed */
1504 /* */
1505
1506 /* 3============================================================ */
1507 /* 3 SW Antenna Diversity */
1508 /* 3============================================================ */
odm_SwAntDivInit(struct odm_dm_struct * pDM_Odm)1509 void odm_SwAntDivInit(struct odm_dm_struct *pDM_Odm)
1510 {
1511 }
1512
ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct * pDM_Odm,u8 StationID,struct odm_phy_status_info * pPhyInfo)1513 void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u8 StationID, struct odm_phy_status_info *pPhyInfo)
1514 {
1515 }
1516
odm_SwAntDivChkAntSwitch(struct odm_dm_struct * pDM_Odm,u8 Step)1517 void odm_SwAntDivChkAntSwitch(struct odm_dm_struct *pDM_Odm, u8 Step)
1518 {
1519 }
1520
ODM_SwAntDivRestAfterLink(struct odm_dm_struct * pDM_Odm)1521 void ODM_SwAntDivRestAfterLink(struct odm_dm_struct *pDM_Odm)
1522 {
1523 }
1524
odm_SwAntDivChkAntSwitchCallback(struct timer_list * t)1525 void odm_SwAntDivChkAntSwitchCallback(struct timer_list *t)
1526 {
1527 }
1528
1529 /* 3============================================================ */
1530 /* 3 SW Antenna Diversity */
1531 /* 3============================================================ */
1532
odm_InitHybridAntDiv(struct odm_dm_struct * pDM_Odm)1533 void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm)
1534 {
1535 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
1536 return;
1537
1538 if (pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D))
1539 ;
1540 else if (pDM_Odm->SupportICType == ODM_RTL8188E)
1541 ODM_AntennaDiversityInit_88E(pDM_Odm);
1542 }
1543
ODM_AntselStatistics_88C(struct odm_dm_struct * pDM_Odm,u8 MacId,u32 PWDBAll,bool isCCKrate)1544 void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate)
1545 {
1546 struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1547
1548 if (pDM_SWAT_Table->antsel == 1) {
1549 if (isCCKrate) {
1550 pDM_SWAT_Table->CCK_Ant1_Cnt[MacId]++;
1551 } else {
1552 pDM_SWAT_Table->OFDM_Ant1_Cnt[MacId]++;
1553 pDM_SWAT_Table->RSSI_Ant1_Sum[MacId] += PWDBAll;
1554 }
1555 } else {
1556 if (isCCKrate) {
1557 pDM_SWAT_Table->CCK_Ant2_Cnt[MacId]++;
1558 } else {
1559 pDM_SWAT_Table->OFDM_Ant2_Cnt[MacId]++;
1560 pDM_SWAT_Table->RSSI_Ant2_Sum[MacId] += PWDBAll;
1561 }
1562 }
1563 }
1564
odm_HwAntDiv(struct odm_dm_struct * pDM_Odm)1565 void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm)
1566 {
1567 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
1568 return;
1569
1570 if (pDM_Odm->SupportICType == ODM_RTL8188E)
1571 ODM_AntennaDiversity_88E(pDM_Odm);
1572 }
1573
1574 /* EDCA Turbo */
ODM_EdcaTurboInit(struct odm_dm_struct * pDM_Odm)1575 void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm)
1576 {
1577 struct adapter *Adapter = pDM_Odm->Adapter;
1578 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1579 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1580 Adapter->recvpriv.bIsAnyNonBEPkts = false;
1581
1582 } /* ODM_InitEdcaTurbo */
1583
odm_EdcaTurboCheck(struct odm_dm_struct * pDM_Odm)1584 void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm)
1585 {
1586 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1587 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1588 /* HW dynamic mechanism. */
1589 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
1590 return;
1591
1592 switch (pDM_Odm->SupportPlatform) {
1593 case ODM_MP:
1594 break;
1595 case ODM_CE:
1596 odm_EdcaTurboCheckCE(pDM_Odm);
1597 break;
1598 case ODM_AP:
1599 case ODM_ADSL:
1600 break;
1601 }
1602 } /* odm_CheckEdcaTurbo */
1603
odm_EdcaTurboCheckCE(struct odm_dm_struct * pDM_Odm)1604 void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm)
1605 {
1606 struct adapter *Adapter = pDM_Odm->Adapter;
1607 u32 trafficIndex;
1608 u32 edca_param;
1609 u64 cur_tx_bytes = 0;
1610 u64 cur_rx_bytes = 0;
1611 u8 bbtchange = false;
1612 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
1613 struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
1614 struct recv_priv *precvpriv = &Adapter->recvpriv;
1615 struct registry_priv *pregpriv = &Adapter->registrypriv;
1616 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1617 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1618
1619 if (pregpriv->wifi_spec == 1)
1620 goto dm_CheckEdcaTurbo_EXIT;
1621
1622 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX)
1623 goto dm_CheckEdcaTurbo_EXIT;
1624
1625 /* Check if the status needs to be changed. */
1626 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
1627 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1628 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1629
1630 /* traffic, TX or RX */
1631 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1632 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1633 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1634 /* Uplink TP is present. */
1635 trafficIndex = UP_LINK;
1636 } else {
1637 /* Balance TP is present. */
1638 trafficIndex = DOWN_LINK;
1639 }
1640 } else {
1641 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1642 /* Downlink TP is present. */
1643 trafficIndex = DOWN_LINK;
1644 } else {
1645 /* Balance TP is present. */
1646 trafficIndex = UP_LINK;
1647 }
1648 }
1649
1650 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1651 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1652 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1653 else
1654 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1655
1656 rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
1657
1658 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1659 }
1660
1661 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1662 } else {
1663 /* Turn Off EDCA turbo here. */
1664 /* Restore original EDCA according to the declaration of AP. */
1665 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
1666 rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
1667 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1668 }
1669 }
1670
1671 dm_CheckEdcaTurbo_EXIT:
1672 /* Set variables for next time. */
1673 precvpriv->bIsAnyNonBEPkts = false;
1674 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1675 precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1676 }
1677
1678 /* need to ODM CE Platform */
1679 /* move to here for ANT detection mechanism using */
1680
GetPSDData(struct odm_dm_struct * pDM_Odm,unsigned int point,u8 initial_gain_psd)1681 u32 GetPSDData(struct odm_dm_struct *pDM_Odm, unsigned int point, u8 initial_gain_psd)
1682 {
1683 u32 psd_report;
1684
1685 /* Set DCO frequency index, offset=(40MHz/SamplePts)*point */
1686 ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
1687
1688 /* Start PSD calculation, Reg808[22]=0->1 */
1689 ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 1);
1690 /* Need to wait for HW PSD report */
1691 ODM_StallExecution(30);
1692 ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 0);
1693 /* Read PSD report, Reg8B4[15:0] */
1694 psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF;
1695
1696 psd_report = (u32)(ConvertTo_dB(psd_report)) + (u32)(initial_gain_psd - 0x1c);
1697
1698 return psd_report;
1699 }
1700
ConvertTo_dB(u32 Value)1701 u32 ConvertTo_dB(u32 Value)
1702 {
1703 u8 i;
1704 u8 j;
1705 u32 dB;
1706
1707 Value = Value & 0xFFFF;
1708 for (i = 0; i < 8; i++) {
1709 if (Value <= dB_Invert_Table[i][11])
1710 break;
1711 }
1712
1713 if (i >= 8)
1714 return 96; /* maximum 96 dB */
1715
1716 for (j = 0; j < 12; j++) {
1717 if (Value <= dB_Invert_Table[i][j])
1718 break;
1719 }
1720
1721 dB = i * 12 + j + 1;
1722
1723 return dB;
1724 }
1725
1726 /* 2011/09/22 MH Add for 92D global spin lock utilization. */
odm_GlobalAdapterCheck(void)1727 void odm_GlobalAdapterCheck(void)
1728 {
1729 } /* odm_GlobalAdapterCheck */
1730
1731 /* Description: */
1732 /* Set Single/Dual Antenna default setting for products that do not do detection in advance. */
1733 /* Added by Joseph, 2012.03.22 */
ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct * pDM_Odm)1734 void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm)
1735 {
1736 struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1737
1738 pDM_SWAT_Table->ANTA_ON = true;
1739 pDM_SWAT_Table->ANTB_ON = true;
1740 }
1741
1742 /* 2 8723A ANT DETECT */
1743
odm_PHY_SaveAFERegisters(struct odm_dm_struct * pDM_Odm,u32 * AFEReg,u32 * AFEBackup,u32 RegisterNum)1744 static void odm_PHY_SaveAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegisterNum)
1745 {
1746 u32 i;
1747
1748 /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
1749 for (i = 0; i < RegisterNum; i++)
1750 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
1751 }
1752
odm_PHY_ReloadAFERegisters(struct odm_dm_struct * pDM_Odm,u32 * AFEReg,u32 * AFEBackup,u32 RegiesterNum)1753 static void odm_PHY_ReloadAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegiesterNum)
1754 {
1755 u32 i;
1756
1757 for (i = 0; i < RegiesterNum; i++)
1758 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
1759 }
1760
1761 /* 2 8723A ANT DETECT */
1762 /* Description: */
1763 /* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */
1764 /* This function is cooperated with BB team Neil. */
ODM_SingleDualAntennaDetection(struct odm_dm_struct * pDM_Odm,u8 mode)1765 bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode)
1766 {
1767 struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1768 u32 CurrentChannel, RfLoopReg;
1769 u8 n;
1770 u32 Reg88c, Regc08, Reg874, Regc50;
1771 u8 initial_gain = 0x5a;
1772 u32 PSD_report_tmp;
1773 u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
1774 bool bResult = true;
1775 u32 AFE_Backup[16];
1776 u32 AFE_REG_8723A[16] = {
1777 rRx_Wait_CCA, rTx_CCK_RFON,
1778 rTx_CCK_BBON, rTx_OFDM_RFON,
1779 rTx_OFDM_BBON, rTx_To_Rx,
1780 rTx_To_Tx, rRx_CCK,
1781 rRx_OFDM, rRx_Wait_RIFS,
1782 rRx_TO_Rx, rStandby,
1783 rSleep, rPMPD_ANAEN,
1784 rFPGA0_XCD_SwitchControl, rBlue_Tooth};
1785
1786 if (!(pDM_Odm->SupportICType & (ODM_RTL8723A | ODM_RTL8192C)))
1787 return bResult;
1788
1789 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
1790 return bResult;
1791
1792 if (pDM_Odm->SupportICType == ODM_RTL8192C) {
1793 /* Which path in ADC/DAC is turnned on for PSD: both I/Q */
1794 ODM_SetBBReg(pDM_Odm, 0x808, BIT(10) | BIT(11), 0x3);
1795 /* Ageraged number: 8 */
1796 ODM_SetBBReg(pDM_Odm, 0x808, BIT(12) | BIT(13), 0x1);
1797 /* pts = 128; */
1798 ODM_SetBBReg(pDM_Odm, 0x808, BIT(14) | BIT(15), 0x0);
1799 }
1800
1801 /* 1 Backup Current RF/BB Settings */
1802
1803 CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
1804 RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
1805 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); /* change to Antenna A */
1806 /* Step 1: USE IQK to transmitter single tone */
1807
1808 ODM_StallExecution(10);
1809
1810 /* Store A Path Register 88c, c08, 874, c50 */
1811 Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
1812 Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
1813 Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
1814 Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
1815
1816 /* Store AFE Registers */
1817 odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1818
1819 /* Set PSD 128 pts */
1820 ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT(14) | BIT(15), 0x0); /* 128 pts */
1821
1822 /* To SET CH1 to do */
1823 ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); /* Channel 1 */
1824
1825 /* AFE all on step */
1826 ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
1827 ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
1828 ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
1829 ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
1830 ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
1831 ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
1832 ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
1833 ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
1834 ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
1835 ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
1836 ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
1837 ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
1838 ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
1839 ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
1840 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
1841 ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
1842
1843 /* 3 wire Disable */
1844 ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
1845
1846 /* BB IQK Setting */
1847 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
1848 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
1849
1850 /* IQK setting tone@ 4.34Mhz */
1851 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
1852 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
1853
1854 /* Page B init */
1855 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
1856 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
1857 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
1858 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
1859 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
1860 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
1861 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
1862
1863 /* RF loop Setting */
1864 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
1865
1866 /* IQK Single tone start */
1867 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
1868 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1869 ODM_StallExecution(1000);
1870 PSD_report_tmp = 0x0;
1871
1872 for (n = 0; n < 2; n++) {
1873 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
1874 if (PSD_report_tmp > AntA_report)
1875 AntA_report = PSD_report_tmp;
1876 }
1877
1878 PSD_report_tmp = 0x0;
1879
1880 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); /* change to Antenna B */
1881 ODM_StallExecution(10);
1882
1883 for (n = 0; n < 2; n++) {
1884 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
1885 if (PSD_report_tmp > AntB_report)
1886 AntB_report = PSD_report_tmp;
1887 }
1888
1889 /* change to open case */
1890 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0); /* change to Ant A and B all open case */
1891 ODM_StallExecution(10);
1892
1893 for (n = 0; n < 2; n++) {
1894 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
1895 if (PSD_report_tmp > AntO_report)
1896 AntO_report = PSD_report_tmp;
1897 }
1898
1899 /* Close IQK Single Tone function */
1900 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
1901 PSD_report_tmp = 0x0;
1902
1903 /* 1 Return to antanna A */
1904 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
1905 ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
1906 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
1907 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
1908 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
1909 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
1910 ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
1911 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
1912
1913 /* Reload AFE Registers */
1914 odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1915
1916 if (pDM_Odm->SupportICType == ODM_RTL8723A) {
1917 /* 2 Test Ant B based on Ant A is ON */
1918 if (mode == ANTTESTB) {
1919 if (AntA_report >= 100) {
1920 if (AntB_report > (AntA_report + 1))
1921 pDM_SWAT_Table->ANTB_ON = false;
1922 else
1923 pDM_SWAT_Table->ANTB_ON = true;
1924 } else {
1925 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */
1926 bResult = false;
1927 }
1928 } else if (mode == ANTTESTALL) {
1929 /* 2 Test Ant A and B based on DPDT Open */
1930 if ((AntO_report >= 100) & (AntO_report < 118)) {
1931 if (AntA_report > (AntO_report + 1))
1932 pDM_SWAT_Table->ANTA_ON = false;
1933 else
1934 pDM_SWAT_Table->ANTA_ON = true;
1935
1936 if (AntB_report > (AntO_report + 2))
1937 pDM_SWAT_Table->ANTB_ON = false;
1938 else
1939 pDM_SWAT_Table->ANTB_ON = true;
1940 }
1941 }
1942 } else if (pDM_Odm->SupportICType == ODM_RTL8192C) {
1943 if (AntA_report >= 100) {
1944 if (AntB_report > (AntA_report + 2)) {
1945 pDM_SWAT_Table->ANTA_ON = false;
1946 pDM_SWAT_Table->ANTB_ON = true;
1947 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);
1948 } else if (AntA_report > (AntB_report + 2)) {
1949 pDM_SWAT_Table->ANTA_ON = true;
1950 pDM_SWAT_Table->ANTB_ON = false;
1951 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
1952 } else {
1953 pDM_SWAT_Table->ANTA_ON = true;
1954 pDM_SWAT_Table->ANTB_ON = true;
1955 }
1956 } else {
1957 pDM_SWAT_Table->ANTA_ON = true; /* Set Antenna A on as default */
1958 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */
1959 bResult = false;
1960 }
1961 }
1962 return bResult;
1963 }
1964
1965 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
odm_dtc(struct odm_dm_struct * pDM_Odm)1966 void odm_dtc(struct odm_dm_struct *pDM_Odm)
1967 {
1968 }
1969