1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #ifndef __ASM_SYSREG_H 10 #define __ASM_SYSREG_H 11 12 #include <linux/bits.h> 13 #include <linux/stringify.h> 14 #include <linux/kasan-tags.h> 15 16 /* 17 * ARMv8 ARM reserves the following encoding for system registers: 18 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 19 * C5.2, version:ARM DDI 0487A.f) 20 * [20-19] : Op0 21 * [18-16] : Op1 22 * [15-12] : CRn 23 * [11-8] : CRm 24 * [7-5] : Op2 25 */ 26 #define Op0_shift 19 27 #define Op0_mask 0x3 28 #define Op1_shift 16 29 #define Op1_mask 0x7 30 #define CRn_shift 12 31 #define CRn_mask 0xf 32 #define CRm_shift 8 33 #define CRm_mask 0xf 34 #define Op2_shift 5 35 #define Op2_mask 0x7 36 37 #define sys_reg(op0, op1, crn, crm, op2) \ 38 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 39 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 40 ((op2) << Op2_shift)) 41 42 #define sys_insn sys_reg 43 44 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 45 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 46 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 47 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 48 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 49 50 #ifndef CONFIG_BROKEN_GAS_INST 51 52 #ifdef __ASSEMBLY__ 53 // The space separator is omitted so that __emit_inst(x) can be parsed as 54 // either an assembler directive or an assembler macro argument. 55 #define __emit_inst(x) .inst(x) 56 #else 57 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 58 #endif 59 60 #else /* CONFIG_BROKEN_GAS_INST */ 61 62 #ifndef CONFIG_CPU_BIG_ENDIAN 63 #define __INSTR_BSWAP(x) (x) 64 #else /* CONFIG_CPU_BIG_ENDIAN */ 65 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 66 (((x) << 8) & 0x00ff0000) | \ 67 (((x) >> 8) & 0x0000ff00) | \ 68 (((x) >> 24) & 0x000000ff)) 69 #endif /* CONFIG_CPU_BIG_ENDIAN */ 70 71 #ifdef __ASSEMBLY__ 72 #define __emit_inst(x) .long __INSTR_BSWAP(x) 73 #else /* __ASSEMBLY__ */ 74 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 75 #endif /* __ASSEMBLY__ */ 76 77 #endif /* CONFIG_BROKEN_GAS_INST */ 78 79 /* 80 * Instructions for modifying PSTATE fields. 81 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 82 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 83 * for accessing PSTATE fields have the following encoding: 84 * Op0 = 0, CRn = 4 85 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 86 * CRm = Imm4 for the instruction. 87 * Rt = 0x1f 88 */ 89 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 90 #define PSTATE_Imm_shift CRm_shift 91 92 #define PSTATE_PAN pstate_field(0, 4) 93 #define PSTATE_UAO pstate_field(0, 3) 94 #define PSTATE_SSBS pstate_field(3, 1) 95 #define PSTATE_TCO pstate_field(3, 4) 96 97 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) 98 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) 99 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) 100 #define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift)) 101 102 #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) 103 #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) 104 #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x)) 105 106 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ 107 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) 108 109 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) 110 111 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 112 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4) 113 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6) 114 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 115 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4) 116 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6) 117 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 118 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4) 119 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6) 120 121 /* 122 * System registers, organised loosely by encoding but grouped together 123 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. 124 */ 125 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3) 126 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3) 127 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3) 128 129 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 130 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 131 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 132 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 133 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 134 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 135 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 136 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 137 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 138 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 139 140 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 141 #define SYS_OSLAR_OSLK BIT(0) 142 143 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 144 #define SYS_OSLSR_OSLM_MASK (BIT(3) | BIT(0)) 145 #define SYS_OSLSR_OSLM_NI 0 146 #define SYS_OSLSR_OSLM_IMPLEMENTED BIT(3) 147 #define SYS_OSLSR_OSLK BIT(1) 148 149 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 150 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 151 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 152 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 153 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 154 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 155 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 156 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 157 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 158 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 159 160 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 161 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 162 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 163 164 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 165 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 166 #define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) 167 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 168 #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5) 169 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 170 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 171 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 172 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 173 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 174 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 175 #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) 176 177 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 178 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 179 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 180 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 181 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 182 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 183 #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) 184 185 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 186 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 187 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 188 189 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 190 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 191 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) 192 #define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4, 5) 193 194 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 195 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 196 197 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 198 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 199 200 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 201 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 202 #define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) 203 204 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 205 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 206 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 207 208 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 209 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 210 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 211 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) 212 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) 213 214 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) 215 #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) 216 #define SYS_SMPRI_EL1 sys_reg(3, 0, 1, 2, 4) 217 #define SYS_SMCR_EL1 sys_reg(3, 0, 1, 2, 6) 218 219 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 220 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 221 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 222 223 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 224 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 225 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 226 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 227 228 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 229 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 230 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 231 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 232 233 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 234 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 235 236 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) 237 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) 238 239 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 240 241 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 242 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 243 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 244 245 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 246 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 247 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 248 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 249 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 250 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 251 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 252 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 253 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0) 254 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1) 255 256 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 257 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 258 259 #define SYS_PAR_EL1_F BIT(0) 260 #define SYS_PAR_EL1_FST GENMASK(6, 1) 261 262 /*** Statistical Profiling Extension ***/ 263 /* ID registers */ 264 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 265 #define SYS_PMSIDR_EL1_FE_SHIFT 0 266 #define SYS_PMSIDR_EL1_FT_SHIFT 1 267 #define SYS_PMSIDR_EL1_FL_SHIFT 2 268 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 269 #define SYS_PMSIDR_EL1_LDS_SHIFT 4 270 #define SYS_PMSIDR_EL1_ERND_SHIFT 5 271 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 272 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 273 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 274 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 275 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 276 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 277 278 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 279 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 280 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 281 #define SYS_PMBIDR_EL1_P_SHIFT 4 282 #define SYS_PMBIDR_EL1_F_SHIFT 5 283 284 /* Sampling controls */ 285 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 286 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0 287 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1 288 #define SYS_PMSCR_EL1_CX_SHIFT 3 289 #define SYS_PMSCR_EL1_PA_SHIFT 4 290 #define SYS_PMSCR_EL1_TS_SHIFT 5 291 #define SYS_PMSCR_EL1_PCT_SHIFT 6 292 293 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 294 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 295 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1 296 #define SYS_PMSCR_EL2_CX_SHIFT 3 297 #define SYS_PMSCR_EL2_PA_SHIFT 4 298 #define SYS_PMSCR_EL2_TS_SHIFT 5 299 #define SYS_PMSCR_EL2_PCT_SHIFT 6 300 301 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 302 303 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 304 #define SYS_PMSIRR_EL1_RND_SHIFT 0 305 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 306 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 307 308 /* Filtering controls */ 309 #define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1) 310 311 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 312 #define SYS_PMSFCR_EL1_FE_SHIFT 0 313 #define SYS_PMSFCR_EL1_FT_SHIFT 1 314 #define SYS_PMSFCR_EL1_FL_SHIFT 2 315 #define SYS_PMSFCR_EL1_B_SHIFT 16 316 #define SYS_PMSFCR_EL1_LD_SHIFT 17 317 #define SYS_PMSFCR_EL1_ST_SHIFT 18 318 319 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 320 #define SYS_PMSEVFR_EL1_RES0_8_2 \ 321 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ 322 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) 323 #define SYS_PMSEVFR_EL1_RES0_8_3 \ 324 (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) 325 326 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 327 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 328 329 /* Buffer controls */ 330 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 331 #define SYS_PMBLIMITR_EL1_E_SHIFT 0 332 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1 333 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 334 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 335 336 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 337 338 /* Buffer error reporting */ 339 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 340 #define SYS_PMBSR_EL1_COLL_SHIFT 16 341 #define SYS_PMBSR_EL1_S_SHIFT 17 342 #define SYS_PMBSR_EL1_EA_SHIFT 18 343 #define SYS_PMBSR_EL1_DL_SHIFT 19 344 #define SYS_PMBSR_EL1_EC_SHIFT 26 345 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL 346 347 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 348 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 349 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 350 351 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 352 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 353 354 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 355 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 356 357 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 358 359 /*** End of Statistical Profiling Extension ***/ 360 361 /* 362 * TRBE Registers 363 */ 364 #define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0) 365 #define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1) 366 #define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2) 367 #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3) 368 #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4) 369 #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) 370 #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7) 371 372 #define TRBLIMITR_LIMIT_MASK GENMASK_ULL(51, 0) 373 #define TRBLIMITR_LIMIT_SHIFT 12 374 #define TRBLIMITR_NVM BIT(5) 375 #define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0) 376 #define TRBLIMITR_TRIG_MODE_SHIFT 3 377 #define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0) 378 #define TRBLIMITR_FILL_MODE_SHIFT 1 379 #define TRBLIMITR_ENABLE BIT(0) 380 #define TRBPTR_PTR_MASK GENMASK_ULL(63, 0) 381 #define TRBPTR_PTR_SHIFT 0 382 #define TRBBASER_BASE_MASK GENMASK_ULL(51, 0) 383 #define TRBBASER_BASE_SHIFT 12 384 #define TRBSR_EC_MASK GENMASK(5, 0) 385 #define TRBSR_EC_SHIFT 26 386 #define TRBSR_IRQ BIT(22) 387 #define TRBSR_TRG BIT(21) 388 #define TRBSR_WRAP BIT(20) 389 #define TRBSR_ABORT BIT(18) 390 #define TRBSR_STOP BIT(17) 391 #define TRBSR_MSS_MASK GENMASK(15, 0) 392 #define TRBSR_MSS_SHIFT 0 393 #define TRBSR_BSC_MASK GENMASK(5, 0) 394 #define TRBSR_BSC_SHIFT 0 395 #define TRBSR_FSC_MASK GENMASK(5, 0) 396 #define TRBSR_FSC_SHIFT 0 397 #define TRBMAR_SHARE_MASK GENMASK(1, 0) 398 #define TRBMAR_SHARE_SHIFT 8 399 #define TRBMAR_OUTER_MASK GENMASK(3, 0) 400 #define TRBMAR_OUTER_SHIFT 4 401 #define TRBMAR_INNER_MASK GENMASK(3, 0) 402 #define TRBMAR_INNER_SHIFT 0 403 #define TRBTRG_TRG_MASK GENMASK(31, 0) 404 #define TRBTRG_TRG_SHIFT 0 405 #define TRBIDR_FLAG BIT(5) 406 #define TRBIDR_PROG BIT(4) 407 #define TRBIDR_ALIGN_MASK GENMASK(3, 0) 408 #define TRBIDR_ALIGN_SHIFT 0 409 410 #define SMPRI_EL1_PRIORITY_MASK 0xf 411 412 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 413 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 414 415 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6) 416 417 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 418 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 419 420 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) 421 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) 422 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) 423 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) 424 #define SYS_MPAMIDR_EL1 sys_reg(3, 0, 10, 4, 4) 425 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) 426 #define SYS_MPAM1_EL1 sys_reg(3, 0, 10, 5, 0) 427 #define SYS_MPAM0_EL1 sys_reg(3, 0, 10, 5, 1) 428 429 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 430 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 431 432 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 433 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 434 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 435 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 436 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 437 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 438 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 439 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 440 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 441 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 442 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 443 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 444 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 445 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 446 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 447 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 448 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 449 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 450 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 451 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 452 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 453 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 454 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 455 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 456 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 457 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 458 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 459 460 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 461 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 462 463 #define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7) 464 465 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 466 467 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) 468 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 469 #define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4) 470 #define SYS_SMIDR_EL1 sys_reg(3, 1, 0, 0, 6) 471 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 472 473 #define SMIDR_EL1_IMPLEMENTER_SHIFT 24 474 #define SMIDR_EL1_SMPS_SHIFT 15 475 #define SMIDR_EL1_AFFINITY_SHIFT 0 476 477 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 478 479 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 480 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 481 482 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) 483 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) 484 485 #define SYS_SVCR sys_reg(3, 3, 4, 2, 2) 486 #define SVCR_ZA_MASK 2 487 #define SVCR_SM_MASK 1 488 489 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 490 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 491 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 492 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 493 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 494 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 495 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 496 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 497 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 498 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 499 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 500 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 501 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 502 503 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 504 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 505 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5) 506 507 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7) 508 509 /* Definitions for system register interface to AMU for ARMv8.4 onwards */ 510 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) 511 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) 512 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) 513 #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) 514 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) 515 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) 516 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) 517 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) 518 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) 519 520 /* 521 * Group 0 of activity monitors (architected): 522 * op0 op1 CRn CRm op2 523 * Counter: 11 011 1101 010:n<3> n<2:0> 524 * Type: 11 011 1101 011:n<3> n<2:0> 525 * n: 0-15 526 * 527 * Group 1 of activity monitors (auxiliary): 528 * op0 op1 CRn CRm op2 529 * Counter: 11 011 1101 110:n<3> n<2:0> 530 * Type: 11 011 1101 111:n<3> n<2:0> 531 * n: 0-15 532 */ 533 534 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) 535 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) 536 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) 537 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) 538 539 /* AMU v1: Fixed (architecturally defined) activity monitors */ 540 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) 541 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) 542 #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) 543 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) 544 545 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 546 547 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 548 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 549 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 550 551 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) 552 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) 553 554 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 555 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 556 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 557 558 #define __PMEV_op2(n) ((n) & 0x7) 559 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 560 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 561 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 562 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 563 564 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) 565 566 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) 567 #define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4) 568 #define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5) 569 #define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6) 570 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 571 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) 572 #define SYS_HCRX_EL2 sys_reg(3, 4, 1, 2, 2) 573 #define SYS_SMPRIMAP_EL2 sys_reg(3, 4, 1, 2, 5) 574 #define SYS_SMCR_EL2 sys_reg(3, 4, 1, 2, 6) 575 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 576 #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4) 577 #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5) 578 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) 579 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) 580 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) 581 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 582 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) 583 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 584 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 585 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0) 586 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) 587 588 #define SYS_MPAMHCR_EL2 sys_reg(3, 4, 10, 4, 0) 589 #define SYS_MPAMVPMV_EL2 sys_reg(3, 4, 10, 4, 1) 590 #define SYS_MPAM2_EL2 sys_reg(3, 4, 10, 5, 0) 591 592 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 593 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 594 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 595 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 596 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 597 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 598 599 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 600 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 601 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 602 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 603 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 604 605 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 606 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 607 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 608 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 609 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 610 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 611 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 612 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 613 614 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 615 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 616 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 617 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 618 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 619 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 620 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 621 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 622 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 623 624 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 625 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 626 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 627 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 628 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 629 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 630 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 631 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 632 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 633 634 /* VHE encodings for architectural EL0/1 system registers */ 635 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) 636 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) 637 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) 638 #define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6) 639 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) 640 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) 641 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) 642 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) 643 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) 644 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) 645 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) 646 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) 647 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) 648 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) 649 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) 650 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) 651 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) 652 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) 653 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) 654 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) 655 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) 656 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) 657 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) 658 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) 659 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) 660 661 /* Common SCTLR_ELx flags. */ 662 #define SCTLR_ELx_ENTP2 (BIT(60)) 663 #define SCTLR_ELx_DSSBS (BIT(44)) 664 #define SCTLR_ELx_ATA (BIT(43)) 665 666 #define SCTLR_ELx_TCF_SHIFT 40 667 #define SCTLR_ELx_TCF_NONE (UL(0x0) << SCTLR_ELx_TCF_SHIFT) 668 #define SCTLR_ELx_TCF_SYNC (UL(0x1) << SCTLR_ELx_TCF_SHIFT) 669 #define SCTLR_ELx_TCF_ASYNC (UL(0x2) << SCTLR_ELx_TCF_SHIFT) 670 #define SCTLR_ELx_TCF_ASYMM (UL(0x3) << SCTLR_ELx_TCF_SHIFT) 671 #define SCTLR_ELx_TCF_MASK (UL(0x3) << SCTLR_ELx_TCF_SHIFT) 672 673 #define SCTLR_ELx_ENIA_SHIFT 31 674 675 #define SCTLR_ELx_ITFSB (BIT(37)) 676 #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT)) 677 #define SCTLR_ELx_ENIB (BIT(30)) 678 #define SCTLR_ELx_ENDA (BIT(27)) 679 #define SCTLR_ELx_EE (BIT(25)) 680 #define SCTLR_ELx_IESB (BIT(21)) 681 #define SCTLR_ELx_WXN (BIT(19)) 682 #define SCTLR_ELx_ENDB (BIT(13)) 683 #define SCTLR_ELx_I (BIT(12)) 684 #define SCTLR_ELx_SA (BIT(3)) 685 #define SCTLR_ELx_C (BIT(2)) 686 #define SCTLR_ELx_A (BIT(1)) 687 #define SCTLR_ELx_M (BIT(0)) 688 689 /* SCTLR_EL2 specific flags. */ 690 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 691 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 692 (BIT(29))) 693 694 #ifdef CONFIG_CPU_BIG_ENDIAN 695 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 696 #else 697 #define ENDIAN_SET_EL2 0 698 #endif 699 700 #define INIT_SCTLR_EL2_MMU_ON \ 701 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \ 702 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | \ 703 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1) 704 705 #define INIT_SCTLR_EL2_MMU_OFF \ 706 (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) 707 708 /* SCTLR_EL1 specific flags. */ 709 #define SCTLR_EL1_EPAN (BIT(57)) 710 #define SCTLR_EL1_ATA0 (BIT(42)) 711 712 #define SCTLR_EL1_TCF0_SHIFT 38 713 #define SCTLR_EL1_TCF0_NONE (UL(0x0) << SCTLR_EL1_TCF0_SHIFT) 714 #define SCTLR_EL1_TCF0_SYNC (UL(0x1) << SCTLR_EL1_TCF0_SHIFT) 715 #define SCTLR_EL1_TCF0_ASYNC (UL(0x2) << SCTLR_EL1_TCF0_SHIFT) 716 #define SCTLR_EL1_TCF0_ASYMM (UL(0x3) << SCTLR_EL1_TCF0_SHIFT) 717 #define SCTLR_EL1_TCF0_MASK (UL(0x3) << SCTLR_EL1_TCF0_SHIFT) 718 719 #define SCTLR_EL1_BT1 (BIT(36)) 720 #define SCTLR_EL1_BT0 (BIT(35)) 721 #define SCTLR_EL1_UCI (BIT(26)) 722 #define SCTLR_EL1_E0E (BIT(24)) 723 #define SCTLR_EL1_SPAN (BIT(23)) 724 #define SCTLR_EL1_NTWE (BIT(18)) 725 #define SCTLR_EL1_NTWI (BIT(16)) 726 #define SCTLR_EL1_UCT (BIT(15)) 727 #define SCTLR_EL1_DZE (BIT(14)) 728 #define SCTLR_EL1_UMA (BIT(9)) 729 #define SCTLR_EL1_SED (BIT(8)) 730 #define SCTLR_EL1_ITD (BIT(7)) 731 #define SCTLR_EL1_CP15BEN (BIT(5)) 732 #define SCTLR_EL1_SA0 (BIT(4)) 733 734 #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \ 735 (BIT(29))) 736 737 #ifdef CONFIG_CPU_BIG_ENDIAN 738 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 739 #else 740 #define ENDIAN_SET_EL1 0 741 #endif 742 743 #define INIT_SCTLR_EL1_MMU_OFF \ 744 (ENDIAN_SET_EL1 | SCTLR_EL1_RES1) 745 746 #define INIT_SCTLR_EL1_MMU_ON \ 747 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_EL1_SA0 | \ 748 SCTLR_EL1_SED | SCTLR_ELx_I | SCTLR_EL1_DZE | SCTLR_EL1_UCT | \ 749 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \ 750 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | SCTLR_EL1_RES1) 751 752 /* MAIR_ELx memory attributes (used by Linux) */ 753 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) 754 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) 755 #define MAIR_ATTR_NORMAL_NC UL(0x44) 756 #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0) 757 #define MAIR_ATTR_NORMAL UL(0xff) 758 #define MAIR_ATTR_MASK UL(0xff) 759 #define MAIR_ATTR_NORMAL_iNC_oWB UL(0xf4) 760 761 /* Position the attr at the correct index */ 762 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) 763 764 /* id_aa64isar0 */ 765 #define ID_AA64ISAR0_EL1_RNDR_SHIFT 60 766 #define ID_AA64ISAR0_EL1_TLB_SHIFT 56 767 #define ID_AA64ISAR0_EL1_TS_SHIFT 52 768 #define ID_AA64ISAR0_EL1_FHM_SHIFT 48 769 #define ID_AA64ISAR0_EL1_DP_SHIFT 44 770 #define ID_AA64ISAR0_EL1_SM4_SHIFT 40 771 #define ID_AA64ISAR0_EL1_SM3_SHIFT 36 772 #define ID_AA64ISAR0_EL1_SHA3_SHIFT 32 773 #define ID_AA64ISAR0_EL1_RDM_SHIFT 28 774 #define ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20 775 #define ID_AA64ISAR0_EL1_CRC32_SHIFT 16 776 #define ID_AA64ISAR0_EL1_SHA2_SHIFT 12 777 #define ID_AA64ISAR0_EL1_SHA1_SHIFT 8 778 #define ID_AA64ISAR0_EL1_AES_SHIFT 4 779 780 #define ID_AA64ISAR0_EL1_TLB_RANGE_NI 0x0 781 #define ID_AA64ISAR0_EL1_TLB_RANGE 0x2 782 783 /* id_aa64isar1 */ 784 #define ID_AA64ISAR1_EL1_I8MM_SHIFT 52 785 #define ID_AA64ISAR1_EL1_DGH_SHIFT 48 786 #define ID_AA64ISAR1_EL1_BF16_SHIFT 44 787 #define ID_AA64ISAR1_EL1_BF16_MASK (0xfUL << ID_AA64ISAR1_EL1_BF16_SHIFT) 788 #define ID_AA64ISAR1_EL1_SPECRES_SHIFT 40 789 #define ID_AA64ISAR1_EL1_SB_SHIFT 36 790 #define ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32 791 #define ID_AA64ISAR1_EL1_GPI_SHIFT 28 792 #define ID_AA64ISAR1_EL1_GPA_SHIFT 24 793 #define ID_AA64ISAR1_EL1_LRCPC_SHIFT 20 794 #define ID_AA64ISAR1_EL1_FCMA_SHIFT 16 795 #define ID_AA64ISAR1_EL1_JSCVT_SHIFT 12 796 #define ID_AA64ISAR1_EL1_API_SHIFT 8 797 #define ID_AA64ISAR1_EL1_APA_SHIFT 4 798 #define ID_AA64ISAR1_EL1_DPB_SHIFT 0 799 800 #define ID_AA64ISAR1_EL1_APA_NI 0x0 801 #define ID_AA64ISAR1_EL1_APA_PAuth 0x1 802 #define ID_AA64ISAR1_EL1_APA_ARCH_EPAC 0x2 803 #define ID_AA64ISAR1_EL1_APA_Pauth2 0x3 804 #define ID_AA64ISAR1_EL1_APA_FPAC 0x4 805 #define ID_AA64ISAR1_EL1_APA_FPACCOMBINE 0x5 806 #define ID_AA64ISAR1_EL1_API_NI 0x0 807 #define ID_AA64ISAR1_EL1_API_PAuth 0x1 808 #define ID_AA64ISAR1_EL1_API_EPAC 0x2 809 #define ID_AA64ISAR1_EL1_API_PAuth2 0x3 810 #define ID_AA64ISAR1_EL1_API_FPAC 0x4 811 #define ID_AA64ISAR1_EL1_API_FPACCOMBINE 0x5 812 #define ID_AA64ISAR1_EL1_GPA_NI 0x0 813 #define ID_AA64ISAR1_EL1_GPA_IMP 0x1 814 #define ID_AA64ISAR1_EL1_GPI_NI 0x0 815 #define ID_AA64ISAR1_EL1_GPI_IMP 0x1 816 817 /* id_aa64isar2 */ 818 #define ID_AA64ISAR2_EL1_BC_SHIFT 28 819 #define ID_AA64ISAR2_EL1_APA3_SHIFT 12 820 #define ID_AA64ISAR2_EL1_GPA3_SHIFT 8 821 #define ID_AA64ISAR2_EL1_RPRES_SHIFT 4 822 #define ID_AA64ISAR2_EL1_WFxT_SHIFT 0 823 824 #define ID_AA64ISAR2_RPRES_8BIT 0x0 825 #define ID_AA64ISAR2_RPRES_12BIT 0x1 826 /* 827 * Value 0x1 has been removed from the architecture, and is 828 * reserved, but has not yet been removed from the ARM ARM 829 * as of ARM DDI 0487G.b. 830 */ 831 #define ID_AA64ISAR2_EL1_WFxT_NI 0x0 832 #define ID_AA64ISAR2_EL1_WFxT_IMP 0x2 833 834 #define ID_AA64ISAR2_EL1_APA3_NI 0x0 835 #define ID_AA64ISAR2_EL1_APA3_PAuth 0x1 836 #define ID_AA64ISAR2_EL1_APA3_EPAC 0x2 837 #define ID_AA64ISAR2_EL1_APA3_PAuth2 0x3 838 #define ID_AA64ISAR2_EL1_APA3_FPAC 0x4 839 #define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE 0x5 840 841 #define ID_AA64ISAR2_EL1_GPA3_NI 0x0 842 #define ID_AA64ISAR2_EL1_GPA3_IMP 0x1 843 844 /* id_aa64pfr0 */ 845 #define ID_AA64PFR0_EL1_CSV3_SHIFT 60 846 #define ID_AA64PFR0_EL1_CSV2_SHIFT 56 847 #define ID_AA64PFR0_EL1_DIT_SHIFT 48 848 #define ID_AA64PFR0_EL1_AMU_SHIFT 44 849 #define ID_AA64PFR0_EL1_MPAM_SHIFT 40 850 #define ID_AA64PFR0_EL1_SEL2_SHIFT 36 851 #define ID_AA64PFR0_EL1_SVE_SHIFT 32 852 #define ID_AA64PFR0_EL1_RAS_SHIFT 28 853 #define ID_AA64PFR0_EL1_GIC_SHIFT 24 854 #define ID_AA64PFR0_EL1_AdvSIMD_SHIFT 20 855 #define ID_AA64PFR0_EL1_FP_SHIFT 16 856 #define ID_AA64PFR0_EL1_EL3_SHIFT 12 857 #define ID_AA64PFR0_EL1_EL2_SHIFT 8 858 #define ID_AA64PFR0_EL1_EL1_SHIFT 4 859 #define ID_AA64PFR0_EL1_EL0_SHIFT 0 860 861 #define ID_AA64PFR0_EL1_AMU_IMP 0x1 862 #define ID_AA64PFR0_EL1_SVE_IMP 0x1 863 #define ID_AA64PFR0_EL1_RAS_IMP 0x1 864 #define ID_AA64PFR0_EL1_RAS_V1P1 0x2 865 #define ID_AA64PFR0_EL1_FP_NI 0xf 866 #define ID_AA64PFR0_EL1_FP_IMP 0x0 867 #define ID_AA64PFR0_EL1_AdvSIMD_NI 0xf 868 #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY 0x1 869 #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT 0x2 870 871 /* id_aa64pfr1 */ 872 #define ID_AA64PFR1_EL1_SME_SHIFT 24 873 #define ID_AA64PFR1_EL1_MPAM_frac_SHIFT 16 874 #define ID_AA64PFR1_EL1_RAS_frac_SHIFT 12 875 #define ID_AA64PFR1_EL1_MTE_SHIFT 8 876 #define ID_AA64PFR1_EL1_SSBS_SHIFT 4 877 #define ID_AA64PFR1_EL1_BT_SHIFT 0 878 879 #define ID_AA64PFR1_EL1_SSBS_NI 0 880 #define ID_AA64PFR1_EL1_SSBS_IMP 1 881 #define ID_AA64PFR1_EL1_SSBS_SSBS2 2 882 #define ID_AA64PFR1_EL1_BT_IMP 0x1 883 #define ID_AA64PFR1_EL1_SME_IMP 1 884 885 #define ID_AA64PFR1_EL1_MTE_NI 0x0 886 #define ID_AA64PFR1_EL1_MTE_IMP 0x1 887 #define ID_AA64PFR1_EL1_MTE_MTE2 0x2 888 #define ID_AA64PFR1_EL1_MTE_MTE3 0x3 889 890 /* id_aa64zfr0 */ 891 #define ID_AA64ZFR0_EL1_F64MM_SHIFT 56 892 #define ID_AA64ZFR0_EL1_F32MM_SHIFT 52 893 #define ID_AA64ZFR0_EL1_I8MM_SHIFT 44 894 #define ID_AA64ZFR0_EL1_SM4_SHIFT 40 895 #define ID_AA64ZFR0_EL1_SHA3_SHIFT 32 896 #define ID_AA64ZFR0_EL1_BF16_SHIFT 20 897 #define ID_AA64ZFR0_EL1_BitPerm_SHIFT 16 898 #define ID_AA64ZFR0_EL1_AES_SHIFT 4 899 #define ID_AA64ZFR0_EL1_SVEver_SHIFT 0 900 901 #define ID_AA64ZFR0_EL1_F64MM_IMP 0x1 902 #define ID_AA64ZFR0_EL1_F32MM_IMP 0x1 903 #define ID_AA64ZFR0_EL1_I8MM_IMP 0x1 904 #define ID_AA64ZFR0_EL1_BF16_IMP 0x1 905 #define ID_AA64ZFR0_EL1_SM4_IMP 0x1 906 #define ID_AA64ZFR0_EL1_SHA3_IMP 0x1 907 #define ID_AA64ZFR0_EL1_BitPerm_IMP 0x1 908 #define ID_AA64ZFR0_EL1_AES_IMP 0x1 909 #define ID_AA64ZFR0_EL1_AES_PMULL128 0x2 910 #define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1 911 912 /* id_aa64smfr0 */ 913 #define ID_AA64SMFR0_EL1_FA64_SHIFT 63 914 #define ID_AA64SMFR0_EL1_I16I64_SHIFT 52 915 #define ID_AA64SMFR0_EL1_F64F64_SHIFT 48 916 #define ID_AA64SMFR0_EL1_I8I32_SHIFT 36 917 #define ID_AA64SMFR0_EL1_F16F32_SHIFT 35 918 #define ID_AA64SMFR0_EL1_B16F32_SHIFT 34 919 #define ID_AA64SMFR0_EL1_F32F32_SHIFT 32 920 921 #define ID_AA64SMFR0_EL1_FA64_IMP 0x1 922 #define ID_AA64SMFR0_EL1_I16I64_IMP 0xf 923 #define ID_AA64SMFR0_EL1_F64F64_IMP 0x1 924 #define ID_AA64SMFR0_EL1_I8I32_IMP 0xf 925 #define ID_AA64SMFR0_EL1_F16F32_IMP 0x1 926 #define ID_AA64SMFR0_EL1_B16F32_IMP 0x1 927 #define ID_AA64SMFR0_EL1_F32F32_IMP 0x1 928 929 /* id_aa64mmfr0 */ 930 #define ID_AA64MMFR0_EL1_ECV_SHIFT 60 931 #define ID_AA64MMFR0_EL1_FGT_SHIFT 56 932 #define ID_AA64MMFR0_EL1_EXS_SHIFT 44 933 #define ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40 934 #define ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36 935 #define ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32 936 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28 937 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24 938 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20 939 #define ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16 940 #define ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12 941 #define ID_AA64MMFR0_EL1_BIGEND_SHIFT 8 942 #define ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4 943 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT 0 944 945 #define ID_AA64MMFR0_EL1_ASIDBITS_8 0x0 946 #define ID_AA64MMFR0_EL1_ASIDBITS_16 0x2 947 948 #define ID_AA64MMFR0_EL1_TGRAN4_NI 0xf 949 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0 950 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7 951 #define ID_AA64MMFR0_EL1_TGRAN64_NI 0xf 952 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0 953 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7 954 #define ID_AA64MMFR0_EL1_TGRAN16_NI 0x0 955 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1 956 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf 957 958 #define ID_AA64MMFR0_EL1_PARANGE_32 0x0 959 #define ID_AA64MMFR0_EL1_PARANGE_36 0x1 960 #define ID_AA64MMFR0_EL1_PARANGE_40 0x2 961 #define ID_AA64MMFR0_EL1_PARANGE_42 0x3 962 #define ID_AA64MMFR0_EL1_PARANGE_44 0x4 963 #define ID_AA64MMFR0_EL1_PARANGE_48 0x5 964 #define ID_AA64MMFR0_EL1_PARANGE_52 0x6 965 966 #define ARM64_MIN_PARANGE_BITS 32 967 968 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0 969 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1 970 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2 971 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 972 973 #ifdef CONFIG_ARM64_PA_BITS_52 974 #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52 975 #else 976 #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48 977 #endif 978 979 /* id_aa64mmfr1 */ 980 #define ID_AA64MMFR1_EL1_ECBHB_SHIFT 60 981 #define ID_AA64MMFR1_EL1_HCX_SHIFT 40 982 #define ID_AA64MMFR1_EL1_AFP_SHIFT 44 983 #define ID_AA64MMFR1_EL1_ETS_SHIFT 36 984 #define ID_AA64MMFR1_EL1_TWED_SHIFT 32 985 #define ID_AA64MMFR1_EL1_XNX_SHIFT 28 986 #define ID_AA64MMFR1_EL1_SpecSEI_SHIFT 24 987 #define ID_AA64MMFR1_EL1_PAN_SHIFT 20 988 #define ID_AA64MMFR1_EL1_LO_SHIFT 16 989 #define ID_AA64MMFR1_EL1_HPDS_SHIFT 12 990 #define ID_AA64MMFR1_EL1_VH_SHIFT 8 991 #define ID_AA64MMFR1_EL1_VMIDBits_SHIFT 4 992 #define ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0 993 994 #define ID_AA64MMFR1_EL1_VMIDBits_8 0 995 #define ID_AA64MMFR1_EL1_VMIDBits_16 2 996 997 /* id_aa64mmfr2 */ 998 #define ID_AA64MMFR2_EL1_E0PD_SHIFT 60 999 #define ID_AA64MMFR2_EL1_EVT_SHIFT 56 1000 #define ID_AA64MMFR2_EL1_BBM_SHIFT 52 1001 #define ID_AA64MMFR2_EL1_TTL_SHIFT 48 1002 #define ID_AA64MMFR2_EL1_FWB_SHIFT 40 1003 #define ID_AA64MMFR2_EL1_IDS_SHIFT 36 1004 #define ID_AA64MMFR2_EL1_AT_SHIFT 32 1005 #define ID_AA64MMFR2_EL1_ST_SHIFT 28 1006 #define ID_AA64MMFR2_EL1_NV_SHIFT 24 1007 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT 20 1008 #define ID_AA64MMFR2_EL1_VARange_SHIFT 16 1009 #define ID_AA64MMFR2_EL1_IESB_SHIFT 12 1010 #define ID_AA64MMFR2_EL1_LSM_SHIFT 8 1011 #define ID_AA64MMFR2_EL1_UAO_SHIFT 4 1012 #define ID_AA64MMFR2_EL1_CnP_SHIFT 0 1013 1014 /* id_aa64dfr0 */ 1015 #define ID_AA64DFR0_EL1_MTPMU_SHIFT 48 1016 #define ID_AA64DFR0_EL1_TraceBuffer_SHIFT 44 1017 #define ID_AA64DFR0_EL1_TraceFilt_SHIFT 40 1018 #define ID_AA64DFR0_EL1_DoubleLock_SHIFT 36 1019 #define ID_AA64DFR0_EL1_PMSVer_SHIFT 32 1020 #define ID_AA64DFR0_EL1_CTX_CMPs_SHIFT 28 1021 #define ID_AA64DFR0_EL1_WRPs_SHIFT 20 1022 #define ID_AA64DFR0_EL1_BRPs_SHIFT 12 1023 #define ID_AA64DFR0_EL1_PMUVer_SHIFT 8 1024 #define ID_AA64DFR0_EL1_TraceVer_SHIFT 4 1025 #define ID_AA64DFR0_EL1_DebugVer_SHIFT 0 1026 1027 #define ID_AA64DFR0_EL1_PMUVer_IMP 0x1 1028 #define ID_AA64DFR0_EL1_PMUVer_V3P1 0x4 1029 #define ID_AA64DFR0_EL1_PMUVer_V3P4 0x5 1030 #define ID_AA64DFR0_EL1_PMUVer_V3P5 0x6 1031 #define ID_AA64DFR0_EL1_PMUVer_V3P7 0x7 1032 #define ID_AA64DFR0_EL1_PMUVer_IMP_DEF 0xf 1033 1034 #define ID_AA64DFR0_EL1_PMSVer_IMP 0x1 1035 #define ID_AA64DFR0_EL1_PMSVer_V1P1 0x2 1036 1037 #define ID_DFR0_PERFMON_SHIFT 24 1038 1039 #define ID_DFR0_PERFMON_8_0 0x3 1040 #define ID_DFR0_PERFMON_8_1 0x4 1041 #define ID_DFR0_PERFMON_8_4 0x5 1042 #define ID_DFR0_PERFMON_8_5 0x6 1043 1044 #define ID_ISAR4_SWP_FRAC_SHIFT 28 1045 #define ID_ISAR4_PSR_M_SHIFT 24 1046 #define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT 20 1047 #define ID_ISAR4_BARRIER_SHIFT 16 1048 #define ID_ISAR4_SMC_SHIFT 12 1049 #define ID_ISAR4_WRITEBACK_SHIFT 8 1050 #define ID_ISAR4_WITHSHIFTS_SHIFT 4 1051 #define ID_ISAR4_UNPRIV_SHIFT 0 1052 1053 #define ID_DFR1_MTPMU_SHIFT 0 1054 1055 #define ID_ISAR0_DIVIDE_SHIFT 24 1056 #define ID_ISAR0_DEBUG_SHIFT 20 1057 #define ID_ISAR0_COPROC_SHIFT 16 1058 #define ID_ISAR0_CMPBRANCH_SHIFT 12 1059 #define ID_ISAR0_BITFIELD_SHIFT 8 1060 #define ID_ISAR0_BITCOUNT_SHIFT 4 1061 #define ID_ISAR0_SWAP_SHIFT 0 1062 1063 #define ID_ISAR5_RDM_SHIFT 24 1064 #define ID_ISAR5_CRC32_SHIFT 16 1065 #define ID_ISAR5_SHA2_SHIFT 12 1066 #define ID_ISAR5_SHA1_SHIFT 8 1067 #define ID_ISAR5_AES_SHIFT 4 1068 #define ID_ISAR5_SEVL_SHIFT 0 1069 1070 #define ID_ISAR6_I8MM_SHIFT 24 1071 #define ID_ISAR6_BF16_SHIFT 20 1072 #define ID_ISAR6_SPECRES_SHIFT 16 1073 #define ID_ISAR6_SB_SHIFT 12 1074 #define ID_ISAR6_FHM_SHIFT 8 1075 #define ID_ISAR6_DP_SHIFT 4 1076 #define ID_ISAR6_JSCVT_SHIFT 0 1077 1078 #define ID_MMFR0_INNERSHR_SHIFT 28 1079 #define ID_MMFR0_FCSE_SHIFT 24 1080 #define ID_MMFR0_AUXREG_SHIFT 20 1081 #define ID_MMFR0_TCM_SHIFT 16 1082 #define ID_MMFR0_SHARELVL_SHIFT 12 1083 #define ID_MMFR0_OUTERSHR_SHIFT 8 1084 #define ID_MMFR0_PMSA_SHIFT 4 1085 #define ID_MMFR0_VMSA_SHIFT 0 1086 1087 #define ID_MMFR4_EVT_SHIFT 28 1088 #define ID_MMFR4_CCIDX_SHIFT 24 1089 #define ID_MMFR4_LSM_SHIFT 20 1090 #define ID_MMFR4_HPDS_SHIFT 16 1091 #define ID_MMFR4_CNP_SHIFT 12 1092 #define ID_MMFR4_XNX_SHIFT 8 1093 #define ID_MMFR4_AC2_SHIFT 4 1094 #define ID_MMFR4_SPECSEI_SHIFT 0 1095 1096 #define ID_MMFR5_ETS_SHIFT 0 1097 1098 #define ID_PFR0_DIT_SHIFT 24 1099 #define ID_PFR0_CSV2_SHIFT 16 1100 #define ID_PFR0_STATE3_SHIFT 12 1101 #define ID_PFR0_STATE2_SHIFT 8 1102 #define ID_PFR0_STATE1_SHIFT 4 1103 #define ID_PFR0_STATE0_SHIFT 0 1104 1105 #define ID_DFR0_PERFMON_SHIFT 24 1106 #define ID_DFR0_MPROFDBG_SHIFT 20 1107 #define ID_DFR0_MMAPTRC_SHIFT 16 1108 #define ID_DFR0_COPTRC_SHIFT 12 1109 #define ID_DFR0_MMAPDBG_SHIFT 8 1110 #define ID_DFR0_COPSDBG_SHIFT 4 1111 #define ID_DFR0_COPDBG_SHIFT 0 1112 1113 #define ID_PFR2_SSBS_SHIFT 4 1114 #define ID_PFR2_CSV3_SHIFT 0 1115 1116 #define MVFR0_FPROUND_SHIFT 28 1117 #define MVFR0_FPSHVEC_SHIFT 24 1118 #define MVFR0_FPSQRT_SHIFT 20 1119 #define MVFR0_FPDIVIDE_SHIFT 16 1120 #define MVFR0_FPTRAP_SHIFT 12 1121 #define MVFR0_FPDP_SHIFT 8 1122 #define MVFR0_FPSP_SHIFT 4 1123 #define MVFR0_SIMD_SHIFT 0 1124 1125 #define MVFR1_SIMDFMAC_SHIFT 28 1126 #define MVFR1_FPHP_SHIFT 24 1127 #define MVFR1_SIMDHP_SHIFT 20 1128 #define MVFR1_SIMDSP_SHIFT 16 1129 #define MVFR1_SIMDINT_SHIFT 12 1130 #define MVFR1_SIMDLS_SHIFT 8 1131 #define MVFR1_FPDNAN_SHIFT 4 1132 #define MVFR1_FPFTZ_SHIFT 0 1133 1134 #define ID_PFR1_GIC_SHIFT 28 1135 #define ID_PFR1_VIRT_FRAC_SHIFT 24 1136 #define ID_PFR1_SEC_FRAC_SHIFT 20 1137 #define ID_PFR1_GENTIMER_SHIFT 16 1138 #define ID_PFR1_VIRTUALIZATION_SHIFT 12 1139 #define ID_PFR1_MPROGMOD_SHIFT 8 1140 #define ID_PFR1_SECURITY_SHIFT 4 1141 #define ID_PFR1_PROGMOD_SHIFT 0 1142 1143 #if defined(CONFIG_ARM64_4K_PAGES) 1144 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT 1145 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 1146 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 1147 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 1148 #elif defined(CONFIG_ARM64_16K_PAGES) 1149 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT 1150 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 1151 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 1152 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 1153 #elif defined(CONFIG_ARM64_64K_PAGES) 1154 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN64_SHIFT 1155 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 1156 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 1157 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 1158 #endif 1159 1160 #define MVFR2_FPMISC_SHIFT 4 1161 #define MVFR2_SIMDMISC_SHIFT 0 1162 1163 #define CTR_EL0_L1Ip_VPIPT 0 1164 #define CTR_EL0_L1Ip_VIPT 2 1165 #define CTR_EL0_L1Ip_PIPT 3 1166 1167 #define CTR_EL0_L1Ip_SHIFT 14 1168 #define CTR_EL0_L1Ip_MASK 3 1169 #define CTR_EL0_DminLine_SHIFT 16 1170 #define CTR_EL0_IminLine_SHIFT 0 1171 #define CTR_EL0_IminLine_MASK 0xf 1172 #define CTR_EL0_ERG_SHIFT 20 1173 #define CTR_EL0_CWG_SHIFT 24 1174 #define CTR_EL0_CWG_MASK 15 1175 #define CTR_EL0_IDC_SHIFT 28 1176 #define CTR_EL0_DIC_SHIFT 29 1177 1178 #define DCZID_EL0_DZP_SHIFT 4 1179 #define DCZID_EL0_BS_SHIFT 0 1180 1181 #define ZCR_ELx_LEN_SHIFT 0 1182 #define ZCR_ELx_LEN_WIDTH 4 1183 #define ZCR_ELx_LEN_MASK 0xf 1184 1185 #define SMCR_ELx_FA64_SHIFT 31 1186 #define SMCR_ELx_FA64_MASK (1 << SMCR_ELx_FA64_SHIFT) 1187 1188 #define SMCR_ELx_LEN_SHIFT 0 1189 #define SMCR_ELx_LEN_WIDTH 4 1190 #define SMCR_ELx_LEN_MASK 0xf 1191 1192 #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ 1193 #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ 1194 1195 #define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */ 1196 #define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */ 1197 1198 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ 1199 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ 1200 1201 /* GCR_EL1 Definitions */ 1202 #define SYS_GCR_EL1_RRND (BIT(16)) 1203 #define SYS_GCR_EL1_EXCL_MASK 0xffffUL 1204 1205 #ifdef CONFIG_KASAN_HW_TAGS 1206 /* 1207 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it 1208 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF. 1209 */ 1210 #define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf) 1211 #define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf) 1212 #define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN) 1213 #define KERNEL_GCR_EL1_EXCL (SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL) 1214 #else 1215 #define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK 1216 #endif 1217 1218 #define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL) 1219 1220 /* RGSR_EL1 Definitions */ 1221 #define SYS_RGSR_EL1_TAG_MASK 0xfUL 1222 #define SYS_RGSR_EL1_SEED_SHIFT 8 1223 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL 1224 1225 /* GMID_EL1 field definitions */ 1226 #define GMID_EL1_BS_SHIFT 0 1227 #define GMID_EL1_BS_SIZE 4 1228 1229 /* TFSR{,E0}_EL1 bit definitions */ 1230 #define SYS_TFSR_EL1_TF0_SHIFT 0 1231 #define SYS_TFSR_EL1_TF1_SHIFT 1 1232 #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) 1233 #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) 1234 1235 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 1236 #define SYS_MPIDR_SAFE_VAL (BIT(31)) 1237 1238 #define TRFCR_ELx_TS_SHIFT 5 1239 #define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) 1240 #define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) 1241 #define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) 1242 #define TRFCR_EL2_CX BIT(3) 1243 #define TRFCR_ELx_ExTRE BIT(1) 1244 #define TRFCR_ELx_E0TRE BIT(0) 1245 1246 /* HCRX_EL2 definitions */ 1247 #define HCRX_EL2_SMPME_MASK (1 << 5) 1248 1249 /* GIC Hypervisor interface registers */ 1250 /* ICH_MISR_EL2 bit definitions */ 1251 #define ICH_MISR_EOI (1 << 0) 1252 #define ICH_MISR_U (1 << 1) 1253 1254 /* ICH_LR*_EL2 bit definitions */ 1255 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) 1256 1257 #define ICH_LR_EOI (1ULL << 41) 1258 #define ICH_LR_GROUP (1ULL << 60) 1259 #define ICH_LR_HW (1ULL << 61) 1260 #define ICH_LR_STATE (3ULL << 62) 1261 #define ICH_LR_PENDING_BIT (1ULL << 62) 1262 #define ICH_LR_ACTIVE_BIT (1ULL << 63) 1263 #define ICH_LR_PHYS_ID_SHIFT 32 1264 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) 1265 #define ICH_LR_PRIORITY_SHIFT 48 1266 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) 1267 1268 /* ICH_HCR_EL2 bit definitions */ 1269 #define ICH_HCR_EN (1 << 0) 1270 #define ICH_HCR_UIE (1 << 1) 1271 #define ICH_HCR_NPIE (1 << 3) 1272 #define ICH_HCR_TC (1 << 10) 1273 #define ICH_HCR_TALL0 (1 << 11) 1274 #define ICH_HCR_TALL1 (1 << 12) 1275 #define ICH_HCR_TDIR (1 << 14) 1276 #define ICH_HCR_EOIcount_SHIFT 27 1277 #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT) 1278 1279 /* ICH_VMCR_EL2 bit definitions */ 1280 #define ICH_VMCR_ACK_CTL_SHIFT 2 1281 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) 1282 #define ICH_VMCR_FIQ_EN_SHIFT 3 1283 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) 1284 #define ICH_VMCR_CBPR_SHIFT 4 1285 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) 1286 #define ICH_VMCR_EOIM_SHIFT 9 1287 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT) 1288 #define ICH_VMCR_BPR1_SHIFT 18 1289 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) 1290 #define ICH_VMCR_BPR0_SHIFT 21 1291 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) 1292 #define ICH_VMCR_PMR_SHIFT 24 1293 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) 1294 #define ICH_VMCR_ENG0_SHIFT 0 1295 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) 1296 #define ICH_VMCR_ENG1_SHIFT 1 1297 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT) 1298 1299 /* ICH_VTR_EL2 bit definitions */ 1300 #define ICH_VTR_PRI_BITS_SHIFT 29 1301 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT) 1302 #define ICH_VTR_ID_BITS_SHIFT 23 1303 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT) 1304 #define ICH_VTR_SEIS_SHIFT 22 1305 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT) 1306 #define ICH_VTR_A3V_SHIFT 21 1307 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT) 1308 #define ICH_VTR_TDS_SHIFT 19 1309 #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT) 1310 1311 /* HFG[WR]TR_EL2 bit definitions */ 1312 #define HFGxTR_EL2_nTPIDR2_EL0_SHIFT 55 1313 #define HFGxTR_EL2_nTPIDR2_EL0_MASK BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT) 1314 #define HFGxTR_EL2_nSMPRI_EL1_SHIFT 54 1315 #define HFGxTR_EL2_nSMPRI_EL1_MASK BIT_MASK(HFGxTR_EL2_nSMPRI_EL1_SHIFT) 1316 1317 #define ARM64_FEATURE_FIELD_BITS 4 1318 1319 /* Create a mask for the feature bits of the specified feature. */ 1320 #define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT)) 1321 1322 #ifdef __ASSEMBLY__ 1323 1324 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 1325 .equ .L__reg_num_x\num, \num 1326 .endr 1327 .equ .L__reg_num_xzr, 31 1328 1329 .macro mrs_s, rt, sreg 1330 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 1331 .endm 1332 1333 .macro msr_s, sreg, rt 1334 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 1335 .endm 1336 1337 #else 1338 1339 #include <linux/bitfield.h> 1340 #include <linux/build_bug.h> 1341 #include <linux/types.h> 1342 #include <asm/alternative.h> 1343 1344 #define __DEFINE_MRS_MSR_S_REGNUM \ 1345 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \ 1346 " .equ .L__reg_num_x\\num, \\num\n" \ 1347 " .endr\n" \ 1348 " .equ .L__reg_num_xzr, 31\n" 1349 1350 #define DEFINE_MRS_S \ 1351 __DEFINE_MRS_MSR_S_REGNUM \ 1352 " .macro mrs_s, rt, sreg\n" \ 1353 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \ 1354 " .endm\n" 1355 1356 #define DEFINE_MSR_S \ 1357 __DEFINE_MRS_MSR_S_REGNUM \ 1358 " .macro msr_s, sreg, rt\n" \ 1359 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \ 1360 " .endm\n" 1361 1362 #define UNDEFINE_MRS_S \ 1363 " .purgem mrs_s\n" 1364 1365 #define UNDEFINE_MSR_S \ 1366 " .purgem msr_s\n" 1367 1368 #define __mrs_s(v, r) \ 1369 DEFINE_MRS_S \ 1370 " mrs_s " v ", " __stringify(r) "\n" \ 1371 UNDEFINE_MRS_S 1372 1373 #define __msr_s(r, v) \ 1374 DEFINE_MSR_S \ 1375 " msr_s " __stringify(r) ", " v "\n" \ 1376 UNDEFINE_MSR_S 1377 1378 /* 1379 * Unlike read_cpuid, calls to read_sysreg are never expected to be 1380 * optimized away or replaced with synthetic values. 1381 */ 1382 #define read_sysreg(r) ({ \ 1383 u64 __val; \ 1384 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 1385 __val; \ 1386 }) 1387 1388 /* 1389 * The "Z" constraint normally means a zero immediate, but when combined with 1390 * the "%x0" template means XZR. 1391 */ 1392 #define write_sysreg(v, r) do { \ 1393 u64 __val = (u64)(v); \ 1394 asm volatile("msr " __stringify(r) ", %x0" \ 1395 : : "rZ" (__val)); \ 1396 } while (0) 1397 1398 /* 1399 * For registers without architectural names, or simply unsupported by 1400 * GAS. 1401 */ 1402 #define read_sysreg_s(r) ({ \ 1403 u64 __val; \ 1404 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ 1405 __val; \ 1406 }) 1407 1408 #define write_sysreg_s(v, r) do { \ 1409 u64 __val = (u64)(v); \ 1410 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ 1411 } while (0) 1412 1413 /* 1414 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 1415 * set mask are set. Other bits are left as-is. 1416 */ 1417 #define sysreg_clear_set(sysreg, clear, set) do { \ 1418 u64 __scs_val = read_sysreg(sysreg); \ 1419 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1420 if (__scs_new != __scs_val) \ 1421 write_sysreg(__scs_new, sysreg); \ 1422 } while (0) 1423 1424 #define sysreg_clear_set_s(sysreg, clear, set) do { \ 1425 u64 __scs_val = read_sysreg_s(sysreg); \ 1426 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1427 if (__scs_new != __scs_val) \ 1428 write_sysreg_s(__scs_new, sysreg); \ 1429 } while (0) 1430 1431 #define read_sysreg_par() ({ \ 1432 u64 par; \ 1433 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1434 par = read_sysreg(par_el1); \ 1435 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1436 par; \ 1437 }) 1438 1439 /* 1440 * Disallow any use of the following backported SYS_FIELD macros. They rely on 1441 * use of pre-shifted masked (for example, as generated by GENMASK). Most of 1442 * the masks defined in this tree are not shifted, making these macros subtly 1443 * dangerous! 1444 */ 1445 #define SYS_FIELD_GET(reg, field, val) \ 1446 BUILD_BUG() 1447 1448 #define SYS_FIELD_PREP(reg, field, val) \ 1449 BUILD_BUG() 1450 1451 #define SYS_FIELD_PREP_ENUM(reg, field, val) \ 1452 BUILD_BUG() 1453 1454 #endif 1455 1456 #endif /* __ASM_SYSREG_H */ 1457