1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2020 Amarula Solutions(India)
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7 #include <drm/drm_of.h>
8 #include <drm/drm_print.h>
9 #include <drm/drm_mipi_dsi.h>
10
11 #include <linux/delay.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/regulator/consumer.h>
16
17 #define VENDOR_ID 0x00
18 #define DEVICE_ID_H 0x01
19 #define DEVICE_ID_L 0x02
20 #define VERSION_ID 0x03
21 #define FIRMWARE_VERSION 0x08
22 #define CONFIG_FINISH 0x09
23 #define PD_CTRL(n) (0x0a + ((n) & 0x3)) /* 0..3 */
24 #define RST_CTRL(n) (0x0e + ((n) & 0x1)) /* 0..1 */
25 #define SYS_CTRL(n) (0x10 + ((n) & 0x7)) /* 0..4 */
26 #define RGB_DRV(n) (0x18 + ((n) & 0x3)) /* 0..3 */
27 #define RGB_DLY(n) (0x1c + ((n) & 0x1)) /* 0..1 */
28 #define RGB_TEST_CTRL 0x1e
29 #define ATE_PLL_EN 0x1f
30 #define HACTIVE_LI 0x20
31 #define VACTIVE_LI 0x21
32 #define VACTIVE_HACTIVE_HI 0x22
33 #define HFP_LI 0x23
34 #define HSYNC_LI 0x24
35 #define HBP_LI 0x25
36 #define HFP_HSW_HBP_HI 0x26
37 #define HFP_HSW_HBP_HI_HFP(n) (((n) & 0x300) >> 4)
38 #define HFP_HSW_HBP_HI_HS(n) (((n) & 0x300) >> 6)
39 #define HFP_HSW_HBP_HI_HBP(n) (((n) & 0x300) >> 8)
40 #define VFP 0x27
41 #define VSYNC 0x28
42 #define VBP 0x29
43 #define BIST_POL 0x2a
44 #define BIST_POL_BIST_MODE(n) (((n) & 0xf) << 4)
45 #define BIST_POL_BIST_GEN BIT(3)
46 #define BIST_POL_HSYNC_POL BIT(2)
47 #define BIST_POL_VSYNC_POL BIT(1)
48 #define BIST_POL_DE_POL BIT(0)
49 #define BIST_RED 0x2b
50 #define BIST_GREEN 0x2c
51 #define BIST_BLUE 0x2d
52 #define BIST_CHESS_X 0x2e
53 #define BIST_CHESS_Y 0x2f
54 #define BIST_CHESS_XY_H 0x30
55 #define BIST_FRAME_TIME_L 0x31
56 #define BIST_FRAME_TIME_H 0x32
57 #define FIFO_MAX_ADDR_LOW 0x33
58 #define SYNC_EVENT_DLY 0x34
59 #define HSW_MIN 0x35
60 #define HFP_MIN 0x36
61 #define LOGIC_RST_NUM 0x37
62 #define OSC_CTRL(n) (0x48 + ((n) & 0x7)) /* 0..5 */
63 #define BG_CTRL 0x4e
64 #define LDO_PLL 0x4f
65 #define PLL_CTRL(n) (0x50 + ((n) & 0xf)) /* 0..15 */
66 #define PLL_CTRL_6_EXTERNAL 0x90
67 #define PLL_CTRL_6_MIPI_CLK 0x92
68 #define PLL_CTRL_6_INTERNAL 0x93
69 #define PLL_REM(n) (0x60 + ((n) & 0x3)) /* 0..2 */
70 #define PLL_DIV(n) (0x63 + ((n) & 0x3)) /* 0..2 */
71 #define PLL_FRAC(n) (0x66 + ((n) & 0x3)) /* 0..2 */
72 #define PLL_INT(n) (0x69 + ((n) & 0x1)) /* 0..1 */
73 #define PLL_REF_DIV 0x6b
74 #define PLL_REF_DIV_P(n) ((n) & 0xf)
75 #define PLL_REF_DIV_Pe BIT(4)
76 #define PLL_REF_DIV_S(n) (((n) & 0x7) << 5)
77 #define PLL_SSC_P(n) (0x6c + ((n) & 0x3)) /* 0..2 */
78 #define PLL_SSC_STEP(n) (0x6f + ((n) & 0x3)) /* 0..2 */
79 #define PLL_SSC_OFFSET(n) (0x72 + ((n) & 0x3)) /* 0..3 */
80 #define GPIO_OEN 0x79
81 #define MIPI_CFG_PW 0x7a
82 #define MIPI_CFG_PW_CONFIG_DSI 0xc1
83 #define MIPI_CFG_PW_CONFIG_I2C 0x3e
84 #define GPIO_SEL(n) (0x7b + ((n) & 0x1)) /* 0..1 */
85 #define IRQ_SEL 0x7d
86 #define DBG_SEL 0x7e
87 #define DBG_SIGNAL 0x7f
88 #define MIPI_ERR_VECTOR_L 0x80
89 #define MIPI_ERR_VECTOR_H 0x81
90 #define MIPI_ERR_VECTOR_EN_L 0x82
91 #define MIPI_ERR_VECTOR_EN_H 0x83
92 #define MIPI_MAX_SIZE_L 0x84
93 #define MIPI_MAX_SIZE_H 0x85
94 #define DSI_CTRL 0x86
95 #define DSI_CTRL_UNKNOWN 0x28
96 #define DSI_CTRL_DSI_LANES(n) ((n) & 0x3)
97 #define MIPI_PN_SWAP 0x87
98 #define MIPI_PN_SWAP_CLK BIT(4)
99 #define MIPI_PN_SWAP_D(n) BIT((n) & 0x3)
100 #define MIPI_SOT_SYNC_BIT_(n) (0x88 + ((n) & 0x1)) /* 0..1 */
101 #define MIPI_ULPS_CTRL 0x8a
102 #define MIPI_CLK_CHK_VAR 0x8e
103 #define MIPI_CLK_CHK_INI 0x8f
104 #define MIPI_T_TERM_EN 0x90
105 #define MIPI_T_HS_SETTLE 0x91
106 #define MIPI_T_TA_SURE_PRE 0x92
107 #define MIPI_T_LPX_SET 0x94
108 #define MIPI_T_CLK_MISS 0x95
109 #define MIPI_INIT_TIME_L 0x96
110 #define MIPI_INIT_TIME_H 0x97
111 #define MIPI_T_CLK_TERM_EN 0x99
112 #define MIPI_T_CLK_SETTLE 0x9a
113 #define MIPI_TO_HS_RX_L 0x9e
114 #define MIPI_TO_HS_RX_H 0x9f
115 #define MIPI_PHY_(n) (0xa0 + ((n) & 0x7)) /* 0..5 */
116 #define MIPI_PD_RX 0xb0
117 #define MIPI_PD_TERM 0xb1
118 #define MIPI_PD_HSRX 0xb2
119 #define MIPI_PD_LPTX 0xb3
120 #define MIPI_PD_LPRX 0xb4
121 #define MIPI_PD_CK_LANE 0xb5
122 #define MIPI_FORCE_0 0xb6
123 #define MIPI_RST_CTRL 0xb7
124 #define MIPI_RST_NUM 0xb8
125 #define MIPI_DBG_SET_(n) (0xc0 + ((n) & 0xf)) /* 0..9 */
126 #define MIPI_DBG_SEL 0xe0
127 #define MIPI_DBG_DATA 0xe1
128 #define MIPI_ATE_TEST_SEL 0xe2
129 #define MIPI_ATE_STATUS_(n) (0xe3 + ((n) & 0x1)) /* 0..1 */
130 #define MIPI_ATE_STATUS_1 0xe4
131 #define ICN6211_MAX_REGISTER MIPI_ATE_STATUS(1)
132
133 struct chipone {
134 struct device *dev;
135 struct drm_bridge bridge;
136 struct drm_bridge *panel_bridge;
137 struct gpio_desc *enable_gpio;
138 struct regulator *vdd1;
139 struct regulator *vdd2;
140 struct regulator *vdd3;
141 };
142
bridge_to_chipone(struct drm_bridge * bridge)143 static inline struct chipone *bridge_to_chipone(struct drm_bridge *bridge)
144 {
145 return container_of(bridge, struct chipone, bridge);
146 }
147
bridge_to_mode(struct drm_bridge * bridge)148 static struct drm_display_mode *bridge_to_mode(struct drm_bridge *bridge)
149 {
150 return &bridge->encoder->crtc->state->adjusted_mode;
151 }
152
chipone_dsi_write(struct chipone * icn,const void * seq,size_t len)153 static inline int chipone_dsi_write(struct chipone *icn, const void *seq,
154 size_t len)
155 {
156 struct mipi_dsi_device *dsi = to_mipi_dsi_device(icn->dev);
157
158 return mipi_dsi_generic_write(dsi, seq, len);
159 }
160
161 #define ICN6211_DSI(icn, seq...) \
162 { \
163 const u8 d[] = { seq }; \
164 chipone_dsi_write(icn, d, ARRAY_SIZE(d)); \
165 }
166
chipone_enable(struct drm_bridge * bridge)167 static void chipone_enable(struct drm_bridge *bridge)
168 {
169 struct chipone *icn = bridge_to_chipone(bridge);
170 struct drm_display_mode *mode = bridge_to_mode(bridge);
171 u16 hfp, hbp, hsync;
172
173 ICN6211_DSI(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI);
174
175 ICN6211_DSI(icn, HACTIVE_LI, mode->hdisplay & 0xff);
176
177 ICN6211_DSI(icn, VACTIVE_LI, mode->vdisplay & 0xff);
178
179 /*
180 * lsb nibble: 2nd nibble of hdisplay
181 * msb nibble: 2nd nibble of vdisplay
182 */
183 ICN6211_DSI(icn, VACTIVE_HACTIVE_HI,
184 ((mode->hdisplay >> 8) & 0xf) |
185 (((mode->vdisplay >> 8) & 0xf) << 4));
186
187 hfp = mode->hsync_start - mode->hdisplay;
188 hsync = mode->hsync_end - mode->hsync_start;
189 hbp = mode->htotal - mode->hsync_end;
190
191 ICN6211_DSI(icn, HFP_LI, hfp & 0xff);
192 ICN6211_DSI(icn, HSYNC_LI, hsync & 0xff);
193 ICN6211_DSI(icn, HBP_LI, hbp & 0xff);
194 /* Top two bits of Horizontal Front porch/Sync/Back porch */
195 ICN6211_DSI(icn, HFP_HSW_HBP_HI,
196 HFP_HSW_HBP_HI_HFP(hfp) |
197 HFP_HSW_HBP_HI_HS(hsync) |
198 HFP_HSW_HBP_HI_HBP(hbp));
199
200 ICN6211_DSI(icn, VFP, mode->vsync_start - mode->vdisplay);
201
202 ICN6211_DSI(icn, VSYNC, mode->vsync_end - mode->vsync_start);
203
204 ICN6211_DSI(icn, VBP, mode->vtotal - mode->vsync_end);
205
206 /* dsi specific sequence */
207 ICN6211_DSI(icn, SYNC_EVENT_DLY, 0x80);
208 ICN6211_DSI(icn, HFP_MIN, hfp & 0xff);
209 ICN6211_DSI(icn, MIPI_PD_CK_LANE, 0xa0);
210 ICN6211_DSI(icn, PLL_CTRL(12), 0xff);
211 ICN6211_DSI(icn, BIST_POL, BIST_POL_DE_POL);
212 ICN6211_DSI(icn, PLL_CTRL(6), PLL_CTRL_6_MIPI_CLK);
213 ICN6211_DSI(icn, PLL_REF_DIV, 0x71);
214 ICN6211_DSI(icn, PLL_INT(0), 0x2b);
215 ICN6211_DSI(icn, SYS_CTRL(0), 0x40);
216 ICN6211_DSI(icn, SYS_CTRL(1), 0x98);
217
218 /* icn6211 specific sequence */
219 ICN6211_DSI(icn, MIPI_FORCE_0, 0x20);
220 ICN6211_DSI(icn, PLL_CTRL(1), 0x20);
221 ICN6211_DSI(icn, CONFIG_FINISH, 0x10);
222
223 usleep_range(10000, 11000);
224 }
225
chipone_pre_enable(struct drm_bridge * bridge)226 static void chipone_pre_enable(struct drm_bridge *bridge)
227 {
228 struct chipone *icn = bridge_to_chipone(bridge);
229 int ret;
230
231 if (icn->vdd1) {
232 ret = regulator_enable(icn->vdd1);
233 if (ret)
234 DRM_DEV_ERROR(icn->dev,
235 "failed to enable VDD1 regulator: %d\n", ret);
236 }
237
238 if (icn->vdd2) {
239 ret = regulator_enable(icn->vdd2);
240 if (ret)
241 DRM_DEV_ERROR(icn->dev,
242 "failed to enable VDD2 regulator: %d\n", ret);
243 }
244
245 if (icn->vdd3) {
246 ret = regulator_enable(icn->vdd3);
247 if (ret)
248 DRM_DEV_ERROR(icn->dev,
249 "failed to enable VDD3 regulator: %d\n", ret);
250 }
251
252 gpiod_set_value(icn->enable_gpio, 1);
253
254 usleep_range(10000, 11000);
255 }
256
chipone_post_disable(struct drm_bridge * bridge)257 static void chipone_post_disable(struct drm_bridge *bridge)
258 {
259 struct chipone *icn = bridge_to_chipone(bridge);
260
261 if (icn->vdd1)
262 regulator_disable(icn->vdd1);
263
264 if (icn->vdd2)
265 regulator_disable(icn->vdd2);
266
267 if (icn->vdd3)
268 regulator_disable(icn->vdd3);
269
270 gpiod_set_value(icn->enable_gpio, 0);
271 }
272
chipone_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)273 static int chipone_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags)
274 {
275 struct chipone *icn = bridge_to_chipone(bridge);
276
277 return drm_bridge_attach(bridge->encoder, icn->panel_bridge, bridge, flags);
278 }
279
280 static const struct drm_bridge_funcs chipone_bridge_funcs = {
281 .attach = chipone_attach,
282 .post_disable = chipone_post_disable,
283 .pre_enable = chipone_pre_enable,
284 .enable = chipone_enable,
285 };
286
chipone_parse_dt(struct chipone * icn)287 static int chipone_parse_dt(struct chipone *icn)
288 {
289 struct device *dev = icn->dev;
290 struct drm_panel *panel;
291 int ret;
292
293 icn->vdd1 = devm_regulator_get_optional(dev, "vdd1");
294 if (IS_ERR(icn->vdd1)) {
295 ret = PTR_ERR(icn->vdd1);
296 if (ret == -EPROBE_DEFER)
297 return -EPROBE_DEFER;
298 icn->vdd1 = NULL;
299 DRM_DEV_DEBUG(dev, "failed to get VDD1 regulator: %d\n", ret);
300 }
301
302 icn->vdd2 = devm_regulator_get_optional(dev, "vdd2");
303 if (IS_ERR(icn->vdd2)) {
304 ret = PTR_ERR(icn->vdd2);
305 if (ret == -EPROBE_DEFER)
306 return -EPROBE_DEFER;
307 icn->vdd2 = NULL;
308 DRM_DEV_DEBUG(dev, "failed to get VDD2 regulator: %d\n", ret);
309 }
310
311 icn->vdd3 = devm_regulator_get_optional(dev, "vdd3");
312 if (IS_ERR(icn->vdd3)) {
313 ret = PTR_ERR(icn->vdd3);
314 if (ret == -EPROBE_DEFER)
315 return -EPROBE_DEFER;
316 icn->vdd3 = NULL;
317 DRM_DEV_DEBUG(dev, "failed to get VDD3 regulator: %d\n", ret);
318 }
319
320 icn->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
321 if (IS_ERR(icn->enable_gpio)) {
322 DRM_DEV_ERROR(dev, "failed to get enable GPIO\n");
323 return PTR_ERR(icn->enable_gpio);
324 }
325
326 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
327 if (ret)
328 return ret;
329
330 icn->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
331 if (IS_ERR(icn->panel_bridge))
332 return PTR_ERR(icn->panel_bridge);
333
334 return 0;
335 }
336
chipone_probe(struct mipi_dsi_device * dsi)337 static int chipone_probe(struct mipi_dsi_device *dsi)
338 {
339 struct device *dev = &dsi->dev;
340 struct chipone *icn;
341 int ret;
342
343 icn = devm_kzalloc(dev, sizeof(struct chipone), GFP_KERNEL);
344 if (!icn)
345 return -ENOMEM;
346
347 mipi_dsi_set_drvdata(dsi, icn);
348 icn->dev = dev;
349
350 ret = chipone_parse_dt(icn);
351 if (ret)
352 return ret;
353
354 icn->bridge.funcs = &chipone_bridge_funcs;
355 icn->bridge.type = DRM_MODE_CONNECTOR_DPI;
356 icn->bridge.of_node = dev->of_node;
357
358 drm_bridge_add(&icn->bridge);
359
360 dsi->lanes = 4;
361 dsi->format = MIPI_DSI_FMT_RGB888;
362 dsi->mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
363
364 ret = mipi_dsi_attach(dsi);
365 if (ret < 0) {
366 drm_bridge_remove(&icn->bridge);
367 dev_err(dev, "failed to attach dsi\n");
368 }
369
370 return ret;
371 }
372
chipone_remove(struct mipi_dsi_device * dsi)373 static int chipone_remove(struct mipi_dsi_device *dsi)
374 {
375 struct chipone *icn = mipi_dsi_get_drvdata(dsi);
376
377 mipi_dsi_detach(dsi);
378 drm_bridge_remove(&icn->bridge);
379
380 return 0;
381 }
382
383 static const struct of_device_id chipone_of_match[] = {
384 { .compatible = "chipone,icn6211", },
385 { /* sentinel */ }
386 };
387 MODULE_DEVICE_TABLE(of, chipone_of_match);
388
389 static struct mipi_dsi_driver chipone_driver = {
390 .probe = chipone_probe,
391 .remove = chipone_remove,
392 .driver = {
393 .name = "chipone-icn6211",
394 .owner = THIS_MODULE,
395 .of_match_table = chipone_of_match,
396 },
397 };
398 module_mipi_dsi_driver(chipone_driver);
399
400 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
401 MODULE_DESCRIPTION("Chipone ICN6211 MIPI-DSI to RGB Converter Bridge");
402 MODULE_LICENSE("GPL");
403