1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
6 #include <linux/slab.h>
7 #include <linux/of_address.h>
8 #include <linux/platform_device.h>
9 #include "dpu_hw_mdss.h"
10 #include "dpu_hw_interrupts.h"
11 #include "dpu_hw_catalog.h"
12 #include "dpu_kms.h"
13
14 #define VIG_MASK \
15 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
16 BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
17 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
18
19 #define VIG_SDM845_MASK \
20 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3))
21
22 #define VIG_SC7180_MASK \
23 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
24
25 #define VIG_SM8250_MASK \
26 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
27
28 #define DMA_SDM845_MASK \
29 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
30 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
31 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
32
33 #define DMA_CURSOR_SDM845_MASK \
34 (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
35
36 #define MIXER_SDM845_MASK \
37 (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
38
39 #define MIXER_SC7180_MASK \
40 (BIT(DPU_DIM_LAYER))
41
42 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
43
44 #define PINGPONG_SDM845_SPLIT_MASK \
45 (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
46
47 #define CTL_SC7280_MASK \
48 (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE))
49
50 #define MERGE_3D_SM8150_MASK (0)
51
52 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
53
54 #define INTF_SDM845_MASK (0)
55
56 #define INTF_SC7180_MASK \
57 (BIT(DPU_INTF_INPUT_CTRL) | \
58 BIT(DPU_INTF_TE) | \
59 BIT(DPU_INTF_STATUS_SUPPORTED) | \
60 BIT(DPU_DATA_HCTL_EN))
61
62 #define INTF_SC7280_MASK (INTF_SC7180_MASK)
63
64 #define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
65 BIT(MDP_SSPP_TOP0_INTR2) | \
66 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
67 BIT(MDP_INTF0_INTR) | \
68 BIT(MDP_INTF1_INTR) | \
69 BIT(MDP_INTF2_INTR) | \
70 BIT(MDP_INTF3_INTR) | \
71 BIT(MDP_INTF4_INTR) | \
72 BIT(MDP_AD4_0_INTR) | \
73 BIT(MDP_AD4_1_INTR))
74
75 #define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
76 BIT(MDP_SSPP_TOP0_INTR2) | \
77 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
78 BIT(MDP_INTF0_INTR) | \
79 BIT(MDP_INTF1_INTR))
80
81 #define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
82 BIT(MDP_SSPP_TOP0_INTR2) | \
83 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
84 BIT(MDP_INTF0_7xxx_INTR) | \
85 BIT(MDP_INTF1_7xxx_INTR) | \
86 BIT(MDP_INTF5_7xxx_INTR))
87
88 #define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
89 BIT(MDP_SSPP_TOP0_INTR2) | \
90 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
91 BIT(MDP_INTF0_INTR) | \
92 BIT(MDP_INTF1_INTR) | \
93 BIT(MDP_INTF2_INTR) | \
94 BIT(MDP_INTF3_INTR) | \
95 BIT(MDP_INTF4_INTR))
96
97
98 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
99 #define DEFAULT_DPU_LINE_WIDTH 2048
100 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
101
102 #define MAX_HORZ_DECIMATION 4
103 #define MAX_VERT_DECIMATION 4
104
105 #define MAX_UPSCALE_RATIO 20
106 #define MAX_DOWNSCALE_RATIO 4
107 #define SSPP_UNITY_SCALE 1
108
109 #define STRCAT(X, Y) (X Y)
110
111 static const uint32_t plane_formats[] = {
112 DRM_FORMAT_ARGB8888,
113 DRM_FORMAT_ABGR8888,
114 DRM_FORMAT_RGBA8888,
115 DRM_FORMAT_BGRA8888,
116 DRM_FORMAT_XRGB8888,
117 DRM_FORMAT_RGBX8888,
118 DRM_FORMAT_BGRX8888,
119 DRM_FORMAT_XBGR8888,
120 DRM_FORMAT_RGB888,
121 DRM_FORMAT_BGR888,
122 DRM_FORMAT_RGB565,
123 DRM_FORMAT_BGR565,
124 DRM_FORMAT_ARGB1555,
125 DRM_FORMAT_ABGR1555,
126 DRM_FORMAT_RGBA5551,
127 DRM_FORMAT_BGRA5551,
128 DRM_FORMAT_XRGB1555,
129 DRM_FORMAT_XBGR1555,
130 DRM_FORMAT_RGBX5551,
131 DRM_FORMAT_BGRX5551,
132 DRM_FORMAT_ARGB4444,
133 DRM_FORMAT_ABGR4444,
134 DRM_FORMAT_RGBA4444,
135 DRM_FORMAT_BGRA4444,
136 DRM_FORMAT_XRGB4444,
137 DRM_FORMAT_XBGR4444,
138 DRM_FORMAT_RGBX4444,
139 DRM_FORMAT_BGRX4444,
140 };
141
142 static const uint32_t plane_formats_yuv[] = {
143 DRM_FORMAT_ARGB8888,
144 DRM_FORMAT_ABGR8888,
145 DRM_FORMAT_RGBA8888,
146 DRM_FORMAT_BGRX8888,
147 DRM_FORMAT_BGRA8888,
148 DRM_FORMAT_XRGB8888,
149 DRM_FORMAT_XBGR8888,
150 DRM_FORMAT_RGBX8888,
151 DRM_FORMAT_RGB888,
152 DRM_FORMAT_BGR888,
153 DRM_FORMAT_RGB565,
154 DRM_FORMAT_BGR565,
155 DRM_FORMAT_ARGB1555,
156 DRM_FORMAT_ABGR1555,
157 DRM_FORMAT_RGBA5551,
158 DRM_FORMAT_BGRA5551,
159 DRM_FORMAT_XRGB1555,
160 DRM_FORMAT_XBGR1555,
161 DRM_FORMAT_RGBX5551,
162 DRM_FORMAT_BGRX5551,
163 DRM_FORMAT_ARGB4444,
164 DRM_FORMAT_ABGR4444,
165 DRM_FORMAT_RGBA4444,
166 DRM_FORMAT_BGRA4444,
167 DRM_FORMAT_XRGB4444,
168 DRM_FORMAT_XBGR4444,
169 DRM_FORMAT_RGBX4444,
170 DRM_FORMAT_BGRX4444,
171
172 DRM_FORMAT_NV12,
173 DRM_FORMAT_NV21,
174 DRM_FORMAT_NV16,
175 DRM_FORMAT_NV61,
176 DRM_FORMAT_VYUY,
177 DRM_FORMAT_UYVY,
178 DRM_FORMAT_YUYV,
179 DRM_FORMAT_YVYU,
180 DRM_FORMAT_YUV420,
181 DRM_FORMAT_YVU420,
182 };
183
184 /*************************************************************
185 * DPU sub blocks config
186 *************************************************************/
187 /* DPU top level caps */
188 static const struct dpu_caps sdm845_dpu_caps = {
189 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
190 .max_mixer_blendstages = 0xb,
191 .qseed_type = DPU_SSPP_SCALER_QSEED3,
192 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
193 .ubwc_version = DPU_HW_UBWC_VER_20,
194 .has_src_split = true,
195 .has_dim_layer = true,
196 .has_idle_pc = true,
197 .has_3d_merge = true,
198 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
199 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
200 .max_hdeci_exp = MAX_HORZ_DECIMATION,
201 .max_vdeci_exp = MAX_VERT_DECIMATION,
202 };
203
204 static const struct dpu_caps sc7180_dpu_caps = {
205 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
206 .max_mixer_blendstages = 0x9,
207 .qseed_type = DPU_SSPP_SCALER_QSEED4,
208 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
209 .ubwc_version = DPU_HW_UBWC_VER_20,
210 .has_dim_layer = true,
211 .has_idle_pc = true,
212 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
213 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
214 };
215
216 static const struct dpu_caps sm8150_dpu_caps = {
217 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
218 .max_mixer_blendstages = 0xb,
219 .qseed_type = DPU_SSPP_SCALER_QSEED3,
220 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
221 .ubwc_version = DPU_HW_UBWC_VER_30,
222 .has_src_split = true,
223 .has_dim_layer = true,
224 .has_idle_pc = true,
225 .has_3d_merge = true,
226 .max_linewidth = 4096,
227 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
228 .max_hdeci_exp = MAX_HORZ_DECIMATION,
229 .max_vdeci_exp = MAX_VERT_DECIMATION,
230 };
231
232 static const struct dpu_caps sm8250_dpu_caps = {
233 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
234 .max_mixer_blendstages = 0xb,
235 .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
236 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
237 .ubwc_version = DPU_HW_UBWC_VER_40,
238 .has_src_split = true,
239 .has_dim_layer = true,
240 .has_idle_pc = true,
241 .has_3d_merge = true,
242 .max_linewidth = 4096,
243 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
244 };
245
246 static const struct dpu_caps sc7280_dpu_caps = {
247 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
248 .max_mixer_blendstages = 0x7,
249 .qseed_type = DPU_SSPP_SCALER_QSEED4,
250 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
251 .ubwc_version = DPU_HW_UBWC_VER_30,
252 .has_dim_layer = true,
253 .has_idle_pc = true,
254 .max_linewidth = 2400,
255 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
256 };
257
258 static const struct dpu_mdp_cfg sdm845_mdp[] = {
259 {
260 .name = "top_0", .id = MDP_TOP,
261 .base = 0x0, .len = 0x45C,
262 .features = 0,
263 .highest_bank_bit = 0x2,
264 .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
265 .reg_off = 0x2AC, .bit_off = 0},
266 .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
267 .reg_off = 0x2B4, .bit_off = 0},
268 .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
269 .reg_off = 0x2BC, .bit_off = 0},
270 .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
271 .reg_off = 0x2C4, .bit_off = 0},
272 .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
273 .reg_off = 0x2AC, .bit_off = 8},
274 .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
275 .reg_off = 0x2B4, .bit_off = 8},
276 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
277 .reg_off = 0x2BC, .bit_off = 8},
278 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
279 .reg_off = 0x2C4, .bit_off = 8},
280 },
281 };
282
283 static const struct dpu_mdp_cfg sc7180_mdp[] = {
284 {
285 .name = "top_0", .id = MDP_TOP,
286 .base = 0x0, .len = 0x494,
287 .features = 0,
288 .highest_bank_bit = 0x3,
289 .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
290 .reg_off = 0x2AC, .bit_off = 0},
291 .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
292 .reg_off = 0x2AC, .bit_off = 8},
293 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
294 .reg_off = 0x2B4, .bit_off = 8},
295 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
296 .reg_off = 0x2C4, .bit_off = 8},
297 },
298 };
299
300 static const struct dpu_mdp_cfg sm8250_mdp[] = {
301 {
302 .name = "top_0", .id = MDP_TOP,
303 .base = 0x0, .len = 0x494,
304 .features = 0,
305 .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
306 .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
307 .reg_off = 0x2AC, .bit_off = 0},
308 .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
309 .reg_off = 0x2B4, .bit_off = 0},
310 .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
311 .reg_off = 0x2BC, .bit_off = 0},
312 .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
313 .reg_off = 0x2C4, .bit_off = 0},
314 .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
315 .reg_off = 0x2AC, .bit_off = 8},
316 .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
317 .reg_off = 0x2B4, .bit_off = 8},
318 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
319 .reg_off = 0x2BC, .bit_off = 8},
320 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
321 .reg_off = 0x2C4, .bit_off = 8},
322 .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
323 .reg_off = 0x2BC, .bit_off = 20},
324 },
325 };
326
327 static const struct dpu_mdp_cfg sc7280_mdp[] = {
328 {
329 .name = "top_0", .id = MDP_TOP,
330 .base = 0x0, .len = 0x2014,
331 .highest_bank_bit = 0x1,
332 .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
333 .reg_off = 0x2AC, .bit_off = 0},
334 .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
335 .reg_off = 0x2AC, .bit_off = 8},
336 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
337 .reg_off = 0x2B4, .bit_off = 8},
338 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
339 .reg_off = 0x2C4, .bit_off = 8},
340 },
341 };
342
343 /*************************************************************
344 * CTL sub blocks config
345 *************************************************************/
346 static const struct dpu_ctl_cfg sdm845_ctl[] = {
347 {
348 .name = "ctl_0", .id = CTL_0,
349 .base = 0x1000, .len = 0xE4,
350 .features = BIT(DPU_CTL_SPLIT_DISPLAY),
351 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
352 },
353 {
354 .name = "ctl_1", .id = CTL_1,
355 .base = 0x1200, .len = 0xE4,
356 .features = BIT(DPU_CTL_SPLIT_DISPLAY),
357 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
358 },
359 {
360 .name = "ctl_2", .id = CTL_2,
361 .base = 0x1400, .len = 0xE4,
362 .features = 0,
363 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
364 },
365 {
366 .name = "ctl_3", .id = CTL_3,
367 .base = 0x1600, .len = 0xE4,
368 .features = 0,
369 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
370 },
371 {
372 .name = "ctl_4", .id = CTL_4,
373 .base = 0x1800, .len = 0xE4,
374 .features = 0,
375 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
376 },
377 };
378
379 static const struct dpu_ctl_cfg sc7180_ctl[] = {
380 {
381 .name = "ctl_0", .id = CTL_0,
382 .base = 0x1000, .len = 0x1dc,
383 .features = BIT(DPU_CTL_ACTIVE_CFG),
384 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
385 },
386 {
387 .name = "ctl_1", .id = CTL_1,
388 .base = 0x1200, .len = 0x1dc,
389 .features = BIT(DPU_CTL_ACTIVE_CFG),
390 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
391 },
392 {
393 .name = "ctl_2", .id = CTL_2,
394 .base = 0x1400, .len = 0x1dc,
395 .features = BIT(DPU_CTL_ACTIVE_CFG),
396 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
397 },
398 };
399
400 static const struct dpu_ctl_cfg sm8150_ctl[] = {
401 {
402 .name = "ctl_0", .id = CTL_0,
403 .base = 0x1000, .len = 0x1e0,
404 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
405 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
406 },
407 {
408 .name = "ctl_1", .id = CTL_1,
409 .base = 0x1200, .len = 0x1e0,
410 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
411 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
412 },
413 {
414 .name = "ctl_2", .id = CTL_2,
415 .base = 0x1400, .len = 0x1e0,
416 .features = BIT(DPU_CTL_ACTIVE_CFG),
417 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
418 },
419 {
420 .name = "ctl_3", .id = CTL_3,
421 .base = 0x1600, .len = 0x1e0,
422 .features = BIT(DPU_CTL_ACTIVE_CFG),
423 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
424 },
425 {
426 .name = "ctl_4", .id = CTL_4,
427 .base = 0x1800, .len = 0x1e0,
428 .features = BIT(DPU_CTL_ACTIVE_CFG),
429 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
430 },
431 {
432 .name = "ctl_5", .id = CTL_5,
433 .base = 0x1a00, .len = 0x1e0,
434 .features = BIT(DPU_CTL_ACTIVE_CFG),
435 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
436 },
437 };
438
439 static const struct dpu_ctl_cfg sc7280_ctl[] = {
440 {
441 .name = "ctl_0", .id = CTL_0,
442 .base = 0x15000, .len = 0x1E8,
443 .features = CTL_SC7280_MASK,
444 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
445 },
446 {
447 .name = "ctl_1", .id = CTL_1,
448 .base = 0x16000, .len = 0x1E8,
449 .features = CTL_SC7280_MASK,
450 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
451 },
452 {
453 .name = "ctl_2", .id = CTL_2,
454 .base = 0x17000, .len = 0x1E8,
455 .features = CTL_SC7280_MASK,
456 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
457 },
458 {
459 .name = "ctl_3", .id = CTL_3,
460 .base = 0x18000, .len = 0x1E8,
461 .features = CTL_SC7280_MASK,
462 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
463 },
464 };
465
466 /*************************************************************
467 * SSPP sub blocks config
468 *************************************************************/
469
470 /* SSPP common configuration */
471
472 #define _VIG_SBLK(num, sdma_pri, qseed_ver) \
473 { \
474 .maxdwnscale = MAX_DOWNSCALE_RATIO, \
475 .maxupscale = MAX_UPSCALE_RATIO, \
476 .smart_dma_priority = sdma_pri, \
477 .src_blk = {.name = STRCAT("sspp_src_", num), \
478 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
479 .scaler_blk = {.name = STRCAT("sspp_scaler", num), \
480 .id = qseed_ver, \
481 .base = 0xa00, .len = 0xa0,}, \
482 .csc_blk = {.name = STRCAT("sspp_csc", num), \
483 .id = DPU_SSPP_CSC_10BIT, \
484 .base = 0x1a00, .len = 0x100,}, \
485 .format_list = plane_formats_yuv, \
486 .num_formats = ARRAY_SIZE(plane_formats_yuv), \
487 .virt_format_list = plane_formats, \
488 .virt_num_formats = ARRAY_SIZE(plane_formats), \
489 }
490
491 #define _DMA_SBLK(num, sdma_pri) \
492 { \
493 .maxdwnscale = SSPP_UNITY_SCALE, \
494 .maxupscale = SSPP_UNITY_SCALE, \
495 .smart_dma_priority = sdma_pri, \
496 .src_blk = {.name = STRCAT("sspp_src_", num), \
497 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
498 .format_list = plane_formats, \
499 .num_formats = ARRAY_SIZE(plane_formats), \
500 .virt_format_list = plane_formats, \
501 .virt_num_formats = ARRAY_SIZE(plane_formats), \
502 }
503
504 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
505 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
506 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
507 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
508 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
509 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
510 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
511 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
512
513 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
514 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
515 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
516 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
517
518 #define SSPP_BLK(_name, _id, _base, _features, \
519 _sblk, _xinid, _type, _clkctrl) \
520 { \
521 .name = _name, .id = _id, \
522 .base = _base, .len = 0x1c8, \
523 .features = _features, \
524 .sblk = &_sblk, \
525 .xin_id = _xinid, \
526 .type = _type, \
527 .clk_ctrl = _clkctrl \
528 }
529
530 static const struct dpu_sspp_cfg sdm845_sspp[] = {
531 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
532 sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
533 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
534 sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
535 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,
536 sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
537 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK,
538 sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
539 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
540 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
541 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
542 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
543 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
544 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
545 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
546 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
547 };
548
549 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
550 _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
551
552 static const struct dpu_sspp_cfg sc7180_sspp[] = {
553 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
554 sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
555 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
556 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
557 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
558 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
559 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
560 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
561 };
562
563 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
564 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
565 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
566 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);
567 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
568 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE);
569 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
570 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
571
572 static const struct dpu_sspp_cfg sm8250_sspp[] = {
573 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
574 sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
575 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
576 sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
577 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,
578 sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
579 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
580 sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
581 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
582 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
583 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
584 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
585 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
586 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
587 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
588 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
589 };
590
591 static const struct dpu_sspp_cfg sc7280_sspp[] = {
592 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
593 sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
594 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
595 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
596 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
597 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
598 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
599 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
600 };
601
602 /*************************************************************
603 * MIXER sub blocks config
604 *************************************************************/
605
606 /* SDM845 */
607
608 static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
609 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
610 .maxblendstages = 11, /* excluding base layer */
611 .blendstage_base = { /* offsets relative to mixer base */
612 0x20, 0x38, 0x50, 0x68, 0x80, 0x98,
613 0xb0, 0xc8, 0xe0, 0xf8, 0x110
614 },
615 };
616
617 #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \
618 { \
619 .name = _name, .id = _id, \
620 .base = _base, .len = 0x320, \
621 .features = _fmask, \
622 .sblk = _sblk, \
623 .pingpong = _pp, \
624 .lm_pair_mask = (1 << _lmpair), \
625 .dspp = _dspp \
626 }
627
628 static const struct dpu_lm_cfg sdm845_lm[] = {
629 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
630 &sdm845_lm_sblk, PINGPONG_0, LM_1, 0),
631 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
632 &sdm845_lm_sblk, PINGPONG_1, LM_0, 0),
633 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
634 &sdm845_lm_sblk, PINGPONG_2, LM_5, 0),
635 LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
636 &sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
637 LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
638 &sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
639 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
640 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
641 };
642
643 /* SC7180 */
644
645 static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
646 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
647 .maxblendstages = 7, /* excluding base layer */
648 .blendstage_base = { /* offsets relative to mixer base */
649 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0
650 },
651 };
652
653 static const struct dpu_lm_cfg sc7180_lm[] = {
654 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
655 &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
656 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK,
657 &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
658 };
659
660 /* SM8150 */
661
662 static const struct dpu_lm_cfg sm8150_lm[] = {
663 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
664 &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
665 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
666 &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
667 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
668 &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
669 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
670 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
671 LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
672 &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
673 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
674 &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
675 };
676
677 static const struct dpu_lm_cfg sc7280_lm[] = {
678 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
679 &sc7180_lm_sblk, PINGPONG_0, 0, 0),
680 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK,
681 &sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
682 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK,
683 &sc7180_lm_sblk, PINGPONG_3, LM_2, 0),
684 };
685
686 /*************************************************************
687 * DSPP sub blocks config
688 *************************************************************/
689 static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = {
690 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
691 .len = 0x90, .version = 0x10000},
692 };
693
694 static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = {
695 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
696 .len = 0x90, .version = 0x40000},
697 };
698
699 #define DSPP_BLK(_name, _id, _base, _mask, _sblk) \
700 {\
701 .name = _name, .id = _id, \
702 .base = _base, .len = 0x1800, \
703 .features = _mask, \
704 .sblk = _sblk \
705 }
706
707 static const struct dpu_dspp_cfg sc7180_dspp[] = {
708 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
709 &sc7180_dspp_sblk),
710 };
711
712 static const struct dpu_dspp_cfg sm8150_dspp[] = {
713 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
714 &sm8150_dspp_sblk),
715 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
716 &sm8150_dspp_sblk),
717 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
718 &sm8150_dspp_sblk),
719 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
720 &sm8150_dspp_sblk),
721 };
722
723 /*************************************************************
724 * PINGPONG sub blocks config
725 *************************************************************/
726 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = {
727 .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0,
728 .version = 0x1},
729 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
730 .len = 0x20, .version = 0x10000},
731 };
732
733 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = {
734 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
735 .len = 0x20, .version = 0x10000},
736 };
737
738 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
739 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0,
740 .len = 0x20, .version = 0x20000},
741 };
742
743 #define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
744 {\
745 .name = _name, .id = _id, \
746 .base = _base, .len = 0xd4, \
747 .features = PINGPONG_SDM845_SPLIT_MASK, \
748 .merge_3d = _merge_3d, \
749 .sblk = &_sblk, \
750 .intr_done = _done, \
751 .intr_rdptr = _rdptr, \
752 }
753 #define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
754 {\
755 .name = _name, .id = _id, \
756 .base = _base, .len = 0xd4, \
757 .features = PINGPONG_SDM845_MASK, \
758 .merge_3d = _merge_3d, \
759 .sblk = &_sblk, \
760 .intr_done = _done, \
761 .intr_rdptr = _rdptr, \
762 }
763
764 static const struct dpu_pingpong_cfg sdm845_pp[] = {
765 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
766 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
767 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
768 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
769 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
770 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
771 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
772 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
773 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
774 PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
775 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
776 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
777 };
778
779 static struct dpu_pingpong_cfg sc7180_pp[] = {
780 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1),
781 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1),
782 };
783
784 static const struct dpu_pingpong_cfg sm8150_pp[] = {
785 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
786 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
787 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
788 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te,
789 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
790 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
791 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
792 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
793 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
794 PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
795 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
796 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
797 PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
798 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
799 -1),
800 PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
801 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
802 -1),
803 };
804
805 /*************************************************************
806 * MERGE_3D sub blocks config
807 *************************************************************/
808 #define MERGE_3D_BLK(_name, _id, _base) \
809 {\
810 .name = _name, .id = _id, \
811 .base = _base, .len = 0x8, \
812 .features = MERGE_3D_SM8150_MASK, \
813 .sblk = NULL \
814 }
815
816 static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
817 MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
818 MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
819 MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
820 };
821
822 static const struct dpu_pingpong_cfg sc7280_pp[] = {
823 PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
824 PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
825 PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
826 PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
827 };
828 /*************************************************************
829 * INTF sub blocks config
830 *************************************************************/
831 #define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
832 {\
833 .name = _name, .id = _id, \
834 .base = _base, .len = 0x280, \
835 .features = _features, \
836 .type = _type, \
837 .controller_id = _ctrl_id, \
838 .prog_fetch_lines_worst_case = _progfetch, \
839 .intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \
840 .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \
841 }
842
843 static const struct dpu_intf_cfg sdm845_intf[] = {
844 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
845 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
846 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
847 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
848 };
849
850 static const struct dpu_intf_cfg sc7180_intf[] = {
851 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
852 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
853 };
854
855 static const struct dpu_intf_cfg sm8150_intf[] = {
856 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
857 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
858 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
859 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
860 };
861
862 static const struct dpu_intf_cfg sc7280_intf[] = {
863 INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
864 INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
865 INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
866 };
867
868 /*************************************************************
869 * VBIF sub blocks config
870 *************************************************************/
871 /* VBIF QOS remap */
872 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6};
873 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3};
874
875 static const struct dpu_vbif_cfg sdm845_vbif[] = {
876 {
877 .name = "vbif_0", .id = VBIF_0,
878 .base = 0, .len = 0x1040,
879 .features = BIT(DPU_VBIF_QOS_REMAP),
880 .xin_halt_timeout = 0x4000,
881 .qos_rt_tbl = {
882 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
883 .priority_lvl = sdm845_rt_pri_lvl,
884 },
885 .qos_nrt_tbl = {
886 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
887 .priority_lvl = sdm845_nrt_pri_lvl,
888 },
889 .memtype_count = 14,
890 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
891 },
892 };
893
894 static const struct dpu_reg_dma_cfg sdm845_regdma = {
895 .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
896 };
897
898 static const struct dpu_reg_dma_cfg sm8150_regdma = {
899 .base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c
900 };
901
902 static const struct dpu_reg_dma_cfg sm8250_regdma = {
903 .base = 0x0,
904 .version = 0x00010002,
905 .trigger_sel_off = 0x119c,
906 .xin_id = 7,
907 .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
908 };
909
910 /*************************************************************
911 * PERF data config
912 *************************************************************/
913
914 /* SSPP QOS LUTs */
915 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = {
916 {.fl = 4, .lut = 0x357},
917 {.fl = 5, .lut = 0x3357},
918 {.fl = 6, .lut = 0x23357},
919 {.fl = 7, .lut = 0x223357},
920 {.fl = 8, .lut = 0x2223357},
921 {.fl = 9, .lut = 0x22223357},
922 {.fl = 10, .lut = 0x222223357},
923 {.fl = 11, .lut = 0x2222223357},
924 {.fl = 12, .lut = 0x22222223357},
925 {.fl = 13, .lut = 0x222222223357},
926 {.fl = 14, .lut = 0x1222222223357},
927 {.fl = 0, .lut = 0x11222222223357}
928 };
929
930 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
931 {.fl = 0, .lut = 0x0011222222335777},
932 };
933
934 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
935 {.fl = 0, .lut = 0x0011222222223357 },
936 };
937
938 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
939 {.fl = 10, .lut = 0x344556677},
940 {.fl = 11, .lut = 0x3344556677},
941 {.fl = 12, .lut = 0x23344556677},
942 {.fl = 13, .lut = 0x223344556677},
943 {.fl = 14, .lut = 0x1223344556677},
944 {.fl = 0, .lut = 0x112233344556677},
945 };
946
947 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
948 {.fl = 0, .lut = 0x0011223344556677},
949 };
950
951 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = {
952 {.fl = 0, .lut = 0x0},
953 };
954
955 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
956 {.fl = 0, .lut = 0x0},
957 };
958
959 static const struct dpu_perf_cfg sdm845_perf_data = {
960 .max_bw_low = 6800000,
961 .max_bw_high = 6800000,
962 .min_core_ib = 2400000,
963 .min_llcc_ib = 800000,
964 .min_dram_ib = 800000,
965 .core_ib_ff = "6.0",
966 .core_clk_ff = "1.0",
967 .comp_ratio_rt =
968 "NV12/5/1/1.23 AB24/5/1/1.23 XB24/5/1/1.23",
969 .comp_ratio_nrt =
970 "NV12/5/1/1.25 AB24/5/1/1.25 XB24/5/1/1.25",
971 .undersized_prefill_lines = 2,
972 .xtra_prefill_lines = 2,
973 .dest_scale_prefill_lines = 3,
974 .macrotile_prefill_lines = 4,
975 .yuv_nv12_prefill_lines = 8,
976 .linear_prefill_lines = 1,
977 .downscaling_prefill_lines = 1,
978 .amortizable_threshold = 25,
979 .min_prefill_lines = 24,
980 .danger_lut_tbl = {0xf, 0xffff, 0x0},
981 .safe_lut_tbl = {0xfff0, 0xf000, 0xffff},
982 .qos_lut_tbl = {
983 {.nentry = ARRAY_SIZE(sdm845_qos_linear),
984 .entries = sdm845_qos_linear
985 },
986 {.nentry = ARRAY_SIZE(sdm845_qos_macrotile),
987 .entries = sdm845_qos_macrotile
988 },
989 {.nentry = ARRAY_SIZE(sdm845_qos_nrt),
990 .entries = sdm845_qos_nrt
991 },
992 },
993 .cdp_cfg = {
994 {.rd_enable = 1, .wr_enable = 1},
995 {.rd_enable = 1, .wr_enable = 0}
996 },
997 .clk_inefficiency_factor = 105,
998 .bw_inefficiency_factor = 120,
999 };
1000
1001 static const struct dpu_perf_cfg sc7180_perf_data = {
1002 .max_bw_low = 6800000,
1003 .max_bw_high = 6800000,
1004 .min_core_ib = 2400000,
1005 .min_llcc_ib = 800000,
1006 .min_dram_ib = 1600000,
1007 .min_prefill_lines = 24,
1008 .danger_lut_tbl = {0xff, 0xffff, 0x0},
1009 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
1010 .qos_lut_tbl = {
1011 {.nentry = ARRAY_SIZE(sc7180_qos_linear),
1012 .entries = sc7180_qos_linear
1013 },
1014 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1015 .entries = sc7180_qos_macrotile
1016 },
1017 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1018 .entries = sc7180_qos_nrt
1019 },
1020 },
1021 .cdp_cfg = {
1022 {.rd_enable = 1, .wr_enable = 1},
1023 {.rd_enable = 1, .wr_enable = 0}
1024 },
1025 .clk_inefficiency_factor = 105,
1026 .bw_inefficiency_factor = 120,
1027 };
1028
1029 static const struct dpu_perf_cfg sm8150_perf_data = {
1030 .max_bw_low = 12800000,
1031 .max_bw_high = 12800000,
1032 .min_core_ib = 2400000,
1033 .min_llcc_ib = 800000,
1034 .min_dram_ib = 800000,
1035 .min_prefill_lines = 24,
1036 .danger_lut_tbl = {0xf, 0xffff, 0x0},
1037 .safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
1038 .qos_lut_tbl = {
1039 {.nentry = ARRAY_SIZE(sm8150_qos_linear),
1040 .entries = sm8150_qos_linear
1041 },
1042 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1043 .entries = sc7180_qos_macrotile
1044 },
1045 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1046 .entries = sc7180_qos_nrt
1047 },
1048 /* TODO: macrotile-qseed is different from macrotile */
1049 },
1050 .cdp_cfg = {
1051 {.rd_enable = 1, .wr_enable = 1},
1052 {.rd_enable = 1, .wr_enable = 0}
1053 },
1054 .clk_inefficiency_factor = 105,
1055 .bw_inefficiency_factor = 120,
1056 };
1057
1058 static const struct dpu_perf_cfg sm8250_perf_data = {
1059 .max_bw_low = 13700000,
1060 .max_bw_high = 16600000,
1061 .min_core_ib = 4800000,
1062 .min_llcc_ib = 0,
1063 .min_dram_ib = 800000,
1064 .min_prefill_lines = 35,
1065 .danger_lut_tbl = {0xf, 0xffff, 0x0},
1066 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
1067 .qos_lut_tbl = {
1068 {.nentry = ARRAY_SIZE(sc7180_qos_linear),
1069 .entries = sc7180_qos_linear
1070 },
1071 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1072 .entries = sc7180_qos_macrotile
1073 },
1074 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1075 .entries = sc7180_qos_nrt
1076 },
1077 /* TODO: macrotile-qseed is different from macrotile */
1078 },
1079 .cdp_cfg = {
1080 {.rd_enable = 1, .wr_enable = 1},
1081 {.rd_enable = 1, .wr_enable = 0}
1082 },
1083 .clk_inefficiency_factor = 105,
1084 .bw_inefficiency_factor = 120,
1085 };
1086
1087 static const struct dpu_perf_cfg sc7280_perf_data = {
1088 .max_bw_low = 4700000,
1089 .max_bw_high = 8800000,
1090 .min_core_ib = 2500000,
1091 .min_llcc_ib = 0,
1092 .min_dram_ib = 1600000,
1093 .min_prefill_lines = 24,
1094 .danger_lut_tbl = {0xffff, 0xffff, 0x0},
1095 .safe_lut_tbl = {0xff00, 0xff00, 0xffff},
1096 .qos_lut_tbl = {
1097 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1098 .entries = sc7180_qos_macrotile
1099 },
1100 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1101 .entries = sc7180_qos_macrotile
1102 },
1103 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1104 .entries = sc7180_qos_nrt
1105 },
1106 },
1107 .cdp_cfg = {
1108 {.rd_enable = 1, .wr_enable = 1},
1109 {.rd_enable = 1, .wr_enable = 0}
1110 },
1111 .clk_inefficiency_factor = 105,
1112 .bw_inefficiency_factor = 120,
1113 };
1114
1115 /*************************************************************
1116 * Hardware catalog init
1117 *************************************************************/
1118
1119 /*
1120 * sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets
1121 * and instance counts.
1122 */
sdm845_cfg_init(struct dpu_mdss_cfg * dpu_cfg)1123 static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
1124 {
1125 *dpu_cfg = (struct dpu_mdss_cfg){
1126 .caps = &sdm845_dpu_caps,
1127 .mdp_count = ARRAY_SIZE(sdm845_mdp),
1128 .mdp = sdm845_mdp,
1129 .ctl_count = ARRAY_SIZE(sdm845_ctl),
1130 .ctl = sdm845_ctl,
1131 .sspp_count = ARRAY_SIZE(sdm845_sspp),
1132 .sspp = sdm845_sspp,
1133 .mixer_count = ARRAY_SIZE(sdm845_lm),
1134 .mixer = sdm845_lm,
1135 .pingpong_count = ARRAY_SIZE(sdm845_pp),
1136 .pingpong = sdm845_pp,
1137 .intf_count = ARRAY_SIZE(sdm845_intf),
1138 .intf = sdm845_intf,
1139 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1140 .vbif = sdm845_vbif,
1141 .reg_dma_count = 1,
1142 .dma_cfg = sdm845_regdma,
1143 .perf = sdm845_perf_data,
1144 .mdss_irqs = IRQ_SDM845_MASK,
1145 };
1146 }
1147
1148 /*
1149 * sc7180_cfg_init(): populate sc7180 dpu sub-blocks reg offsets
1150 * and instance counts.
1151 */
sc7180_cfg_init(struct dpu_mdss_cfg * dpu_cfg)1152 static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
1153 {
1154 *dpu_cfg = (struct dpu_mdss_cfg){
1155 .caps = &sc7180_dpu_caps,
1156 .mdp_count = ARRAY_SIZE(sc7180_mdp),
1157 .mdp = sc7180_mdp,
1158 .ctl_count = ARRAY_SIZE(sc7180_ctl),
1159 .ctl = sc7180_ctl,
1160 .sspp_count = ARRAY_SIZE(sc7180_sspp),
1161 .sspp = sc7180_sspp,
1162 .mixer_count = ARRAY_SIZE(sc7180_lm),
1163 .mixer = sc7180_lm,
1164 .dspp_count = ARRAY_SIZE(sc7180_dspp),
1165 .dspp = sc7180_dspp,
1166 .pingpong_count = ARRAY_SIZE(sc7180_pp),
1167 .pingpong = sc7180_pp,
1168 .intf_count = ARRAY_SIZE(sc7180_intf),
1169 .intf = sc7180_intf,
1170 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1171 .vbif = sdm845_vbif,
1172 .reg_dma_count = 1,
1173 .dma_cfg = sdm845_regdma,
1174 .perf = sc7180_perf_data,
1175 .mdss_irqs = IRQ_SC7180_MASK,
1176 };
1177 }
1178
1179 /*
1180 * sm8150_cfg_init(): populate sm8150 dpu sub-blocks reg offsets
1181 * and instance counts.
1182 */
sm8150_cfg_init(struct dpu_mdss_cfg * dpu_cfg)1183 static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
1184 {
1185 *dpu_cfg = (struct dpu_mdss_cfg){
1186 .caps = &sm8150_dpu_caps,
1187 .mdp_count = ARRAY_SIZE(sdm845_mdp),
1188 .mdp = sdm845_mdp,
1189 .ctl_count = ARRAY_SIZE(sm8150_ctl),
1190 .ctl = sm8150_ctl,
1191 .sspp_count = ARRAY_SIZE(sdm845_sspp),
1192 .sspp = sdm845_sspp,
1193 .mixer_count = ARRAY_SIZE(sm8150_lm),
1194 .mixer = sm8150_lm,
1195 .dspp_count = ARRAY_SIZE(sm8150_dspp),
1196 .dspp = sm8150_dspp,
1197 .pingpong_count = ARRAY_SIZE(sm8150_pp),
1198 .pingpong = sm8150_pp,
1199 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
1200 .merge_3d = sm8150_merge_3d,
1201 .intf_count = ARRAY_SIZE(sm8150_intf),
1202 .intf = sm8150_intf,
1203 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1204 .vbif = sdm845_vbif,
1205 .reg_dma_count = 1,
1206 .dma_cfg = sm8150_regdma,
1207 .perf = sm8150_perf_data,
1208 .mdss_irqs = IRQ_SDM845_MASK,
1209 };
1210 }
1211
1212 /*
1213 * sm8250_cfg_init(): populate sm8250 dpu sub-blocks reg offsets
1214 * and instance counts.
1215 */
sm8250_cfg_init(struct dpu_mdss_cfg * dpu_cfg)1216 static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
1217 {
1218 *dpu_cfg = (struct dpu_mdss_cfg){
1219 .caps = &sm8250_dpu_caps,
1220 .mdp_count = ARRAY_SIZE(sm8250_mdp),
1221 .mdp = sm8250_mdp,
1222 .ctl_count = ARRAY_SIZE(sm8150_ctl),
1223 .ctl = sm8150_ctl,
1224 .sspp_count = ARRAY_SIZE(sm8250_sspp),
1225 .sspp = sm8250_sspp,
1226 .mixer_count = ARRAY_SIZE(sm8150_lm),
1227 .mixer = sm8150_lm,
1228 .dspp_count = ARRAY_SIZE(sm8150_dspp),
1229 .dspp = sm8150_dspp,
1230 .pingpong_count = ARRAY_SIZE(sm8150_pp),
1231 .pingpong = sm8150_pp,
1232 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
1233 .merge_3d = sm8150_merge_3d,
1234 .intf_count = ARRAY_SIZE(sm8150_intf),
1235 .intf = sm8150_intf,
1236 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1237 .vbif = sdm845_vbif,
1238 .reg_dma_count = 1,
1239 .dma_cfg = sm8250_regdma,
1240 .perf = sm8250_perf_data,
1241 .mdss_irqs = IRQ_SM8250_MASK,
1242 };
1243 }
1244
sc7280_cfg_init(struct dpu_mdss_cfg * dpu_cfg)1245 static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
1246 {
1247 *dpu_cfg = (struct dpu_mdss_cfg){
1248 .caps = &sc7280_dpu_caps,
1249 .mdp_count = ARRAY_SIZE(sc7280_mdp),
1250 .mdp = sc7280_mdp,
1251 .ctl_count = ARRAY_SIZE(sc7280_ctl),
1252 .ctl = sc7280_ctl,
1253 .sspp_count = ARRAY_SIZE(sc7280_sspp),
1254 .sspp = sc7280_sspp,
1255 .mixer_count = ARRAY_SIZE(sc7280_lm),
1256 .mixer = sc7280_lm,
1257 .pingpong_count = ARRAY_SIZE(sc7280_pp),
1258 .pingpong = sc7280_pp,
1259 .intf_count = ARRAY_SIZE(sc7280_intf),
1260 .intf = sc7280_intf,
1261 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1262 .vbif = sdm845_vbif,
1263 .perf = sc7280_perf_data,
1264 .mdss_irqs = IRQ_SC7280_MASK,
1265 };
1266 }
1267
1268 static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
1269 { .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init},
1270 { .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init},
1271 { .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init},
1272 { .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init},
1273 { .hw_rev = DPU_HW_VER_600, .cfg_init = sm8250_cfg_init},
1274 { .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init},
1275 { .hw_rev = DPU_HW_VER_720, .cfg_init = sc7280_cfg_init},
1276 };
1277
dpu_hw_catalog_deinit(struct dpu_mdss_cfg * dpu_cfg)1278 void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg)
1279 {
1280 kfree(dpu_cfg);
1281 }
1282
dpu_hw_catalog_init(u32 hw_rev)1283 struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
1284 {
1285 int i;
1286 struct dpu_mdss_cfg *dpu_cfg;
1287
1288 dpu_cfg = kzalloc(sizeof(*dpu_cfg), GFP_KERNEL);
1289 if (!dpu_cfg)
1290 return ERR_PTR(-ENOMEM);
1291
1292 for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
1293 if (cfg_handler[i].hw_rev == hw_rev) {
1294 cfg_handler[i].cfg_init(dpu_cfg);
1295 dpu_cfg->hwversion = hw_rev;
1296 return dpu_cfg;
1297 }
1298 }
1299
1300 DPU_ERROR("unsupported chipset id:%X\n", hw_rev);
1301 dpu_hw_catalog_deinit(dpu_cfg);
1302 return ERR_PTR(-ENODEV);
1303 }
1304
1305