| /drivers/clk/sprd/ |
| D | gate.h | 31 #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
47 #define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ argument
54 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ argument
60 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
72 #define SPRD_PLL_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
81 #define SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg, \ argument
90 #define SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \ argument
97 #define SPRD_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
104 #define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
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| D | mux.h | 40 _reg, _shift, _width, _flags, _fn) \ argument
52 _reg, _shift, _width, _flags) \ argument
57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument
63 _reg, _shift, _width, _flags) \ argument
68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \ argument
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| D | composite.h | 21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument
53 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument
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| D | pll.h | 64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \ argument
112 #define SPRD_PLL_HW(_struct, _name, _parent, _reg, _regs_num, _itable, \ argument
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| D | div.h | 38 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
50 #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \ argument
55 #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \ argument
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| /drivers/clk/meson/ |
| D | axg-audio.c | 23 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ argument
37 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ argument
53 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ argument
69 #define AUD_PCLK_GATE(_name, _reg, _bit) { \ argument
82 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ argument
105 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ argument
133 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ argument
150 #define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ argument
185 #define AUD_MST_MUX(_name, _reg, _flag) \ argument
188 #define AUD_MST_DIV(_name, _reg, _flag) \ argument
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| D | clk-regmap.h | 117 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
132 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
135 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
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| /drivers/clk/sunxi-ng/ |
| D | ccu_gate.h | 19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
71 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ argument
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| D | ccu_div.h | 87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
113 _reg, \ argument
130 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
139 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
149 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
164 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
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| D | ccu_mp.h | 34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
55 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
74 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
103 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
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| D | ccu_nm.h | 38 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
61 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
86 _reg, _min_rate, \ argument
112 _parent, _reg, \ argument
140 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
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| D | ccu_mux.h | 51 _reg, _shift, _width, _gate, \ argument
65 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
71 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
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| /drivers/regulator/ |
| D | mc13xxx.h | 55 #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \ argument
73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
88 #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
103 #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument
105 #define MC13xxx_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument
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| /drivers/clk/pistachio/ |
| D | clk.h | 19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
130 #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ argument
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| /drivers/clk/actions/ |
| D | owl-gate.h | 27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument
34 #define OWL_GATE(_struct, _name, _parent, _reg, \ argument
47 #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ argument
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| D | owl-pll.h | 41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
55 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument
70 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
84 #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
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| D | owl-mux.h | 27 #define OWL_MUX_HW(_reg, _shift, _width) \ argument
34 #define OWL_MUX(_struct, _name, _parents, _reg, \ argument
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| /drivers/reset/sti/ |
| D | reset-stih407.c | 57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
60 #define STIH407_SRST_SBC(_reg, _bit) \ argument
63 #define STIH407_SRST_LPM(_reg, _bit) \ argument
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| /drivers/net/ethernet/amd/xgbe/ |
| D | xgbe-common.h | 1462 #define XGMAC_IOREAD(_pdata, _reg) \ argument
1465 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ argument
1470 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ argument
1473 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ argument
1486 #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \ argument
1490 #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ argument
1495 #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ argument
1499 #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ argument
1512 #define XGMAC_DMA_IOREAD(_channel, _reg) \ argument
1515 #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ argument
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| /drivers/ufs/host/ |
| D | ufs-renesas.c | 41 #define PARAM_RESTORE(_reg, _index) \ argument
45 #define PARAM_SAVE(_reg, _mask, _index) \ argument
48 #define PARAM_POLL(_reg, _expected, _mask) \ argument
54 #define PARAM_WRITE(_reg, _val) \ argument
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| /drivers/i2c/busses/ |
| D | i2c-brcmstb.c | 177 #define __bsc_readl(_reg) ioread32be(_reg) argument
178 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg) argument
180 #define __bsc_readl(_reg) ioread32(_reg) argument
181 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg) argument
184 #define bsc_readl(_dev, _reg) \ argument
187 #define bsc_writel(_dev, _val, _reg) \ argument
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| /drivers/clk/mediatek/ |
| D | clk-mtk.h | 82 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
102 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
111 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
115 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
119 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
191 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
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| /drivers/clk/x86/ |
| D | clk-cgu.h | 118 _reg, _type) \ argument
146 #define LGM_DDIV(_id, _name, _pname, _flags, _reg, \ argument
203 #define LGM_MUX(_id, _name, _pdata, _f, _reg, \ argument
219 #define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \ argument
241 #define LGM_GATE(_id, _name, _pname, _f, _reg, \ argument
259 #define LGM_FIXED(_id, _name, _pname, _f, _reg, \ argument
279 #define LGM_FIXED_FACTOR(_id, _name, _pname, _f, _reg, \ argument
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| /drivers/net/ethernet/freescale/fs_enet/ |
| D | mac-fec.c | 62 #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v)) argument
65 #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg) argument
68 #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v)) argument
71 #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v)) argument
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| /drivers/power/supply/ |
| D | max77650-charger.c | 21 #define MAX77650_CHG_DETAILS_BITS(_reg) \ argument
52 #define MAX77650_CHGIN_DETAILS_BITS(_reg) \ argument
60 #define MAX77650_CHARGER_CHG_CHARGING(_reg) \ argument
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