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1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef __MLX5_EN_STATS_H__
34 #define __MLX5_EN_STATS_H__
35 
36 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
37 	(*(u64 *)((char *)ptr + dsc[i].offset))
38 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
39 	be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
40 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
41 	(*(u32 *)((char *)ptr + dsc[i].offset))
42 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
43 	be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
44 
45 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
46 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
47 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
48 #define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld)
49 #define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld)
50 #define MLX5E_DECLARE_XSKRQ_STAT(type, fld) "rx%d_xsk_"#fld, offsetof(type, fld)
51 #define MLX5E_DECLARE_XSKSQ_STAT(type, fld) "tx%d_xsk_"#fld, offsetof(type, fld)
52 #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld)
53 
54 #define MLX5E_DECLARE_PTP_TX_STAT(type, fld) "ptp_tx%d_"#fld, offsetof(type, fld)
55 #define MLX5E_DECLARE_PTP_CH_STAT(type, fld) "ptp_ch_"#fld, offsetof(type, fld)
56 #define MLX5E_DECLARE_PTP_CQ_STAT(type, fld) "ptp_cq%d_"#fld, offsetof(type, fld)
57 #define MLX5E_DECLARE_PTP_RQ_STAT(type, fld) "ptp_rq%d_"#fld, offsetof(type, fld)
58 
59 #define MLX5E_DECLARE_QOS_TX_STAT(type, fld) "qos_tx%d_"#fld, offsetof(type, fld)
60 
61 struct counter_desc {
62 	char		format[ETH_GSTRING_LEN];
63 	size_t		offset; /* Byte offset */
64 };
65 
66 enum {
67 	MLX5E_NDO_UPDATE_STATS = BIT(0x1),
68 };
69 
70 struct mlx5e_priv;
71 struct mlx5e_stats_grp {
72 	u16 update_stats_mask;
73 	int (*get_num_stats)(struct mlx5e_priv *priv);
74 	int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx);
75 	int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx);
76 	void (*update_stats)(struct mlx5e_priv *priv);
77 };
78 
79 typedef const struct mlx5e_stats_grp *const mlx5e_stats_grp_t;
80 
81 #define MLX5E_STATS_GRP_OP(grp, name) mlx5e_stats_grp_ ## grp ## _ ## name
82 
83 #define MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(grp) \
84 	int MLX5E_STATS_GRP_OP(grp, num_stats)(struct mlx5e_priv *priv)
85 
86 #define MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(grp) \
87 	void MLX5E_STATS_GRP_OP(grp, update_stats)(struct mlx5e_priv *priv)
88 
89 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(grp) \
90 	int MLX5E_STATS_GRP_OP(grp, fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx)
91 
92 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(grp) \
93 	int MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx)
94 
95 #define MLX5E_STATS_GRP(grp) mlx5e_stats_grp_ ## grp
96 
97 #define MLX5E_DECLARE_STATS_GRP(grp) \
98 	const struct mlx5e_stats_grp MLX5E_STATS_GRP(grp)
99 
100 #define MLX5E_DEFINE_STATS_GRP(grp, mask) \
101 MLX5E_DECLARE_STATS_GRP(grp) = { \
102 	.get_num_stats = MLX5E_STATS_GRP_OP(grp, num_stats), \
103 	.fill_stats    = MLX5E_STATS_GRP_OP(grp, fill_stats), \
104 	.fill_strings  = MLX5E_STATS_GRP_OP(grp, fill_strings), \
105 	.update_stats  = MLX5E_STATS_GRP_OP(grp, update_stats), \
106 	.update_stats_mask = mask, \
107 }
108 
109 unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv);
110 void mlx5e_stats_update(struct mlx5e_priv *priv);
111 void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx);
112 void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data);
113 void mlx5e_stats_update_ndo_stats(struct mlx5e_priv *priv);
114 
115 void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
116 			   struct ethtool_pause_stats *pause_stats);
117 void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
118 			 struct ethtool_fec_stats *fec_stats);
119 
120 void mlx5e_stats_eth_phy_get(struct mlx5e_priv *priv,
121 			     struct ethtool_eth_phy_stats *phy_stats);
122 void mlx5e_stats_eth_mac_get(struct mlx5e_priv *priv,
123 			     struct ethtool_eth_mac_stats *mac_stats);
124 void mlx5e_stats_eth_ctrl_get(struct mlx5e_priv *priv,
125 			      struct ethtool_eth_ctrl_stats *ctrl_stats);
126 void mlx5e_stats_rmon_get(struct mlx5e_priv *priv,
127 			  struct ethtool_rmon_stats *rmon,
128 			  const struct ethtool_rmon_hist_range **ranges);
129 
130 /* Concrete NIC Stats */
131 
132 struct mlx5e_sw_stats {
133 	u64 rx_packets;
134 	u64 rx_bytes;
135 	u64 tx_packets;
136 	u64 tx_bytes;
137 	u64 tx_tso_packets;
138 	u64 tx_tso_bytes;
139 	u64 tx_tso_inner_packets;
140 	u64 tx_tso_inner_bytes;
141 	u64 tx_added_vlan_packets;
142 	u64 tx_nop;
143 	u64 tx_mpwqe_blks;
144 	u64 tx_mpwqe_pkts;
145 	u64 rx_lro_packets;
146 	u64 rx_lro_bytes;
147 	u64 rx_mcast_packets;
148 	u64 rx_ecn_mark;
149 	u64 rx_removed_vlan_packets;
150 	u64 rx_csum_unnecessary;
151 	u64 rx_csum_none;
152 	u64 rx_csum_complete;
153 	u64 rx_csum_complete_tail;
154 	u64 rx_csum_complete_tail_slow;
155 	u64 rx_csum_unnecessary_inner;
156 	u64 rx_xdp_drop;
157 	u64 rx_xdp_redirect;
158 	u64 rx_xdp_tx_xmit;
159 	u64 rx_xdp_tx_mpwqe;
160 	u64 rx_xdp_tx_inlnw;
161 	u64 rx_xdp_tx_nops;
162 	u64 rx_xdp_tx_full;
163 	u64 rx_xdp_tx_err;
164 	u64 rx_xdp_tx_cqe;
165 	u64 tx_csum_none;
166 	u64 tx_csum_partial;
167 	u64 tx_csum_partial_inner;
168 	u64 tx_queue_stopped;
169 	u64 tx_queue_dropped;
170 	u64 tx_xmit_more;
171 	u64 tx_recover;
172 	u64 tx_cqes;
173 	u64 tx_queue_wake;
174 	u64 tx_cqe_err;
175 	u64 tx_xdp_xmit;
176 	u64 tx_xdp_mpwqe;
177 	u64 tx_xdp_inlnw;
178 	u64 tx_xdp_nops;
179 	u64 tx_xdp_full;
180 	u64 tx_xdp_err;
181 	u64 tx_xdp_cqes;
182 	u64 rx_wqe_err;
183 	u64 rx_mpwqe_filler_cqes;
184 	u64 rx_mpwqe_filler_strides;
185 	u64 rx_oversize_pkts_sw_drop;
186 	u64 rx_buff_alloc_err;
187 	u64 rx_cqe_compress_blks;
188 	u64 rx_cqe_compress_pkts;
189 	u64 rx_cache_reuse;
190 	u64 rx_cache_full;
191 	u64 rx_cache_empty;
192 	u64 rx_cache_busy;
193 	u64 rx_cache_waive;
194 	u64 rx_congst_umr;
195 	u64 rx_arfs_err;
196 	u64 rx_recover;
197 	u64 ch_events;
198 	u64 ch_poll;
199 	u64 ch_arm;
200 	u64 ch_aff_change;
201 	u64 ch_force_irq;
202 	u64 ch_eq_rearm;
203 
204 #ifdef CONFIG_MLX5_EN_TLS
205 	u64 tx_tls_encrypted_packets;
206 	u64 tx_tls_encrypted_bytes;
207 	u64 tx_tls_ooo;
208 	u64 tx_tls_dump_packets;
209 	u64 tx_tls_dump_bytes;
210 	u64 tx_tls_resync_bytes;
211 	u64 tx_tls_skip_no_sync_data;
212 	u64 tx_tls_drop_no_sync_data;
213 	u64 tx_tls_drop_bypass_req;
214 
215 	u64 rx_tls_decrypted_packets;
216 	u64 rx_tls_decrypted_bytes;
217 	u64 rx_tls_resync_req_pkt;
218 	u64 rx_tls_resync_req_start;
219 	u64 rx_tls_resync_req_end;
220 	u64 rx_tls_resync_req_skip;
221 	u64 rx_tls_resync_res_ok;
222 	u64 rx_tls_resync_res_retry;
223 	u64 rx_tls_resync_res_skip;
224 	u64 rx_tls_err;
225 #endif
226 
227 	u64 rx_xsk_packets;
228 	u64 rx_xsk_bytes;
229 	u64 rx_xsk_csum_complete;
230 	u64 rx_xsk_csum_unnecessary;
231 	u64 rx_xsk_csum_unnecessary_inner;
232 	u64 rx_xsk_csum_none;
233 	u64 rx_xsk_ecn_mark;
234 	u64 rx_xsk_removed_vlan_packets;
235 	u64 rx_xsk_xdp_drop;
236 	u64 rx_xsk_xdp_redirect;
237 	u64 rx_xsk_wqe_err;
238 	u64 rx_xsk_mpwqe_filler_cqes;
239 	u64 rx_xsk_mpwqe_filler_strides;
240 	u64 rx_xsk_oversize_pkts_sw_drop;
241 	u64 rx_xsk_buff_alloc_err;
242 	u64 rx_xsk_cqe_compress_blks;
243 	u64 rx_xsk_cqe_compress_pkts;
244 	u64 rx_xsk_congst_umr;
245 	u64 rx_xsk_arfs_err;
246 	u64 tx_xsk_xmit;
247 	u64 tx_xsk_mpwqe;
248 	u64 tx_xsk_inlnw;
249 	u64 tx_xsk_full;
250 	u64 tx_xsk_err;
251 	u64 tx_xsk_cqes;
252 };
253 
254 struct mlx5e_qcounter_stats {
255 	u32 rx_out_of_buffer;
256 	u32 rx_if_down_packets;
257 };
258 
259 struct mlx5e_vnic_env_stats {
260 	__be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)];
261 };
262 
263 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
264 						vstats->query_vport_out, c)
265 
266 struct mlx5e_vport_stats {
267 	__be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
268 };
269 
270 #define PPORT_802_3_GET(pstats, c) \
271 	MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
272 		   counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
273 #define PPORT_2863_GET(pstats, c) \
274 	MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
275 		   counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
276 #define PPORT_2819_GET(pstats, c) \
277 	MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
278 		   counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
279 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \
280 	MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
281 		   counter_set.phys_layer_statistical_cntrs.c##_high)
282 #define PPORT_PER_PRIO_GET(pstats, prio, c) \
283 	MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
284 		   counter_set.eth_per_prio_grp_data_layout.c##_high)
285 #define NUM_PPORT_PRIO				8
286 #define PPORT_ETH_EXT_GET(pstats, c) \
287 	MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
288 		   counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
289 
290 struct mlx5e_pport_stats {
291 	__be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
292 	__be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
293 	__be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
294 	__be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
295 	__be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
296 	__be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
297 	__be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
298 	__be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
299 	__be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
300 };
301 
302 #define PCIE_PERF_GET(pcie_stats, c) \
303 	MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
304 		 counter_set.pcie_perf_cntrs_grp_data_layout.c)
305 
306 #define PCIE_PERF_GET64(pcie_stats, c) \
307 	MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
308 		   counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
309 
310 struct mlx5e_pcie_stats {
311 	__be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
312 };
313 
314 struct mlx5e_rq_stats {
315 	u64 packets;
316 	u64 bytes;
317 	u64 csum_complete;
318 	u64 csum_complete_tail;
319 	u64 csum_complete_tail_slow;
320 	u64 csum_unnecessary;
321 	u64 csum_unnecessary_inner;
322 	u64 csum_none;
323 	u64 lro_packets;
324 	u64 lro_bytes;
325 	u64 mcast_packets;
326 	u64 ecn_mark;
327 	u64 removed_vlan_packets;
328 	u64 xdp_drop;
329 	u64 xdp_redirect;
330 	u64 wqe_err;
331 	u64 mpwqe_filler_cqes;
332 	u64 mpwqe_filler_strides;
333 	u64 oversize_pkts_sw_drop;
334 	u64 buff_alloc_err;
335 	u64 cqe_compress_blks;
336 	u64 cqe_compress_pkts;
337 	u64 cache_reuse;
338 	u64 cache_full;
339 	u64 cache_empty;
340 	u64 cache_busy;
341 	u64 cache_waive;
342 	u64 congst_umr;
343 	u64 arfs_err;
344 	u64 recover;
345 #ifdef CONFIG_MLX5_EN_TLS
346 	u64 tls_decrypted_packets;
347 	u64 tls_decrypted_bytes;
348 	u64 tls_resync_req_pkt;
349 	u64 tls_resync_req_start;
350 	u64 tls_resync_req_end;
351 	u64 tls_resync_req_skip;
352 	u64 tls_resync_res_ok;
353 	u64 tls_resync_res_retry;
354 	u64 tls_resync_res_skip;
355 	u64 tls_err;
356 #endif
357 };
358 
359 struct mlx5e_sq_stats {
360 	/* commonly accessed in data path */
361 	u64 packets;
362 	u64 bytes;
363 	u64 xmit_more;
364 	u64 tso_packets;
365 	u64 tso_bytes;
366 	u64 tso_inner_packets;
367 	u64 tso_inner_bytes;
368 	u64 csum_partial;
369 	u64 csum_partial_inner;
370 	u64 added_vlan_packets;
371 	u64 nop;
372 	u64 mpwqe_blks;
373 	u64 mpwqe_pkts;
374 #ifdef CONFIG_MLX5_EN_TLS
375 	u64 tls_encrypted_packets;
376 	u64 tls_encrypted_bytes;
377 	u64 tls_ooo;
378 	u64 tls_dump_packets;
379 	u64 tls_dump_bytes;
380 	u64 tls_resync_bytes;
381 	u64 tls_skip_no_sync_data;
382 	u64 tls_drop_no_sync_data;
383 	u64 tls_drop_bypass_req;
384 #endif
385 	/* less likely accessed in data path */
386 	u64 csum_none;
387 	u64 stopped;
388 	u64 dropped;
389 	u64 recover;
390 	/* dirtied @completion */
391 	u64 cqes ____cacheline_aligned_in_smp;
392 	u64 wake;
393 	u64 cqe_err;
394 };
395 
396 struct mlx5e_xdpsq_stats {
397 	u64 xmit;
398 	u64 mpwqe;
399 	u64 inlnw;
400 	u64 nops;
401 	u64 full;
402 	u64 err;
403 	/* dirtied @completion */
404 	u64 cqes ____cacheline_aligned_in_smp;
405 };
406 
407 struct mlx5e_ch_stats {
408 	u64 events;
409 	u64 poll;
410 	u64 arm;
411 	u64 aff_change;
412 	u64 force_irq;
413 	u64 eq_rearm;
414 };
415 
416 struct mlx5e_ptp_cq_stats {
417 	u64 cqe;
418 	u64 err_cqe;
419 	u64 abort;
420 	u64 abort_abs_diff_ns;
421 };
422 
423 struct mlx5e_stats {
424 	struct mlx5e_sw_stats sw;
425 	struct mlx5e_qcounter_stats qcnt;
426 	struct mlx5e_vnic_env_stats vnic;
427 	struct mlx5e_vport_stats vport;
428 	struct mlx5e_pport_stats pport;
429 	struct rtnl_link_stats64 vf_vport;
430 	struct mlx5e_pcie_stats pcie;
431 };
432 
433 extern mlx5e_stats_grp_t mlx5e_nic_stats_grps[];
434 unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv);
435 
436 extern MLX5E_DECLARE_STATS_GRP(sw);
437 extern MLX5E_DECLARE_STATS_GRP(qcnt);
438 extern MLX5E_DECLARE_STATS_GRP(vnic_env);
439 extern MLX5E_DECLARE_STATS_GRP(vport);
440 extern MLX5E_DECLARE_STATS_GRP(802_3);
441 extern MLX5E_DECLARE_STATS_GRP(2863);
442 extern MLX5E_DECLARE_STATS_GRP(2819);
443 extern MLX5E_DECLARE_STATS_GRP(phy);
444 extern MLX5E_DECLARE_STATS_GRP(eth_ext);
445 extern MLX5E_DECLARE_STATS_GRP(pcie);
446 extern MLX5E_DECLARE_STATS_GRP(per_prio);
447 extern MLX5E_DECLARE_STATS_GRP(pme);
448 extern MLX5E_DECLARE_STATS_GRP(channels);
449 extern MLX5E_DECLARE_STATS_GRP(per_port_buff_congest);
450 extern MLX5E_DECLARE_STATS_GRP(ipsec_hw);
451 extern MLX5E_DECLARE_STATS_GRP(ipsec_sw);
452 
453 #endif /* __MLX5_EN_STATS_H__ */
454