1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #ifndef __MSM_DRV_H__
9 #define __MSM_DRV_H__
10
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/cpufreq.h>
14 #include <linux/module.h>
15 #include <linux/component.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <linux/list.h>
21 #include <linux/iommu.h>
22 #include <linux/types.h>
23 #include <linux/of_graph.h>
24 #include <linux/of_device.h>
25 #include <linux/sizes.h>
26 #include <linux/kthread.h>
27
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_plane_helper.h>
31 #include <drm/drm_probe_helper.h>
32 #include <drm/drm_fb_helper.h>
33 #include <drm/msm_drm.h>
34 #include <drm/drm_gem.h>
35
36 struct msm_kms;
37 struct msm_gpu;
38 struct msm_mmu;
39 struct msm_mdss;
40 struct msm_rd_state;
41 struct msm_perf_state;
42 struct msm_gem_submit;
43 struct msm_fence_context;
44 struct msm_gem_address_space;
45 struct msm_gem_vma;
46 struct msm_disp_state;
47
48 #define MAX_CRTCS 8
49 #define MAX_PLANES 20
50 #define MAX_ENCODERS 8
51 #define MAX_BRIDGES 8
52 #define MAX_CONNECTORS 8
53
54 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
55
56 enum msm_mdp_plane_property {
57 PLANE_PROP_ZPOS,
58 PLANE_PROP_ALPHA,
59 PLANE_PROP_PREMULTIPLIED,
60 PLANE_PROP_MAX_NUM
61 };
62
63 #define MSM_GPU_MAX_RINGS 4
64 #define MAX_H_TILES_PER_DISPLAY 2
65
66 /**
67 * enum msm_display_caps - features/capabilities supported by displays
68 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
69 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
70 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
71 * @MSM_DISPLAY_CAP_EDID: EDID supported
72 */
73 enum msm_display_caps {
74 MSM_DISPLAY_CAP_VID_MODE = BIT(0),
75 MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
76 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
77 MSM_DISPLAY_CAP_EDID = BIT(3),
78 };
79
80 /**
81 * enum msm_event_wait - type of HW events to wait for
82 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
83 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
84 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
85 */
86 enum msm_event_wait {
87 MSM_ENC_COMMIT_DONE = 0,
88 MSM_ENC_TX_COMPLETE,
89 MSM_ENC_VBLANK,
90 };
91
92 /**
93 * struct msm_display_topology - defines a display topology pipeline
94 * @num_lm: number of layer mixers used
95 * @num_enc: number of compression encoder blocks used
96 * @num_intf: number of interfaces the panel is mounted on
97 */
98 struct msm_display_topology {
99 u32 num_lm;
100 u32 num_enc;
101 u32 num_intf;
102 u32 num_dspp;
103 };
104
105 /**
106 * struct msm_display_info - defines display properties
107 * @intf_type: DRM_MODE_ENCODER_ type
108 * @capabilities: Bitmask of display flags
109 * @num_of_h_tiles: Number of horizontal tiles in case of split interface
110 * @h_tile_instance: Controller instance used per tile. Number of elements is
111 * based on num_of_h_tiles
112 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
113 * used instead of panel TE in cmd mode panels
114 */
115 struct msm_display_info {
116 int intf_type;
117 uint32_t capabilities;
118 uint32_t num_of_h_tiles;
119 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
120 bool is_te_using_watchdog_timer;
121 };
122
123 /* Commit/Event thread specific structure */
124 struct msm_drm_thread {
125 struct drm_device *dev;
126 unsigned int crtc_id;
127 struct kthread_worker *worker;
128 };
129
130 struct msm_drm_private {
131
132 struct drm_device *dev;
133
134 struct msm_kms *kms;
135
136 /* subordinate devices, if present: */
137 struct platform_device *gpu_pdev;
138
139 /* top level MDSS wrapper device (for MDP5/DPU only) */
140 struct msm_mdss *mdss;
141
142 /* possibly this should be in the kms component, but it is
143 * shared by both mdp4 and mdp5..
144 */
145 struct hdmi *hdmi;
146
147 /* eDP is for mdp5 only, but kms has not been created
148 * when edp_bind() and edp_init() are called. Here is the only
149 * place to keep the edp instance.
150 */
151 struct msm_edp *edp;
152
153 /* DSI is shared by mdp4 and mdp5 */
154 struct msm_dsi *dsi[2];
155
156 struct msm_dp *dp;
157
158 /* when we have more than one 'msm_gpu' these need to be an array: */
159 struct msm_gpu *gpu;
160 struct msm_file_private *lastctx;
161 /* gpu is only set on open(), but we need this info earlier */
162 bool is_a2xx;
163 bool has_cached_coherent;
164
165 struct drm_fb_helper *fbdev;
166
167 struct msm_rd_state *rd; /* debugfs to dump all submits */
168 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
169 struct msm_perf_state *perf;
170
171 /**
172 * List of all GEM objects (mainly for debugfs, protected by obj_lock
173 * (acquire before per GEM object lock)
174 */
175 struct list_head objects;
176 struct mutex obj_lock;
177
178 /**
179 * LRUs of inactive GEM objects. Every bo is either in one of the
180 * inactive lists (depending on whether or not it is shrinkable) or
181 * gpu->active_list (for the gpu it is active on[1]), or transiently
182 * on a temporary list as the shrinker is running.
183 *
184 * Note that inactive_willneed also contains pinned and vmap'd bos,
185 * but the number of pinned-but-not-active objects is small (scanout
186 * buffers, ringbuffer, etc).
187 *
188 * These lists are protected by mm_lock (which should be acquired
189 * before per GEM object lock). One should *not* hold mm_lock in
190 * get_pages()/vmap()/etc paths, as they can trigger the shrinker.
191 *
192 * [1] if someone ever added support for the old 2d cores, there could be
193 * more than one gpu object
194 */
195 struct list_head inactive_willneed; /* inactive + potentially unpin/evictable */
196 struct list_head inactive_dontneed; /* inactive + shrinkable */
197 struct list_head inactive_unpinned; /* inactive + purged or unpinned */
198 long shrinkable_count; /* write access under mm_lock */
199 long evictable_count; /* write access under mm_lock */
200 struct mutex mm_lock;
201
202 struct workqueue_struct *wq;
203
204 unsigned int num_planes;
205 struct drm_plane *planes[MAX_PLANES];
206
207 unsigned int num_crtcs;
208 struct drm_crtc *crtcs[MAX_CRTCS];
209
210 struct msm_drm_thread event_thread[MAX_CRTCS];
211
212 unsigned int num_encoders;
213 struct drm_encoder *encoders[MAX_ENCODERS];
214
215 unsigned int num_bridges;
216 struct drm_bridge *bridges[MAX_BRIDGES];
217
218 unsigned int num_connectors;
219 struct drm_connector *connectors[MAX_CONNECTORS];
220
221 /* Properties */
222 struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
223
224 /* VRAM carveout, used when no IOMMU: */
225 struct {
226 unsigned long size;
227 dma_addr_t paddr;
228 /* NOTE: mm managed at the page level, size is in # of pages
229 * and position mm_node->start is in # of pages:
230 */
231 struct drm_mm mm;
232 spinlock_t lock; /* Protects drm_mm node allocation/removal */
233 } vram;
234
235 struct notifier_block vmap_notifier;
236 struct shrinker shrinker;
237
238 struct drm_atomic_state *pm_state;
239
240 /* For hang detection, in ms */
241 unsigned int hangcheck_period;
242 };
243
244 struct msm_format {
245 uint32_t pixel_format;
246 };
247
248 struct msm_pending_timer;
249
250 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
251 struct msm_kms *kms, int crtc_idx);
252 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer);
253 void msm_atomic_commit_tail(struct drm_atomic_state *state);
254 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
255 void msm_atomic_state_clear(struct drm_atomic_state *state);
256 void msm_atomic_state_free(struct drm_atomic_state *state);
257
258 int msm_crtc_enable_vblank(struct drm_crtc *crtc);
259 void msm_crtc_disable_vblank(struct drm_crtc *crtc);
260
261 int msm_gem_init_vma(struct msm_gem_address_space *aspace,
262 struct msm_gem_vma *vma, int npages,
263 u64 range_start, u64 range_end);
264 void msm_gem_purge_vma(struct msm_gem_address_space *aspace,
265 struct msm_gem_vma *vma);
266 void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
267 struct msm_gem_vma *vma);
268 int msm_gem_map_vma(struct msm_gem_address_space *aspace,
269 struct msm_gem_vma *vma, int prot,
270 struct sg_table *sgt, int npages);
271 void msm_gem_close_vma(struct msm_gem_address_space *aspace,
272 struct msm_gem_vma *vma);
273
274
275 struct msm_gem_address_space *
276 msm_gem_address_space_get(struct msm_gem_address_space *aspace);
277
278 void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
279
280 struct msm_gem_address_space *
281 msm_gem_address_space_create(struct msm_mmu *mmu, const char *name,
282 u64 va_start, u64 size);
283
284 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
285 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
286
287 bool msm_use_mmu(struct drm_device *dev);
288
289 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
290 struct drm_file *file);
291
292 #ifdef CONFIG_DEBUG_FS
293 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
294 #endif
295
296 void msm_gem_shrinker_init(struct drm_device *dev);
297 void msm_gem_shrinker_cleanup(struct drm_device *dev);
298
299 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
300 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
301 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
302 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
303 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
304 struct dma_buf_attachment *attach, struct sg_table *sg);
305 int msm_gem_prime_pin(struct drm_gem_object *obj);
306 void msm_gem_prime_unpin(struct drm_gem_object *obj);
307
308 int msm_framebuffer_prepare(struct drm_framebuffer *fb,
309 struct msm_gem_address_space *aspace, bool needs_dirtyfb);
310 void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
311 struct msm_gem_address_space *aspace, bool needed_dirtyfb);
312 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
313 struct msm_gem_address_space *aspace, int plane);
314 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
315 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
316 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
317 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
318 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
319 int w, int h, int p, uint32_t format);
320
321 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
322 void msm_fbdev_free(struct drm_device *dev);
323
324 struct hdmi;
325 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
326 struct drm_encoder *encoder);
327 void __init msm_hdmi_register(void);
328 void __exit msm_hdmi_unregister(void);
329
330 struct msm_edp;
331 void __init msm_edp_register(void);
332 void __exit msm_edp_unregister(void);
333 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
334 struct drm_encoder *encoder);
335
336 struct msm_dsi;
337 #ifdef CONFIG_DRM_MSM_DSI
338 void __init msm_dsi_register(void);
339 void __exit msm_dsi_unregister(void);
340 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
341 struct drm_encoder *encoder);
342 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
343 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
344 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
345 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
346 #else
msm_dsi_register(void)347 static inline void __init msm_dsi_register(void)
348 {
349 }
msm_dsi_unregister(void)350 static inline void __exit msm_dsi_unregister(void)
351 {
352 }
msm_dsi_modeset_init(struct msm_dsi * msm_dsi,struct drm_device * dev,struct drm_encoder * encoder)353 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
354 struct drm_device *dev,
355 struct drm_encoder *encoder)
356 {
357 return -EINVAL;
358 }
msm_dsi_snapshot(struct msm_disp_state * disp_state,struct msm_dsi * msm_dsi)359 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
360 {
361 }
msm_dsi_is_cmd_mode(struct msm_dsi * msm_dsi)362 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
363 {
364 return false;
365 }
msm_dsi_is_bonded_dsi(struct msm_dsi * msm_dsi)366 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi)
367 {
368 return false;
369 }
msm_dsi_is_master_dsi(struct msm_dsi * msm_dsi)370 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
371 {
372 return false;
373 }
374 #endif
375
376 #ifdef CONFIG_DRM_MSM_DP
377 int __init msm_dp_register(void);
378 void __exit msm_dp_unregister(void);
379 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
380 struct drm_encoder *encoder);
381 int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder);
382 int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder);
383 int msm_dp_display_pre_disable(struct msm_dp *dp, struct drm_encoder *encoder);
384 void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder,
385 struct drm_display_mode *mode,
386 struct drm_display_mode *adjusted_mode);
387 void msm_dp_irq_postinstall(struct msm_dp *dp_display);
388 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
389
390 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
391
392 #else
msm_dp_register(void)393 static inline int __init msm_dp_register(void)
394 {
395 return -EINVAL;
396 }
msm_dp_unregister(void)397 static inline void __exit msm_dp_unregister(void)
398 {
399 }
msm_dp_modeset_init(struct msm_dp * dp_display,struct drm_device * dev,struct drm_encoder * encoder)400 static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
401 struct drm_device *dev,
402 struct drm_encoder *encoder)
403 {
404 return -EINVAL;
405 }
msm_dp_display_enable(struct msm_dp * dp,struct drm_encoder * encoder)406 static inline int msm_dp_display_enable(struct msm_dp *dp,
407 struct drm_encoder *encoder)
408 {
409 return -EINVAL;
410 }
msm_dp_display_disable(struct msm_dp * dp,struct drm_encoder * encoder)411 static inline int msm_dp_display_disable(struct msm_dp *dp,
412 struct drm_encoder *encoder)
413 {
414 return -EINVAL;
415 }
msm_dp_display_pre_disable(struct msm_dp * dp,struct drm_encoder * encoder)416 static inline int msm_dp_display_pre_disable(struct msm_dp *dp,
417 struct drm_encoder *encoder)
418 {
419 return -EINVAL;
420 }
msm_dp_display_mode_set(struct msm_dp * dp,struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)421 static inline void msm_dp_display_mode_set(struct msm_dp *dp,
422 struct drm_encoder *encoder,
423 struct drm_display_mode *mode,
424 struct drm_display_mode *adjusted_mode)
425 {
426 }
427
msm_dp_irq_postinstall(struct msm_dp * dp_display)428 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display)
429 {
430 }
431
msm_dp_snapshot(struct msm_disp_state * disp_state,struct msm_dp * dp_display)432 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
433 {
434 }
435
msm_dp_debugfs_init(struct msm_dp * dp_display,struct drm_minor * minor)436 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,
437 struct drm_minor *minor)
438 {
439 }
440
441 #endif
442
443 void __init msm_mdp_register(void);
444 void __exit msm_mdp_unregister(void);
445 void __init msm_dpu_register(void);
446 void __exit msm_dpu_unregister(void);
447
448 #ifdef CONFIG_DEBUG_FS
449 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
450 int msm_debugfs_late_init(struct drm_device *dev);
451 int msm_rd_debugfs_init(struct drm_minor *minor);
452 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
453 __printf(3, 4)
454 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
455 const char *fmt, ...);
456 int msm_perf_debugfs_init(struct drm_minor *minor);
457 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
458 #else
msm_debugfs_late_init(struct drm_device * dev)459 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
460 __printf(3, 4)
msm_rd_dump_submit(struct msm_rd_state * rd,struct msm_gem_submit * submit,const char * fmt,...)461 static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
462 struct msm_gem_submit *submit,
463 const char *fmt, ...) {}
msm_rd_debugfs_cleanup(struct msm_drm_private * priv)464 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
msm_perf_debugfs_cleanup(struct msm_drm_private * priv)465 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
466 #endif
467
468 struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
469
470 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
471 const char *name);
472 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
473 const char *dbgname);
474 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
475 const char *dbgname, phys_addr_t *size);
476 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
477 const char *dbgname);
478 void msm_writel(u32 data, void __iomem *addr);
479 u32 msm_readl(const void __iomem *addr);
480 void msm_rmw(void __iomem *addr, u32 mask, u32 or);
481
482 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
483 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
484
align_pitch(int width,int bpp)485 static inline int align_pitch(int width, int bpp)
486 {
487 int bytespp = (bpp + 7) / 8;
488 /* adreno needs pitch aligned to 32 pixels: */
489 return bytespp * ALIGN(width, 32);
490 }
491
492 /* for the generated headers: */
493 #define INVALID_IDX(idx) ({BUG(); 0;})
494 #define fui(x) ({BUG(); 0;})
495 #define _mesa_float_to_half(x) ({BUG(); 0;})
496
497
498 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
499
500 /* for conditionally setting boolean flag(s): */
501 #define COND(bool, val) ((bool) ? (val) : 0)
502
timeout_to_jiffies(const ktime_t * timeout)503 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
504 {
505 ktime_t now = ktime_get();
506 s64 remaining_jiffies;
507
508 if (ktime_compare(*timeout, now) < 0) {
509 remaining_jiffies = 0;
510 } else {
511 ktime_t rem = ktime_sub(*timeout, now);
512 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
513 }
514
515 return clamp(remaining_jiffies, 0LL, (s64)INT_MAX);
516 }
517
518 #endif /* __MSM_DRV_H__ */
519