1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "amdgpu_amdkfd.h"
24 #include "amd_pcie.h"
25 #include "amd_shared.h"
26
27 #include "amdgpu.h"
28 #include "amdgpu_gfx.h"
29 #include "amdgpu_dma_buf.h"
30 #include <linux/module.h>
31 #include <linux/dma-buf.h>
32 #include "amdgpu_xgmi.h"
33 #include <uapi/linux/kfd_ioctl.h>
34
35 /* Total memory size in system memory and all GPU VRAM. Used to
36 * estimate worst case amount of memory to reserve for page tables
37 */
38 uint64_t amdgpu_amdkfd_total_mem_size;
39
40 static bool kfd_initialized;
41
amdgpu_amdkfd_init(void)42 int amdgpu_amdkfd_init(void)
43 {
44 struct sysinfo si;
45 int ret;
46
47 si_meminfo(&si);
48 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh;
49 amdgpu_amdkfd_total_mem_size *= si.mem_unit;
50
51 ret = kgd2kfd_init();
52 amdgpu_amdkfd_gpuvm_init_mem_limits();
53 kfd_initialized = !ret;
54
55 return ret;
56 }
57
amdgpu_amdkfd_fini(void)58 void amdgpu_amdkfd_fini(void)
59 {
60 if (kfd_initialized) {
61 kgd2kfd_exit();
62 kfd_initialized = false;
63 }
64 }
65
amdgpu_amdkfd_device_probe(struct amdgpu_device * adev)66 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
67 {
68 bool vf = amdgpu_sriov_vf(adev);
69
70 if (!kfd_initialized)
71 return;
72
73 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
74 adev->pdev, adev->asic_type, vf);
75
76 if (adev->kfd.dev)
77 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
78 }
79
80 /**
81 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
82 * setup amdkfd
83 *
84 * @adev: amdgpu_device pointer
85 * @aperture_base: output returning doorbell aperture base physical address
86 * @aperture_size: output returning doorbell aperture size in bytes
87 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
88 *
89 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
90 * takes doorbells required for its own rings and reports the setup to amdkfd.
91 * amdgpu reserved doorbells are at the start of the doorbell aperture.
92 */
amdgpu_doorbell_get_kfd_info(struct amdgpu_device * adev,phys_addr_t * aperture_base,size_t * aperture_size,size_t * start_offset)93 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
94 phys_addr_t *aperture_base,
95 size_t *aperture_size,
96 size_t *start_offset)
97 {
98 /*
99 * The first num_doorbells are used by amdgpu.
100 * amdkfd takes whatever's left in the aperture.
101 */
102 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
103 *aperture_base = adev->doorbell.base;
104 *aperture_size = adev->doorbell.size;
105 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
106 } else {
107 *aperture_base = 0;
108 *aperture_size = 0;
109 *start_offset = 0;
110 }
111 }
112
amdgpu_amdkfd_device_init(struct amdgpu_device * adev)113 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
114 {
115 int i;
116 int last_valid_bit;
117
118 if (adev->kfd.dev) {
119 struct kgd2kfd_shared_resources gpu_resources = {
120 .compute_vmid_bitmap =
121 ((1 << AMDGPU_NUM_VMID) - 1) -
122 ((1 << adev->vm_manager.first_kfd_vmid) - 1),
123 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
124 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
125 .gpuvm_size = min(adev->vm_manager.max_pfn
126 << AMDGPU_GPU_PAGE_SHIFT,
127 AMDGPU_GMC_HOLE_START),
128 .drm_render_minor = adev_to_drm(adev)->render->index,
129 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
130
131 };
132
133 /* this is going to have a few of the MSBs set that we need to
134 * clear
135 */
136 bitmap_complement(gpu_resources.cp_queue_bitmap,
137 adev->gfx.mec.queue_bitmap,
138 KGD_MAX_QUEUES);
139
140 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
141 * nbits is not compile time constant
142 */
143 last_valid_bit = 1 /* only first MEC can have compute queues */
144 * adev->gfx.mec.num_pipe_per_mec
145 * adev->gfx.mec.num_queue_per_pipe;
146 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
147 clear_bit(i, gpu_resources.cp_queue_bitmap);
148
149 amdgpu_doorbell_get_kfd_info(adev,
150 &gpu_resources.doorbell_physical_address,
151 &gpu_resources.doorbell_aperture_size,
152 &gpu_resources.doorbell_start_offset);
153
154 /* Since SOC15, BIF starts to statically use the
155 * lower 12 bits of doorbell addresses for routing
156 * based on settings in registers like
157 * SDMA0_DOORBELL_RANGE etc..
158 * In order to route a doorbell to CP engine, the lower
159 * 12 bits of its address has to be outside the range
160 * set for SDMA, VCN, and IH blocks.
161 */
162 if (adev->asic_type >= CHIP_VEGA10) {
163 gpu_resources.non_cp_doorbells_start =
164 adev->doorbell_index.first_non_cp;
165 gpu_resources.non_cp_doorbells_end =
166 adev->doorbell_index.last_non_cp;
167 }
168
169 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
170 adev_to_drm(adev), &gpu_resources);
171 }
172 }
173
amdgpu_amdkfd_device_fini_sw(struct amdgpu_device * adev)174 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev)
175 {
176 if (adev->kfd.dev) {
177 kgd2kfd_device_exit(adev->kfd.dev);
178 adev->kfd.dev = NULL;
179 }
180 }
181
amdgpu_amdkfd_interrupt(struct amdgpu_device * adev,const void * ih_ring_entry)182 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
183 const void *ih_ring_entry)
184 {
185 if (adev->kfd.dev)
186 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
187 }
188
amdgpu_amdkfd_suspend(struct amdgpu_device * adev,bool run_pm)189 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
190 {
191 if (adev->kfd.dev)
192 kgd2kfd_suspend(adev->kfd.dev, run_pm);
193 }
194
amdgpu_amdkfd_resume_iommu(struct amdgpu_device * adev)195 int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev)
196 {
197 int r = 0;
198
199 if (adev->kfd.dev)
200 r = kgd2kfd_resume_iommu(adev->kfd.dev);
201
202 return r;
203 }
204
amdgpu_amdkfd_resume(struct amdgpu_device * adev,bool run_pm)205 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
206 {
207 int r = 0;
208
209 if (adev->kfd.dev)
210 r = kgd2kfd_resume(adev->kfd.dev, run_pm);
211
212 return r;
213 }
214
amdgpu_amdkfd_pre_reset(struct amdgpu_device * adev)215 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
216 {
217 int r = 0;
218
219 if (adev->kfd.dev)
220 r = kgd2kfd_pre_reset(adev->kfd.dev);
221
222 return r;
223 }
224
amdgpu_amdkfd_post_reset(struct amdgpu_device * adev)225 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
226 {
227 int r = 0;
228
229 if (adev->kfd.dev)
230 r = kgd2kfd_post_reset(adev->kfd.dev);
231
232 return r;
233 }
234
amdgpu_amdkfd_gpu_reset(struct kgd_dev * kgd)235 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
236 {
237 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
238
239 if (amdgpu_device_should_recover_gpu(adev))
240 amdgpu_device_gpu_recover(adev, NULL);
241 }
242
amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev * kgd,size_t size,void ** mem_obj,uint64_t * gpu_addr,void ** cpu_ptr,bool cp_mqd_gfx9)243 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
244 void **mem_obj, uint64_t *gpu_addr,
245 void **cpu_ptr, bool cp_mqd_gfx9)
246 {
247 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
248 struct amdgpu_bo *bo = NULL;
249 struct amdgpu_bo_param bp;
250 int r;
251 void *cpu_ptr_tmp = NULL;
252
253 memset(&bp, 0, sizeof(bp));
254 bp.size = size;
255 bp.byte_align = PAGE_SIZE;
256 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
257 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
258 bp.type = ttm_bo_type_kernel;
259 bp.resv = NULL;
260 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
261
262 if (cp_mqd_gfx9)
263 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
264
265 r = amdgpu_bo_create(adev, &bp, &bo);
266 if (r) {
267 dev_err(adev->dev,
268 "failed to allocate BO for amdkfd (%d)\n", r);
269 return r;
270 }
271
272 /* map the buffer */
273 r = amdgpu_bo_reserve(bo, true);
274 if (r) {
275 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
276 goto allocate_mem_reserve_bo_failed;
277 }
278
279 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
280 if (r) {
281 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
282 goto allocate_mem_pin_bo_failed;
283 }
284
285 r = amdgpu_ttm_alloc_gart(&bo->tbo);
286 if (r) {
287 dev_err(adev->dev, "%p bind failed\n", bo);
288 goto allocate_mem_kmap_bo_failed;
289 }
290
291 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
292 if (r) {
293 dev_err(adev->dev,
294 "(%d) failed to map bo to kernel for amdkfd\n", r);
295 goto allocate_mem_kmap_bo_failed;
296 }
297
298 *mem_obj = bo;
299 *gpu_addr = amdgpu_bo_gpu_offset(bo);
300 *cpu_ptr = cpu_ptr_tmp;
301
302 amdgpu_bo_unreserve(bo);
303
304 return 0;
305
306 allocate_mem_kmap_bo_failed:
307 amdgpu_bo_unpin(bo);
308 allocate_mem_pin_bo_failed:
309 amdgpu_bo_unreserve(bo);
310 allocate_mem_reserve_bo_failed:
311 amdgpu_bo_unref(&bo);
312
313 return r;
314 }
315
amdgpu_amdkfd_free_gtt_mem(struct kgd_dev * kgd,void * mem_obj)316 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
317 {
318 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
319
320 amdgpu_bo_reserve(bo, true);
321 amdgpu_bo_kunmap(bo);
322 amdgpu_bo_unpin(bo);
323 amdgpu_bo_unreserve(bo);
324 amdgpu_bo_unref(&(bo));
325 }
326
amdgpu_amdkfd_alloc_gws(struct kgd_dev * kgd,size_t size,void ** mem_obj)327 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size,
328 void **mem_obj)
329 {
330 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
331 struct amdgpu_bo *bo = NULL;
332 struct amdgpu_bo_user *ubo;
333 struct amdgpu_bo_param bp;
334 int r;
335
336 memset(&bp, 0, sizeof(bp));
337 bp.size = size;
338 bp.byte_align = 1;
339 bp.domain = AMDGPU_GEM_DOMAIN_GWS;
340 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
341 bp.type = ttm_bo_type_device;
342 bp.resv = NULL;
343 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
344
345 r = amdgpu_bo_create_user(adev, &bp, &ubo);
346 if (r) {
347 dev_err(adev->dev,
348 "failed to allocate gws BO for amdkfd (%d)\n", r);
349 return r;
350 }
351
352 bo = &ubo->bo;
353 *mem_obj = bo;
354 return 0;
355 }
356
amdgpu_amdkfd_free_gws(struct kgd_dev * kgd,void * mem_obj)357 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj)
358 {
359 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
360
361 amdgpu_bo_unref(&bo);
362 }
363
amdgpu_amdkfd_get_fw_version(struct kgd_dev * kgd,enum kgd_engine_type type)364 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
365 enum kgd_engine_type type)
366 {
367 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
368
369 switch (type) {
370 case KGD_ENGINE_PFP:
371 return adev->gfx.pfp_fw_version;
372
373 case KGD_ENGINE_ME:
374 return adev->gfx.me_fw_version;
375
376 case KGD_ENGINE_CE:
377 return adev->gfx.ce_fw_version;
378
379 case KGD_ENGINE_MEC1:
380 return adev->gfx.mec_fw_version;
381
382 case KGD_ENGINE_MEC2:
383 return adev->gfx.mec2_fw_version;
384
385 case KGD_ENGINE_RLC:
386 return adev->gfx.rlc_fw_version;
387
388 case KGD_ENGINE_SDMA1:
389 return adev->sdma.instance[0].fw_version;
390
391 case KGD_ENGINE_SDMA2:
392 return adev->sdma.instance[1].fw_version;
393
394 default:
395 return 0;
396 }
397
398 return 0;
399 }
400
amdgpu_amdkfd_get_local_mem_info(struct kgd_dev * kgd,struct kfd_local_mem_info * mem_info)401 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
402 struct kfd_local_mem_info *mem_info)
403 {
404 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
405
406 memset(mem_info, 0, sizeof(*mem_info));
407
408 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
409 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
410 adev->gmc.visible_vram_size;
411
412 mem_info->vram_width = adev->gmc.vram_width;
413
414 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
415 &adev->gmc.aper_base,
416 mem_info->local_mem_size_public,
417 mem_info->local_mem_size_private);
418
419 if (amdgpu_sriov_vf(adev))
420 mem_info->mem_clk_max = adev->clock.default_mclk / 100;
421 else if (adev->pm.dpm_enabled) {
422 if (amdgpu_emu_mode == 1)
423 mem_info->mem_clk_max = 0;
424 else
425 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
426 } else
427 mem_info->mem_clk_max = 100;
428 }
429
amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev * kgd)430 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd)
431 {
432 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
433
434 if (adev->gfx.funcs->get_gpu_clock_counter)
435 return adev->gfx.funcs->get_gpu_clock_counter(adev);
436 return 0;
437 }
438
amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev * kgd)439 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
440 {
441 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
442
443 /* the sclk is in quantas of 10kHz */
444 if (amdgpu_sriov_vf(adev))
445 return adev->clock.default_sclk / 100;
446 else if (adev->pm.dpm_enabled)
447 return amdgpu_dpm_get_sclk(adev, false) / 100;
448 else
449 return 100;
450 }
451
amdgpu_amdkfd_get_cu_info(struct kgd_dev * kgd,struct kfd_cu_info * cu_info)452 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
453 {
454 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
455 struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
456
457 memset(cu_info, 0, sizeof(*cu_info));
458 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
459 return;
460
461 cu_info->cu_active_number = acu_info.number;
462 cu_info->cu_ao_mask = acu_info.ao_cu_mask;
463 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
464 sizeof(acu_info.bitmap));
465 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
466 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
467 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
468 cu_info->simd_per_cu = acu_info.simd_per_cu;
469 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
470 cu_info->wave_front_size = acu_info.wave_front_size;
471 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
472 cu_info->lds_size = acu_info.lds_size;
473 }
474
amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev * kgd,int dma_buf_fd,struct kgd_dev ** dma_buf_kgd,uint64_t * bo_size,void * metadata_buffer,size_t buffer_size,uint32_t * metadata_size,uint32_t * flags)475 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
476 struct kgd_dev **dma_buf_kgd,
477 uint64_t *bo_size, void *metadata_buffer,
478 size_t buffer_size, uint32_t *metadata_size,
479 uint32_t *flags)
480 {
481 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
482 struct dma_buf *dma_buf;
483 struct drm_gem_object *obj;
484 struct amdgpu_bo *bo;
485 uint64_t metadata_flags;
486 int r = -EINVAL;
487
488 dma_buf = dma_buf_get(dma_buf_fd);
489 if (IS_ERR(dma_buf))
490 return PTR_ERR(dma_buf);
491
492 if (dma_buf->ops != &amdgpu_dmabuf_ops)
493 /* Can't handle non-graphics buffers */
494 goto out_put;
495
496 obj = dma_buf->priv;
497 if (obj->dev->driver != adev_to_drm(adev)->driver)
498 /* Can't handle buffers from different drivers */
499 goto out_put;
500
501 adev = drm_to_adev(obj->dev);
502 bo = gem_to_amdgpu_bo(obj);
503 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
504 AMDGPU_GEM_DOMAIN_GTT)))
505 /* Only VRAM and GTT BOs are supported */
506 goto out_put;
507
508 r = 0;
509 if (dma_buf_kgd)
510 *dma_buf_kgd = (struct kgd_dev *)adev;
511 if (bo_size)
512 *bo_size = amdgpu_bo_size(bo);
513 if (metadata_buffer)
514 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
515 metadata_size, &metadata_flags);
516 if (flags) {
517 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
518 KFD_IOC_ALLOC_MEM_FLAGS_VRAM
519 : KFD_IOC_ALLOC_MEM_FLAGS_GTT;
520
521 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
522 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
523 }
524
525 out_put:
526 dma_buf_put(dma_buf);
527 return r;
528 }
529
amdgpu_amdkfd_get_vram_usage(struct kgd_dev * kgd)530 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
531 {
532 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
533 struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
534
535 return amdgpu_vram_mgr_usage(vram_man);
536 }
537
amdgpu_amdkfd_get_hive_id(struct kgd_dev * kgd)538 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
539 {
540 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
541
542 return adev->gmc.xgmi.hive_id;
543 }
544
amdgpu_amdkfd_get_unique_id(struct kgd_dev * kgd)545 uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd)
546 {
547 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
548
549 return adev->unique_id;
550 }
551
amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev * dst,struct kgd_dev * src)552 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src)
553 {
554 struct amdgpu_device *peer_adev = (struct amdgpu_device *)src;
555 struct amdgpu_device *adev = (struct amdgpu_device *)dst;
556 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);
557
558 if (ret < 0) {
559 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n",
560 adev->gmc.xgmi.physical_node_id,
561 peer_adev->gmc.xgmi.physical_node_id, ret);
562 ret = 0;
563 }
564 return (uint8_t)ret;
565 }
566
amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct kgd_dev * dst,struct kgd_dev * src,bool is_min)567 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct kgd_dev *dst, struct kgd_dev *src, bool is_min)
568 {
569 struct amdgpu_device *adev = (struct amdgpu_device *)dst, *peer_adev;
570 int num_links;
571
572 if (adev->asic_type != CHIP_ALDEBARAN)
573 return 0;
574
575 if (src)
576 peer_adev = (struct amdgpu_device *)src;
577
578 /* num links returns 0 for indirect peers since indirect route is unknown. */
579 num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev);
580 if (num_links < 0) {
581 DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n",
582 adev->gmc.xgmi.physical_node_id,
583 peer_adev->gmc.xgmi.physical_node_id, num_links);
584 num_links = 0;
585 }
586
587 /* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */
588 return (num_links * 16 * 25000)/BITS_PER_BYTE;
589 }
590
amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct kgd_dev * dev,bool is_min)591 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct kgd_dev *dev, bool is_min)
592 {
593 struct amdgpu_device *adev = (struct amdgpu_device *)dev;
594 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) :
595 fls(adev->pm.pcie_mlw_mask)) - 1;
596 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask &
597 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) :
598 fls(adev->pm.pcie_gen_mask &
599 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1;
600 uint32_t num_lanes_mask = 1 << num_lanes_shift;
601 uint32_t gen_speed_mask = 1 << gen_speed_shift;
602 int num_lanes_factor = 0, gen_speed_mbits_factor = 0;
603
604 switch (num_lanes_mask) {
605 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
606 num_lanes_factor = 1;
607 break;
608 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
609 num_lanes_factor = 2;
610 break;
611 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
612 num_lanes_factor = 4;
613 break;
614 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
615 num_lanes_factor = 8;
616 break;
617 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
618 num_lanes_factor = 12;
619 break;
620 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
621 num_lanes_factor = 16;
622 break;
623 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
624 num_lanes_factor = 32;
625 break;
626 }
627
628 switch (gen_speed_mask) {
629 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1:
630 gen_speed_mbits_factor = 2500;
631 break;
632 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2:
633 gen_speed_mbits_factor = 5000;
634 break;
635 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3:
636 gen_speed_mbits_factor = 8000;
637 break;
638 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4:
639 gen_speed_mbits_factor = 16000;
640 break;
641 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5:
642 gen_speed_mbits_factor = 32000;
643 break;
644 }
645
646 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE;
647 }
648
amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev * kgd)649 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)
650 {
651 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
652
653 return adev->rmmio_remap.bus_addr;
654 }
655
amdgpu_amdkfd_get_num_gws(struct kgd_dev * kgd)656 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd)
657 {
658 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
659
660 return adev->gds.gws_size;
661 }
662
amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev * kgd)663 uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd)
664 {
665 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
666
667 return adev->rev_id;
668 }
669
amdgpu_amdkfd_get_noretry(struct kgd_dev * kgd)670 int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd)
671 {
672 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
673
674 return adev->gmc.noretry;
675 }
676
amdgpu_amdkfd_submit_ib(struct kgd_dev * kgd,enum kgd_engine_type engine,uint32_t vmid,uint64_t gpu_addr,uint32_t * ib_cmd,uint32_t ib_len)677 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
678 uint32_t vmid, uint64_t gpu_addr,
679 uint32_t *ib_cmd, uint32_t ib_len)
680 {
681 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
682 struct amdgpu_job *job;
683 struct amdgpu_ib *ib;
684 struct amdgpu_ring *ring;
685 struct dma_fence *f = NULL;
686 int ret;
687
688 switch (engine) {
689 case KGD_ENGINE_MEC1:
690 ring = &adev->gfx.compute_ring[0];
691 break;
692 case KGD_ENGINE_SDMA1:
693 ring = &adev->sdma.instance[0].ring;
694 break;
695 case KGD_ENGINE_SDMA2:
696 ring = &adev->sdma.instance[1].ring;
697 break;
698 default:
699 pr_err("Invalid engine in IB submission: %d\n", engine);
700 ret = -EINVAL;
701 goto err;
702 }
703
704 ret = amdgpu_job_alloc(adev, 1, &job, NULL);
705 if (ret)
706 goto err;
707
708 ib = &job->ibs[0];
709 memset(ib, 0, sizeof(struct amdgpu_ib));
710
711 ib->gpu_addr = gpu_addr;
712 ib->ptr = ib_cmd;
713 ib->length_dw = ib_len;
714 /* This works for NO_HWS. TODO: need to handle without knowing VMID */
715 job->vmid = vmid;
716
717 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
718
719 if (ret) {
720 DRM_ERROR("amdgpu: failed to schedule IB.\n");
721 goto err_ib_sched;
722 }
723
724 ret = dma_fence_wait(f, false);
725
726 err_ib_sched:
727 amdgpu_job_free(job);
728 err:
729 return ret;
730 }
731
amdgpu_amdkfd_set_compute_idle(struct kgd_dev * kgd,bool idle)732 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
733 {
734 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
735
736 amdgpu_dpm_switch_power_profile(adev,
737 PP_SMC_POWER_PROFILE_COMPUTE,
738 !idle);
739 }
740
amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device * adev,u32 vmid)741 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
742 {
743 if (adev->kfd.dev)
744 return vmid >= adev->vm_manager.first_kfd_vmid;
745
746 return false;
747 }
748
amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev * kgd,uint16_t vmid)749 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid)
750 {
751 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
752
753 if (adev->family == AMDGPU_FAMILY_AI) {
754 int i;
755
756 for (i = 0; i < adev->num_vmhubs; i++)
757 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
758 } else {
759 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
760 }
761
762 return 0;
763 }
764
amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev * kgd,uint16_t pasid,enum TLB_FLUSH_TYPE flush_type)765 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid,
766 enum TLB_FLUSH_TYPE flush_type)
767 {
768 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
769 bool all_hub = false;
770
771 if (adev->family == AMDGPU_FAMILY_AI ||
772 adev->family == AMDGPU_FAMILY_RV)
773 all_hub = true;
774
775 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
776 }
777
amdgpu_amdkfd_have_atomics_support(struct kgd_dev * kgd)778 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd)
779 {
780 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
781
782 return adev->have_atomics_support;
783 }
784