1 /*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <drm/amdgpu_drm.h>
26 #include <drm/drm_drv.h>
27 #include <drm/drm_gem.h>
28 #include <drm/drm_vblank.h>
29 #include <drm/drm_managed.h>
30 #include "amdgpu_drv.h"
31
32 #include <drm/drm_pciids.h>
33 #include <linux/console.h>
34 #include <linux/module.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_probe_helper.h>
38 #include <linux/mmu_notifier.h>
39 #include <linux/suspend.h>
40 #include <linux/fb.h>
41
42 #include "amdgpu.h"
43 #include "amdgpu_irq.h"
44 #include "amdgpu_dma_buf.h"
45 #include "amdgpu_sched.h"
46 #include "amdgpu_fdinfo.h"
47 #include "amdgpu_amdkfd.h"
48
49 #include "amdgpu_ras.h"
50 #include "amdgpu_xgmi.h"
51 #include "amdgpu_reset.h"
52
53 /*
54 * KMS wrapper.
55 * - 3.0.0 - initial driver
56 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
57 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
58 * at the end of IBs.
59 * - 3.3.0 - Add VM support for UVD on supported hardware.
60 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
61 * - 3.5.0 - Add support for new UVD_NO_OP register.
62 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
63 * - 3.7.0 - Add support for VCE clock list packet
64 * - 3.8.0 - Add support raster config init in the kernel
65 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
66 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
67 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
68 * - 3.12.0 - Add query for double offchip LDS buffers
69 * - 3.13.0 - Add PRT support
70 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
71 * - 3.15.0 - Export more gpu info for gfx9
72 * - 3.16.0 - Add reserved vmid support
73 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
74 * - 3.18.0 - Export gpu always on cu bitmap
75 * - 3.19.0 - Add support for UVD MJPEG decode
76 * - 3.20.0 - Add support for local BOs
77 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
78 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
79 * - 3.23.0 - Add query for VRAM lost counter
80 * - 3.24.0 - Add high priority compute support for gfx9
81 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
82 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
83 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
84 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
85 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
86 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
87 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
88 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
89 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
90 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
91 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
92 * - 3.36.0 - Allow reading more status registers on si/cik
93 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
94 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
95 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
96 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
97 * - 3.41.0 - Add video codec query
98 * - 3.42.0 - Add 16bpc fixed point display support
99 */
100 #define KMS_DRIVER_MAJOR 3
101 #define KMS_DRIVER_MINOR 42
102 #define KMS_DRIVER_PATCHLEVEL 0
103
104 int amdgpu_vram_limit;
105 int amdgpu_vis_vram_limit;
106 int amdgpu_gart_size = -1; /* auto */
107 int amdgpu_gtt_size = -1; /* auto */
108 int amdgpu_moverate = -1; /* auto */
109 int amdgpu_benchmarking;
110 int amdgpu_testing;
111 int amdgpu_audio = -1;
112 int amdgpu_disp_priority;
113 int amdgpu_hw_i2c;
114 int amdgpu_pcie_gen2 = -1;
115 int amdgpu_msi = -1;
116 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
117 int amdgpu_dpm = -1;
118 int amdgpu_fw_load_type = -1;
119 int amdgpu_aspm = -1;
120 int amdgpu_runtime_pm = -1;
121 uint amdgpu_ip_block_mask = 0xffffffff;
122 int amdgpu_bapm = -1;
123 int amdgpu_deep_color;
124 int amdgpu_vm_size = -1;
125 int amdgpu_vm_fragment_size = -1;
126 int amdgpu_vm_block_size = -1;
127 int amdgpu_vm_fault_stop;
128 int amdgpu_vm_debug;
129 int amdgpu_vm_update_mode = -1;
130 int amdgpu_exp_hw_support;
131 int amdgpu_dc = -1;
132 int amdgpu_sched_jobs = 32;
133 int amdgpu_sched_hw_submission = 2;
134 uint amdgpu_pcie_gen_cap;
135 uint amdgpu_pcie_lane_cap;
136 uint amdgpu_cg_mask = 0xffffffff;
137 uint amdgpu_pg_mask = 0xffffffff;
138 uint amdgpu_sdma_phase_quantum = 32;
139 char *amdgpu_disable_cu = NULL;
140 char *amdgpu_virtual_display = NULL;
141
142 /*
143 * OverDrive(bit 14) disabled by default
144 * GFX DCS(bit 19) disabled by default
145 */
146 uint amdgpu_pp_feature_mask = 0xfff7bfff;
147 uint amdgpu_force_long_training;
148 int amdgpu_job_hang_limit;
149 int amdgpu_lbpw = -1;
150 int amdgpu_compute_multipipe = -1;
151 int amdgpu_gpu_recovery = -1; /* auto */
152 int amdgpu_emu_mode;
153 uint amdgpu_smu_memory_pool_size;
154 int amdgpu_smu_pptable_id = -1;
155 /*
156 * FBC (bit 0) disabled by default
157 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
158 * - With this, for multiple monitors in sync(e.g. with the same model),
159 * mclk switching will be allowed. And the mclk will be not foced to the
160 * highest. That helps saving some idle power.
161 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
162 * PSR (bit 3) disabled by default
163 * EDP NO POWER SEQUENCING (bit 4) disabled by default
164 */
165 uint amdgpu_dc_feature_mask = 2;
166 uint amdgpu_dc_debug_mask;
167 int amdgpu_async_gfx_ring = 1;
168 int amdgpu_mcbp;
169 int amdgpu_discovery = -1;
170 int amdgpu_mes;
171 int amdgpu_noretry = -1;
172 int amdgpu_force_asic_type = -1;
173 int amdgpu_tmz = -1; /* auto */
174 uint amdgpu_freesync_vid_mode;
175 int amdgpu_reset_method = -1; /* auto */
176 int amdgpu_num_kcq = -1;
177 int amdgpu_smartshift_bias;
178
179 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
180
181 struct amdgpu_mgpu_info mgpu_info = {
182 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
183 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
184 mgpu_info.delayed_reset_work,
185 amdgpu_drv_delayed_reset_work_handler, 0),
186 };
187 int amdgpu_ras_enable = -1;
188 uint amdgpu_ras_mask = 0xffffffff;
189 int amdgpu_bad_page_threshold = -1;
190 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
191 .timeout_fatal_disable = false,
192 .period = 0x0, /* default to 0x0 (timeout disable) */
193 };
194
195 /**
196 * DOC: vramlimit (int)
197 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
198 */
199 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
200 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
201
202 /**
203 * DOC: vis_vramlimit (int)
204 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
205 */
206 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
207 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
208
209 /**
210 * DOC: gartsize (uint)
211 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
212 */
213 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
214 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
215
216 /**
217 * DOC: gttsize (int)
218 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
219 * otherwise 3/4 RAM size).
220 */
221 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
222 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
223
224 /**
225 * DOC: moverate (int)
226 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
227 */
228 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
229 module_param_named(moverate, amdgpu_moverate, int, 0600);
230
231 /**
232 * DOC: benchmark (int)
233 * Run benchmarks. The default is 0 (Skip benchmarks).
234 */
235 MODULE_PARM_DESC(benchmark, "Run benchmark");
236 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
237
238 /**
239 * DOC: test (int)
240 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
241 */
242 MODULE_PARM_DESC(test, "Run tests");
243 module_param_named(test, amdgpu_testing, int, 0444);
244
245 /**
246 * DOC: audio (int)
247 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
248 */
249 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
250 module_param_named(audio, amdgpu_audio, int, 0444);
251
252 /**
253 * DOC: disp_priority (int)
254 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
255 */
256 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
257 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
258
259 /**
260 * DOC: hw_i2c (int)
261 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
262 */
263 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
264 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
265
266 /**
267 * DOC: pcie_gen2 (int)
268 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
269 */
270 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
271 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
272
273 /**
274 * DOC: msi (int)
275 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
276 */
277 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
278 module_param_named(msi, amdgpu_msi, int, 0444);
279
280 /**
281 * DOC: lockup_timeout (string)
282 * Set GPU scheduler timeout value in ms.
283 *
284 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
285 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
286 * to the default timeout.
287 *
288 * - With one value specified, the setting will apply to all non-compute jobs.
289 * - With multiple values specified, the first one will be for GFX.
290 * The second one is for Compute. The third and fourth ones are
291 * for SDMA and Video.
292 *
293 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
294 * jobs is 10000. The timeout for compute is 60000.
295 */
296 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
297 "for passthrough or sriov, 10000 for all jobs."
298 " 0: keep default value. negative: infinity timeout), "
299 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
300 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
301 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
302
303 /**
304 * DOC: dpm (int)
305 * Override for dynamic power management setting
306 * (0 = disable, 1 = enable)
307 * The default is -1 (auto).
308 */
309 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
310 module_param_named(dpm, amdgpu_dpm, int, 0444);
311
312 /**
313 * DOC: fw_load_type (int)
314 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto).
315 */
316 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
317 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
318
319 /**
320 * DOC: aspm (int)
321 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
322 */
323 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
324 module_param_named(aspm, amdgpu_aspm, int, 0444);
325
326 /**
327 * DOC: runpm (int)
328 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down
329 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.
330 */
331 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)");
332 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
333
334 /**
335 * DOC: ip_block_mask (uint)
336 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
337 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
338 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
339 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
340 */
341 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
342 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
343
344 /**
345 * DOC: bapm (int)
346 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
347 * The default -1 (auto, enabled)
348 */
349 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
350 module_param_named(bapm, amdgpu_bapm, int, 0444);
351
352 /**
353 * DOC: deep_color (int)
354 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
355 */
356 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
357 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
358
359 /**
360 * DOC: vm_size (int)
361 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
362 */
363 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
364 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
365
366 /**
367 * DOC: vm_fragment_size (int)
368 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
369 */
370 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
371 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
372
373 /**
374 * DOC: vm_block_size (int)
375 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
376 */
377 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
378 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
379
380 /**
381 * DOC: vm_fault_stop (int)
382 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
383 */
384 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
385 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
386
387 /**
388 * DOC: vm_debug (int)
389 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
390 */
391 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
392 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
393
394 /**
395 * DOC: vm_update_mode (int)
396 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
397 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
398 */
399 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
400 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
401
402 /**
403 * DOC: exp_hw_support (int)
404 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
405 */
406 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
407 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
408
409 /**
410 * DOC: dc (int)
411 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
412 */
413 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
414 module_param_named(dc, amdgpu_dc, int, 0444);
415
416 /**
417 * DOC: sched_jobs (int)
418 * Override the max number of jobs supported in the sw queue. The default is 32.
419 */
420 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
421 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
422
423 /**
424 * DOC: sched_hw_submission (int)
425 * Override the max number of HW submissions. The default is 2.
426 */
427 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
428 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
429
430 /**
431 * DOC: ppfeaturemask (hexint)
432 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
433 * The default is the current set of stable power features.
434 */
435 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
436 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
437
438 /**
439 * DOC: forcelongtraining (uint)
440 * Force long memory training in resume.
441 * The default is zero, indicates short training in resume.
442 */
443 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
444 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
445
446 /**
447 * DOC: pcie_gen_cap (uint)
448 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
449 * The default is 0 (automatic for each asic).
450 */
451 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
452 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
453
454 /**
455 * DOC: pcie_lane_cap (uint)
456 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
457 * The default is 0 (automatic for each asic).
458 */
459 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
460 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
461
462 /**
463 * DOC: cg_mask (uint)
464 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
465 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
466 */
467 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
468 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
469
470 /**
471 * DOC: pg_mask (uint)
472 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
473 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
474 */
475 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
476 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
477
478 /**
479 * DOC: sdma_phase_quantum (uint)
480 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
481 */
482 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
483 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
484
485 /**
486 * DOC: disable_cu (charp)
487 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
488 */
489 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
490 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
491
492 /**
493 * DOC: virtual_display (charp)
494 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
495 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
496 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
497 * device at 26:00.0. The default is NULL.
498 */
499 MODULE_PARM_DESC(virtual_display,
500 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
501 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
502
503 /**
504 * DOC: job_hang_limit (int)
505 * Set how much time allow a job hang and not drop it. The default is 0.
506 */
507 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
508 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
509
510 /**
511 * DOC: lbpw (int)
512 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
513 */
514 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
515 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
516
517 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
518 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
519
520 /**
521 * DOC: gpu_recovery (int)
522 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
523 */
524 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)");
525 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
526
527 /**
528 * DOC: emu_mode (int)
529 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
530 */
531 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
532 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
533
534 /**
535 * DOC: ras_enable (int)
536 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
537 */
538 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
539 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
540
541 /**
542 * DOC: ras_mask (uint)
543 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
544 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
545 */
546 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
547 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
548
549 /**
550 * DOC: timeout_fatal_disable (bool)
551 * Disable Watchdog timeout fatal error event
552 */
553 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
554 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
555
556 /**
557 * DOC: timeout_period (uint)
558 * Modify the watchdog timeout max_cycles as (1 << period)
559 */
560 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
561 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
562
563 /**
564 * DOC: si_support (int)
565 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
566 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
567 * otherwise using amdgpu driver.
568 */
569 #ifdef CONFIG_DRM_AMDGPU_SI
570
571 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
572 int amdgpu_si_support = 0;
573 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
574 #else
575 int amdgpu_si_support = 1;
576 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
577 #endif
578
579 module_param_named(si_support, amdgpu_si_support, int, 0444);
580 #endif
581
582 /**
583 * DOC: cik_support (int)
584 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
585 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
586 * otherwise using amdgpu driver.
587 */
588 #ifdef CONFIG_DRM_AMDGPU_CIK
589
590 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
591 int amdgpu_cik_support = 0;
592 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
593 #else
594 int amdgpu_cik_support = 1;
595 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
596 #endif
597
598 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
599 #endif
600
601 /**
602 * DOC: smu_memory_pool_size (uint)
603 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
604 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
605 */
606 MODULE_PARM_DESC(smu_memory_pool_size,
607 "reserve gtt for smu debug usage, 0 = disable,"
608 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
609 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
610
611 /**
612 * DOC: async_gfx_ring (int)
613 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
614 */
615 MODULE_PARM_DESC(async_gfx_ring,
616 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
617 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
618
619 /**
620 * DOC: mcbp (int)
621 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
622 */
623 MODULE_PARM_DESC(mcbp,
624 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
625 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
626
627 /**
628 * DOC: discovery (int)
629 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
630 * (-1 = auto (default), 0 = disabled, 1 = enabled)
631 */
632 MODULE_PARM_DESC(discovery,
633 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
634 module_param_named(discovery, amdgpu_discovery, int, 0444);
635
636 /**
637 * DOC: mes (int)
638 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
639 * (0 = disabled (default), 1 = enabled)
640 */
641 MODULE_PARM_DESC(mes,
642 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
643 module_param_named(mes, amdgpu_mes, int, 0444);
644
645 /**
646 * DOC: noretry (int)
647 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
648 * do not support per-process XNACK this also disables retry page faults.
649 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
650 */
651 MODULE_PARM_DESC(noretry,
652 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
653 module_param_named(noretry, amdgpu_noretry, int, 0644);
654
655 /**
656 * DOC: force_asic_type (int)
657 * A non negative value used to specify the asic type for all supported GPUs.
658 */
659 MODULE_PARM_DESC(force_asic_type,
660 "A non negative value used to specify the asic type for all supported GPUs");
661 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
662
663
664
665 #ifdef CONFIG_HSA_AMD
666 /**
667 * DOC: sched_policy (int)
668 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
669 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
670 * assigns queues to HQDs.
671 */
672 int sched_policy = KFD_SCHED_POLICY_HWS;
673 module_param(sched_policy, int, 0444);
674 MODULE_PARM_DESC(sched_policy,
675 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
676
677 /**
678 * DOC: hws_max_conc_proc (int)
679 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
680 * number of VMIDs assigned to the HWS, which is also the default.
681 */
682 int hws_max_conc_proc = -1;
683 module_param(hws_max_conc_proc, int, 0444);
684 MODULE_PARM_DESC(hws_max_conc_proc,
685 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
686
687 /**
688 * DOC: cwsr_enable (int)
689 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
690 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
691 * disables it.
692 */
693 int cwsr_enable = 1;
694 module_param(cwsr_enable, int, 0444);
695 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
696
697 /**
698 * DOC: max_num_of_queues_per_device (int)
699 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
700 * is 4096.
701 */
702 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
703 module_param(max_num_of_queues_per_device, int, 0444);
704 MODULE_PARM_DESC(max_num_of_queues_per_device,
705 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
706
707 /**
708 * DOC: send_sigterm (int)
709 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
710 * but just print errors on dmesg. Setting 1 enables sending sigterm.
711 */
712 int send_sigterm;
713 module_param(send_sigterm, int, 0444);
714 MODULE_PARM_DESC(send_sigterm,
715 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
716
717 /**
718 * DOC: debug_largebar (int)
719 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
720 * system. This limits the VRAM size reported to ROCm applications to the visible
721 * size, usually 256MB.
722 * Default value is 0, diabled.
723 */
724 int debug_largebar;
725 module_param(debug_largebar, int, 0444);
726 MODULE_PARM_DESC(debug_largebar,
727 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
728
729 /**
730 * DOC: ignore_crat (int)
731 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
732 * table to get information about AMD APUs. This option can serve as a workaround on
733 * systems with a broken CRAT table.
734 *
735 * Default is auto (according to asic type, iommu_v2, and crat table, to decide
736 * whehter use CRAT)
737 */
738 int ignore_crat;
739 module_param(ignore_crat, int, 0444);
740 MODULE_PARM_DESC(ignore_crat,
741 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
742
743 /**
744 * DOC: halt_if_hws_hang (int)
745 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
746 * Setting 1 enables halt on hang.
747 */
748 int halt_if_hws_hang;
749 module_param(halt_if_hws_hang, int, 0644);
750 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
751
752 /**
753 * DOC: hws_gws_support(bool)
754 * Assume that HWS supports GWS barriers regardless of what firmware version
755 * check says. Default value: false (rely on MEC2 firmware version check).
756 */
757 bool hws_gws_support;
758 module_param(hws_gws_support, bool, 0444);
759 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
760
761 /**
762 * DOC: queue_preemption_timeout_ms (int)
763 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
764 */
765 int queue_preemption_timeout_ms = 9000;
766 module_param(queue_preemption_timeout_ms, int, 0644);
767 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
768
769 /**
770 * DOC: debug_evictions(bool)
771 * Enable extra debug messages to help determine the cause of evictions
772 */
773 bool debug_evictions;
774 module_param(debug_evictions, bool, 0644);
775 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
776
777 /**
778 * DOC: no_system_mem_limit(bool)
779 * Disable system memory limit, to support multiple process shared memory
780 */
781 bool no_system_mem_limit;
782 module_param(no_system_mem_limit, bool, 0644);
783 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
784
785 /**
786 * DOC: no_queue_eviction_on_vm_fault (int)
787 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
788 */
789 int amdgpu_no_queue_eviction_on_vm_fault = 0;
790 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
791 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
792 #endif
793
794 /**
795 * DOC: dcfeaturemask (uint)
796 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
797 * The default is the current set of stable display features.
798 */
799 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
800 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
801
802 /**
803 * DOC: dcdebugmask (uint)
804 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
805 */
806 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
807 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
808
809 /**
810 * DOC: abmlevel (uint)
811 * Override the default ABM (Adaptive Backlight Management) level used for DC
812 * enabled hardware. Requires DMCU to be supported and loaded.
813 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
814 * default. Values 1-4 control the maximum allowable brightness reduction via
815 * the ABM algorithm, with 1 being the least reduction and 4 being the most
816 * reduction.
817 *
818 * Defaults to 0, or disabled. Userspace can still override this level later
819 * after boot.
820 */
821 uint amdgpu_dm_abm_level;
822 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
823 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
824
825 int amdgpu_backlight = -1;
826 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
827 module_param_named(backlight, amdgpu_backlight, bint, 0444);
828
829 /**
830 * DOC: tmz (int)
831 * Trusted Memory Zone (TMZ) is a method to protect data being written
832 * to or read from memory.
833 *
834 * The default value: 0 (off). TODO: change to auto till it is completed.
835 */
836 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
837 module_param_named(tmz, amdgpu_tmz, int, 0444);
838
839 /**
840 * DOC: freesync_video (uint)
841 * Enable the optimization to adjust front porch timing to achieve seamless
842 * mode change experience when setting a freesync supported mode for which full
843 * modeset is not needed.
844 *
845 * The Display Core will add a set of modes derived from the base FreeSync
846 * video mode into the corresponding connector's mode list based on commonly
847 * used refresh rates and VRR range of the connected display, when users enable
848 * this feature. From the userspace perspective, they can see a seamless mode
849 * change experience when the change between different refresh rates under the
850 * same resolution. Additionally, userspace applications such as Video playback
851 * can read this modeset list and change the refresh rate based on the video
852 * frame rate. Finally, the userspace can also derive an appropriate mode for a
853 * particular refresh rate based on the FreeSync Mode and add it to the
854 * connector's mode list.
855 *
856 * Note: This is an experimental feature.
857 *
858 * The default value: 0 (off).
859 */
860 MODULE_PARM_DESC(
861 freesync_video,
862 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
863 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
864
865 /**
866 * DOC: reset_method (int)
867 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci)
868 */
869 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)");
870 module_param_named(reset_method, amdgpu_reset_method, int, 0444);
871
872 /**
873 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
874 * threshold value of faulty pages detected by RAS ECC, which may
875 * result in the GPU entering bad status when the number of total
876 * faulty pages by ECC exceeds the threshold value.
877 */
878 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)");
879 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
880
881 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
882 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
883
884 /**
885 * DOC: smu_pptable_id (int)
886 * Used to override pptable id. id = 0 use VBIOS pptable.
887 * id > 0 use the soft pptable with specicfied id.
888 */
889 MODULE_PARM_DESC(smu_pptable_id,
890 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
891 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
892
893 /* These devices are not supported by amdgpu.
894 * They are supported by the mach64, r128, radeon drivers
895 */
896 static const u16 amdgpu_unsupported_pciidlist[] = {
897 /* mach64 */
898 0x4354,
899 0x4358,
900 0x4554,
901 0x4742,
902 0x4744,
903 0x4749,
904 0x474C,
905 0x474D,
906 0x474E,
907 0x474F,
908 0x4750,
909 0x4751,
910 0x4752,
911 0x4753,
912 0x4754,
913 0x4755,
914 0x4756,
915 0x4757,
916 0x4758,
917 0x4759,
918 0x475A,
919 0x4C42,
920 0x4C44,
921 0x4C47,
922 0x4C49,
923 0x4C4D,
924 0x4C4E,
925 0x4C50,
926 0x4C51,
927 0x4C52,
928 0x4C53,
929 0x5654,
930 0x5655,
931 0x5656,
932 /* r128 */
933 0x4c45,
934 0x4c46,
935 0x4d46,
936 0x4d4c,
937 0x5041,
938 0x5042,
939 0x5043,
940 0x5044,
941 0x5045,
942 0x5046,
943 0x5047,
944 0x5048,
945 0x5049,
946 0x504A,
947 0x504B,
948 0x504C,
949 0x504D,
950 0x504E,
951 0x504F,
952 0x5050,
953 0x5051,
954 0x5052,
955 0x5053,
956 0x5054,
957 0x5055,
958 0x5056,
959 0x5057,
960 0x5058,
961 0x5245,
962 0x5246,
963 0x5247,
964 0x524b,
965 0x524c,
966 0x534d,
967 0x5446,
968 0x544C,
969 0x5452,
970 /* radeon */
971 0x3150,
972 0x3151,
973 0x3152,
974 0x3154,
975 0x3155,
976 0x3E50,
977 0x3E54,
978 0x4136,
979 0x4137,
980 0x4144,
981 0x4145,
982 0x4146,
983 0x4147,
984 0x4148,
985 0x4149,
986 0x414A,
987 0x414B,
988 0x4150,
989 0x4151,
990 0x4152,
991 0x4153,
992 0x4154,
993 0x4155,
994 0x4156,
995 0x4237,
996 0x4242,
997 0x4336,
998 0x4337,
999 0x4437,
1000 0x4966,
1001 0x4967,
1002 0x4A48,
1003 0x4A49,
1004 0x4A4A,
1005 0x4A4B,
1006 0x4A4C,
1007 0x4A4D,
1008 0x4A4E,
1009 0x4A4F,
1010 0x4A50,
1011 0x4A54,
1012 0x4B48,
1013 0x4B49,
1014 0x4B4A,
1015 0x4B4B,
1016 0x4B4C,
1017 0x4C57,
1018 0x4C58,
1019 0x4C59,
1020 0x4C5A,
1021 0x4C64,
1022 0x4C66,
1023 0x4C67,
1024 0x4E44,
1025 0x4E45,
1026 0x4E46,
1027 0x4E47,
1028 0x4E48,
1029 0x4E49,
1030 0x4E4A,
1031 0x4E4B,
1032 0x4E50,
1033 0x4E51,
1034 0x4E52,
1035 0x4E53,
1036 0x4E54,
1037 0x4E56,
1038 0x5144,
1039 0x5145,
1040 0x5146,
1041 0x5147,
1042 0x5148,
1043 0x514C,
1044 0x514D,
1045 0x5157,
1046 0x5158,
1047 0x5159,
1048 0x515A,
1049 0x515E,
1050 0x5460,
1051 0x5462,
1052 0x5464,
1053 0x5548,
1054 0x5549,
1055 0x554A,
1056 0x554B,
1057 0x554C,
1058 0x554D,
1059 0x554E,
1060 0x554F,
1061 0x5550,
1062 0x5551,
1063 0x5552,
1064 0x5554,
1065 0x564A,
1066 0x564B,
1067 0x564F,
1068 0x5652,
1069 0x5653,
1070 0x5657,
1071 0x5834,
1072 0x5835,
1073 0x5954,
1074 0x5955,
1075 0x5974,
1076 0x5975,
1077 0x5960,
1078 0x5961,
1079 0x5962,
1080 0x5964,
1081 0x5965,
1082 0x5969,
1083 0x5a41,
1084 0x5a42,
1085 0x5a61,
1086 0x5a62,
1087 0x5b60,
1088 0x5b62,
1089 0x5b63,
1090 0x5b64,
1091 0x5b65,
1092 0x5c61,
1093 0x5c63,
1094 0x5d48,
1095 0x5d49,
1096 0x5d4a,
1097 0x5d4c,
1098 0x5d4d,
1099 0x5d4e,
1100 0x5d4f,
1101 0x5d50,
1102 0x5d52,
1103 0x5d57,
1104 0x5e48,
1105 0x5e4a,
1106 0x5e4b,
1107 0x5e4c,
1108 0x5e4d,
1109 0x5e4f,
1110 0x6700,
1111 0x6701,
1112 0x6702,
1113 0x6703,
1114 0x6704,
1115 0x6705,
1116 0x6706,
1117 0x6707,
1118 0x6708,
1119 0x6709,
1120 0x6718,
1121 0x6719,
1122 0x671c,
1123 0x671d,
1124 0x671f,
1125 0x6720,
1126 0x6721,
1127 0x6722,
1128 0x6723,
1129 0x6724,
1130 0x6725,
1131 0x6726,
1132 0x6727,
1133 0x6728,
1134 0x6729,
1135 0x6738,
1136 0x6739,
1137 0x673e,
1138 0x6740,
1139 0x6741,
1140 0x6742,
1141 0x6743,
1142 0x6744,
1143 0x6745,
1144 0x6746,
1145 0x6747,
1146 0x6748,
1147 0x6749,
1148 0x674A,
1149 0x6750,
1150 0x6751,
1151 0x6758,
1152 0x6759,
1153 0x675B,
1154 0x675D,
1155 0x675F,
1156 0x6760,
1157 0x6761,
1158 0x6762,
1159 0x6763,
1160 0x6764,
1161 0x6765,
1162 0x6766,
1163 0x6767,
1164 0x6768,
1165 0x6770,
1166 0x6771,
1167 0x6772,
1168 0x6778,
1169 0x6779,
1170 0x677B,
1171 0x6840,
1172 0x6841,
1173 0x6842,
1174 0x6843,
1175 0x6849,
1176 0x684C,
1177 0x6850,
1178 0x6858,
1179 0x6859,
1180 0x6880,
1181 0x6888,
1182 0x6889,
1183 0x688A,
1184 0x688C,
1185 0x688D,
1186 0x6898,
1187 0x6899,
1188 0x689b,
1189 0x689c,
1190 0x689d,
1191 0x689e,
1192 0x68a0,
1193 0x68a1,
1194 0x68a8,
1195 0x68a9,
1196 0x68b0,
1197 0x68b8,
1198 0x68b9,
1199 0x68ba,
1200 0x68be,
1201 0x68bf,
1202 0x68c0,
1203 0x68c1,
1204 0x68c7,
1205 0x68c8,
1206 0x68c9,
1207 0x68d8,
1208 0x68d9,
1209 0x68da,
1210 0x68de,
1211 0x68e0,
1212 0x68e1,
1213 0x68e4,
1214 0x68e5,
1215 0x68e8,
1216 0x68e9,
1217 0x68f1,
1218 0x68f2,
1219 0x68f8,
1220 0x68f9,
1221 0x68fa,
1222 0x68fe,
1223 0x7100,
1224 0x7101,
1225 0x7102,
1226 0x7103,
1227 0x7104,
1228 0x7105,
1229 0x7106,
1230 0x7108,
1231 0x7109,
1232 0x710A,
1233 0x710B,
1234 0x710C,
1235 0x710E,
1236 0x710F,
1237 0x7140,
1238 0x7141,
1239 0x7142,
1240 0x7143,
1241 0x7144,
1242 0x7145,
1243 0x7146,
1244 0x7147,
1245 0x7149,
1246 0x714A,
1247 0x714B,
1248 0x714C,
1249 0x714D,
1250 0x714E,
1251 0x714F,
1252 0x7151,
1253 0x7152,
1254 0x7153,
1255 0x715E,
1256 0x715F,
1257 0x7180,
1258 0x7181,
1259 0x7183,
1260 0x7186,
1261 0x7187,
1262 0x7188,
1263 0x718A,
1264 0x718B,
1265 0x718C,
1266 0x718D,
1267 0x718F,
1268 0x7193,
1269 0x7196,
1270 0x719B,
1271 0x719F,
1272 0x71C0,
1273 0x71C1,
1274 0x71C2,
1275 0x71C3,
1276 0x71C4,
1277 0x71C5,
1278 0x71C6,
1279 0x71C7,
1280 0x71CD,
1281 0x71CE,
1282 0x71D2,
1283 0x71D4,
1284 0x71D5,
1285 0x71D6,
1286 0x71DA,
1287 0x71DE,
1288 0x7200,
1289 0x7210,
1290 0x7211,
1291 0x7240,
1292 0x7243,
1293 0x7244,
1294 0x7245,
1295 0x7246,
1296 0x7247,
1297 0x7248,
1298 0x7249,
1299 0x724A,
1300 0x724B,
1301 0x724C,
1302 0x724D,
1303 0x724E,
1304 0x724F,
1305 0x7280,
1306 0x7281,
1307 0x7283,
1308 0x7284,
1309 0x7287,
1310 0x7288,
1311 0x7289,
1312 0x728B,
1313 0x728C,
1314 0x7290,
1315 0x7291,
1316 0x7293,
1317 0x7297,
1318 0x7834,
1319 0x7835,
1320 0x791e,
1321 0x791f,
1322 0x793f,
1323 0x7941,
1324 0x7942,
1325 0x796c,
1326 0x796d,
1327 0x796e,
1328 0x796f,
1329 0x9400,
1330 0x9401,
1331 0x9402,
1332 0x9403,
1333 0x9405,
1334 0x940A,
1335 0x940B,
1336 0x940F,
1337 0x94A0,
1338 0x94A1,
1339 0x94A3,
1340 0x94B1,
1341 0x94B3,
1342 0x94B4,
1343 0x94B5,
1344 0x94B9,
1345 0x9440,
1346 0x9441,
1347 0x9442,
1348 0x9443,
1349 0x9444,
1350 0x9446,
1351 0x944A,
1352 0x944B,
1353 0x944C,
1354 0x944E,
1355 0x9450,
1356 0x9452,
1357 0x9456,
1358 0x945A,
1359 0x945B,
1360 0x945E,
1361 0x9460,
1362 0x9462,
1363 0x946A,
1364 0x946B,
1365 0x947A,
1366 0x947B,
1367 0x9480,
1368 0x9487,
1369 0x9488,
1370 0x9489,
1371 0x948A,
1372 0x948F,
1373 0x9490,
1374 0x9491,
1375 0x9495,
1376 0x9498,
1377 0x949C,
1378 0x949E,
1379 0x949F,
1380 0x94C0,
1381 0x94C1,
1382 0x94C3,
1383 0x94C4,
1384 0x94C5,
1385 0x94C6,
1386 0x94C7,
1387 0x94C8,
1388 0x94C9,
1389 0x94CB,
1390 0x94CC,
1391 0x94CD,
1392 0x9500,
1393 0x9501,
1394 0x9504,
1395 0x9505,
1396 0x9506,
1397 0x9507,
1398 0x9508,
1399 0x9509,
1400 0x950F,
1401 0x9511,
1402 0x9515,
1403 0x9517,
1404 0x9519,
1405 0x9540,
1406 0x9541,
1407 0x9542,
1408 0x954E,
1409 0x954F,
1410 0x9552,
1411 0x9553,
1412 0x9555,
1413 0x9557,
1414 0x955f,
1415 0x9580,
1416 0x9581,
1417 0x9583,
1418 0x9586,
1419 0x9587,
1420 0x9588,
1421 0x9589,
1422 0x958A,
1423 0x958B,
1424 0x958C,
1425 0x958D,
1426 0x958E,
1427 0x958F,
1428 0x9590,
1429 0x9591,
1430 0x9593,
1431 0x9595,
1432 0x9596,
1433 0x9597,
1434 0x9598,
1435 0x9599,
1436 0x959B,
1437 0x95C0,
1438 0x95C2,
1439 0x95C4,
1440 0x95C5,
1441 0x95C6,
1442 0x95C7,
1443 0x95C9,
1444 0x95CC,
1445 0x95CD,
1446 0x95CE,
1447 0x95CF,
1448 0x9610,
1449 0x9611,
1450 0x9612,
1451 0x9613,
1452 0x9614,
1453 0x9615,
1454 0x9616,
1455 0x9640,
1456 0x9641,
1457 0x9642,
1458 0x9643,
1459 0x9644,
1460 0x9645,
1461 0x9647,
1462 0x9648,
1463 0x9649,
1464 0x964a,
1465 0x964b,
1466 0x964c,
1467 0x964e,
1468 0x964f,
1469 0x9710,
1470 0x9711,
1471 0x9712,
1472 0x9713,
1473 0x9714,
1474 0x9715,
1475 0x9802,
1476 0x9803,
1477 0x9804,
1478 0x9805,
1479 0x9806,
1480 0x9807,
1481 0x9808,
1482 0x9809,
1483 0x980A,
1484 0x9900,
1485 0x9901,
1486 0x9903,
1487 0x9904,
1488 0x9905,
1489 0x9906,
1490 0x9907,
1491 0x9908,
1492 0x9909,
1493 0x990A,
1494 0x990B,
1495 0x990C,
1496 0x990D,
1497 0x990E,
1498 0x990F,
1499 0x9910,
1500 0x9913,
1501 0x9917,
1502 0x9918,
1503 0x9919,
1504 0x9990,
1505 0x9991,
1506 0x9992,
1507 0x9993,
1508 0x9994,
1509 0x9995,
1510 0x9996,
1511 0x9997,
1512 0x9998,
1513 0x9999,
1514 0x999A,
1515 0x999B,
1516 0x999C,
1517 0x999D,
1518 0x99A0,
1519 0x99A2,
1520 0x99A4,
1521 /* radeon secondary ids */
1522 0x3171,
1523 0x3e70,
1524 0x4164,
1525 0x4165,
1526 0x4166,
1527 0x4168,
1528 0x4170,
1529 0x4171,
1530 0x4172,
1531 0x4173,
1532 0x496e,
1533 0x4a69,
1534 0x4a6a,
1535 0x4a6b,
1536 0x4a70,
1537 0x4a74,
1538 0x4b69,
1539 0x4b6b,
1540 0x4b6c,
1541 0x4c6e,
1542 0x4e64,
1543 0x4e65,
1544 0x4e66,
1545 0x4e67,
1546 0x4e68,
1547 0x4e69,
1548 0x4e6a,
1549 0x4e71,
1550 0x4f73,
1551 0x5569,
1552 0x556b,
1553 0x556d,
1554 0x556f,
1555 0x5571,
1556 0x5854,
1557 0x5874,
1558 0x5940,
1559 0x5941,
1560 0x5b70,
1561 0x5b72,
1562 0x5b73,
1563 0x5b74,
1564 0x5b75,
1565 0x5d44,
1566 0x5d45,
1567 0x5d6d,
1568 0x5d6f,
1569 0x5d72,
1570 0x5d77,
1571 0x5e6b,
1572 0x5e6d,
1573 0x7120,
1574 0x7124,
1575 0x7129,
1576 0x712e,
1577 0x712f,
1578 0x7162,
1579 0x7163,
1580 0x7166,
1581 0x7167,
1582 0x7172,
1583 0x7173,
1584 0x71a0,
1585 0x71a1,
1586 0x71a3,
1587 0x71a7,
1588 0x71bb,
1589 0x71e0,
1590 0x71e1,
1591 0x71e2,
1592 0x71e6,
1593 0x71e7,
1594 0x71f2,
1595 0x7269,
1596 0x726b,
1597 0x726e,
1598 0x72a0,
1599 0x72a8,
1600 0x72b1,
1601 0x72b3,
1602 0x793f,
1603 };
1604
1605 static const struct pci_device_id pciidlist[] = {
1606 #ifdef CONFIG_DRM_AMDGPU_SI
1607 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1608 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1609 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1610 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1611 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1612 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1613 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1614 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1615 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1616 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1617 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1618 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1619 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1620 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1621 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1622 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1623 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1624 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1625 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1626 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1627 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1628 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1629 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1630 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1631 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1632 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1633 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1634 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1635 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1636 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1637 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1638 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1639 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1640 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1641 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1642 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1643 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1644 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1645 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1646 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1647 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1648 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1649 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1650 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1651 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1652 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1653 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1654 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1655 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1656 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1657 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1658 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1659 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1660 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1661 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1662 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1663 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1664 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1665 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1666 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1667 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1668 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1669 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1670 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1671 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1672 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1673 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1674 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1675 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1676 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1677 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1678 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1679 #endif
1680 #ifdef CONFIG_DRM_AMDGPU_CIK
1681 /* Kaveri */
1682 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1683 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1684 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1685 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1686 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1687 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1688 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1689 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1690 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1691 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1692 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1693 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1694 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1695 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1696 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1697 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1698 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1699 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1700 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1701 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1702 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1703 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1704 /* Bonaire */
1705 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1706 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1707 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1708 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1709 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1710 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1711 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1712 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1713 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1714 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1715 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1716 /* Hawaii */
1717 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1718 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1719 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1720 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1721 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1722 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1723 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1724 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1725 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1726 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1727 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1728 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1729 /* Kabini */
1730 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1731 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1732 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1733 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1734 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1735 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1736 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1737 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1738 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1739 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1740 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1741 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1742 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1743 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1744 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1745 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1746 /* mullins */
1747 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1748 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1749 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1750 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1751 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1752 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1753 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1754 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1755 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1756 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1757 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1758 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1759 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1760 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1761 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1762 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1763 #endif
1764 /* topaz */
1765 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1766 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1767 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1768 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1769 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1770 /* tonga */
1771 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1772 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1773 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1774 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1775 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1776 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1777 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1778 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1779 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1780 /* fiji */
1781 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1782 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1783 /* carrizo */
1784 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1785 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1786 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1787 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1788 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1789 /* stoney */
1790 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1791 /* Polaris11 */
1792 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1793 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1794 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1795 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1796 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1797 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1798 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1799 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1800 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1801 /* Polaris10 */
1802 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1803 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1804 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1805 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1806 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1807 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1808 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1809 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1810 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1811 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1812 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1813 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1814 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1815 /* Polaris12 */
1816 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1817 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1818 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1819 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1820 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1821 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1822 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1823 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1824 /* VEGAM */
1825 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1826 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1827 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1828 /* Vega 10 */
1829 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1830 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1831 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1832 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1833 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1834 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1835 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1836 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1837 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1838 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1839 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1840 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1841 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1842 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1843 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1844 /* Vega 12 */
1845 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1846 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1847 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1848 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1849 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1850 /* Vega 20 */
1851 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1852 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1853 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1854 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1855 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1856 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1857 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1858 /* Raven */
1859 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1860 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1861 /* Arcturus */
1862 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1863 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1864 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1865 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1866 /* Navi10 */
1867 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1868 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1869 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1870 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1871 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1872 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1873 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1874 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1875 /* Navi14 */
1876 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1877 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1878 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1879 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1880
1881 /* Renoir */
1882 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1883 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1884 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1885 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1886
1887 /* Navi12 */
1888 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1889 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1890
1891 /* Sienna_Cichlid */
1892 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1893 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1894 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1895 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1896 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1897 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1898 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1899 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1900 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1901 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1902 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1903 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1904 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1905
1906 /* Van Gogh */
1907 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
1908
1909 /* Yellow Carp */
1910 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1911 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1912
1913 /* Navy_Flounder */
1914 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1915 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1916 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1917 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1918 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1919 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1920 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1921 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1922 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1923
1924 /* DIMGREY_CAVEFISH */
1925 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1926 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1927 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1928 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1929 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1930 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1931 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1932 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1933 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1934 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1935 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1936 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1937
1938 /* Aldebaran */
1939 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1940 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1941 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1942 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1943
1944 /* CYAN_SKILLFISH */
1945 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1946
1947 /* BEIGE_GOBY */
1948 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1949 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1950 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1951 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1952 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1953 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1954
1955 {0, 0, 0}
1956 };
1957
1958 MODULE_DEVICE_TABLE(pci, pciidlist);
1959
1960 static const struct drm_driver amdgpu_kms_driver;
1961
amdgpu_is_fw_framebuffer(resource_size_t base,resource_size_t size)1962 static bool amdgpu_is_fw_framebuffer(resource_size_t base,
1963 resource_size_t size)
1964 {
1965 bool found = false;
1966 #if IS_REACHABLE(CONFIG_FB)
1967 struct apertures_struct *a;
1968
1969 a = alloc_apertures(1);
1970 if (!a)
1971 return false;
1972
1973 a->ranges[0].base = base;
1974 a->ranges[0].size = size;
1975
1976 found = is_firmware_framebuffer(a);
1977 kfree(a);
1978 #endif
1979 return found;
1980 }
1981
amdgpu_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1982 static int amdgpu_pci_probe(struct pci_dev *pdev,
1983 const struct pci_device_id *ent)
1984 {
1985 struct drm_device *ddev;
1986 struct amdgpu_device *adev;
1987 unsigned long flags = ent->driver_data;
1988 int ret, retry = 0, i;
1989 bool supports_atomic = false;
1990 bool is_fw_fb;
1991 resource_size_t base, size;
1992
1993 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
1994 amdgpu_aspm = 0;
1995
1996 /* skip devices which are owned by radeon */
1997 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
1998 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
1999 return -ENODEV;
2000 }
2001
2002 if (amdgpu_virtual_display ||
2003 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2004 supports_atomic = true;
2005
2006 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2007 DRM_INFO("This hardware requires experimental hardware support.\n"
2008 "See modparam exp_hw_support\n");
2009 return -ENODEV;
2010 }
2011 /* differentiate between P10 and P11 asics with the same DID */
2012 if (pdev->device == 0x67FF &&
2013 (pdev->revision == 0xE3 ||
2014 pdev->revision == 0xE7 ||
2015 pdev->revision == 0xF3 ||
2016 pdev->revision == 0xF7)) {
2017 flags &= ~AMD_ASIC_MASK;
2018 flags |= CHIP_POLARIS10;
2019 }
2020
2021 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2022 * however, SME requires an indirect IOMMU mapping because the encryption
2023 * bit is beyond the DMA mask of the chip.
2024 */
2025 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2026 dev_info(&pdev->dev,
2027 "SME is not compatible with RAVEN\n");
2028 return -ENOTSUPP;
2029 }
2030
2031 #ifdef CONFIG_DRM_AMDGPU_SI
2032 if (!amdgpu_si_support) {
2033 switch (flags & AMD_ASIC_MASK) {
2034 case CHIP_TAHITI:
2035 case CHIP_PITCAIRN:
2036 case CHIP_VERDE:
2037 case CHIP_OLAND:
2038 case CHIP_HAINAN:
2039 dev_info(&pdev->dev,
2040 "SI support provided by radeon.\n");
2041 dev_info(&pdev->dev,
2042 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2043 );
2044 return -ENODEV;
2045 }
2046 }
2047 #endif
2048 #ifdef CONFIG_DRM_AMDGPU_CIK
2049 if (!amdgpu_cik_support) {
2050 switch (flags & AMD_ASIC_MASK) {
2051 case CHIP_KAVERI:
2052 case CHIP_BONAIRE:
2053 case CHIP_HAWAII:
2054 case CHIP_KABINI:
2055 case CHIP_MULLINS:
2056 dev_info(&pdev->dev,
2057 "CIK support provided by radeon.\n");
2058 dev_info(&pdev->dev,
2059 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2060 );
2061 return -ENODEV;
2062 }
2063 }
2064 #endif
2065
2066 base = pci_resource_start(pdev, 0);
2067 size = pci_resource_len(pdev, 0);
2068 is_fw_fb = amdgpu_is_fw_framebuffer(base, size);
2069
2070 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2071 if (IS_ERR(adev))
2072 return PTR_ERR(adev);
2073
2074 adev->dev = &pdev->dev;
2075 adev->pdev = pdev;
2076 ddev = adev_to_drm(adev);
2077 adev->is_fw_fb = is_fw_fb;
2078
2079 if (!supports_atomic)
2080 ddev->driver_features &= ~DRIVER_ATOMIC;
2081
2082 ret = pci_enable_device(pdev);
2083 if (ret)
2084 return ret;
2085
2086 pci_set_drvdata(pdev, ddev);
2087
2088 ret = amdgpu_driver_load_kms(adev, flags);
2089 if (ret)
2090 goto err_pci;
2091
2092 retry_init:
2093 ret = drm_dev_register(ddev, flags);
2094 if (ret == -EAGAIN && ++retry <= 3) {
2095 DRM_INFO("retry init %d\n", retry);
2096 /* Don't request EX mode too frequently which is attacking */
2097 msleep(5000);
2098 goto retry_init;
2099 } else if (ret) {
2100 goto err_pci;
2101 }
2102
2103 ret = amdgpu_debugfs_init(adev);
2104 if (ret)
2105 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2106
2107 return 0;
2108
2109 err_pci:
2110 pci_disable_device(pdev);
2111 return ret;
2112 }
2113
2114 static void
amdgpu_pci_remove(struct pci_dev * pdev)2115 amdgpu_pci_remove(struct pci_dev *pdev)
2116 {
2117 struct drm_device *dev = pci_get_drvdata(pdev);
2118
2119 drm_dev_unplug(dev);
2120 amdgpu_driver_unload_kms(dev);
2121
2122 /*
2123 * Flush any in flight DMA operations from device.
2124 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2125 * StatusTransactions Pending bit.
2126 */
2127 pci_disable_device(pdev);
2128 pci_wait_for_pending_transaction(pdev);
2129 }
2130
2131 static void
amdgpu_pci_shutdown(struct pci_dev * pdev)2132 amdgpu_pci_shutdown(struct pci_dev *pdev)
2133 {
2134 struct drm_device *dev = pci_get_drvdata(pdev);
2135 struct amdgpu_device *adev = drm_to_adev(dev);
2136
2137 if (amdgpu_ras_intr_triggered())
2138 return;
2139
2140 /* if we are running in a VM, make sure the device
2141 * torn down properly on reboot/shutdown.
2142 * unfortunately we can't detect certain
2143 * hypervisors so just do this all the time.
2144 */
2145 if (!amdgpu_passthrough(adev))
2146 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2147 amdgpu_device_ip_suspend(adev);
2148 adev->mp1_state = PP_MP1_STATE_NONE;
2149 }
2150
2151 /**
2152 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2153 *
2154 * @work: work_struct.
2155 */
amdgpu_drv_delayed_reset_work_handler(struct work_struct * work)2156 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2157 {
2158 struct list_head device_list;
2159 struct amdgpu_device *adev;
2160 int i, r;
2161 struct amdgpu_reset_context reset_context;
2162
2163 memset(&reset_context, 0, sizeof(reset_context));
2164
2165 mutex_lock(&mgpu_info.mutex);
2166 if (mgpu_info.pending_reset == true) {
2167 mutex_unlock(&mgpu_info.mutex);
2168 return;
2169 }
2170 mgpu_info.pending_reset = true;
2171 mutex_unlock(&mgpu_info.mutex);
2172
2173 /* Use a common context, just need to make sure full reset is done */
2174 reset_context.method = AMD_RESET_METHOD_NONE;
2175 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2176
2177 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2178 adev = mgpu_info.gpu_ins[i].adev;
2179 reset_context.reset_req_dev = adev;
2180 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
2181 if (r) {
2182 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2183 r, adev_to_drm(adev)->unique);
2184 }
2185 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2186 r = -EALREADY;
2187 }
2188 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2189 adev = mgpu_info.gpu_ins[i].adev;
2190 flush_work(&adev->xgmi_reset_work);
2191 adev->gmc.xgmi.pending_reset = false;
2192 }
2193
2194 /* reset function will rebuild the xgmi hive info , clear it now */
2195 for (i = 0; i < mgpu_info.num_dgpu; i++)
2196 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2197
2198 INIT_LIST_HEAD(&device_list);
2199
2200 for (i = 0; i < mgpu_info.num_dgpu; i++)
2201 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2202
2203 /* unregister the GPU first, reset function will add them back */
2204 list_for_each_entry(adev, &device_list, reset_list)
2205 amdgpu_unregister_gpu_instance(adev);
2206
2207 /* Use a common context, just need to make sure full reset is done */
2208 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2209 r = amdgpu_do_asic_reset(&device_list, &reset_context);
2210
2211 if (r) {
2212 DRM_ERROR("reinit gpus failure");
2213 return;
2214 }
2215 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2216 adev = mgpu_info.gpu_ins[i].adev;
2217 if (!adev->kfd.init_complete)
2218 amdgpu_amdkfd_device_init(adev);
2219 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2220 }
2221 return;
2222 }
2223
amdgpu_pmops_prepare(struct device * dev)2224 static int amdgpu_pmops_prepare(struct device *dev)
2225 {
2226 struct drm_device *drm_dev = dev_get_drvdata(dev);
2227 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2228
2229 /* Return a positive number here so
2230 * DPM_FLAG_SMART_SUSPEND works properly
2231 */
2232 if (amdgpu_device_supports_boco(drm_dev))
2233 return pm_runtime_suspended(dev);
2234
2235 /* if we will not support s3 or s2i for the device
2236 * then skip suspend
2237 */
2238 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2239 !amdgpu_acpi_is_s3_active(adev))
2240 return 1;
2241
2242 return 0;
2243 }
2244
amdgpu_pmops_complete(struct device * dev)2245 static void amdgpu_pmops_complete(struct device *dev)
2246 {
2247 /* nothing to do */
2248 }
2249
amdgpu_pmops_suspend(struct device * dev)2250 static int amdgpu_pmops_suspend(struct device *dev)
2251 {
2252 struct drm_device *drm_dev = dev_get_drvdata(dev);
2253 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2254
2255 adev->suspend_complete = false;
2256 if (amdgpu_acpi_is_s0ix_active(adev))
2257 adev->in_s0ix = true;
2258 else
2259 adev->in_s3 = true;
2260 return amdgpu_device_suspend(drm_dev, true);
2261 }
2262
amdgpu_pmops_suspend_noirq(struct device * dev)2263 static int amdgpu_pmops_suspend_noirq(struct device *dev)
2264 {
2265 struct drm_device *drm_dev = dev_get_drvdata(dev);
2266 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2267
2268 adev->suspend_complete = true;
2269 if (amdgpu_acpi_should_gpu_reset(adev))
2270 return amdgpu_asic_reset(adev);
2271
2272 return 0;
2273 }
2274
amdgpu_pmops_resume(struct device * dev)2275 static int amdgpu_pmops_resume(struct device *dev)
2276 {
2277 struct drm_device *drm_dev = dev_get_drvdata(dev);
2278 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2279 int r;
2280
2281 r = amdgpu_device_resume(drm_dev, true);
2282 if (amdgpu_acpi_is_s0ix_active(adev))
2283 adev->in_s0ix = false;
2284 else
2285 adev->in_s3 = false;
2286 return r;
2287 }
2288
amdgpu_pmops_freeze(struct device * dev)2289 static int amdgpu_pmops_freeze(struct device *dev)
2290 {
2291 struct drm_device *drm_dev = dev_get_drvdata(dev);
2292 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2293 int r;
2294
2295 adev->in_s4 = true;
2296 r = amdgpu_device_suspend(drm_dev, true);
2297 adev->in_s4 = false;
2298 if (r)
2299 return r;
2300 return amdgpu_asic_reset(adev);
2301 }
2302
amdgpu_pmops_thaw(struct device * dev)2303 static int amdgpu_pmops_thaw(struct device *dev)
2304 {
2305 struct drm_device *drm_dev = dev_get_drvdata(dev);
2306
2307 return amdgpu_device_resume(drm_dev, true);
2308 }
2309
amdgpu_pmops_poweroff(struct device * dev)2310 static int amdgpu_pmops_poweroff(struct device *dev)
2311 {
2312 struct drm_device *drm_dev = dev_get_drvdata(dev);
2313
2314 return amdgpu_device_suspend(drm_dev, true);
2315 }
2316
amdgpu_pmops_restore(struct device * dev)2317 static int amdgpu_pmops_restore(struct device *dev)
2318 {
2319 struct drm_device *drm_dev = dev_get_drvdata(dev);
2320
2321 return amdgpu_device_resume(drm_dev, true);
2322 }
2323
amdgpu_pmops_runtime_suspend(struct device * dev)2324 static int amdgpu_pmops_runtime_suspend(struct device *dev)
2325 {
2326 struct pci_dev *pdev = to_pci_dev(dev);
2327 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2328 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2329 int ret, i;
2330
2331 if (!adev->runpm) {
2332 pm_runtime_forbid(dev);
2333 return -EBUSY;
2334 }
2335
2336 /* wait for all rings to drain before suspending */
2337 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2338 struct amdgpu_ring *ring = adev->rings[i];
2339 if (ring && ring->sched.ready) {
2340 ret = amdgpu_fence_wait_empty(ring);
2341 if (ret)
2342 return -EBUSY;
2343 }
2344 }
2345
2346 adev->in_runpm = true;
2347 if (amdgpu_device_supports_px(drm_dev))
2348 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2349
2350 /*
2351 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2352 * proper cleanups and put itself into a state ready for PNP. That
2353 * can address some random resuming failure observed on BOCO capable
2354 * platforms.
2355 * TODO: this may be also needed for PX capable platform.
2356 */
2357 if (amdgpu_device_supports_boco(drm_dev))
2358 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2359
2360 ret = amdgpu_device_suspend(drm_dev, false);
2361 if (ret) {
2362 adev->in_runpm = false;
2363 if (amdgpu_device_supports_boco(drm_dev))
2364 adev->mp1_state = PP_MP1_STATE_NONE;
2365 return ret;
2366 }
2367
2368 if (amdgpu_device_supports_boco(drm_dev))
2369 adev->mp1_state = PP_MP1_STATE_NONE;
2370
2371 if (amdgpu_device_supports_px(drm_dev)) {
2372 /* Only need to handle PCI state in the driver for ATPX
2373 * PCI core handles it for _PR3.
2374 */
2375 amdgpu_device_cache_pci_state(pdev);
2376 pci_disable_device(pdev);
2377 pci_ignore_hotplug(pdev);
2378 pci_set_power_state(pdev, PCI_D3cold);
2379 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2380 } else if (amdgpu_device_supports_boco(drm_dev)) {
2381 /* nothing to do */
2382 } else if (amdgpu_device_supports_baco(drm_dev)) {
2383 amdgpu_device_baco_enter(drm_dev);
2384 }
2385
2386 return 0;
2387 }
2388
amdgpu_pmops_runtime_resume(struct device * dev)2389 static int amdgpu_pmops_runtime_resume(struct device *dev)
2390 {
2391 struct pci_dev *pdev = to_pci_dev(dev);
2392 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2393 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2394 int ret;
2395
2396 if (!adev->runpm)
2397 return -EINVAL;
2398
2399 /* Avoids registers access if device is physically gone */
2400 if (!pci_device_is_present(adev->pdev))
2401 adev->no_hw_access = true;
2402
2403 if (amdgpu_device_supports_px(drm_dev)) {
2404 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2405
2406 /* Only need to handle PCI state in the driver for ATPX
2407 * PCI core handles it for _PR3.
2408 */
2409 pci_set_power_state(pdev, PCI_D0);
2410 amdgpu_device_load_pci_state(pdev);
2411 ret = pci_enable_device(pdev);
2412 if (ret)
2413 return ret;
2414 pci_set_master(pdev);
2415 } else if (amdgpu_device_supports_boco(drm_dev)) {
2416 /* Only need to handle PCI state in the driver for ATPX
2417 * PCI core handles it for _PR3.
2418 */
2419 pci_set_master(pdev);
2420 } else if (amdgpu_device_supports_baco(drm_dev)) {
2421 amdgpu_device_baco_exit(drm_dev);
2422 }
2423 ret = amdgpu_device_resume(drm_dev, false);
2424 if (ret) {
2425 if (amdgpu_device_supports_px(drm_dev))
2426 pci_disable_device(pdev);
2427 return ret;
2428 }
2429
2430 if (amdgpu_device_supports_px(drm_dev))
2431 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2432 adev->in_runpm = false;
2433 return 0;
2434 }
2435
amdgpu_pmops_runtime_idle(struct device * dev)2436 static int amdgpu_pmops_runtime_idle(struct device *dev)
2437 {
2438 struct drm_device *drm_dev = dev_get_drvdata(dev);
2439 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2440 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2441 int ret = 1;
2442
2443 if (!adev->runpm) {
2444 pm_runtime_forbid(dev);
2445 return -EBUSY;
2446 }
2447
2448 if (amdgpu_device_has_dc_support(adev)) {
2449 struct drm_crtc *crtc;
2450
2451 drm_for_each_crtc(crtc, drm_dev) {
2452 drm_modeset_lock(&crtc->mutex, NULL);
2453 if (crtc->state->active)
2454 ret = -EBUSY;
2455 drm_modeset_unlock(&crtc->mutex);
2456 if (ret < 0)
2457 break;
2458 }
2459
2460 } else {
2461 struct drm_connector *list_connector;
2462 struct drm_connector_list_iter iter;
2463
2464 mutex_lock(&drm_dev->mode_config.mutex);
2465 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2466
2467 drm_connector_list_iter_begin(drm_dev, &iter);
2468 drm_for_each_connector_iter(list_connector, &iter) {
2469 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2470 ret = -EBUSY;
2471 break;
2472 }
2473 }
2474
2475 drm_connector_list_iter_end(&iter);
2476
2477 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2478 mutex_unlock(&drm_dev->mode_config.mutex);
2479 }
2480
2481 if (ret == -EBUSY)
2482 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
2483
2484 pm_runtime_mark_last_busy(dev);
2485 pm_runtime_autosuspend(dev);
2486 return ret;
2487 }
2488
amdgpu_drm_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)2489 long amdgpu_drm_ioctl(struct file *filp,
2490 unsigned int cmd, unsigned long arg)
2491 {
2492 struct drm_file *file_priv = filp->private_data;
2493 struct drm_device *dev;
2494 long ret;
2495 dev = file_priv->minor->dev;
2496 ret = pm_runtime_get_sync(dev->dev);
2497 if (ret < 0)
2498 goto out;
2499
2500 ret = drm_ioctl(filp, cmd, arg);
2501
2502 pm_runtime_mark_last_busy(dev->dev);
2503 out:
2504 pm_runtime_put_autosuspend(dev->dev);
2505 return ret;
2506 }
2507
2508 static const struct dev_pm_ops amdgpu_pm_ops = {
2509 .prepare = amdgpu_pmops_prepare,
2510 .complete = amdgpu_pmops_complete,
2511 .suspend = amdgpu_pmops_suspend,
2512 .suspend_noirq = amdgpu_pmops_suspend_noirq,
2513 .resume = amdgpu_pmops_resume,
2514 .freeze = amdgpu_pmops_freeze,
2515 .thaw = amdgpu_pmops_thaw,
2516 .poweroff = amdgpu_pmops_poweroff,
2517 .restore = amdgpu_pmops_restore,
2518 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2519 .runtime_resume = amdgpu_pmops_runtime_resume,
2520 .runtime_idle = amdgpu_pmops_runtime_idle,
2521 };
2522
amdgpu_flush(struct file * f,fl_owner_t id)2523 static int amdgpu_flush(struct file *f, fl_owner_t id)
2524 {
2525 struct drm_file *file_priv = f->private_data;
2526 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2527 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
2528
2529 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2530 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
2531
2532 return timeout >= 0 ? 0 : timeout;
2533 }
2534
2535 static const struct file_operations amdgpu_driver_kms_fops = {
2536 .owner = THIS_MODULE,
2537 .open = drm_open,
2538 .flush = amdgpu_flush,
2539 .release = drm_release,
2540 .unlocked_ioctl = amdgpu_drm_ioctl,
2541 .mmap = drm_gem_mmap,
2542 .poll = drm_poll,
2543 .read = drm_read,
2544 #ifdef CONFIG_COMPAT
2545 .compat_ioctl = amdgpu_kms_compat_ioctl,
2546 #endif
2547 #ifdef CONFIG_PROC_FS
2548 .show_fdinfo = amdgpu_show_fdinfo
2549 #endif
2550 };
2551
amdgpu_file_to_fpriv(struct file * filp,struct amdgpu_fpriv ** fpriv)2552 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2553 {
2554 struct drm_file *file;
2555
2556 if (!filp)
2557 return -EINVAL;
2558
2559 if (filp->f_op != &amdgpu_driver_kms_fops) {
2560 return -EINVAL;
2561 }
2562
2563 file = filp->private_data;
2564 *fpriv = file->driver_priv;
2565 return 0;
2566 }
2567
2568 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2569 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2570 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2571 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2572 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2573 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2574 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2575 /* KMS */
2576 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2577 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2578 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2579 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2580 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2581 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2582 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2583 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2584 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2585 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2586 };
2587
2588 static const struct drm_driver amdgpu_kms_driver = {
2589 .driver_features =
2590 DRIVER_ATOMIC |
2591 DRIVER_GEM |
2592 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2593 DRIVER_SYNCOBJ_TIMELINE,
2594 .open = amdgpu_driver_open_kms,
2595 .postclose = amdgpu_driver_postclose_kms,
2596 .lastclose = amdgpu_driver_lastclose_kms,
2597 .ioctls = amdgpu_ioctls_kms,
2598 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2599 .dumb_create = amdgpu_mode_dumb_create,
2600 .dumb_map_offset = amdgpu_mode_dumb_mmap,
2601 .fops = &amdgpu_driver_kms_fops,
2602 .release = &amdgpu_driver_release_kms,
2603
2604 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2605 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2606 .gem_prime_import = amdgpu_gem_prime_import,
2607 .gem_prime_mmap = drm_gem_prime_mmap,
2608
2609 .name = DRIVER_NAME,
2610 .desc = DRIVER_DESC,
2611 .date = DRIVER_DATE,
2612 .major = KMS_DRIVER_MAJOR,
2613 .minor = KMS_DRIVER_MINOR,
2614 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2615 };
2616
2617 static struct pci_error_handlers amdgpu_pci_err_handler = {
2618 .error_detected = amdgpu_pci_error_detected,
2619 .mmio_enabled = amdgpu_pci_mmio_enabled,
2620 .slot_reset = amdgpu_pci_slot_reset,
2621 .resume = amdgpu_pci_resume,
2622 };
2623
2624 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2625 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2626 extern const struct attribute_group amdgpu_vbios_version_attr_group;
2627
2628 static const struct attribute_group *amdgpu_sysfs_groups[] = {
2629 &amdgpu_vram_mgr_attr_group,
2630 &amdgpu_gtt_mgr_attr_group,
2631 &amdgpu_vbios_version_attr_group,
2632 NULL,
2633 };
2634
2635
2636 static struct pci_driver amdgpu_kms_pci_driver = {
2637 .name = DRIVER_NAME,
2638 .id_table = pciidlist,
2639 .probe = amdgpu_pci_probe,
2640 .remove = amdgpu_pci_remove,
2641 .shutdown = amdgpu_pci_shutdown,
2642 .driver.pm = &amdgpu_pm_ops,
2643 .err_handler = &amdgpu_pci_err_handler,
2644 .dev_groups = amdgpu_sysfs_groups,
2645 };
2646
amdgpu_init(void)2647 static int __init amdgpu_init(void)
2648 {
2649 int r;
2650
2651 if (vgacon_text_force()) {
2652 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
2653 return -EINVAL;
2654 }
2655
2656 r = amdgpu_sync_init();
2657 if (r)
2658 goto error_sync;
2659
2660 r = amdgpu_fence_slab_init();
2661 if (r)
2662 goto error_fence;
2663
2664 DRM_INFO("amdgpu kernel modesetting enabled.\n");
2665 amdgpu_register_atpx_handler();
2666 amdgpu_acpi_detect();
2667
2668 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2669 amdgpu_amdkfd_init();
2670
2671 /* let modprobe override vga console setting */
2672 return pci_register_driver(&amdgpu_kms_pci_driver);
2673
2674 error_fence:
2675 amdgpu_sync_fini();
2676
2677 error_sync:
2678 return r;
2679 }
2680
amdgpu_exit(void)2681 static void __exit amdgpu_exit(void)
2682 {
2683 amdgpu_amdkfd_fini();
2684 pci_unregister_driver(&amdgpu_kms_pci_driver);
2685 amdgpu_unregister_atpx_handler();
2686 amdgpu_sync_fini();
2687 amdgpu_fence_slab_fini();
2688 mmu_notifier_synchronize();
2689 }
2690
2691 module_init(amdgpu_init);
2692 module_exit(amdgpu_exit);
2693
2694 MODULE_AUTHOR(DRIVER_AUTHOR);
2695 MODULE_DESCRIPTION(DRIVER_DESC);
2696 MODULE_LICENSE("GPL and additional rights");
2697