1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_i2c.h"
30 #include "atom.h"
31 #include "amdgpu_connectors.h"
32 #include "amdgpu_display.h"
33 #include <asm/div64.h>
34
35 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <drm/drm_crtc_helper.h>
38 #include <drm/drm_edid.h>
39 #include <drm/drm_gem_framebuffer_helper.h>
40 #include <drm/drm_fb_helper.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_vblank.h>
43
amdgpu_display_flip_callback(struct dma_fence * f,struct dma_fence_cb * cb)44 static void amdgpu_display_flip_callback(struct dma_fence *f,
45 struct dma_fence_cb *cb)
46 {
47 struct amdgpu_flip_work *work =
48 container_of(cb, struct amdgpu_flip_work, cb);
49
50 dma_fence_put(f);
51 schedule_work(&work->flip_work.work);
52 }
53
amdgpu_display_flip_handle_fence(struct amdgpu_flip_work * work,struct dma_fence ** f)54 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
55 struct dma_fence **f)
56 {
57 struct dma_fence *fence= *f;
58
59 if (fence == NULL)
60 return false;
61
62 *f = NULL;
63
64 if (!dma_fence_add_callback(fence, &work->cb,
65 amdgpu_display_flip_callback))
66 return true;
67
68 dma_fence_put(fence);
69 return false;
70 }
71
amdgpu_display_flip_work_func(struct work_struct * __work)72 static void amdgpu_display_flip_work_func(struct work_struct *__work)
73 {
74 struct delayed_work *delayed_work =
75 container_of(__work, struct delayed_work, work);
76 struct amdgpu_flip_work *work =
77 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
78 struct amdgpu_device *adev = work->adev;
79 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
80
81 struct drm_crtc *crtc = &amdgpu_crtc->base;
82 unsigned long flags;
83 unsigned int i;
84 int vpos, hpos;
85
86 if (amdgpu_display_flip_handle_fence(work, &work->excl))
87 return;
88
89 for (i = 0; i < work->shared_count; ++i)
90 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
91 return;
92
93 /* Wait until we're out of the vertical blank period before the one
94 * targeted by the flip
95 */
96 if (amdgpu_crtc->enabled &&
97 (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
98 &vpos, &hpos, NULL, NULL,
99 &crtc->hwmode)
100 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
101 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
102 (int)(work->target_vblank -
103 amdgpu_get_vblank_counter_kms(crtc)) > 0) {
104 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
105 return;
106 }
107
108 /* We borrow the event spin lock for protecting flip_status */
109 spin_lock_irqsave(&crtc->dev->event_lock, flags);
110
111 /* Do the flip (mmio) */
112 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
113
114 /* Set the flip status */
115 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
116 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
117
118
119 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
120 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
121
122 }
123
124 /*
125 * Handle unpin events outside the interrupt handler proper.
126 */
amdgpu_display_unpin_work_func(struct work_struct * __work)127 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
128 {
129 struct amdgpu_flip_work *work =
130 container_of(__work, struct amdgpu_flip_work, unpin_work);
131 int r;
132
133 /* unpin of the old buffer */
134 r = amdgpu_bo_reserve(work->old_abo, true);
135 if (likely(r == 0)) {
136 amdgpu_bo_unpin(work->old_abo);
137 amdgpu_bo_unreserve(work->old_abo);
138 } else
139 DRM_ERROR("failed to reserve buffer after flip\n");
140
141 amdgpu_bo_unref(&work->old_abo);
142 kfree(work->shared);
143 kfree(work);
144 }
145
amdgpu_display_crtc_page_flip_target(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t page_flip_flags,uint32_t target,struct drm_modeset_acquire_ctx * ctx)146 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
147 struct drm_framebuffer *fb,
148 struct drm_pending_vblank_event *event,
149 uint32_t page_flip_flags, uint32_t target,
150 struct drm_modeset_acquire_ctx *ctx)
151 {
152 struct drm_device *dev = crtc->dev;
153 struct amdgpu_device *adev = drm_to_adev(dev);
154 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
155 struct drm_gem_object *obj;
156 struct amdgpu_flip_work *work;
157 struct amdgpu_bo *new_abo;
158 unsigned long flags;
159 u64 tiling_flags;
160 int i, r;
161
162 work = kzalloc(sizeof(*work), GFP_KERNEL);
163 if (work == NULL)
164 return -ENOMEM;
165
166 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
167 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
168
169 work->event = event;
170 work->adev = adev;
171 work->crtc_id = amdgpu_crtc->crtc_id;
172 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
173
174 /* schedule unpin of the old buffer */
175 obj = crtc->primary->fb->obj[0];
176
177 /* take a reference to the old object */
178 work->old_abo = gem_to_amdgpu_bo(obj);
179 amdgpu_bo_ref(work->old_abo);
180
181 obj = fb->obj[0];
182 new_abo = gem_to_amdgpu_bo(obj);
183
184 /* pin the new buffer */
185 r = amdgpu_bo_reserve(new_abo, false);
186 if (unlikely(r != 0)) {
187 DRM_ERROR("failed to reserve new abo buffer before flip\n");
188 goto cleanup;
189 }
190
191 if (!adev->enable_virtual_display) {
192 r = amdgpu_bo_pin(new_abo,
193 amdgpu_display_supported_domains(adev, new_abo->flags));
194 if (unlikely(r != 0)) {
195 DRM_ERROR("failed to pin new abo buffer before flip\n");
196 goto unreserve;
197 }
198 }
199
200 r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
201 if (unlikely(r != 0)) {
202 DRM_ERROR("%p bind failed\n", new_abo);
203 goto unpin;
204 }
205
206 r = dma_resv_get_fences(new_abo->tbo.base.resv, &work->excl,
207 &work->shared_count, &work->shared);
208 if (unlikely(r != 0)) {
209 DRM_ERROR("failed to get fences for buffer\n");
210 goto unpin;
211 }
212
213 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
214 amdgpu_bo_unreserve(new_abo);
215
216 if (!adev->enable_virtual_display)
217 work->base = amdgpu_bo_gpu_offset(new_abo);
218 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
219 amdgpu_get_vblank_counter_kms(crtc);
220
221 /* we borrow the event spin lock for protecting flip_wrok */
222 spin_lock_irqsave(&crtc->dev->event_lock, flags);
223 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
224 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
225 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
226 r = -EBUSY;
227 goto pflip_cleanup;
228 }
229
230 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
231 amdgpu_crtc->pflip_works = work;
232
233
234 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
235 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
236 /* update crtc fb */
237 crtc->primary->fb = fb;
238 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
239 amdgpu_display_flip_work_func(&work->flip_work.work);
240 return 0;
241
242 pflip_cleanup:
243 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
244 DRM_ERROR("failed to reserve new abo in error path\n");
245 goto cleanup;
246 }
247 unpin:
248 if (!adev->enable_virtual_display)
249 amdgpu_bo_unpin(new_abo);
250
251 unreserve:
252 amdgpu_bo_unreserve(new_abo);
253
254 cleanup:
255 amdgpu_bo_unref(&work->old_abo);
256 dma_fence_put(work->excl);
257 for (i = 0; i < work->shared_count; ++i)
258 dma_fence_put(work->shared[i]);
259 kfree(work->shared);
260 kfree(work);
261
262 return r;
263 }
264
amdgpu_display_crtc_set_config(struct drm_mode_set * set,struct drm_modeset_acquire_ctx * ctx)265 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
266 struct drm_modeset_acquire_ctx *ctx)
267 {
268 struct drm_device *dev;
269 struct amdgpu_device *adev;
270 struct drm_crtc *crtc;
271 bool active = false;
272 int ret;
273
274 if (!set || !set->crtc)
275 return -EINVAL;
276
277 dev = set->crtc->dev;
278
279 ret = pm_runtime_get_sync(dev->dev);
280 if (ret < 0)
281 goto out;
282
283 ret = drm_crtc_helper_set_config(set, ctx);
284
285 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
286 if (crtc->enabled)
287 active = true;
288
289 pm_runtime_mark_last_busy(dev->dev);
290
291 adev = drm_to_adev(dev);
292 /* if we have active crtcs and we don't have a power ref,
293 * take the current one
294 */
295 if (active && !adev->have_disp_power_ref) {
296 adev->have_disp_power_ref = true;
297 return ret;
298 }
299 /* if we have no active crtcs, then go to
300 * drop the power ref we got before
301 */
302 if (!active && adev->have_disp_power_ref)
303 adev->have_disp_power_ref = false;
304 out:
305 /* drop the power reference we got coming in here */
306 pm_runtime_put_autosuspend(dev->dev);
307 return ret;
308 }
309
310 static const char *encoder_names[41] = {
311 "NONE",
312 "INTERNAL_LVDS",
313 "INTERNAL_TMDS1",
314 "INTERNAL_TMDS2",
315 "INTERNAL_DAC1",
316 "INTERNAL_DAC2",
317 "INTERNAL_SDVOA",
318 "INTERNAL_SDVOB",
319 "SI170B",
320 "CH7303",
321 "CH7301",
322 "INTERNAL_DVO1",
323 "EXTERNAL_SDVOA",
324 "EXTERNAL_SDVOB",
325 "TITFP513",
326 "INTERNAL_LVTM1",
327 "VT1623",
328 "HDMI_SI1930",
329 "HDMI_INTERNAL",
330 "INTERNAL_KLDSCP_TMDS1",
331 "INTERNAL_KLDSCP_DVO1",
332 "INTERNAL_KLDSCP_DAC1",
333 "INTERNAL_KLDSCP_DAC2",
334 "SI178",
335 "MVPU_FPGA",
336 "INTERNAL_DDI",
337 "VT1625",
338 "HDMI_SI1932",
339 "DP_AN9801",
340 "DP_DP501",
341 "INTERNAL_UNIPHY",
342 "INTERNAL_KLDSCP_LVTMA",
343 "INTERNAL_UNIPHY1",
344 "INTERNAL_UNIPHY2",
345 "NUTMEG",
346 "TRAVIS",
347 "INTERNAL_VCE",
348 "INTERNAL_UNIPHY3",
349 "HDMI_ANX9805",
350 "INTERNAL_AMCLK",
351 "VIRTUAL",
352 };
353
354 static const char *hpd_names[6] = {
355 "HPD1",
356 "HPD2",
357 "HPD3",
358 "HPD4",
359 "HPD5",
360 "HPD6",
361 };
362
amdgpu_display_print_display_setup(struct drm_device * dev)363 void amdgpu_display_print_display_setup(struct drm_device *dev)
364 {
365 struct drm_connector *connector;
366 struct amdgpu_connector *amdgpu_connector;
367 struct drm_encoder *encoder;
368 struct amdgpu_encoder *amdgpu_encoder;
369 struct drm_connector_list_iter iter;
370 uint32_t devices;
371 int i = 0;
372
373 drm_connector_list_iter_begin(dev, &iter);
374 DRM_INFO("AMDGPU Display Connectors\n");
375 drm_for_each_connector_iter(connector, &iter) {
376 amdgpu_connector = to_amdgpu_connector(connector);
377 DRM_INFO("Connector %d:\n", i);
378 DRM_INFO(" %s\n", connector->name);
379 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
380 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
381 if (amdgpu_connector->ddc_bus) {
382 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
383 amdgpu_connector->ddc_bus->rec.mask_clk_reg,
384 amdgpu_connector->ddc_bus->rec.mask_data_reg,
385 amdgpu_connector->ddc_bus->rec.a_clk_reg,
386 amdgpu_connector->ddc_bus->rec.a_data_reg,
387 amdgpu_connector->ddc_bus->rec.en_clk_reg,
388 amdgpu_connector->ddc_bus->rec.en_data_reg,
389 amdgpu_connector->ddc_bus->rec.y_clk_reg,
390 amdgpu_connector->ddc_bus->rec.y_data_reg);
391 if (amdgpu_connector->router.ddc_valid)
392 DRM_INFO(" DDC Router 0x%x/0x%x\n",
393 amdgpu_connector->router.ddc_mux_control_pin,
394 amdgpu_connector->router.ddc_mux_state);
395 if (amdgpu_connector->router.cd_valid)
396 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
397 amdgpu_connector->router.cd_mux_control_pin,
398 amdgpu_connector->router.cd_mux_state);
399 } else {
400 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
401 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
402 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
403 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
404 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
405 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
406 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
407 }
408 DRM_INFO(" Encoders:\n");
409 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
410 amdgpu_encoder = to_amdgpu_encoder(encoder);
411 devices = amdgpu_encoder->devices & amdgpu_connector->devices;
412 if (devices) {
413 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
414 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
415 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
416 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
417 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
418 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
419 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
420 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
421 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
422 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
423 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
424 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
425 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
426 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
427 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
428 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
429 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
430 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
431 if (devices & ATOM_DEVICE_TV1_SUPPORT)
432 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
433 if (devices & ATOM_DEVICE_CV_SUPPORT)
434 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
435 }
436 }
437 i++;
438 }
439 drm_connector_list_iter_end(&iter);
440 }
441
amdgpu_display_ddc_probe(struct amdgpu_connector * amdgpu_connector,bool use_aux)442 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
443 bool use_aux)
444 {
445 u8 out = 0x0;
446 u8 buf[8];
447 int ret;
448 struct i2c_msg msgs[] = {
449 {
450 .addr = DDC_ADDR,
451 .flags = 0,
452 .len = 1,
453 .buf = &out,
454 },
455 {
456 .addr = DDC_ADDR,
457 .flags = I2C_M_RD,
458 .len = 8,
459 .buf = buf,
460 }
461 };
462
463 /* on hw with routers, select right port */
464 if (amdgpu_connector->router.ddc_valid)
465 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
466
467 if (use_aux)
468 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
469 else
470 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
471
472 if (ret != 2)
473 /* Couldn't find an accessible DDC on this connector */
474 return false;
475 /* Probe also for valid EDID header
476 * EDID header starts with:
477 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
478 * Only the first 6 bytes must be valid as
479 * drm_edid_block_valid() can fix the last 2 bytes
480 */
481 if (drm_edid_header_is_valid(buf) < 6) {
482 /* Couldn't find an accessible EDID on this
483 * connector
484 */
485 return false;
486 }
487 return true;
488 }
489
490 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
491 .destroy = drm_gem_fb_destroy,
492 .create_handle = drm_gem_fb_create_handle,
493 };
494
amdgpu_display_supported_domains(struct amdgpu_device * adev,uint64_t bo_flags)495 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
496 uint64_t bo_flags)
497 {
498 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
499
500 #if defined(CONFIG_DRM_AMD_DC)
501 /*
502 * if amdgpu_bo_support_uswc returns false it means that USWC mappings
503 * is not supported for this board. But this mapping is required
504 * to avoid hang caused by placement of scanout BO in GTT on certain
505 * APUs. So force the BO placement to VRAM in case this architecture
506 * will not allow USWC mappings.
507 * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
508 */
509 if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
510 amdgpu_bo_support_uswc(bo_flags) &&
511 amdgpu_device_asic_has_dc_support(adev->asic_type)) {
512 switch (adev->asic_type) {
513 case CHIP_CARRIZO:
514 case CHIP_STONEY:
515 domain |= AMDGPU_GEM_DOMAIN_GTT;
516 break;
517 case CHIP_RAVEN:
518 /* enable S/G on PCO and RV2 */
519 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
520 (adev->apu_flags & AMD_APU_IS_PICASSO))
521 domain |= AMDGPU_GEM_DOMAIN_GTT;
522 break;
523 case CHIP_RENOIR:
524 case CHIP_VANGOGH:
525 case CHIP_YELLOW_CARP:
526 domain |= AMDGPU_GEM_DOMAIN_GTT;
527 break;
528
529 default:
530 break;
531 }
532 }
533 #endif
534
535 return domain;
536 }
537
538 static const struct drm_format_info dcc_formats[] = {
539 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
540 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
541 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
542 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
543 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
544 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
545 .has_alpha = true, },
546 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
547 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
548 .has_alpha = true, },
549 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
550 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
551 .has_alpha = true, },
552 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
553 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
554 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
555 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
556 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
557 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
558 .has_alpha = true, },
559 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
560 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
561 .has_alpha = true, },
562 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
563 .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
564 };
565
566 static const struct drm_format_info dcc_retile_formats[] = {
567 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
568 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
569 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
570 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
571 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
572 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
573 .has_alpha = true, },
574 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
575 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
576 .has_alpha = true, },
577 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
578 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
579 .has_alpha = true, },
580 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
581 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
582 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
583 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
584 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
585 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
586 .has_alpha = true, },
587 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
588 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
589 .has_alpha = true, },
590 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
591 .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
592 };
593
594 static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],int num_formats,u32 format)595 lookup_format_info(const struct drm_format_info formats[],
596 int num_formats, u32 format)
597 {
598 int i;
599
600 for (i = 0; i < num_formats; i++) {
601 if (formats[i].format == format)
602 return &formats[i];
603 }
604
605 return NULL;
606 }
607
608 const struct drm_format_info *
amdgpu_lookup_format_info(u32 format,uint64_t modifier)609 amdgpu_lookup_format_info(u32 format, uint64_t modifier)
610 {
611 if (!IS_AMD_FMT_MOD(modifier))
612 return NULL;
613
614 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
615 return lookup_format_info(dcc_retile_formats,
616 ARRAY_SIZE(dcc_retile_formats),
617 format);
618
619 if (AMD_FMT_MOD_GET(DCC, modifier))
620 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
621 format);
622
623 /* returning NULL will cause the default format structs to be used. */
624 return NULL;
625 }
626
627
628 /*
629 * Tries to extract the renderable DCC offset from the opaque metadata attached
630 * to the buffer.
631 */
632 static int
extract_render_dcc_offset(struct amdgpu_device * adev,struct drm_gem_object * obj,uint64_t * offset)633 extract_render_dcc_offset(struct amdgpu_device *adev,
634 struct drm_gem_object *obj,
635 uint64_t *offset)
636 {
637 struct amdgpu_bo *rbo;
638 int r = 0;
639 uint32_t metadata[10]; /* Something that fits a descriptor + header. */
640 uint32_t size;
641
642 rbo = gem_to_amdgpu_bo(obj);
643 r = amdgpu_bo_reserve(rbo, false);
644
645 if (unlikely(r)) {
646 /* Don't show error message when returning -ERESTARTSYS */
647 if (r != -ERESTARTSYS)
648 DRM_ERROR("Unable to reserve buffer: %d\n", r);
649 return r;
650 }
651
652 r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
653 amdgpu_bo_unreserve(rbo);
654
655 if (r)
656 return r;
657
658 /*
659 * The first word is the metadata version, and we need space for at least
660 * the version + pci vendor+device id + 8 words for a descriptor.
661 */
662 if (size < 40 || metadata[0] != 1)
663 return -EINVAL;
664
665 if (adev->family >= AMDGPU_FAMILY_NV) {
666 /* resource word 6/7 META_DATA_ADDRESS{_LO} */
667 *offset = ((u64)metadata[9] << 16u) |
668 ((metadata[8] & 0xFF000000u) >> 16);
669 } else {
670 /* resource word 5/7 META_DATA_ADDRESS */
671 *offset = ((u64)metadata[9] << 8u) |
672 ((u64)(metadata[7] & 0x1FE0000u) << 23);
673 }
674
675 return 0;
676 }
677
convert_tiling_flags_to_modifier(struct amdgpu_framebuffer * afb)678 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
679 {
680 struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
681 uint64_t modifier = 0;
682
683 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
684 modifier = DRM_FORMAT_MOD_LINEAR;
685 } else {
686 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
687 bool has_xor = swizzle >= 16;
688 int block_size_bits;
689 int version;
690 int pipe_xor_bits = 0;
691 int bank_xor_bits = 0;
692 int packers = 0;
693 int rb = 0;
694 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
695 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
696
697 switch (swizzle >> 2) {
698 case 0: /* 256B */
699 block_size_bits = 8;
700 break;
701 case 1: /* 4KiB */
702 case 5: /* 4KiB _X */
703 block_size_bits = 12;
704 break;
705 case 2: /* 64KiB */
706 case 4: /* 64 KiB _T */
707 case 6: /* 64 KiB _X */
708 block_size_bits = 16;
709 break;
710 default:
711 /* RESERVED or VAR */
712 return -EINVAL;
713 }
714
715 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
716 version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
717 else if (adev->family == AMDGPU_FAMILY_NV)
718 version = AMD_FMT_MOD_TILE_VER_GFX10;
719 else
720 version = AMD_FMT_MOD_TILE_VER_GFX9;
721
722 switch (swizzle & 3) {
723 case 0: /* Z microtiling */
724 return -EINVAL;
725 case 1: /* S microtiling */
726 if (!has_xor)
727 version = AMD_FMT_MOD_TILE_VER_GFX9;
728 break;
729 case 2:
730 if (!has_xor && afb->base.format->cpp[0] != 4)
731 version = AMD_FMT_MOD_TILE_VER_GFX9;
732 break;
733 case 3:
734 break;
735 }
736
737 if (has_xor) {
738 switch (version) {
739 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
740 pipe_xor_bits = min(block_size_bits - 8, pipes);
741 packers = min(block_size_bits - 8 - pipe_xor_bits,
742 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
743 break;
744 case AMD_FMT_MOD_TILE_VER_GFX10:
745 pipe_xor_bits = min(block_size_bits - 8, pipes);
746 break;
747 case AMD_FMT_MOD_TILE_VER_GFX9:
748 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
749 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
750 pipe_xor_bits = min(block_size_bits - 8, pipes +
751 ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
752 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
753 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
754 break;
755 }
756 }
757
758 modifier = AMD_FMT_MOD |
759 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
760 AMD_FMT_MOD_SET(TILE_VERSION, version) |
761 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
762 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
763 AMD_FMT_MOD_SET(PACKERS, packers);
764
765 if (dcc_offset != 0) {
766 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
767 bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
768 const struct drm_format_info *format_info;
769 u64 render_dcc_offset;
770
771 /* Enable constant encode on RAVEN2 and later. */
772 bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN ||
773 (adev->asic_type == CHIP_RAVEN &&
774 adev->external_rev_id >= 0x81);
775
776 int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
777 dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
778 AMD_FMT_MOD_DCC_BLOCK_256B;
779
780 modifier |= AMD_FMT_MOD_SET(DCC, 1) |
781 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
782 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
783 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
784 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
785
786 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
787 afb->base.pitches[1] =
788 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
789
790 /*
791 * If the userspace driver uses retiling the tiling flags do not contain
792 * info on the renderable DCC buffer. Luckily the opaque metadata contains
793 * the info so we can try to extract it. The kernel does not use this info
794 * but we should convert it to a modifier plane for getfb2, so the
795 * userspace driver that gets it doesn't have to juggle around another DCC
796 * plane internally.
797 */
798 if (extract_render_dcc_offset(adev, afb->base.obj[0],
799 &render_dcc_offset) == 0 &&
800 render_dcc_offset != 0 &&
801 render_dcc_offset != afb->base.offsets[1] &&
802 render_dcc_offset < UINT_MAX) {
803 uint32_t dcc_block_bits; /* of base surface data */
804
805 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
806 afb->base.offsets[2] = render_dcc_offset;
807
808 if (adev->family >= AMDGPU_FAMILY_NV) {
809 int extra_pipe = 0;
810
811 if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
812 pipes == packers && pipes > 1)
813 extra_pipe = 1;
814
815 dcc_block_bits = max(20, 16 + pipes + extra_pipe);
816 } else {
817 modifier |= AMD_FMT_MOD_SET(RB, rb) |
818 AMD_FMT_MOD_SET(PIPE, pipes);
819 dcc_block_bits = max(20, 18 + rb);
820 }
821
822 dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
823 afb->base.pitches[2] = ALIGN(afb->base.width,
824 1u << ((dcc_block_bits + 1) / 2));
825 }
826 format_info = amdgpu_lookup_format_info(afb->base.format->format,
827 modifier);
828 if (!format_info)
829 return -EINVAL;
830
831 afb->base.format = format_info;
832 }
833 }
834
835 afb->base.modifier = modifier;
836 afb->base.flags |= DRM_MODE_FB_MODIFIERS;
837 return 0;
838 }
839
840 /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
check_tiling_flags_gfx6(struct amdgpu_framebuffer * afb)841 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
842 {
843 u64 micro_tile_mode;
844
845 /* Zero swizzle mode means linear */
846 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)
847 return 0;
848
849 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
850 switch (micro_tile_mode) {
851 case 0: /* DISPLAY */
852 case 3: /* RENDER */
853 return 0;
854 default:
855 drm_dbg_kms(afb->base.dev,
856 "Micro tile mode %llu not supported for scanout\n",
857 micro_tile_mode);
858 return -EINVAL;
859 }
860 }
861
get_block_dimensions(unsigned int block_log2,unsigned int cpp,unsigned int * width,unsigned int * height)862 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
863 unsigned int *width, unsigned int *height)
864 {
865 unsigned int cpp_log2 = ilog2(cpp);
866 unsigned int pixel_log2 = block_log2 - cpp_log2;
867 unsigned int width_log2 = (pixel_log2 + 1) / 2;
868 unsigned int height_log2 = pixel_log2 - width_log2;
869
870 *width = 1 << width_log2;
871 *height = 1 << height_log2;
872 }
873
get_dcc_block_size(uint64_t modifier,bool rb_aligned,bool pipe_aligned)874 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
875 bool pipe_aligned)
876 {
877 unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
878
879 switch (ver) {
880 case AMD_FMT_MOD_TILE_VER_GFX9: {
881 /*
882 * TODO: for pipe aligned we may need to check the alignment of the
883 * total size of the surface, which may need to be bigger than the
884 * natural alignment due to some HW workarounds
885 */
886 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
887 }
888 case AMD_FMT_MOD_TILE_VER_GFX10:
889 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: {
890 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
891
892 if (ver == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
893 AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
894 ++pipes_log2;
895
896 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12);
897 }
898 default:
899 return 0;
900 }
901 }
902
amdgpu_display_verify_plane(struct amdgpu_framebuffer * rfb,int plane,const struct drm_format_info * format,unsigned int block_width,unsigned int block_height,unsigned int block_size_log2)903 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,
904 const struct drm_format_info *format,
905 unsigned int block_width, unsigned int block_height,
906 unsigned int block_size_log2)
907 {
908 unsigned int width = rfb->base.width /
909 ((plane && plane < format->num_planes) ? format->hsub : 1);
910 unsigned int height = rfb->base.height /
911 ((plane && plane < format->num_planes) ? format->vsub : 1);
912 unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;
913 unsigned int block_pitch = block_width * cpp;
914 unsigned int min_pitch = ALIGN(width * cpp, block_pitch);
915 unsigned int block_size = 1 << block_size_log2;
916 uint64_t size;
917
918 if (rfb->base.pitches[plane] % block_pitch) {
919 drm_dbg_kms(rfb->base.dev,
920 "pitch %d for plane %d is not a multiple of block pitch %d\n",
921 rfb->base.pitches[plane], plane, block_pitch);
922 return -EINVAL;
923 }
924 if (rfb->base.pitches[plane] < min_pitch) {
925 drm_dbg_kms(rfb->base.dev,
926 "pitch %d for plane %d is less than minimum pitch %d\n",
927 rfb->base.pitches[plane], plane, min_pitch);
928 return -EINVAL;
929 }
930
931 /* Force at least natural alignment. */
932 if (rfb->base.offsets[plane] % block_size) {
933 drm_dbg_kms(rfb->base.dev,
934 "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
935 rfb->base.offsets[plane], plane, block_size);
936 return -EINVAL;
937 }
938
939 size = rfb->base.offsets[plane] +
940 (uint64_t)rfb->base.pitches[plane] / block_pitch *
941 block_size * DIV_ROUND_UP(height, block_height);
942
943 if (rfb->base.obj[0]->size < size) {
944 drm_dbg_kms(rfb->base.dev,
945 "BO size 0x%zx is less than 0x%llx required for plane %d\n",
946 rfb->base.obj[0]->size, size, plane);
947 return -EINVAL;
948 }
949
950 return 0;
951 }
952
953
amdgpu_display_verify_sizes(struct amdgpu_framebuffer * rfb)954 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
955 {
956 const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);
957 uint64_t modifier = rfb->base.modifier;
958 int ret;
959 unsigned int i, block_width, block_height, block_size_log2;
960
961 if (!rfb->base.dev->mode_config.allow_fb_modifiers)
962 return 0;
963
964 for (i = 0; i < format_info->num_planes; ++i) {
965 if (modifier == DRM_FORMAT_MOD_LINEAR) {
966 block_width = 256 / format_info->cpp[i];
967 block_height = 1;
968 block_size_log2 = 8;
969 } else {
970 int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
971
972 switch ((swizzle & ~3) + 1) {
973 case DC_SW_256B_S:
974 block_size_log2 = 8;
975 break;
976 case DC_SW_4KB_S:
977 case DC_SW_4KB_S_X:
978 block_size_log2 = 12;
979 break;
980 case DC_SW_64KB_S:
981 case DC_SW_64KB_S_T:
982 case DC_SW_64KB_S_X:
983 block_size_log2 = 16;
984 break;
985 default:
986 drm_dbg_kms(rfb->base.dev,
987 "Swizzle mode with unknown block size: %d\n", swizzle);
988 return -EINVAL;
989 }
990
991 get_block_dimensions(block_size_log2, format_info->cpp[i],
992 &block_width, &block_height);
993 }
994
995 ret = amdgpu_display_verify_plane(rfb, i, format_info,
996 block_width, block_height, block_size_log2);
997 if (ret)
998 return ret;
999 }
1000
1001 if (AMD_FMT_MOD_GET(DCC, modifier)) {
1002 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
1003 block_size_log2 = get_dcc_block_size(modifier, false, false);
1004 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1005 &block_width, &block_height);
1006 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1007 block_width, block_height,
1008 block_size_log2);
1009 if (ret)
1010 return ret;
1011
1012 ++i;
1013 block_size_log2 = get_dcc_block_size(modifier, true, true);
1014 } else {
1015 bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
1016
1017 block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
1018 }
1019 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1020 &block_width, &block_height);
1021 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1022 block_width, block_height, block_size_log2);
1023 if (ret)
1024 return ret;
1025 }
1026
1027 return 0;
1028 }
1029
amdgpu_display_get_fb_info(const struct amdgpu_framebuffer * amdgpu_fb,uint64_t * tiling_flags,bool * tmz_surface)1030 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1031 uint64_t *tiling_flags, bool *tmz_surface)
1032 {
1033 struct amdgpu_bo *rbo;
1034 int r;
1035
1036 if (!amdgpu_fb) {
1037 *tiling_flags = 0;
1038 *tmz_surface = false;
1039 return 0;
1040 }
1041
1042 rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1043 r = amdgpu_bo_reserve(rbo, false);
1044
1045 if (unlikely(r)) {
1046 /* Don't show error message when returning -ERESTARTSYS */
1047 if (r != -ERESTARTSYS)
1048 DRM_ERROR("Unable to reserve buffer: %d\n", r);
1049 return r;
1050 }
1051
1052 if (tiling_flags)
1053 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1054
1055 if (tmz_surface)
1056 *tmz_surface = amdgpu_bo_encrypted(rbo);
1057
1058 amdgpu_bo_unreserve(rbo);
1059
1060 return r;
1061 }
1062
amdgpu_display_gem_fb_init(struct drm_device * dev,struct amdgpu_framebuffer * rfb,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1063 int amdgpu_display_gem_fb_init(struct drm_device *dev,
1064 struct amdgpu_framebuffer *rfb,
1065 const struct drm_mode_fb_cmd2 *mode_cmd,
1066 struct drm_gem_object *obj)
1067 {
1068 int ret;
1069
1070 rfb->base.obj[0] = obj;
1071 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1072
1073 ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1074 if (ret)
1075 goto err;
1076
1077 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1078 if (ret)
1079 goto err;
1080
1081 return 0;
1082 err:
1083 drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret);
1084 rfb->base.obj[0] = NULL;
1085 return ret;
1086 }
1087
amdgpu_display_gem_fb_verify_and_init(struct drm_device * dev,struct amdgpu_framebuffer * rfb,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1088 int amdgpu_display_gem_fb_verify_and_init(
1089 struct drm_device *dev, struct amdgpu_framebuffer *rfb,
1090 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd,
1091 struct drm_gem_object *obj)
1092 {
1093 int ret;
1094
1095 rfb->base.obj[0] = obj;
1096 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1097 /* Verify that the modifier is supported. */
1098 if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
1099 mode_cmd->modifier[0])) {
1100 drm_dbg_kms(dev,
1101 "unsupported pixel format %p4cc / modifier 0x%llx\n",
1102 &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1103
1104 ret = -EINVAL;
1105 goto err;
1106 }
1107
1108 ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1109 if (ret)
1110 goto err;
1111
1112 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1113
1114 if (ret)
1115 goto err;
1116
1117 return 0;
1118 err:
1119 drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
1120 rfb->base.obj[0] = NULL;
1121 return ret;
1122 }
1123
amdgpu_display_framebuffer_init(struct drm_device * dev,struct amdgpu_framebuffer * rfb,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1124 int amdgpu_display_framebuffer_init(struct drm_device *dev,
1125 struct amdgpu_framebuffer *rfb,
1126 const struct drm_mode_fb_cmd2 *mode_cmd,
1127 struct drm_gem_object *obj)
1128 {
1129 struct amdgpu_device *adev = drm_to_adev(dev);
1130 int ret, i;
1131
1132 /*
1133 * This needs to happen before modifier conversion as that might change
1134 * the number of planes.
1135 */
1136 for (i = 1; i < rfb->base.format->num_planes; ++i) {
1137 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1138 drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
1139 i, mode_cmd->handles[0], mode_cmd->handles[i]);
1140 ret = -EINVAL;
1141 return ret;
1142 }
1143 }
1144
1145 ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
1146 if (ret)
1147 return ret;
1148
1149 if (!dev->mode_config.allow_fb_modifiers && !adev->enable_virtual_display) {
1150 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
1151 "GFX9+ requires FB check based on format modifier\n");
1152 ret = check_tiling_flags_gfx6(rfb);
1153 if (ret)
1154 return ret;
1155 }
1156
1157 if (dev->mode_config.allow_fb_modifiers &&
1158 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
1159 ret = convert_tiling_flags_to_modifier(rfb);
1160 if (ret) {
1161 drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
1162 rfb->tiling_flags);
1163 return ret;
1164 }
1165 }
1166
1167 ret = amdgpu_display_verify_sizes(rfb);
1168 if (ret)
1169 return ret;
1170
1171 for (i = 0; i < rfb->base.format->num_planes; ++i) {
1172 drm_gem_object_get(rfb->base.obj[0]);
1173 rfb->base.obj[i] = rfb->base.obj[0];
1174 }
1175
1176 return 0;
1177 }
1178
1179 struct drm_framebuffer *
amdgpu_display_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd)1180 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
1181 struct drm_file *file_priv,
1182 const struct drm_mode_fb_cmd2 *mode_cmd)
1183 {
1184 struct amdgpu_framebuffer *amdgpu_fb;
1185 struct drm_gem_object *obj;
1186 struct amdgpu_bo *bo;
1187 uint32_t domains;
1188 int ret;
1189
1190 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1191 if (obj == NULL) {
1192 drm_dbg_kms(dev,
1193 "No GEM object associated to handle 0x%08X, can't create framebuffer\n",
1194 mode_cmd->handles[0]);
1195
1196 return ERR_PTR(-ENOENT);
1197 }
1198
1199 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1200 bo = gem_to_amdgpu_bo(obj);
1201 domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1202 if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1203 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1204 drm_gem_object_put(obj);
1205 return ERR_PTR(-EINVAL);
1206 }
1207
1208 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1209 if (amdgpu_fb == NULL) {
1210 drm_gem_object_put(obj);
1211 return ERR_PTR(-ENOMEM);
1212 }
1213
1214 ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1215 mode_cmd, obj);
1216 if (ret) {
1217 kfree(amdgpu_fb);
1218 drm_gem_object_put(obj);
1219 return ERR_PTR(ret);
1220 }
1221
1222 drm_gem_object_put(obj);
1223 return &amdgpu_fb->base;
1224 }
1225
1226 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
1227 .fb_create = amdgpu_display_user_framebuffer_create,
1228 .output_poll_changed = drm_fb_helper_output_poll_changed,
1229 };
1230
1231 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
1232 { { UNDERSCAN_OFF, "off" },
1233 { UNDERSCAN_ON, "on" },
1234 { UNDERSCAN_AUTO, "auto" },
1235 };
1236
1237 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
1238 { { AMDGPU_AUDIO_DISABLE, "off" },
1239 { AMDGPU_AUDIO_ENABLE, "on" },
1240 { AMDGPU_AUDIO_AUTO, "auto" },
1241 };
1242
1243 /* XXX support different dither options? spatial, temporal, both, etc. */
1244 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
1245 { { AMDGPU_FMT_DITHER_DISABLE, "off" },
1246 { AMDGPU_FMT_DITHER_ENABLE, "on" },
1247 };
1248
amdgpu_display_modeset_create_props(struct amdgpu_device * adev)1249 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1250 {
1251 int sz;
1252
1253 adev->mode_info.coherent_mode_property =
1254 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1255 if (!adev->mode_info.coherent_mode_property)
1256 return -ENOMEM;
1257
1258 adev->mode_info.load_detect_property =
1259 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1260 if (!adev->mode_info.load_detect_property)
1261 return -ENOMEM;
1262
1263 drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1264
1265 sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1266 adev->mode_info.underscan_property =
1267 drm_property_create_enum(adev_to_drm(adev), 0,
1268 "underscan",
1269 amdgpu_underscan_enum_list, sz);
1270
1271 adev->mode_info.underscan_hborder_property =
1272 drm_property_create_range(adev_to_drm(adev), 0,
1273 "underscan hborder", 0, 128);
1274 if (!adev->mode_info.underscan_hborder_property)
1275 return -ENOMEM;
1276
1277 adev->mode_info.underscan_vborder_property =
1278 drm_property_create_range(adev_to_drm(adev), 0,
1279 "underscan vborder", 0, 128);
1280 if (!adev->mode_info.underscan_vborder_property)
1281 return -ENOMEM;
1282
1283 sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1284 adev->mode_info.audio_property =
1285 drm_property_create_enum(adev_to_drm(adev), 0,
1286 "audio",
1287 amdgpu_audio_enum_list, sz);
1288
1289 sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1290 adev->mode_info.dither_property =
1291 drm_property_create_enum(adev_to_drm(adev), 0,
1292 "dither",
1293 amdgpu_dither_enum_list, sz);
1294
1295 if (amdgpu_device_has_dc_support(adev)) {
1296 adev->mode_info.abm_level_property =
1297 drm_property_create_range(adev_to_drm(adev), 0,
1298 "abm level", 0, 4);
1299 if (!adev->mode_info.abm_level_property)
1300 return -ENOMEM;
1301 }
1302
1303 return 0;
1304 }
1305
amdgpu_display_update_priority(struct amdgpu_device * adev)1306 void amdgpu_display_update_priority(struct amdgpu_device *adev)
1307 {
1308 /* adjustment options for the display watermarks */
1309 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1310 adev->mode_info.disp_priority = 0;
1311 else
1312 adev->mode_info.disp_priority = amdgpu_disp_priority;
1313
1314 }
1315
amdgpu_display_is_hdtv_mode(const struct drm_display_mode * mode)1316 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1317 {
1318 /* try and guess if this is a tv or a monitor */
1319 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1320 (mode->vdisplay == 576) || /* 576p */
1321 (mode->vdisplay == 720) || /* 720p */
1322 (mode->vdisplay == 1080)) /* 1080p */
1323 return true;
1324 else
1325 return false;
1326 }
1327
amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1328 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1329 const struct drm_display_mode *mode,
1330 struct drm_display_mode *adjusted_mode)
1331 {
1332 struct drm_device *dev = crtc->dev;
1333 struct drm_encoder *encoder;
1334 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1335 struct amdgpu_encoder *amdgpu_encoder;
1336 struct drm_connector *connector;
1337 u32 src_v = 1, dst_v = 1;
1338 u32 src_h = 1, dst_h = 1;
1339
1340 amdgpu_crtc->h_border = 0;
1341 amdgpu_crtc->v_border = 0;
1342
1343 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1344 if (encoder->crtc != crtc)
1345 continue;
1346 amdgpu_encoder = to_amdgpu_encoder(encoder);
1347 connector = amdgpu_get_connector_for_encoder(encoder);
1348
1349 /* set scaling */
1350 if (amdgpu_encoder->rmx_type == RMX_OFF)
1351 amdgpu_crtc->rmx_type = RMX_OFF;
1352 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1353 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1354 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1355 else
1356 amdgpu_crtc->rmx_type = RMX_OFF;
1357 /* copy native mode */
1358 memcpy(&amdgpu_crtc->native_mode,
1359 &amdgpu_encoder->native_mode,
1360 sizeof(struct drm_display_mode));
1361 src_v = crtc->mode.vdisplay;
1362 dst_v = amdgpu_crtc->native_mode.vdisplay;
1363 src_h = crtc->mode.hdisplay;
1364 dst_h = amdgpu_crtc->native_mode.hdisplay;
1365
1366 /* fix up for overscan on hdmi */
1367 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1368 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1369 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1370 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
1371 amdgpu_display_is_hdtv_mode(mode)))) {
1372 if (amdgpu_encoder->underscan_hborder != 0)
1373 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1374 else
1375 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1376 if (amdgpu_encoder->underscan_vborder != 0)
1377 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1378 else
1379 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1380 amdgpu_crtc->rmx_type = RMX_FULL;
1381 src_v = crtc->mode.vdisplay;
1382 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1383 src_h = crtc->mode.hdisplay;
1384 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1385 }
1386 }
1387 if (amdgpu_crtc->rmx_type != RMX_OFF) {
1388 fixed20_12 a, b;
1389
1390 a.full = dfixed_const(src_v);
1391 b.full = dfixed_const(dst_v);
1392 amdgpu_crtc->vsc.full = dfixed_div(a, b);
1393 a.full = dfixed_const(src_h);
1394 b.full = dfixed_const(dst_h);
1395 amdgpu_crtc->hsc.full = dfixed_div(a, b);
1396 } else {
1397 amdgpu_crtc->vsc.full = dfixed_const(1);
1398 amdgpu_crtc->hsc.full = dfixed_const(1);
1399 }
1400 return true;
1401 }
1402
1403 /*
1404 * Retrieve current video scanout position of crtc on a given gpu, and
1405 * an optional accurate timestamp of when query happened.
1406 *
1407 * \param dev Device to query.
1408 * \param pipe Crtc to query.
1409 * \param flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1410 * For driver internal use only also supports these flags:
1411 *
1412 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1413 * of a fudged earlier start of vblank.
1414 *
1415 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1416 * fudged earlier start of vblank in *vpos and the distance
1417 * to true start of vblank in *hpos.
1418 *
1419 * \param *vpos Location where vertical scanout position should be stored.
1420 * \param *hpos Location where horizontal scanout position should go.
1421 * \param *stime Target location for timestamp taken immediately before
1422 * scanout position query. Can be NULL to skip timestamp.
1423 * \param *etime Target location for timestamp taken immediately after
1424 * scanout position query. Can be NULL to skip timestamp.
1425 *
1426 * Returns vpos as a positive number while in active scanout area.
1427 * Returns vpos as a negative number inside vblank, counting the number
1428 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1429 * until start of active scanout / end of vblank."
1430 *
1431 * \return Flags, or'ed together as follows:
1432 *
1433 * DRM_SCANOUTPOS_VALID = Query successful.
1434 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1435 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1436 * this flag means that returned position may be offset by a constant but
1437 * unknown small number of scanlines wrt. real scanout position.
1438 *
1439 */
amdgpu_display_get_crtc_scanoutpos(struct drm_device * dev,unsigned int pipe,unsigned int flags,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1440 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1441 unsigned int pipe, unsigned int flags, int *vpos,
1442 int *hpos, ktime_t *stime, ktime_t *etime,
1443 const struct drm_display_mode *mode)
1444 {
1445 u32 vbl = 0, position = 0;
1446 int vbl_start, vbl_end, vtotal, ret = 0;
1447 bool in_vbl = true;
1448
1449 struct amdgpu_device *adev = drm_to_adev(dev);
1450
1451 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1452
1453 /* Get optional system timestamp before query. */
1454 if (stime)
1455 *stime = ktime_get();
1456
1457 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1458 ret |= DRM_SCANOUTPOS_VALID;
1459
1460 /* Get optional system timestamp after query. */
1461 if (etime)
1462 *etime = ktime_get();
1463
1464 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1465
1466 /* Decode into vertical and horizontal scanout position. */
1467 *vpos = position & 0x1fff;
1468 *hpos = (position >> 16) & 0x1fff;
1469
1470 /* Valid vblank area boundaries from gpu retrieved? */
1471 if (vbl > 0) {
1472 /* Yes: Decode. */
1473 ret |= DRM_SCANOUTPOS_ACCURATE;
1474 vbl_start = vbl & 0x1fff;
1475 vbl_end = (vbl >> 16) & 0x1fff;
1476 }
1477 else {
1478 /* No: Fake something reasonable which gives at least ok results. */
1479 vbl_start = mode->crtc_vdisplay;
1480 vbl_end = 0;
1481 }
1482
1483 /* Called from driver internal vblank counter query code? */
1484 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1485 /* Caller wants distance from real vbl_start in *hpos */
1486 *hpos = *vpos - vbl_start;
1487 }
1488
1489 /* Fudge vblank to start a few scanlines earlier to handle the
1490 * problem that vblank irqs fire a few scanlines before start
1491 * of vblank. Some driver internal callers need the true vblank
1492 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1493 *
1494 * The cause of the "early" vblank irq is that the irq is triggered
1495 * by the line buffer logic when the line buffer read position enters
1496 * the vblank, whereas our crtc scanout position naturally lags the
1497 * line buffer read position.
1498 */
1499 if (!(flags & USE_REAL_VBLANKSTART))
1500 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1501
1502 /* Test scanout position against vblank region. */
1503 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1504 in_vbl = false;
1505
1506 /* In vblank? */
1507 if (in_vbl)
1508 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1509
1510 /* Called from driver internal vblank counter query code? */
1511 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1512 /* Caller wants distance from fudged earlier vbl_start */
1513 *vpos -= vbl_start;
1514 return ret;
1515 }
1516
1517 /* Check if inside vblank area and apply corrective offsets:
1518 * vpos will then be >=0 in video scanout area, but negative
1519 * within vblank area, counting down the number of lines until
1520 * start of scanout.
1521 */
1522
1523 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1524 if (in_vbl && (*vpos >= vbl_start)) {
1525 vtotal = mode->crtc_vtotal;
1526
1527 /* With variable refresh rate displays the vpos can exceed
1528 * the vtotal value. Clamp to 0 to return -vbl_end instead
1529 * of guessing the remaining number of lines until scanout.
1530 */
1531 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1532 }
1533
1534 /* Correct for shifted end of vbl at vbl_end. */
1535 *vpos = *vpos - vbl_end;
1536
1537 return ret;
1538 }
1539
amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device * adev,int crtc)1540 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1541 {
1542 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1543 return AMDGPU_CRTC_IRQ_NONE;
1544
1545 switch (crtc) {
1546 case 0:
1547 return AMDGPU_CRTC_IRQ_VBLANK1;
1548 case 1:
1549 return AMDGPU_CRTC_IRQ_VBLANK2;
1550 case 2:
1551 return AMDGPU_CRTC_IRQ_VBLANK3;
1552 case 3:
1553 return AMDGPU_CRTC_IRQ_VBLANK4;
1554 case 4:
1555 return AMDGPU_CRTC_IRQ_VBLANK5;
1556 case 5:
1557 return AMDGPU_CRTC_IRQ_VBLANK6;
1558 default:
1559 return AMDGPU_CRTC_IRQ_NONE;
1560 }
1561 }
1562
amdgpu_crtc_get_scanout_position(struct drm_crtc * crtc,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1563 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1564 bool in_vblank_irq, int *vpos,
1565 int *hpos, ktime_t *stime, ktime_t *etime,
1566 const struct drm_display_mode *mode)
1567 {
1568 struct drm_device *dev = crtc->dev;
1569 unsigned int pipe = crtc->index;
1570
1571 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1572 stime, etime, mode);
1573 }
1574
amdgpu_display_suspend_helper(struct amdgpu_device * adev)1575 int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1576 {
1577 struct drm_device *dev = adev_to_drm(adev);
1578 struct drm_crtc *crtc;
1579 struct drm_connector *connector;
1580 struct drm_connector_list_iter iter;
1581 int r;
1582
1583 /* turn off display hw */
1584 drm_modeset_lock_all(dev);
1585 drm_connector_list_iter_begin(dev, &iter);
1586 drm_for_each_connector_iter(connector, &iter)
1587 drm_helper_connector_dpms(connector,
1588 DRM_MODE_DPMS_OFF);
1589 drm_connector_list_iter_end(&iter);
1590 drm_modeset_unlock_all(dev);
1591 /* unpin the front buffers and cursors */
1592 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1593 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1594 struct drm_framebuffer *fb = crtc->primary->fb;
1595 struct amdgpu_bo *robj;
1596
1597 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1598 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1599
1600 r = amdgpu_bo_reserve(aobj, true);
1601 if (r == 0) {
1602 amdgpu_bo_unpin(aobj);
1603 amdgpu_bo_unreserve(aobj);
1604 }
1605 }
1606
1607 if (!fb || !fb->obj[0])
1608 continue;
1609
1610 robj = gem_to_amdgpu_bo(fb->obj[0]);
1611 /* don't unpin kernel fb objects */
1612 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1613 r = amdgpu_bo_reserve(robj, true);
1614 if (r == 0) {
1615 amdgpu_bo_unpin(robj);
1616 amdgpu_bo_unreserve(robj);
1617 }
1618 }
1619 }
1620 return 0;
1621 }
1622
amdgpu_display_resume_helper(struct amdgpu_device * adev)1623 int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1624 {
1625 struct drm_device *dev = adev_to_drm(adev);
1626 struct drm_connector *connector;
1627 struct drm_connector_list_iter iter;
1628 struct drm_crtc *crtc;
1629 int r;
1630
1631 /* pin cursors */
1632 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1633 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1634
1635 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1636 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1637
1638 r = amdgpu_bo_reserve(aobj, true);
1639 if (r == 0) {
1640 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1641 if (r != 0)
1642 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1643 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1644 amdgpu_bo_unreserve(aobj);
1645 }
1646 }
1647 }
1648
1649 drm_helper_resume_force_mode(dev);
1650
1651 /* turn on display hw */
1652 drm_modeset_lock_all(dev);
1653
1654 drm_connector_list_iter_begin(dev, &iter);
1655 drm_for_each_connector_iter(connector, &iter)
1656 drm_helper_connector_dpms(connector,
1657 DRM_MODE_DPMS_ON);
1658 drm_connector_list_iter_end(&iter);
1659
1660 drm_modeset_unlock_all(dev);
1661
1662 return 0;
1663 }
1664
1665