1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include "amdgpu.h"
30 #include <drm/amdgpu_drm.h>
31 #include <drm/drm_drv.h>
32 #include "amdgpu_uvd.h"
33 #include "amdgpu_vce.h"
34 #include "atom.h"
35
36 #include <linux/vga_switcheroo.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pci.h>
40 #include <linux/pm_runtime.h>
41 #include "amdgpu_amdkfd.h"
42 #include "amdgpu_gem.h"
43 #include "amdgpu_display.h"
44 #include "amdgpu_ras.h"
45
amdgpu_runtime_pm_quirk(struct amdgpu_device * adev)46 static void amdgpu_runtime_pm_quirk(struct amdgpu_device *adev)
47 {
48 /*
49 * Add below quirk on several sienna_cichlid cards to disable
50 * runtime pm to fix EMI failures.
51 */
52 if (((adev->pdev->device == 0x73A1) && (adev->pdev->revision == 0x00)) ||
53 ((adev->pdev->device == 0x73BF) && (adev->pdev->revision == 0xCF)))
54 adev->runpm = false;
55 }
56
amdgpu_unregister_gpu_instance(struct amdgpu_device * adev)57 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
58 {
59 struct amdgpu_gpu_instance *gpu_instance;
60 int i;
61
62 mutex_lock(&mgpu_info.mutex);
63
64 for (i = 0; i < mgpu_info.num_gpu; i++) {
65 gpu_instance = &(mgpu_info.gpu_ins[i]);
66 if (gpu_instance->adev == adev) {
67 mgpu_info.gpu_ins[i] =
68 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
69 mgpu_info.num_gpu--;
70 if (adev->flags & AMD_IS_APU)
71 mgpu_info.num_apu--;
72 else
73 mgpu_info.num_dgpu--;
74 break;
75 }
76 }
77
78 mutex_unlock(&mgpu_info.mutex);
79 }
80
81 /**
82 * amdgpu_driver_unload_kms - Main unload function for KMS.
83 *
84 * @dev: drm dev pointer
85 *
86 * This is the main unload function for KMS (all asics).
87 * Returns 0 on success.
88 */
amdgpu_driver_unload_kms(struct drm_device * dev)89 void amdgpu_driver_unload_kms(struct drm_device *dev)
90 {
91 struct amdgpu_device *adev = drm_to_adev(dev);
92
93 if (adev == NULL)
94 return;
95
96 amdgpu_unregister_gpu_instance(adev);
97
98 if (adev->rmmio == NULL)
99 return;
100
101 if (adev->runpm) {
102 pm_runtime_get_sync(dev->dev);
103 pm_runtime_forbid(dev->dev);
104 }
105
106 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
107 DRM_WARN("smart shift update failed\n");
108
109 amdgpu_acpi_fini(adev);
110 amdgpu_device_fini_hw(adev);
111 }
112
amdgpu_register_gpu_instance(struct amdgpu_device * adev)113 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
114 {
115 struct amdgpu_gpu_instance *gpu_instance;
116
117 mutex_lock(&mgpu_info.mutex);
118
119 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
120 DRM_ERROR("Cannot register more gpu instance\n");
121 mutex_unlock(&mgpu_info.mutex);
122 return;
123 }
124
125 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
126 gpu_instance->adev = adev;
127 gpu_instance->mgpu_fan_enabled = 0;
128
129 mgpu_info.num_gpu++;
130 if (adev->flags & AMD_IS_APU)
131 mgpu_info.num_apu++;
132 else
133 mgpu_info.num_dgpu++;
134
135 mutex_unlock(&mgpu_info.mutex);
136 }
137
amdgpu_get_audio_func(struct amdgpu_device * adev)138 static void amdgpu_get_audio_func(struct amdgpu_device *adev)
139 {
140 struct pci_dev *p = NULL;
141
142 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
143 adev->pdev->bus->number, 1);
144 if (p) {
145 pm_runtime_get_sync(&p->dev);
146
147 pm_runtime_mark_last_busy(&p->dev);
148 pm_runtime_put_autosuspend(&p->dev);
149
150 pci_dev_put(p);
151 }
152 }
153
154 /**
155 * amdgpu_driver_load_kms - Main load function for KMS.
156 *
157 * @adev: pointer to struct amdgpu_device
158 * @flags: device flags
159 *
160 * This is the main load function for KMS (all asics).
161 * Returns 0 on success, error on failure.
162 */
amdgpu_driver_load_kms(struct amdgpu_device * adev,unsigned long flags)163 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
164 {
165 struct drm_device *dev;
166 int r, acpi_status;
167
168 dev = adev_to_drm(adev);
169
170 /* amdgpu_device_init should report only fatal error
171 * like memory allocation failure or iomapping failure,
172 * or memory manager initialization failure, it must
173 * properly initialize the GPU MC controller and permit
174 * VRAM allocation
175 */
176 r = amdgpu_device_init(adev, flags);
177 if (r) {
178 dev_err(dev->dev, "Fatal error during GPU init\n");
179 goto out;
180 }
181
182 if (amdgpu_device_supports_px(dev) &&
183 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */
184 adev->runpm = true;
185 dev_info(adev->dev, "Using ATPX for runtime pm\n");
186 } else if (amdgpu_device_supports_boco(dev) &&
187 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
188 adev->runpm = true;
189 dev_info(adev->dev, "Using BOCO for runtime pm\n");
190 } else if (amdgpu_device_supports_baco(dev) &&
191 (amdgpu_runtime_pm != 0)) {
192 switch (adev->asic_type) {
193 case CHIP_VEGA20:
194 case CHIP_ARCTURUS:
195 /* enable runpm if runpm=1 */
196 if (amdgpu_runtime_pm > 0)
197 adev->runpm = true;
198 break;
199 case CHIP_VEGA10:
200 /* turn runpm on if noretry=0 */
201 if (!adev->gmc.noretry)
202 adev->runpm = true;
203 break;
204 default:
205 /* enable runpm on CI+ */
206 adev->runpm = true;
207 break;
208 }
209 /* XXX: disable runtime pm if we are the primary adapter
210 * to avoid displays being re-enabled after DPMS.
211 * This needs to be sorted out and fixed properly.
212 */
213 if (adev->is_fw_fb)
214 adev->runpm = false;
215
216 amdgpu_runtime_pm_quirk(adev);
217
218 if (adev->runpm)
219 dev_info(adev->dev, "Using BACO for runtime pm\n");
220 }
221
222 /* Call ACPI methods: require modeset init
223 * but failure is not fatal
224 */
225
226 acpi_status = amdgpu_acpi_init(adev);
227 if (acpi_status)
228 dev_dbg(dev->dev, "Error during ACPI methods call\n");
229
230 if (adev->runpm) {
231 /* only need to skip on ATPX */
232 if (amdgpu_device_supports_px(dev))
233 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
234 /* we want direct complete for BOCO */
235 if (amdgpu_device_supports_boco(dev))
236 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_SMART_PREPARE |
237 DPM_FLAG_SMART_SUSPEND |
238 DPM_FLAG_MAY_SKIP_RESUME);
239 pm_runtime_use_autosuspend(dev->dev);
240 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
241
242 pm_runtime_allow(dev->dev);
243
244 pm_runtime_mark_last_busy(dev->dev);
245 pm_runtime_put_autosuspend(dev->dev);
246
247 /*
248 * For runpm implemented via BACO, PMFW will handle the
249 * timing for BACO in and out:
250 * - put ASIC into BACO state only when both video and
251 * audio functions are in D3 state.
252 * - pull ASIC out of BACO state when either video or
253 * audio function is in D0 state.
254 * Also, at startup, PMFW assumes both functions are in
255 * D0 state.
256 *
257 * So if snd driver was loaded prior to amdgpu driver
258 * and audio function was put into D3 state, there will
259 * be no PMFW-aware D-state transition(D0->D3) on runpm
260 * suspend. Thus the BACO will be not correctly kicked in.
261 *
262 * Via amdgpu_get_audio_func(), the audio dev is put
263 * into D0 state. Then there will be a PMFW-aware D-state
264 * transition(D0->D3) on runpm suspend.
265 */
266 if (amdgpu_device_supports_baco(dev) &&
267 !(adev->flags & AMD_IS_APU) &&
268 (adev->asic_type >= CHIP_NAVI10))
269 amdgpu_get_audio_func(adev);
270 }
271
272 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
273 DRM_WARN("smart shift update failed\n");
274
275 out:
276 if (r) {
277 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
278 if (adev->rmmio && adev->runpm)
279 pm_runtime_put_noidle(dev->dev);
280 amdgpu_driver_unload_kms(dev);
281 }
282
283 return r;
284 }
285
amdgpu_firmware_info(struct drm_amdgpu_info_firmware * fw_info,struct drm_amdgpu_query_fw * query_fw,struct amdgpu_device * adev)286 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
287 struct drm_amdgpu_query_fw *query_fw,
288 struct amdgpu_device *adev)
289 {
290 switch (query_fw->fw_type) {
291 case AMDGPU_INFO_FW_VCE:
292 fw_info->ver = adev->vce.fw_version;
293 fw_info->feature = adev->vce.fb_version;
294 break;
295 case AMDGPU_INFO_FW_UVD:
296 fw_info->ver = adev->uvd.fw_version;
297 fw_info->feature = 0;
298 break;
299 case AMDGPU_INFO_FW_VCN:
300 fw_info->ver = adev->vcn.fw_version;
301 fw_info->feature = 0;
302 break;
303 case AMDGPU_INFO_FW_GMC:
304 fw_info->ver = adev->gmc.fw_version;
305 fw_info->feature = 0;
306 break;
307 case AMDGPU_INFO_FW_GFX_ME:
308 fw_info->ver = adev->gfx.me_fw_version;
309 fw_info->feature = adev->gfx.me_feature_version;
310 break;
311 case AMDGPU_INFO_FW_GFX_PFP:
312 fw_info->ver = adev->gfx.pfp_fw_version;
313 fw_info->feature = adev->gfx.pfp_feature_version;
314 break;
315 case AMDGPU_INFO_FW_GFX_CE:
316 fw_info->ver = adev->gfx.ce_fw_version;
317 fw_info->feature = adev->gfx.ce_feature_version;
318 break;
319 case AMDGPU_INFO_FW_GFX_RLC:
320 fw_info->ver = adev->gfx.rlc_fw_version;
321 fw_info->feature = adev->gfx.rlc_feature_version;
322 break;
323 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
324 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
325 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
326 break;
327 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
328 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
329 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
330 break;
331 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
332 fw_info->ver = adev->gfx.rlc_srls_fw_version;
333 fw_info->feature = adev->gfx.rlc_srls_feature_version;
334 break;
335 case AMDGPU_INFO_FW_GFX_MEC:
336 if (query_fw->index == 0) {
337 fw_info->ver = adev->gfx.mec_fw_version;
338 fw_info->feature = adev->gfx.mec_feature_version;
339 } else if (query_fw->index == 1) {
340 fw_info->ver = adev->gfx.mec2_fw_version;
341 fw_info->feature = adev->gfx.mec2_feature_version;
342 } else
343 return -EINVAL;
344 break;
345 case AMDGPU_INFO_FW_SMC:
346 fw_info->ver = adev->pm.fw_version;
347 fw_info->feature = 0;
348 break;
349 case AMDGPU_INFO_FW_TA:
350 switch (query_fw->index) {
351 case TA_FW_TYPE_PSP_XGMI:
352 fw_info->ver = adev->psp.ta_fw_version;
353 fw_info->feature = adev->psp.xgmi.feature_version;
354 break;
355 case TA_FW_TYPE_PSP_RAS:
356 fw_info->ver = adev->psp.ta_fw_version;
357 fw_info->feature = adev->psp.ras.feature_version;
358 break;
359 case TA_FW_TYPE_PSP_HDCP:
360 fw_info->ver = adev->psp.ta_fw_version;
361 fw_info->feature = adev->psp.hdcp.feature_version;
362 break;
363 case TA_FW_TYPE_PSP_DTM:
364 fw_info->ver = adev->psp.ta_fw_version;
365 fw_info->feature = adev->psp.dtm.feature_version;
366 break;
367 case TA_FW_TYPE_PSP_RAP:
368 fw_info->ver = adev->psp.ta_fw_version;
369 fw_info->feature = adev->psp.rap.feature_version;
370 break;
371 case TA_FW_TYPE_PSP_SECUREDISPLAY:
372 fw_info->ver = adev->psp.ta_fw_version;
373 fw_info->feature = adev->psp.securedisplay.feature_version;
374 break;
375 default:
376 return -EINVAL;
377 }
378 break;
379 case AMDGPU_INFO_FW_SDMA:
380 if (query_fw->index >= adev->sdma.num_instances)
381 return -EINVAL;
382 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
383 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
384 break;
385 case AMDGPU_INFO_FW_SOS:
386 fw_info->ver = adev->psp.sos.fw_version;
387 fw_info->feature = adev->psp.sos.feature_version;
388 break;
389 case AMDGPU_INFO_FW_ASD:
390 fw_info->ver = adev->psp.asd.fw_version;
391 fw_info->feature = adev->psp.asd.feature_version;
392 break;
393 case AMDGPU_INFO_FW_DMCU:
394 fw_info->ver = adev->dm.dmcu_fw_version;
395 fw_info->feature = 0;
396 break;
397 case AMDGPU_INFO_FW_DMCUB:
398 fw_info->ver = adev->dm.dmcub_fw_version;
399 fw_info->feature = 0;
400 break;
401 case AMDGPU_INFO_FW_TOC:
402 fw_info->ver = adev->psp.toc.fw_version;
403 fw_info->feature = adev->psp.toc.feature_version;
404 break;
405 default:
406 return -EINVAL;
407 }
408 return 0;
409 }
410
amdgpu_hw_ip_info(struct amdgpu_device * adev,struct drm_amdgpu_info * info,struct drm_amdgpu_info_hw_ip * result)411 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
412 struct drm_amdgpu_info *info,
413 struct drm_amdgpu_info_hw_ip *result)
414 {
415 uint32_t ib_start_alignment = 0;
416 uint32_t ib_size_alignment = 0;
417 enum amd_ip_block_type type;
418 unsigned int num_rings = 0;
419 unsigned int i, j;
420
421 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
422 return -EINVAL;
423
424 switch (info->query_hw_ip.type) {
425 case AMDGPU_HW_IP_GFX:
426 type = AMD_IP_BLOCK_TYPE_GFX;
427 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
428 if (adev->gfx.gfx_ring[i].sched.ready)
429 ++num_rings;
430 ib_start_alignment = 32;
431 ib_size_alignment = 32;
432 break;
433 case AMDGPU_HW_IP_COMPUTE:
434 type = AMD_IP_BLOCK_TYPE_GFX;
435 for (i = 0; i < adev->gfx.num_compute_rings; i++)
436 if (adev->gfx.compute_ring[i].sched.ready)
437 ++num_rings;
438 ib_start_alignment = 32;
439 ib_size_alignment = 32;
440 break;
441 case AMDGPU_HW_IP_DMA:
442 type = AMD_IP_BLOCK_TYPE_SDMA;
443 for (i = 0; i < adev->sdma.num_instances; i++)
444 if (adev->sdma.instance[i].ring.sched.ready)
445 ++num_rings;
446 ib_start_alignment = 256;
447 ib_size_alignment = 4;
448 break;
449 case AMDGPU_HW_IP_UVD:
450 type = AMD_IP_BLOCK_TYPE_UVD;
451 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
452 if (adev->uvd.harvest_config & (1 << i))
453 continue;
454
455 if (adev->uvd.inst[i].ring.sched.ready)
456 ++num_rings;
457 }
458 ib_start_alignment = 64;
459 ib_size_alignment = 64;
460 break;
461 case AMDGPU_HW_IP_VCE:
462 type = AMD_IP_BLOCK_TYPE_VCE;
463 for (i = 0; i < adev->vce.num_rings; i++)
464 if (adev->vce.ring[i].sched.ready)
465 ++num_rings;
466 ib_start_alignment = 4;
467 ib_size_alignment = 1;
468 break;
469 case AMDGPU_HW_IP_UVD_ENC:
470 type = AMD_IP_BLOCK_TYPE_UVD;
471 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
472 if (adev->uvd.harvest_config & (1 << i))
473 continue;
474
475 for (j = 0; j < adev->uvd.num_enc_rings; j++)
476 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
477 ++num_rings;
478 }
479 ib_start_alignment = 64;
480 ib_size_alignment = 64;
481 break;
482 case AMDGPU_HW_IP_VCN_DEC:
483 type = AMD_IP_BLOCK_TYPE_VCN;
484 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
485 if (adev->uvd.harvest_config & (1 << i))
486 continue;
487
488 if (adev->vcn.inst[i].ring_dec.sched.ready)
489 ++num_rings;
490 }
491 ib_start_alignment = 16;
492 ib_size_alignment = 16;
493 break;
494 case AMDGPU_HW_IP_VCN_ENC:
495 type = AMD_IP_BLOCK_TYPE_VCN;
496 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
497 if (adev->uvd.harvest_config & (1 << i))
498 continue;
499
500 for (j = 0; j < adev->vcn.num_enc_rings; j++)
501 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
502 ++num_rings;
503 }
504 ib_start_alignment = 64;
505 ib_size_alignment = 1;
506 break;
507 case AMDGPU_HW_IP_VCN_JPEG:
508 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
509 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
510
511 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
512 if (adev->jpeg.harvest_config & (1 << i))
513 continue;
514
515 if (adev->jpeg.inst[i].ring_dec.sched.ready)
516 ++num_rings;
517 }
518 ib_start_alignment = 16;
519 ib_size_alignment = 16;
520 break;
521 default:
522 return -EINVAL;
523 }
524
525 for (i = 0; i < adev->num_ip_blocks; i++)
526 if (adev->ip_blocks[i].version->type == type &&
527 adev->ip_blocks[i].status.valid)
528 break;
529
530 if (i == adev->num_ip_blocks)
531 return 0;
532
533 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
534 num_rings);
535
536 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
537 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
538 result->capabilities_flags = 0;
539 result->available_rings = (1 << num_rings) - 1;
540 result->ib_start_alignment = ib_start_alignment;
541 result->ib_size_alignment = ib_size_alignment;
542 return 0;
543 }
544
545 /*
546 * Userspace get information ioctl
547 */
548 /**
549 * amdgpu_info_ioctl - answer a device specific request.
550 *
551 * @dev: drm device pointer
552 * @data: request object
553 * @filp: drm filp
554 *
555 * This function is used to pass device specific parameters to the userspace
556 * drivers. Examples include: pci device id, pipeline parms, tiling params,
557 * etc. (all asics).
558 * Returns 0 on success, -EINVAL on failure.
559 */
amdgpu_info_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)560 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
561 {
562 struct amdgpu_device *adev = drm_to_adev(dev);
563 struct drm_amdgpu_info *info = data;
564 struct amdgpu_mode_info *minfo = &adev->mode_info;
565 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
566 uint32_t size = info->return_size;
567 struct drm_crtc *crtc;
568 uint32_t ui32 = 0;
569 uint64_t ui64 = 0;
570 int i, found;
571 int ui32_size = sizeof(ui32);
572
573 if (!info->return_size || !info->return_pointer)
574 return -EINVAL;
575
576 switch (info->query) {
577 case AMDGPU_INFO_ACCEL_WORKING:
578 ui32 = adev->accel_working;
579 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
580 case AMDGPU_INFO_CRTC_FROM_ID:
581 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
582 crtc = (struct drm_crtc *)minfo->crtcs[i];
583 if (crtc && crtc->base.id == info->mode_crtc.id) {
584 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
585
586 ui32 = amdgpu_crtc->crtc_id;
587 found = 1;
588 break;
589 }
590 }
591 if (!found) {
592 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
593 return -EINVAL;
594 }
595 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
596 case AMDGPU_INFO_HW_IP_INFO: {
597 struct drm_amdgpu_info_hw_ip ip = {};
598 int ret;
599
600 ret = amdgpu_hw_ip_info(adev, info, &ip);
601 if (ret)
602 return ret;
603
604 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
605 return ret ? -EFAULT : 0;
606 }
607 case AMDGPU_INFO_HW_IP_COUNT: {
608 enum amd_ip_block_type type;
609 uint32_t count = 0;
610
611 switch (info->query_hw_ip.type) {
612 case AMDGPU_HW_IP_GFX:
613 type = AMD_IP_BLOCK_TYPE_GFX;
614 break;
615 case AMDGPU_HW_IP_COMPUTE:
616 type = AMD_IP_BLOCK_TYPE_GFX;
617 break;
618 case AMDGPU_HW_IP_DMA:
619 type = AMD_IP_BLOCK_TYPE_SDMA;
620 break;
621 case AMDGPU_HW_IP_UVD:
622 type = AMD_IP_BLOCK_TYPE_UVD;
623 break;
624 case AMDGPU_HW_IP_VCE:
625 type = AMD_IP_BLOCK_TYPE_VCE;
626 break;
627 case AMDGPU_HW_IP_UVD_ENC:
628 type = AMD_IP_BLOCK_TYPE_UVD;
629 break;
630 case AMDGPU_HW_IP_VCN_DEC:
631 case AMDGPU_HW_IP_VCN_ENC:
632 type = AMD_IP_BLOCK_TYPE_VCN;
633 break;
634 case AMDGPU_HW_IP_VCN_JPEG:
635 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
636 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
637 break;
638 default:
639 return -EINVAL;
640 }
641
642 for (i = 0; i < adev->num_ip_blocks; i++)
643 if (adev->ip_blocks[i].version->type == type &&
644 adev->ip_blocks[i].status.valid &&
645 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
646 count++;
647
648 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
649 }
650 case AMDGPU_INFO_TIMESTAMP:
651 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
652 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
653 case AMDGPU_INFO_FW_VERSION: {
654 struct drm_amdgpu_info_firmware fw_info;
655 int ret;
656
657 /* We only support one instance of each IP block right now. */
658 if (info->query_fw.ip_instance != 0)
659 return -EINVAL;
660
661 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
662 if (ret)
663 return ret;
664
665 return copy_to_user(out, &fw_info,
666 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
667 }
668 case AMDGPU_INFO_NUM_BYTES_MOVED:
669 ui64 = atomic64_read(&adev->num_bytes_moved);
670 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
671 case AMDGPU_INFO_NUM_EVICTIONS:
672 ui64 = atomic64_read(&adev->num_evictions);
673 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
674 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
675 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
676 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
677 case AMDGPU_INFO_VRAM_USAGE:
678 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
679 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
680 case AMDGPU_INFO_VIS_VRAM_USAGE:
681 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
682 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
683 case AMDGPU_INFO_GTT_USAGE:
684 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
685 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
686 case AMDGPU_INFO_GDS_CONFIG: {
687 struct drm_amdgpu_info_gds gds_info;
688
689 memset(&gds_info, 0, sizeof(gds_info));
690 gds_info.compute_partition_size = adev->gds.gds_size;
691 gds_info.gds_total_size = adev->gds.gds_size;
692 gds_info.gws_per_compute_partition = adev->gds.gws_size;
693 gds_info.oa_per_compute_partition = adev->gds.oa_size;
694 return copy_to_user(out, &gds_info,
695 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
696 }
697 case AMDGPU_INFO_VRAM_GTT: {
698 struct drm_amdgpu_info_vram_gtt vram_gtt;
699
700 vram_gtt.vram_size = adev->gmc.real_vram_size -
701 atomic64_read(&adev->vram_pin_size) -
702 AMDGPU_VM_RESERVED_VRAM;
703 vram_gtt.vram_cpu_accessible_size =
704 min(adev->gmc.visible_vram_size -
705 atomic64_read(&adev->visible_pin_size),
706 vram_gtt.vram_size);
707 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
708 vram_gtt.gtt_size *= PAGE_SIZE;
709 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
710 return copy_to_user(out, &vram_gtt,
711 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
712 }
713 case AMDGPU_INFO_MEMORY: {
714 struct drm_amdgpu_memory_info mem;
715 struct ttm_resource_manager *vram_man =
716 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
717 struct ttm_resource_manager *gtt_man =
718 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
719 memset(&mem, 0, sizeof(mem));
720 mem.vram.total_heap_size = adev->gmc.real_vram_size;
721 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
722 atomic64_read(&adev->vram_pin_size) -
723 AMDGPU_VM_RESERVED_VRAM;
724 mem.vram.heap_usage =
725 amdgpu_vram_mgr_usage(vram_man);
726 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
727
728 mem.cpu_accessible_vram.total_heap_size =
729 adev->gmc.visible_vram_size;
730 mem.cpu_accessible_vram.usable_heap_size =
731 min(adev->gmc.visible_vram_size -
732 atomic64_read(&adev->visible_pin_size),
733 mem.vram.usable_heap_size);
734 mem.cpu_accessible_vram.heap_usage =
735 amdgpu_vram_mgr_vis_usage(vram_man);
736 mem.cpu_accessible_vram.max_allocation =
737 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
738
739 mem.gtt.total_heap_size = gtt_man->size;
740 mem.gtt.total_heap_size *= PAGE_SIZE;
741 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
742 atomic64_read(&adev->gart_pin_size);
743 mem.gtt.heap_usage =
744 amdgpu_gtt_mgr_usage(gtt_man);
745 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
746
747 return copy_to_user(out, &mem,
748 min((size_t)size, sizeof(mem)))
749 ? -EFAULT : 0;
750 }
751 case AMDGPU_INFO_READ_MMR_REG: {
752 unsigned int n, alloc_size;
753 uint32_t *regs;
754 unsigned int se_num = (info->read_mmr_reg.instance >>
755 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
756 AMDGPU_INFO_MMR_SE_INDEX_MASK;
757 unsigned int sh_num = (info->read_mmr_reg.instance >>
758 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
759 AMDGPU_INFO_MMR_SH_INDEX_MASK;
760
761 /* set full masks if the userspace set all bits
762 * in the bitfields
763 */
764 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
765 se_num = 0xffffffff;
766 else if (se_num >= AMDGPU_GFX_MAX_SE)
767 return -EINVAL;
768 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
769 sh_num = 0xffffffff;
770 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
771 return -EINVAL;
772
773 if (info->read_mmr_reg.count > 128)
774 return -EINVAL;
775
776 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
777 if (!regs)
778 return -ENOMEM;
779 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
780
781 amdgpu_gfx_off_ctrl(adev, false);
782 for (i = 0; i < info->read_mmr_reg.count; i++) {
783 if (amdgpu_asic_read_register(adev, se_num, sh_num,
784 info->read_mmr_reg.dword_offset + i,
785 ®s[i])) {
786 DRM_DEBUG_KMS("unallowed offset %#x\n",
787 info->read_mmr_reg.dword_offset + i);
788 kfree(regs);
789 amdgpu_gfx_off_ctrl(adev, true);
790 return -EFAULT;
791 }
792 }
793 amdgpu_gfx_off_ctrl(adev, true);
794 n = copy_to_user(out, regs, min(size, alloc_size));
795 kfree(regs);
796 return n ? -EFAULT : 0;
797 }
798 case AMDGPU_INFO_DEV_INFO: {
799 struct drm_amdgpu_info_device *dev_info;
800 uint64_t vm_size;
801 int ret;
802
803 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
804 if (!dev_info)
805 return -ENOMEM;
806
807 dev_info->device_id = adev->pdev->device;
808 dev_info->chip_rev = adev->rev_id;
809 dev_info->external_rev = adev->external_rev_id;
810 dev_info->pci_rev = adev->pdev->revision;
811 dev_info->family = adev->family;
812 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
813 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
814 /* return all clocks in KHz */
815 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
816 if (adev->pm.dpm_enabled) {
817 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
818 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
819 } else {
820 dev_info->max_engine_clock = adev->clock.default_sclk * 10;
821 dev_info->max_memory_clock = adev->clock.default_mclk * 10;
822 }
823 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
824 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
825 adev->gfx.config.max_shader_engines;
826 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
827 dev_info->_pad = 0;
828 dev_info->ids_flags = 0;
829 if (adev->flags & AMD_IS_APU)
830 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
831 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
832 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
833 if (amdgpu_is_tmz(adev))
834 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
835
836 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
837 vm_size -= AMDGPU_VA_RESERVED_SIZE;
838
839 /* Older VCE FW versions are buggy and can handle only 40bits */
840 if (adev->vce.fw_version &&
841 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
842 vm_size = min(vm_size, 1ULL << 40);
843
844 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
845 dev_info->virtual_address_max =
846 min(vm_size, AMDGPU_GMC_HOLE_START);
847
848 if (vm_size > AMDGPU_GMC_HOLE_START) {
849 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
850 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
851 }
852 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
853 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
854 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
855 dev_info->cu_active_number = adev->gfx.cu_info.number;
856 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
857 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
858 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
859 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
860 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
861 sizeof(adev->gfx.cu_info.bitmap));
862 dev_info->vram_type = adev->gmc.vram_type;
863 dev_info->vram_bit_width = adev->gmc.vram_width;
864 dev_info->vce_harvest_config = adev->vce.harvest_config;
865 dev_info->gc_double_offchip_lds_buf =
866 adev->gfx.config.double_offchip_lds_buf;
867 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
868 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
869 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
870 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
871 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
872 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
873 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
874
875 if (adev->family >= AMDGPU_FAMILY_NV)
876 dev_info->pa_sc_tile_steering_override =
877 adev->gfx.config.pa_sc_tile_steering_override;
878
879 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
880
881 ret = copy_to_user(out, dev_info,
882 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
883 kfree(dev_info);
884 return ret;
885 }
886 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
887 unsigned int i;
888 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
889 struct amd_vce_state *vce_state;
890
891 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
892 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
893 if (vce_state) {
894 vce_clk_table.entries[i].sclk = vce_state->sclk;
895 vce_clk_table.entries[i].mclk = vce_state->mclk;
896 vce_clk_table.entries[i].eclk = vce_state->evclk;
897 vce_clk_table.num_valid_entries++;
898 }
899 }
900
901 return copy_to_user(out, &vce_clk_table,
902 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
903 }
904 case AMDGPU_INFO_VBIOS: {
905 uint32_t bios_size = adev->bios_size;
906
907 switch (info->vbios_info.type) {
908 case AMDGPU_INFO_VBIOS_SIZE:
909 return copy_to_user(out, &bios_size,
910 min((size_t)size, sizeof(bios_size)))
911 ? -EFAULT : 0;
912 case AMDGPU_INFO_VBIOS_IMAGE: {
913 uint8_t *bios;
914 uint32_t bios_offset = info->vbios_info.offset;
915
916 if (bios_offset >= bios_size)
917 return -EINVAL;
918
919 bios = adev->bios + bios_offset;
920 return copy_to_user(out, bios,
921 min((size_t)size, (size_t)(bios_size - bios_offset)))
922 ? -EFAULT : 0;
923 }
924 case AMDGPU_INFO_VBIOS_INFO: {
925 struct drm_amdgpu_info_vbios vbios_info = {};
926 struct atom_context *atom_context;
927
928 atom_context = adev->mode_info.atom_context;
929 if (atom_context) {
930 memcpy(vbios_info.name, atom_context->name,
931 sizeof(atom_context->name));
932 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn,
933 sizeof(atom_context->vbios_pn));
934 vbios_info.version = atom_context->version;
935 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
936 sizeof(atom_context->vbios_ver_str));
937 memcpy(vbios_info.date, atom_context->date,
938 sizeof(atom_context->date));
939 }
940
941 return copy_to_user(out, &vbios_info,
942 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
943 }
944 default:
945 DRM_DEBUG_KMS("Invalid request %d\n",
946 info->vbios_info.type);
947 return -EINVAL;
948 }
949 }
950 case AMDGPU_INFO_NUM_HANDLES: {
951 struct drm_amdgpu_info_num_handles handle;
952
953 switch (info->query_hw_ip.type) {
954 case AMDGPU_HW_IP_UVD:
955 /* Starting Polaris, we support unlimited UVD handles */
956 if (adev->asic_type < CHIP_POLARIS10) {
957 handle.uvd_max_handles = adev->uvd.max_handles;
958 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
959
960 return copy_to_user(out, &handle,
961 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
962 } else {
963 return -ENODATA;
964 }
965
966 break;
967 default:
968 return -EINVAL;
969 }
970 }
971 case AMDGPU_INFO_SENSOR: {
972 if (!adev->pm.dpm_enabled)
973 return -ENOENT;
974
975 switch (info->sensor_info.type) {
976 case AMDGPU_INFO_SENSOR_GFX_SCLK:
977 /* get sclk in Mhz */
978 if (amdgpu_dpm_read_sensor(adev,
979 AMDGPU_PP_SENSOR_GFX_SCLK,
980 (void *)&ui32, &ui32_size)) {
981 return -EINVAL;
982 }
983 ui32 /= 100;
984 break;
985 case AMDGPU_INFO_SENSOR_GFX_MCLK:
986 /* get mclk in Mhz */
987 if (amdgpu_dpm_read_sensor(adev,
988 AMDGPU_PP_SENSOR_GFX_MCLK,
989 (void *)&ui32, &ui32_size)) {
990 return -EINVAL;
991 }
992 ui32 /= 100;
993 break;
994 case AMDGPU_INFO_SENSOR_GPU_TEMP:
995 /* get temperature in millidegrees C */
996 if (amdgpu_dpm_read_sensor(adev,
997 AMDGPU_PP_SENSOR_GPU_TEMP,
998 (void *)&ui32, &ui32_size)) {
999 return -EINVAL;
1000 }
1001 break;
1002 case AMDGPU_INFO_SENSOR_GPU_LOAD:
1003 /* get GPU load */
1004 if (amdgpu_dpm_read_sensor(adev,
1005 AMDGPU_PP_SENSOR_GPU_LOAD,
1006 (void *)&ui32, &ui32_size)) {
1007 return -EINVAL;
1008 }
1009 break;
1010 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
1011 /* get average GPU power */
1012 if (amdgpu_dpm_read_sensor(adev,
1013 AMDGPU_PP_SENSOR_GPU_POWER,
1014 (void *)&ui32, &ui32_size)) {
1015 return -EINVAL;
1016 }
1017 ui32 >>= 8;
1018 break;
1019 case AMDGPU_INFO_SENSOR_VDDNB:
1020 /* get VDDNB in millivolts */
1021 if (amdgpu_dpm_read_sensor(adev,
1022 AMDGPU_PP_SENSOR_VDDNB,
1023 (void *)&ui32, &ui32_size)) {
1024 return -EINVAL;
1025 }
1026 break;
1027 case AMDGPU_INFO_SENSOR_VDDGFX:
1028 /* get VDDGFX in millivolts */
1029 if (amdgpu_dpm_read_sensor(adev,
1030 AMDGPU_PP_SENSOR_VDDGFX,
1031 (void *)&ui32, &ui32_size)) {
1032 return -EINVAL;
1033 }
1034 break;
1035 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1036 /* get stable pstate sclk in Mhz */
1037 if (amdgpu_dpm_read_sensor(adev,
1038 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1039 (void *)&ui32, &ui32_size)) {
1040 return -EINVAL;
1041 }
1042 ui32 /= 100;
1043 break;
1044 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1045 /* get stable pstate mclk in Mhz */
1046 if (amdgpu_dpm_read_sensor(adev,
1047 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1048 (void *)&ui32, &ui32_size)) {
1049 return -EINVAL;
1050 }
1051 ui32 /= 100;
1052 break;
1053 default:
1054 DRM_DEBUG_KMS("Invalid request %d\n",
1055 info->sensor_info.type);
1056 return -EINVAL;
1057 }
1058 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1059 }
1060 case AMDGPU_INFO_VRAM_LOST_COUNTER:
1061 ui32 = atomic_read(&adev->vram_lost_counter);
1062 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1063 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1064 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1065 uint64_t ras_mask;
1066
1067 if (!ras)
1068 return -EINVAL;
1069 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1070
1071 return copy_to_user(out, &ras_mask,
1072 min_t(u64, size, sizeof(ras_mask))) ?
1073 -EFAULT : 0;
1074 }
1075 case AMDGPU_INFO_VIDEO_CAPS: {
1076 const struct amdgpu_video_codecs *codecs;
1077 struct drm_amdgpu_info_video_caps *caps;
1078 int r;
1079
1080 switch (info->video_cap.type) {
1081 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1082 r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1083 if (r)
1084 return -EINVAL;
1085 break;
1086 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1087 r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1088 if (r)
1089 return -EINVAL;
1090 break;
1091 default:
1092 DRM_DEBUG_KMS("Invalid request %d\n",
1093 info->video_cap.type);
1094 return -EINVAL;
1095 }
1096
1097 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1098 if (!caps)
1099 return -ENOMEM;
1100
1101 for (i = 0; i < codecs->codec_count; i++) {
1102 int idx = codecs->codec_array[i].codec_type;
1103
1104 switch (idx) {
1105 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1106 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1107 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1108 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1109 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1110 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1111 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1112 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1113 caps->codec_info[idx].valid = 1;
1114 caps->codec_info[idx].max_width =
1115 codecs->codec_array[i].max_width;
1116 caps->codec_info[idx].max_height =
1117 codecs->codec_array[i].max_height;
1118 caps->codec_info[idx].max_pixels_per_frame =
1119 codecs->codec_array[i].max_pixels_per_frame;
1120 caps->codec_info[idx].max_level =
1121 codecs->codec_array[i].max_level;
1122 break;
1123 default:
1124 break;
1125 }
1126 }
1127 r = copy_to_user(out, caps,
1128 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1129 kfree(caps);
1130 return r;
1131 }
1132 default:
1133 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1134 return -EINVAL;
1135 }
1136 return 0;
1137 }
1138
1139
1140 /*
1141 * Outdated mess for old drm with Xorg being in charge (void function now).
1142 */
1143 /**
1144 * amdgpu_driver_lastclose_kms - drm callback for last close
1145 *
1146 * @dev: drm dev pointer
1147 *
1148 * Switch vga_switcheroo state after last close (all asics).
1149 */
amdgpu_driver_lastclose_kms(struct drm_device * dev)1150 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1151 {
1152 drm_fb_helper_lastclose(dev);
1153 vga_switcheroo_process_delayed_switch();
1154 }
1155
1156 /**
1157 * amdgpu_driver_open_kms - drm callback for open
1158 *
1159 * @dev: drm dev pointer
1160 * @file_priv: drm file
1161 *
1162 * On device open, init vm on cayman+ (all asics).
1163 * Returns 0 on success, error on failure.
1164 */
amdgpu_driver_open_kms(struct drm_device * dev,struct drm_file * file_priv)1165 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1166 {
1167 struct amdgpu_device *adev = drm_to_adev(dev);
1168 struct amdgpu_fpriv *fpriv;
1169 int r, pasid;
1170
1171 /* Ensure IB tests are run on ring */
1172 flush_delayed_work(&adev->delayed_init_work);
1173
1174
1175 if (amdgpu_ras_intr_triggered()) {
1176 DRM_ERROR("RAS Intr triggered, device disabled!!");
1177 return -EHWPOISON;
1178 }
1179
1180 file_priv->driver_priv = NULL;
1181
1182 r = pm_runtime_get_sync(dev->dev);
1183 if (r < 0)
1184 goto pm_put;
1185
1186 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1187 if (unlikely(!fpriv)) {
1188 r = -ENOMEM;
1189 goto out_suspend;
1190 }
1191
1192 pasid = amdgpu_pasid_alloc(16);
1193 if (pasid < 0) {
1194 dev_warn(adev->dev, "No more PASIDs available!");
1195 pasid = 0;
1196 }
1197
1198 r = amdgpu_vm_init(adev, &fpriv->vm);
1199 if (r)
1200 goto error_pasid;
1201
1202 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1203 if (r)
1204 goto error_vm;
1205
1206 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1207 if (!fpriv->prt_va) {
1208 r = -ENOMEM;
1209 goto error_vm;
1210 }
1211
1212 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1213 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1214
1215 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1216 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1217 if (r)
1218 goto error_vm;
1219 }
1220
1221 mutex_init(&fpriv->bo_list_lock);
1222 idr_init(&fpriv->bo_list_handles);
1223
1224 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1225
1226 file_priv->driver_priv = fpriv;
1227 goto out_suspend;
1228
1229 error_vm:
1230 amdgpu_vm_fini(adev, &fpriv->vm);
1231
1232 error_pasid:
1233 if (pasid) {
1234 amdgpu_pasid_free(pasid);
1235 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1236 }
1237
1238 kfree(fpriv);
1239
1240 out_suspend:
1241 pm_runtime_mark_last_busy(dev->dev);
1242 pm_put:
1243 pm_runtime_put_autosuspend(dev->dev);
1244
1245 return r;
1246 }
1247
1248 /**
1249 * amdgpu_driver_postclose_kms - drm callback for post close
1250 *
1251 * @dev: drm dev pointer
1252 * @file_priv: drm file
1253 *
1254 * On device post close, tear down vm on cayman+ (all asics).
1255 */
amdgpu_driver_postclose_kms(struct drm_device * dev,struct drm_file * file_priv)1256 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1257 struct drm_file *file_priv)
1258 {
1259 struct amdgpu_device *adev = drm_to_adev(dev);
1260 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1261 struct amdgpu_bo_list *list;
1262 struct amdgpu_bo *pd;
1263 u32 pasid;
1264 int handle;
1265
1266 if (!fpriv)
1267 return;
1268
1269 pm_runtime_get_sync(dev->dev);
1270
1271 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1272 amdgpu_uvd_free_handles(adev, file_priv);
1273 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1274 amdgpu_vce_free_handles(adev, file_priv);
1275
1276 amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1277
1278 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1279 /* TODO: how to handle reserve failure */
1280 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1281 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1282 fpriv->csa_va = NULL;
1283 amdgpu_bo_unreserve(adev->virt.csa_obj);
1284 }
1285
1286 pasid = fpriv->vm.pasid;
1287 pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1288
1289 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1290 amdgpu_vm_fini(adev, &fpriv->vm);
1291
1292 if (pasid)
1293 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1294 amdgpu_bo_unref(&pd);
1295
1296 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1297 amdgpu_bo_list_put(list);
1298
1299 idr_destroy(&fpriv->bo_list_handles);
1300 mutex_destroy(&fpriv->bo_list_lock);
1301
1302 kfree(fpriv);
1303 file_priv->driver_priv = NULL;
1304
1305 pm_runtime_mark_last_busy(dev->dev);
1306 pm_runtime_put_autosuspend(dev->dev);
1307 }
1308
1309
amdgpu_driver_release_kms(struct drm_device * dev)1310 void amdgpu_driver_release_kms(struct drm_device *dev)
1311 {
1312 struct amdgpu_device *adev = drm_to_adev(dev);
1313
1314 amdgpu_device_fini_sw(adev);
1315 pci_set_drvdata(adev->pdev, NULL);
1316 }
1317
1318 /*
1319 * VBlank related functions.
1320 */
1321 /**
1322 * amdgpu_get_vblank_counter_kms - get frame count
1323 *
1324 * @crtc: crtc to get the frame count from
1325 *
1326 * Gets the frame count on the requested crtc (all asics).
1327 * Returns frame count on success, -EINVAL on failure.
1328 */
amdgpu_get_vblank_counter_kms(struct drm_crtc * crtc)1329 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1330 {
1331 struct drm_device *dev = crtc->dev;
1332 unsigned int pipe = crtc->index;
1333 struct amdgpu_device *adev = drm_to_adev(dev);
1334 int vpos, hpos, stat;
1335 u32 count;
1336
1337 if (pipe >= adev->mode_info.num_crtc) {
1338 DRM_ERROR("Invalid crtc %u\n", pipe);
1339 return -EINVAL;
1340 }
1341
1342 /* The hw increments its frame counter at start of vsync, not at start
1343 * of vblank, as is required by DRM core vblank counter handling.
1344 * Cook the hw count here to make it appear to the caller as if it
1345 * incremented at start of vblank. We measure distance to start of
1346 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1347 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1348 * result by 1 to give the proper appearance to caller.
1349 */
1350 if (adev->mode_info.crtcs[pipe]) {
1351 /* Repeat readout if needed to provide stable result if
1352 * we cross start of vsync during the queries.
1353 */
1354 do {
1355 count = amdgpu_display_vblank_get_counter(adev, pipe);
1356 /* Ask amdgpu_display_get_crtc_scanoutpos to return
1357 * vpos as distance to start of vblank, instead of
1358 * regular vertical scanout pos.
1359 */
1360 stat = amdgpu_display_get_crtc_scanoutpos(
1361 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1362 &vpos, &hpos, NULL, NULL,
1363 &adev->mode_info.crtcs[pipe]->base.hwmode);
1364 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1365
1366 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1367 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1368 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1369 } else {
1370 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1371 pipe, vpos);
1372
1373 /* Bump counter if we are at >= leading edge of vblank,
1374 * but before vsync where vpos would turn negative and
1375 * the hw counter really increments.
1376 */
1377 if (vpos >= 0)
1378 count++;
1379 }
1380 } else {
1381 /* Fallback to use value as is. */
1382 count = amdgpu_display_vblank_get_counter(adev, pipe);
1383 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1384 }
1385
1386 return count;
1387 }
1388
1389 /**
1390 * amdgpu_enable_vblank_kms - enable vblank interrupt
1391 *
1392 * @crtc: crtc to enable vblank interrupt for
1393 *
1394 * Enable the interrupt on the requested crtc (all asics).
1395 * Returns 0 on success, -EINVAL on failure.
1396 */
amdgpu_enable_vblank_kms(struct drm_crtc * crtc)1397 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1398 {
1399 struct drm_device *dev = crtc->dev;
1400 unsigned int pipe = crtc->index;
1401 struct amdgpu_device *adev = drm_to_adev(dev);
1402 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1403
1404 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1405 }
1406
1407 /**
1408 * amdgpu_disable_vblank_kms - disable vblank interrupt
1409 *
1410 * @crtc: crtc to disable vblank interrupt for
1411 *
1412 * Disable the interrupt on the requested crtc (all asics).
1413 */
amdgpu_disable_vblank_kms(struct drm_crtc * crtc)1414 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1415 {
1416 struct drm_device *dev = crtc->dev;
1417 unsigned int pipe = crtc->index;
1418 struct amdgpu_device *adev = drm_to_adev(dev);
1419 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1420
1421 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1422 }
1423
1424 /*
1425 * Debugfs info
1426 */
1427 #if defined(CONFIG_DEBUG_FS)
1428
amdgpu_debugfs_firmware_info_show(struct seq_file * m,void * unused)1429 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1430 {
1431 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1432 struct drm_amdgpu_info_firmware fw_info;
1433 struct drm_amdgpu_query_fw query_fw;
1434 struct atom_context *ctx = adev->mode_info.atom_context;
1435 int ret, i;
1436
1437 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1438 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1439 TA_FW_NAME(XGMI),
1440 TA_FW_NAME(RAS),
1441 TA_FW_NAME(HDCP),
1442 TA_FW_NAME(DTM),
1443 TA_FW_NAME(RAP),
1444 TA_FW_NAME(SECUREDISPLAY),
1445 #undef TA_FW_NAME
1446 };
1447
1448 /* VCE */
1449 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1450 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1451 if (ret)
1452 return ret;
1453 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1454 fw_info.feature, fw_info.ver);
1455
1456 /* UVD */
1457 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1458 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1459 if (ret)
1460 return ret;
1461 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1462 fw_info.feature, fw_info.ver);
1463
1464 /* GMC */
1465 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1466 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1467 if (ret)
1468 return ret;
1469 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1470 fw_info.feature, fw_info.ver);
1471
1472 /* ME */
1473 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1474 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1475 if (ret)
1476 return ret;
1477 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1478 fw_info.feature, fw_info.ver);
1479
1480 /* PFP */
1481 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1482 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1483 if (ret)
1484 return ret;
1485 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1486 fw_info.feature, fw_info.ver);
1487
1488 /* CE */
1489 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1490 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1491 if (ret)
1492 return ret;
1493 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1494 fw_info.feature, fw_info.ver);
1495
1496 /* RLC */
1497 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1498 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1499 if (ret)
1500 return ret;
1501 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1502 fw_info.feature, fw_info.ver);
1503
1504 /* RLC SAVE RESTORE LIST CNTL */
1505 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1506 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1507 if (ret)
1508 return ret;
1509 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1510 fw_info.feature, fw_info.ver);
1511
1512 /* RLC SAVE RESTORE LIST GPM MEM */
1513 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1514 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1515 if (ret)
1516 return ret;
1517 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1518 fw_info.feature, fw_info.ver);
1519
1520 /* RLC SAVE RESTORE LIST SRM MEM */
1521 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1522 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1523 if (ret)
1524 return ret;
1525 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1526 fw_info.feature, fw_info.ver);
1527
1528 /* MEC */
1529 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1530 query_fw.index = 0;
1531 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1532 if (ret)
1533 return ret;
1534 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1535 fw_info.feature, fw_info.ver);
1536
1537 /* MEC2 */
1538 if (adev->gfx.mec2_fw) {
1539 query_fw.index = 1;
1540 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1541 if (ret)
1542 return ret;
1543 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1544 fw_info.feature, fw_info.ver);
1545 }
1546
1547 /* PSP SOS */
1548 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1549 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1550 if (ret)
1551 return ret;
1552 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1553 fw_info.feature, fw_info.ver);
1554
1555
1556 /* PSP ASD */
1557 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1558 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1559 if (ret)
1560 return ret;
1561 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1562 fw_info.feature, fw_info.ver);
1563
1564 query_fw.fw_type = AMDGPU_INFO_FW_TA;
1565 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1566 query_fw.index = i;
1567 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1568 if (ret)
1569 continue;
1570
1571 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1572 ta_fw_name[i], fw_info.feature, fw_info.ver);
1573 }
1574
1575 /* SMC */
1576 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1577 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1578 if (ret)
1579 return ret;
1580 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1581 fw_info.feature, fw_info.ver);
1582
1583 /* SDMA */
1584 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1585 for (i = 0; i < adev->sdma.num_instances; i++) {
1586 query_fw.index = i;
1587 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1588 if (ret)
1589 return ret;
1590 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1591 i, fw_info.feature, fw_info.ver);
1592 }
1593
1594 /* VCN */
1595 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1596 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1597 if (ret)
1598 return ret;
1599 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1600 fw_info.feature, fw_info.ver);
1601
1602 /* DMCU */
1603 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1604 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1605 if (ret)
1606 return ret;
1607 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1608 fw_info.feature, fw_info.ver);
1609
1610 /* DMCUB */
1611 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1612 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1613 if (ret)
1614 return ret;
1615 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1616 fw_info.feature, fw_info.ver);
1617
1618 /* TOC */
1619 query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1620 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1621 if (ret)
1622 return ret;
1623 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1624 fw_info.feature, fw_info.ver);
1625
1626 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1627
1628 return 0;
1629 }
1630
1631 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1632
1633 #endif
1634
amdgpu_debugfs_firmware_init(struct amdgpu_device * adev)1635 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1636 {
1637 #if defined(CONFIG_DEBUG_FS)
1638 struct drm_minor *minor = adev_to_drm(adev)->primary;
1639 struct dentry *root = minor->debugfs_root;
1640
1641 debugfs_create_file("amdgpu_firmware_info", 0444, root,
1642 adev, &amdgpu_debugfs_firmware_info_fops);
1643
1644 #endif
1645 }
1646