1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "amdgpu_ras_eeprom.h"
25 #include "amdgpu.h"
26 #include "amdgpu_ras.h"
27 #include <linux/bits.h>
28 #include "atom.h"
29 #include "amdgpu_eeprom.h"
30 #include "amdgpu_atomfirmware.h"
31 #include <linux/debugfs.h>
32 #include <linux/uaccess.h>
33
34 #define EEPROM_I2C_MADDR_VEGA20 0x0
35 #define EEPROM_I2C_MADDR_ARCTURUS 0x40000
36 #define EEPROM_I2C_MADDR_ARCTURUS_D342 0x0
37 #define EEPROM_I2C_MADDR_SIENNA_CICHLID 0x0
38 #define EEPROM_I2C_MADDR_ALDEBARAN 0x0
39
40 /*
41 * The 2 macros bellow represent the actual size in bytes that
42 * those entities occupy in the EEPROM memory.
43 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
44 * uses uint64 to store 6b fields such as retired_page.
45 */
46 #define RAS_TABLE_HEADER_SIZE 20
47 #define RAS_TABLE_RECORD_SIZE 24
48
49 /* Table hdr is 'AMDR' */
50 #define RAS_TABLE_HDR_VAL 0x414d4452
51 #define RAS_TABLE_VER 0x00010000
52
53 /* Bad GPU tag ‘BADG’ */
54 #define RAS_TABLE_HDR_BAD 0x42414447
55
56 /* Assume 2-Mbit size EEPROM and take up the whole space. */
57 #define RAS_TBL_SIZE_BYTES (256 * 1024)
58 #define RAS_TABLE_START 0
59 #define RAS_HDR_START RAS_TABLE_START
60 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE)
61 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \
62 / RAS_TABLE_RECORD_SIZE)
63
64 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM
65 * offset off of RAS_TABLE_START. That is, this is something you can
66 * add to control->i2c_address, and then tell I2C layer to read
67 * from/write to there. _N is the so called absolute index,
68 * because it starts right after the table header.
69 */
70 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \
71 (_N) * RAS_TABLE_RECORD_SIZE)
72
73 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \
74 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE)
75
76 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off
77 * of "fri", return the absolute record index off of the end of
78 * the table header.
79 */
80 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \
81 (_C)->ras_max_record_count)
82
83 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \
84 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)
85
86 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev
87
__is_ras_eeprom_supported(struct amdgpu_device * adev)88 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
89 {
90 return adev->asic_type == CHIP_VEGA20 ||
91 adev->asic_type == CHIP_ARCTURUS ||
92 adev->asic_type == CHIP_SIENNA_CICHLID ||
93 adev->asic_type == CHIP_ALDEBARAN;
94 }
95
__get_eeprom_i2c_addr_arct(struct amdgpu_device * adev,struct amdgpu_ras_eeprom_control * control)96 static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev,
97 struct amdgpu_ras_eeprom_control *control)
98 {
99 struct atom_context *atom_ctx = adev->mode_info.atom_context;
100
101 if (!control || !atom_ctx)
102 return false;
103
104 if (strnstr(atom_ctx->vbios_version,
105 "D342",
106 sizeof(atom_ctx->vbios_version)))
107 control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS_D342;
108 else
109 control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;
110
111 return true;
112 }
113
__get_eeprom_i2c_addr(struct amdgpu_device * adev,struct amdgpu_ras_eeprom_control * control)114 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
115 struct amdgpu_ras_eeprom_control *control)
116 {
117 u8 i2c_addr;
118
119 if (!control)
120 return false;
121
122 if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) {
123 /* The address given by VBIOS is an 8-bit, wire-format
124 * address, i.e. the most significant byte.
125 *
126 * Normalize it to a 19-bit EEPROM address. Remove the
127 * device type identifier and make it a 7-bit address;
128 * then make it a 19-bit EEPROM address. See top of
129 * amdgpu_eeprom.c.
130 */
131 i2c_addr = (i2c_addr & 0x0F) >> 1;
132 control->i2c_address = ((u32) i2c_addr) << 16;
133
134 return true;
135 }
136
137 switch (adev->asic_type) {
138 case CHIP_VEGA20:
139 control->i2c_address = EEPROM_I2C_MADDR_VEGA20;
140 break;
141
142 case CHIP_ARCTURUS:
143 return __get_eeprom_i2c_addr_arct(adev, control);
144
145 case CHIP_SIENNA_CICHLID:
146 control->i2c_address = EEPROM_I2C_MADDR_SIENNA_CICHLID;
147 break;
148
149 case CHIP_ALDEBARAN:
150 control->i2c_address = EEPROM_I2C_MADDR_ALDEBARAN;
151 break;
152
153 default:
154 return false;
155 }
156
157 return true;
158 }
159
160 static void
__encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header * hdr,unsigned char * buf)161 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr,
162 unsigned char *buf)
163 {
164 u32 *pp = (uint32_t *)buf;
165
166 pp[0] = cpu_to_le32(hdr->header);
167 pp[1] = cpu_to_le32(hdr->version);
168 pp[2] = cpu_to_le32(hdr->first_rec_offset);
169 pp[3] = cpu_to_le32(hdr->tbl_size);
170 pp[4] = cpu_to_le32(hdr->checksum);
171 }
172
173 static void
__decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header * hdr,unsigned char * buf)174 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr,
175 unsigned char *buf)
176 {
177 u32 *pp = (uint32_t *)buf;
178
179 hdr->header = le32_to_cpu(pp[0]);
180 hdr->version = le32_to_cpu(pp[1]);
181 hdr->first_rec_offset = le32_to_cpu(pp[2]);
182 hdr->tbl_size = le32_to_cpu(pp[3]);
183 hdr->checksum = le32_to_cpu(pp[4]);
184 }
185
__write_table_header(struct amdgpu_ras_eeprom_control * control)186 static int __write_table_header(struct amdgpu_ras_eeprom_control *control)
187 {
188 u8 buf[RAS_TABLE_HEADER_SIZE];
189 struct amdgpu_device *adev = to_amdgpu_device(control);
190 int res;
191
192 memset(buf, 0, sizeof(buf));
193 __encode_table_header_to_buf(&control->tbl_hdr, buf);
194
195 /* i2c may be unstable in gpu reset */
196 down_read(&adev->reset_sem);
197 res = amdgpu_eeprom_write(&adev->pm.smu_i2c,
198 control->i2c_address +
199 control->ras_header_offset,
200 buf, RAS_TABLE_HEADER_SIZE);
201 up_read(&adev->reset_sem);
202
203 if (res < 0) {
204 DRM_ERROR("Failed to write EEPROM table header:%d", res);
205 } else if (res < RAS_TABLE_HEADER_SIZE) {
206 DRM_ERROR("Short write:%d out of %d\n",
207 res, RAS_TABLE_HEADER_SIZE);
208 res = -EIO;
209 } else {
210 res = 0;
211 }
212
213 return res;
214 }
215
__calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control * control)216 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)
217 {
218 int ii;
219 u8 *pp, csum;
220 size_t sz;
221
222 /* Header checksum, skip checksum field in the calculation */
223 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum);
224 pp = (u8 *) &control->tbl_hdr;
225 csum = 0;
226 for (ii = 0; ii < sz; ii++, pp++)
227 csum += *pp;
228
229 return csum;
230 }
231
amdgpu_ras_eeprom_correct_header_tag(struct amdgpu_ras_eeprom_control * control,uint32_t header)232 static int amdgpu_ras_eeprom_correct_header_tag(
233 struct amdgpu_ras_eeprom_control *control,
234 uint32_t header)
235 {
236 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
237 u8 *hh;
238 int res;
239 u8 csum;
240
241 csum = -hdr->checksum;
242
243 hh = (void *) &hdr->header;
244 csum -= (hh[0] + hh[1] + hh[2] + hh[3]);
245 hh = (void *) &header;
246 csum += hh[0] + hh[1] + hh[2] + hh[3];
247 csum = -csum;
248 mutex_lock(&control->ras_tbl_mutex);
249 hdr->header = header;
250 hdr->checksum = csum;
251 res = __write_table_header(control);
252 mutex_unlock(&control->ras_tbl_mutex);
253
254 return res;
255 }
256
257 /**
258 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table
259 * @control: pointer to control structure
260 *
261 * Reset the contents of the header of the RAS EEPROM table.
262 * Return 0 on success, -errno on error.
263 */
amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control * control)264 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
265 {
266 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
267 u8 csum;
268 int res;
269
270 mutex_lock(&control->ras_tbl_mutex);
271
272 hdr->header = RAS_TABLE_HDR_VAL;
273 hdr->version = RAS_TABLE_VER;
274 hdr->first_rec_offset = RAS_RECORD_START;
275 hdr->tbl_size = RAS_TABLE_HEADER_SIZE;
276
277 csum = __calc_hdr_byte_sum(control);
278 csum = -csum;
279 hdr->checksum = csum;
280 res = __write_table_header(control);
281
282 control->ras_num_recs = 0;
283 control->ras_fri = 0;
284
285 amdgpu_ras_debugfs_set_ret_size(control);
286
287 mutex_unlock(&control->ras_tbl_mutex);
288
289 return res;
290 }
291
292 static void
__encode_table_record_to_buf(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,unsigned char * buf)293 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control,
294 struct eeprom_table_record *record,
295 unsigned char *buf)
296 {
297 __le64 tmp = 0;
298 int i = 0;
299
300 /* Next are all record fields according to EEPROM page spec in LE foramt */
301 buf[i++] = record->err_type;
302
303 buf[i++] = record->bank;
304
305 tmp = cpu_to_le64(record->ts);
306 memcpy(buf + i, &tmp, 8);
307 i += 8;
308
309 tmp = cpu_to_le64((record->offset & 0xffffffffffff));
310 memcpy(buf + i, &tmp, 6);
311 i += 6;
312
313 buf[i++] = record->mem_channel;
314 buf[i++] = record->mcumc_id;
315
316 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
317 memcpy(buf + i, &tmp, 6);
318 }
319
320 static void
__decode_table_record_from_buf(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,unsigned char * buf)321 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control,
322 struct eeprom_table_record *record,
323 unsigned char *buf)
324 {
325 __le64 tmp = 0;
326 int i = 0;
327
328 /* Next are all record fields according to EEPROM page spec in LE foramt */
329 record->err_type = buf[i++];
330
331 record->bank = buf[i++];
332
333 memcpy(&tmp, buf + i, 8);
334 record->ts = le64_to_cpu(tmp);
335 i += 8;
336
337 memcpy(&tmp, buf + i, 6);
338 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
339 i += 6;
340
341 record->mem_channel = buf[i++];
342 record->mcumc_id = buf[i++];
343
344 memcpy(&tmp, buf + i, 6);
345 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
346 }
347
amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device * adev)348 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev)
349 {
350 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
351
352 if (!__is_ras_eeprom_supported(adev))
353 return false;
354
355 /* skip check eeprom table for VEGA20 Gaming */
356 if (!con)
357 return false;
358 else
359 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC)))
360 return false;
361
362 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) {
363 dev_warn(adev->dev, "This GPU is in BAD status.");
364 dev_warn(adev->dev, "Please retire it or set a larger "
365 "threshold value when reloading driver.\n");
366 return true;
367 }
368
369 return false;
370 }
371
372 /**
373 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM
374 * @control: pointer to control structure
375 * @buf: pointer to buffer containing data to write
376 * @fri: start writing at this index
377 * @num: number of records to write
378 *
379 * The caller must hold the table mutex in @control.
380 * Return 0 on success, -errno otherwise.
381 */
__amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control * control,u8 * buf,const u32 fri,const u32 num)382 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,
383 u8 *buf, const u32 fri, const u32 num)
384 {
385 struct amdgpu_device *adev = to_amdgpu_device(control);
386 u32 buf_size;
387 int res;
388
389 /* i2c may be unstable in gpu reset */
390 down_read(&adev->reset_sem);
391 buf_size = num * RAS_TABLE_RECORD_SIZE;
392 res = amdgpu_eeprom_write(&adev->pm.smu_i2c,
393 control->i2c_address +
394 RAS_INDEX_TO_OFFSET(control, fri),
395 buf, buf_size);
396 up_read(&adev->reset_sem);
397 if (res < 0) {
398 DRM_ERROR("Writing %d EEPROM table records error:%d",
399 num, res);
400 } else if (res < buf_size) {
401 /* Short write, return error.
402 */
403 DRM_ERROR("Wrote %d records out of %d",
404 res / RAS_TABLE_RECORD_SIZE, num);
405 res = -EIO;
406 } else {
407 res = 0;
408 }
409
410 return res;
411 }
412
413 static int
amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,const u32 num)414 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,
415 struct eeprom_table_record *record,
416 const u32 num)
417 {
418 u32 a, b, i;
419 u8 *buf, *pp;
420 int res;
421
422 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
423 if (!buf)
424 return -ENOMEM;
425
426 /* Encode all of them in one go.
427 */
428 pp = buf;
429 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE)
430 __encode_table_record_to_buf(control, &record[i], pp);
431
432 /* a, first record index to write into.
433 * b, last record index to write into.
434 * a = first index to read (fri) + number of records in the table,
435 * b = a + @num - 1.
436 * Let N = control->ras_max_num_record_count, then we have,
437 * case 0: 0 <= a <= b < N,
438 * just append @num records starting at a;
439 * case 1: 0 <= a < N <= b,
440 * append (N - a) records starting at a, and
441 * append the remainder, b % N + 1, starting at 0.
442 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases,
443 * case 2a: 0 <= a <= b < N
444 * append num records starting at a; and fix fri if b overwrote it,
445 * and since a <= b, if b overwrote it then a must've also,
446 * and if b didn't overwrite it, then a didn't also.
447 * case 2b: 0 <= b < a < N
448 * write num records starting at a, which wraps around 0=N
449 * and overwrite fri unconditionally. Now from case 2a,
450 * this means that b eclipsed fri to overwrite it and wrap
451 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally
452 * set fri = b + 1 (mod N).
453 * Now, since fri is updated in every case, except the trivial case 0,
454 * the number of records present in the table after writing, is,
455 * num_recs - 1 = b - fri (mod N), and we take the positive value,
456 * by adding an arbitrary multiple of N before taking the modulo N
457 * as shown below.
458 */
459 a = control->ras_fri + control->ras_num_recs;
460 b = a + num - 1;
461 if (b < control->ras_max_record_count) {
462 res = __amdgpu_ras_eeprom_write(control, buf, a, num);
463 } else if (a < control->ras_max_record_count) {
464 u32 g0, g1;
465
466 g0 = control->ras_max_record_count - a;
467 g1 = b % control->ras_max_record_count + 1;
468 res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
469 if (res)
470 goto Out;
471 res = __amdgpu_ras_eeprom_write(control,
472 buf + g0 * RAS_TABLE_RECORD_SIZE,
473 0, g1);
474 if (res)
475 goto Out;
476 if (g1 > control->ras_fri)
477 control->ras_fri = g1 % control->ras_max_record_count;
478 } else {
479 a %= control->ras_max_record_count;
480 b %= control->ras_max_record_count;
481
482 if (a <= b) {
483 /* Note that, b - a + 1 = num. */
484 res = __amdgpu_ras_eeprom_write(control, buf, a, num);
485 if (res)
486 goto Out;
487 if (b >= control->ras_fri)
488 control->ras_fri = (b + 1) % control->ras_max_record_count;
489 } else {
490 u32 g0, g1;
491
492 /* b < a, which means, we write from
493 * a to the end of the table, and from
494 * the start of the table to b.
495 */
496 g0 = control->ras_max_record_count - a;
497 g1 = b + 1;
498 res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
499 if (res)
500 goto Out;
501 res = __amdgpu_ras_eeprom_write(control,
502 buf + g0 * RAS_TABLE_RECORD_SIZE,
503 0, g1);
504 if (res)
505 goto Out;
506 control->ras_fri = g1 % control->ras_max_record_count;
507 }
508 }
509 control->ras_num_recs = 1 + (control->ras_max_record_count + b
510 - control->ras_fri)
511 % control->ras_max_record_count;
512 Out:
513 kfree(buf);
514 return res;
515 }
516
517 static int
amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control * control)518 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)
519 {
520 struct amdgpu_device *adev = to_amdgpu_device(control);
521 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
522 u8 *buf, *pp, csum;
523 u32 buf_size;
524 int res;
525
526 /* Modify the header if it exceeds.
527 */
528 if (amdgpu_bad_page_threshold != 0 &&
529 control->ras_num_recs >= ras->bad_page_cnt_threshold) {
530 dev_warn(adev->dev,
531 "Saved bad pages %d reaches threshold value %d\n",
532 control->ras_num_recs, ras->bad_page_cnt_threshold);
533 control->tbl_hdr.header = RAS_TABLE_HDR_BAD;
534 }
535
536 control->tbl_hdr.version = RAS_TABLE_VER;
537 control->tbl_hdr.first_rec_offset = RAS_INDEX_TO_OFFSET(control, control->ras_fri);
538 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
539 control->tbl_hdr.checksum = 0;
540
541 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
542 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
543 if (!buf) {
544 DRM_ERROR("allocating memory for table of size %d bytes failed\n",
545 control->tbl_hdr.tbl_size);
546 res = -ENOMEM;
547 goto Out;
548 }
549
550 down_read(&adev->reset_sem);
551 res = amdgpu_eeprom_read(&adev->pm.smu_i2c,
552 control->i2c_address +
553 control->ras_record_offset,
554 buf, buf_size);
555 up_read(&adev->reset_sem);
556 if (res < 0) {
557 DRM_ERROR("EEPROM failed reading records:%d\n",
558 res);
559 goto Out;
560 } else if (res < buf_size) {
561 DRM_ERROR("EEPROM read %d out of %d bytes\n",
562 res, buf_size);
563 res = -EIO;
564 goto Out;
565 }
566
567 /* Recalc the checksum.
568 */
569 csum = 0;
570 for (pp = buf; pp < buf + buf_size; pp++)
571 csum += *pp;
572
573 csum += __calc_hdr_byte_sum(control);
574 /* avoid sign extension when assigning to "checksum" */
575 csum = -csum;
576 control->tbl_hdr.checksum = csum;
577 res = __write_table_header(control);
578 Out:
579 kfree(buf);
580 return res;
581 }
582
583 /**
584 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table
585 * @control: pointer to control structure
586 * @record: array of records to append
587 * @num: number of records in @record array
588 *
589 * Append @num records to the table, calculate the checksum and write
590 * the table back to EEPROM. The maximum number of records that
591 * can be appended is between 1 and control->ras_max_record_count,
592 * regardless of how many records are already stored in the table.
593 *
594 * Return 0 on success or if EEPROM is not supported, -errno on error.
595 */
amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,const u32 num)596 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
597 struct eeprom_table_record *record,
598 const u32 num)
599 {
600 struct amdgpu_device *adev = to_amdgpu_device(control);
601 int res;
602
603 if (!__is_ras_eeprom_supported(adev))
604 return 0;
605
606 if (num == 0) {
607 DRM_ERROR("will not append 0 records\n");
608 return -EINVAL;
609 } else if (num > control->ras_max_record_count) {
610 DRM_ERROR("cannot append %d records than the size of table %d\n",
611 num, control->ras_max_record_count);
612 return -EINVAL;
613 }
614
615 mutex_lock(&control->ras_tbl_mutex);
616
617 res = amdgpu_ras_eeprom_append_table(control, record, num);
618 if (!res)
619 res = amdgpu_ras_eeprom_update_header(control);
620 if (!res)
621 amdgpu_ras_debugfs_set_ret_size(control);
622
623 mutex_unlock(&control->ras_tbl_mutex);
624 return res;
625 }
626
627 /**
628 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer
629 * @control: pointer to control structure
630 * @buf: pointer to buffer to read into
631 * @fri: first record index, start reading at this index, absolute index
632 * @num: number of records to read
633 *
634 * The caller must hold the table mutex in @control.
635 * Return 0 on success, -errno otherwise.
636 */
__amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control * control,u8 * buf,const u32 fri,const u32 num)637 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
638 u8 *buf, const u32 fri, const u32 num)
639 {
640 struct amdgpu_device *adev = to_amdgpu_device(control);
641 u32 buf_size;
642 int res;
643
644 /* i2c may be unstable in gpu reset */
645 down_read(&adev->reset_sem);
646 buf_size = num * RAS_TABLE_RECORD_SIZE;
647 res = amdgpu_eeprom_read(&adev->pm.smu_i2c,
648 control->i2c_address +
649 RAS_INDEX_TO_OFFSET(control, fri),
650 buf, buf_size);
651 up_read(&adev->reset_sem);
652 if (res < 0) {
653 DRM_ERROR("Reading %d EEPROM table records error:%d",
654 num, res);
655 } else if (res < buf_size) {
656 /* Short read, return error.
657 */
658 DRM_ERROR("Read %d records out of %d",
659 res / RAS_TABLE_RECORD_SIZE, num);
660 res = -EIO;
661 } else {
662 res = 0;
663 }
664
665 return res;
666 }
667
668 /**
669 * amdgpu_ras_eeprom_read -- read EEPROM
670 * @control: pointer to control structure
671 * @record: array of records to read into
672 * @num: number of records in @record
673 *
674 * Reads num records from the RAS table in EEPROM and
675 * writes the data into @record array.
676 *
677 * Returns 0 on success, -errno on error.
678 */
amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,const u32 num)679 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
680 struct eeprom_table_record *record,
681 const u32 num)
682 {
683 struct amdgpu_device *adev = to_amdgpu_device(control);
684 int i, res;
685 u8 *buf, *pp;
686 u32 g0, g1;
687
688 if (!__is_ras_eeprom_supported(adev))
689 return 0;
690
691 if (num == 0) {
692 DRM_ERROR("will not read 0 records\n");
693 return -EINVAL;
694 } else if (num > control->ras_num_recs) {
695 DRM_ERROR("too many records to read:%d available:%d\n",
696 num, control->ras_num_recs);
697 return -EINVAL;
698 }
699
700 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
701 if (!buf)
702 return -ENOMEM;
703
704 /* Determine how many records to read, from the first record
705 * index, fri, to the end of the table, and from the beginning
706 * of the table, such that the total number of records is
707 * @num, and we handle wrap around when fri > 0 and
708 * fri + num > RAS_MAX_RECORD_COUNT.
709 *
710 * First we compute the index of the last element
711 * which would be fetched from each region,
712 * g0 is in [fri, fri + num - 1], and
713 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1].
714 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of
715 * the last element to fetch, we set g0 to _the number_
716 * of elements to fetch, @num, since we know that the last
717 * indexed to be fetched does not exceed the table.
718 *
719 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then
720 * we set g0 to the number of elements to read
721 * until the end of the table, and g1 to the number of
722 * elements to read from the beginning of the table.
723 */
724 g0 = control->ras_fri + num - 1;
725 g1 = g0 % control->ras_max_record_count;
726 if (g0 < control->ras_max_record_count) {
727 g0 = num;
728 g1 = 0;
729 } else {
730 g0 = control->ras_max_record_count - control->ras_fri;
731 g1 += 1;
732 }
733
734 mutex_lock(&control->ras_tbl_mutex);
735 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0);
736 if (res)
737 goto Out;
738 if (g1) {
739 res = __amdgpu_ras_eeprom_read(control,
740 buf + g0 * RAS_TABLE_RECORD_SIZE,
741 0, g1);
742 if (res)
743 goto Out;
744 }
745
746 res = 0;
747
748 /* Read up everything? Then transform.
749 */
750 pp = buf;
751 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE)
752 __decode_table_record_from_buf(control, &record[i], pp);
753 Out:
754 kfree(buf);
755 mutex_unlock(&control->ras_tbl_mutex);
756
757 return res;
758 }
759
amdgpu_ras_eeprom_max_record_count(void)760 uint32_t amdgpu_ras_eeprom_max_record_count(void)
761 {
762 return RAS_MAX_RECORD_COUNT;
763 }
764
765 static ssize_t
amdgpu_ras_debugfs_eeprom_size_read(struct file * f,char __user * buf,size_t size,loff_t * pos)766 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf,
767 size_t size, loff_t *pos)
768 {
769 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
770 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
771 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
772 u8 data[50];
773 int res;
774
775 if (!size)
776 return size;
777
778 if (!ras || !control) {
779 res = snprintf(data, sizeof(data), "Not supported\n");
780 } else {
781 res = snprintf(data, sizeof(data), "%d bytes or %d records\n",
782 RAS_TBL_SIZE_BYTES, control->ras_max_record_count);
783 }
784
785 if (*pos >= res)
786 return 0;
787
788 res -= *pos;
789 res = min_t(size_t, res, size);
790
791 if (copy_to_user(buf, &data[*pos], res))
792 return -EFAULT;
793
794 *pos += res;
795
796 return res;
797 }
798
799 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = {
800 .owner = THIS_MODULE,
801 .read = amdgpu_ras_debugfs_eeprom_size_read,
802 .write = NULL,
803 .llseek = default_llseek,
804 };
805
806 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n";
807 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n";
808 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1)
809 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n";
810 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n";
811 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1)
812
813 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = {
814 "ignore",
815 "re",
816 "ue",
817 };
818
amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control * control)819 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)
820 {
821 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size +
822 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;
823 }
824
amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control * control)825 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)
826 {
827 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,
828 eeprom_control);
829 struct dentry *de = ras->de_ras_eeprom_table;
830
831 if (de)
832 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);
833 }
834
amdgpu_ras_debugfs_table_read(struct file * f,char __user * buf,size_t size,loff_t * pos)835 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf,
836 size_t size, loff_t *pos)
837 {
838 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
839 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
840 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;
841 const size_t orig_size = size;
842 int res = -EFAULT;
843 size_t data_len;
844
845 mutex_lock(&control->ras_tbl_mutex);
846
847 /* We want *pos - data_len > 0, which means there's
848 * bytes to be printed from data.
849 */
850 data_len = strlen(tbl_hdr_str);
851 if (*pos < data_len) {
852 data_len -= *pos;
853 data_len = min_t(size_t, data_len, size);
854 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len))
855 goto Out;
856 buf += data_len;
857 size -= data_len;
858 *pos += data_len;
859 }
860
861 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size;
862 if (*pos < data_len && size > 0) {
863 u8 data[tbl_hdr_fmt_size + 1];
864 loff_t lpos;
865
866 snprintf(data, sizeof(data), tbl_hdr_fmt,
867 control->tbl_hdr.header,
868 control->tbl_hdr.version,
869 control->tbl_hdr.first_rec_offset,
870 control->tbl_hdr.tbl_size,
871 control->tbl_hdr.checksum);
872
873 data_len -= *pos;
874 data_len = min_t(size_t, data_len, size);
875 lpos = *pos - strlen(tbl_hdr_str);
876 if (copy_to_user(buf, &data[lpos], data_len))
877 goto Out;
878 buf += data_len;
879 size -= data_len;
880 *pos += data_len;
881 }
882
883 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str);
884 if (*pos < data_len && size > 0) {
885 loff_t lpos;
886
887 data_len -= *pos;
888 data_len = min_t(size_t, data_len, size);
889 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size;
890 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len))
891 goto Out;
892 buf += data_len;
893 size -= data_len;
894 *pos += data_len;
895 }
896
897 data_len = amdgpu_ras_debugfs_table_size(control);
898 if (*pos < data_len && size > 0) {
899 u8 dare[RAS_TABLE_RECORD_SIZE];
900 u8 data[rec_hdr_fmt_size + 1];
901 struct eeprom_table_record record;
902 int s, r;
903
904 /* Find the starting record index
905 */
906 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
907 strlen(rec_hdr_str);
908 s = s / rec_hdr_fmt_size;
909 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
910 strlen(rec_hdr_str);
911 r = r % rec_hdr_fmt_size;
912
913 for ( ; size > 0 && s < control->ras_num_recs; s++) {
914 u32 ai = RAS_RI_TO_AI(control, s);
915 /* Read a single record
916 */
917 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1);
918 if (res)
919 goto Out;
920 __decode_table_record_from_buf(control, &record, dare);
921 snprintf(data, sizeof(data), rec_hdr_fmt,
922 s,
923 RAS_INDEX_TO_OFFSET(control, ai),
924 record_err_type_str[record.err_type],
925 record.bank,
926 record.ts,
927 record.offset,
928 record.mem_channel,
929 record.mcumc_id,
930 record.retired_page);
931
932 data_len = min_t(size_t, rec_hdr_fmt_size - r, size);
933 if (copy_to_user(buf, &data[r], data_len)) {
934 res = -EFAULT;
935 goto Out;
936 }
937 buf += data_len;
938 size -= data_len;
939 *pos += data_len;
940 r = 0;
941 }
942 }
943 res = 0;
944 Out:
945 mutex_unlock(&control->ras_tbl_mutex);
946 return res < 0 ? res : orig_size - size;
947 }
948
949 static ssize_t
amdgpu_ras_debugfs_eeprom_table_read(struct file * f,char __user * buf,size_t size,loff_t * pos)950 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf,
951 size_t size, loff_t *pos)
952 {
953 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
954 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
955 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
956 u8 data[81];
957 int res;
958
959 if (!size)
960 return size;
961
962 if (!ras || !control) {
963 res = snprintf(data, sizeof(data), "Not supported\n");
964 if (*pos >= res)
965 return 0;
966
967 res -= *pos;
968 res = min_t(size_t, res, size);
969
970 if (copy_to_user(buf, &data[*pos], res))
971 return -EFAULT;
972
973 *pos += res;
974
975 return res;
976 } else {
977 return amdgpu_ras_debugfs_table_read(f, buf, size, pos);
978 }
979 }
980
981 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = {
982 .owner = THIS_MODULE,
983 .read = amdgpu_ras_debugfs_eeprom_table_read,
984 .write = NULL,
985 .llseek = default_llseek,
986 };
987
988 /**
989 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum
990 * @control: pointer to control structure
991 *
992 * Check the checksum of the stored in EEPROM RAS table.
993 *
994 * Return 0 if the checksum is correct,
995 * positive if it is not correct, and
996 * -errno on I/O error.
997 */
__verify_ras_table_checksum(struct amdgpu_ras_eeprom_control * control)998 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control)
999 {
1000 struct amdgpu_device *adev = to_amdgpu_device(control);
1001 int buf_size, res;
1002 u8 csum, *buf, *pp;
1003
1004 buf_size = RAS_TABLE_HEADER_SIZE +
1005 control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
1006 buf = kzalloc(buf_size, GFP_KERNEL);
1007 if (!buf) {
1008 DRM_ERROR("Out of memory checking RAS table checksum.\n");
1009 return -ENOMEM;
1010 }
1011
1012 res = amdgpu_eeprom_read(&adev->pm.smu_i2c,
1013 control->i2c_address +
1014 control->ras_header_offset,
1015 buf, buf_size);
1016 if (res < buf_size) {
1017 DRM_ERROR("Partial read for checksum, res:%d\n", res);
1018 /* On partial reads, return -EIO.
1019 */
1020 if (res >= 0)
1021 res = -EIO;
1022 goto Out;
1023 }
1024
1025 csum = 0;
1026 for (pp = buf; pp < buf + buf_size; pp++)
1027 csum += *pp;
1028 Out:
1029 kfree(buf);
1030 return res < 0 ? res : csum;
1031 }
1032
amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control * control,bool * exceed_err_limit)1033 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
1034 bool *exceed_err_limit)
1035 {
1036 struct amdgpu_device *adev = to_amdgpu_device(control);
1037 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 };
1038 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
1039 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1040 int res;
1041
1042 *exceed_err_limit = false;
1043
1044 if (!__is_ras_eeprom_supported(adev))
1045 return 0;
1046
1047 /* Verify i2c adapter is initialized */
1048 if (!adev->pm.smu_i2c.algo)
1049 return -ENOENT;
1050
1051 if (!__get_eeprom_i2c_addr(adev, control))
1052 return -EINVAL;
1053
1054 control->ras_header_offset = RAS_HDR_START;
1055 control->ras_record_offset = RAS_RECORD_START;
1056 control->ras_max_record_count = RAS_MAX_RECORD_COUNT;
1057 mutex_init(&control->ras_tbl_mutex);
1058
1059 /* Read the table header from EEPROM address */
1060 res = amdgpu_eeprom_read(&adev->pm.smu_i2c,
1061 control->i2c_address + control->ras_header_offset,
1062 buf, RAS_TABLE_HEADER_SIZE);
1063 if (res < RAS_TABLE_HEADER_SIZE) {
1064 DRM_ERROR("Failed to read EEPROM table header, res:%d", res);
1065 return res >= 0 ? -EIO : res;
1066 }
1067
1068 __decode_table_header_from_buf(hdr, buf);
1069
1070 control->ras_num_recs = RAS_NUM_RECS(hdr);
1071 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);
1072
1073 if (hdr->header == RAS_TABLE_HDR_VAL) {
1074 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
1075 control->ras_num_recs);
1076 res = __verify_ras_table_checksum(control);
1077 if (res)
1078 DRM_ERROR("RAS table incorrect checksum or error:%d\n",
1079 res);
1080 } else if (hdr->header == RAS_TABLE_HDR_BAD &&
1081 amdgpu_bad_page_threshold != 0) {
1082 res = __verify_ras_table_checksum(control);
1083 if (res)
1084 DRM_ERROR("RAS Table incorrect checksum or error:%d\n",
1085 res);
1086 if (ras->bad_page_cnt_threshold > control->ras_num_recs) {
1087 /* This means that, the threshold was increased since
1088 * the last time the system was booted, and now,
1089 * ras->bad_page_cnt_threshold - control->num_recs > 0,
1090 * so that at least one more record can be saved,
1091 * before the page count threshold is reached.
1092 */
1093 dev_info(adev->dev,
1094 "records:%d threshold:%d, resetting "
1095 "RAS table header signature",
1096 control->ras_num_recs,
1097 ras->bad_page_cnt_threshold);
1098 res = amdgpu_ras_eeprom_correct_header_tag(control,
1099 RAS_TABLE_HDR_VAL);
1100 } else {
1101 *exceed_err_limit = true;
1102 dev_err(adev->dev,
1103 "RAS records:%d exceed threshold:%d, "
1104 "maybe retire this GPU?",
1105 control->ras_num_recs, ras->bad_page_cnt_threshold);
1106 }
1107 } else {
1108 DRM_INFO("Creating a new EEPROM table");
1109
1110 res = amdgpu_ras_eeprom_reset_table(control);
1111 }
1112
1113 return res < 0 ? res : 0;
1114 }
1115