1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
6 */
7
8 #include <linux/module.h>
9 #include <linux/firmware.h>
10 #include <linux/of.h>
11 #include <linux/property.h>
12 #include <linux/dmi.h>
13 #include <linux/ctype.h>
14 #include <linux/pm_qos.h>
15 #include <asm/byteorder.h>
16
17 #include "core.h"
18 #include "mac.h"
19 #include "htc.h"
20 #include "hif.h"
21 #include "wmi.h"
22 #include "bmi.h"
23 #include "debug.h"
24 #include "htt.h"
25 #include "testmode.h"
26 #include "wmi-ops.h"
27 #include "coredump.h"
28
29 unsigned int ath10k_debug_mask;
30 EXPORT_SYMBOL(ath10k_debug_mask);
31
32 static unsigned int ath10k_cryptmode_param;
33 static bool uart_print;
34 static bool skip_otp;
35 static bool rawmode;
36 static bool fw_diag_log;
37
38 unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) |
39 BIT(ATH10K_FW_CRASH_DUMP_CE_DATA);
40
41 /* FIXME: most of these should be readonly */
42 module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
43 module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
44 module_param(uart_print, bool, 0644);
45 module_param(skip_otp, bool, 0644);
46 module_param(rawmode, bool, 0644);
47 module_param(fw_diag_log, bool, 0644);
48 module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444);
49
50 MODULE_PARM_DESC(debug_mask, "Debugging mask");
51 MODULE_PARM_DESC(uart_print, "Uart target debugging");
52 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
53 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
54 MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath");
55 MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file");
56 MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging");
57
58 static const struct ath10k_hw_params ath10k_hw_params_list[] = {
59 {
60 .id = QCA988X_HW_2_0_VERSION,
61 .dev_id = QCA988X_2_0_DEVICE_ID,
62 .bus = ATH10K_BUS_PCI,
63 .name = "qca988x hw2.0",
64 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
65 .uart_pin = 7,
66 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
67 .otp_exe_param = 0,
68 .channel_counters_freq_hz = 88000,
69 .max_probe_resp_desc_thres = 0,
70 .cal_data_len = 2116,
71 .fw = {
72 .dir = QCA988X_HW_2_0_FW_DIR,
73 .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
74 .board_size = QCA988X_BOARD_DATA_SZ,
75 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
76 },
77 .hw_ops = &qca988x_ops,
78 .decap_align_bytes = 4,
79 .spectral_bin_discard = 0,
80 .spectral_bin_offset = 0,
81 .vht160_mcs_rx_highest = 0,
82 .vht160_mcs_tx_highest = 0,
83 .n_cipher_suites = 8,
84 .ast_skid_limit = 0x10,
85 .num_wds_entries = 0x20,
86 .target_64bit = false,
87 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
88 .shadow_reg_support = false,
89 .rri_on_ddr = false,
90 .hw_filter_reset_required = true,
91 .fw_diag_ce_download = false,
92 .credit_size_workaround = false,
93 .tx_stats_over_pktlog = true,
94 .dynamic_sar_support = false,
95 },
96 {
97 .id = QCA988X_HW_2_0_VERSION,
98 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT,
99 .name = "qca988x hw2.0 ubiquiti",
100 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
101 .uart_pin = 7,
102 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
103 .otp_exe_param = 0,
104 .channel_counters_freq_hz = 88000,
105 .max_probe_resp_desc_thres = 0,
106 .cal_data_len = 2116,
107 .fw = {
108 .dir = QCA988X_HW_2_0_FW_DIR,
109 .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
110 .board_size = QCA988X_BOARD_DATA_SZ,
111 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
112 },
113 .hw_ops = &qca988x_ops,
114 .decap_align_bytes = 4,
115 .spectral_bin_discard = 0,
116 .spectral_bin_offset = 0,
117 .vht160_mcs_rx_highest = 0,
118 .vht160_mcs_tx_highest = 0,
119 .n_cipher_suites = 8,
120 .ast_skid_limit = 0x10,
121 .num_wds_entries = 0x20,
122 .target_64bit = false,
123 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
124 .shadow_reg_support = false,
125 .rri_on_ddr = false,
126 .hw_filter_reset_required = true,
127 .fw_diag_ce_download = false,
128 .credit_size_workaround = false,
129 .tx_stats_over_pktlog = true,
130 .dynamic_sar_support = false,
131 },
132 {
133 .id = QCA9887_HW_1_0_VERSION,
134 .dev_id = QCA9887_1_0_DEVICE_ID,
135 .bus = ATH10K_BUS_PCI,
136 .name = "qca9887 hw1.0",
137 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
138 .uart_pin = 7,
139 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
140 .otp_exe_param = 0,
141 .channel_counters_freq_hz = 88000,
142 .max_probe_resp_desc_thres = 0,
143 .cal_data_len = 2116,
144 .fw = {
145 .dir = QCA9887_HW_1_0_FW_DIR,
146 .board = QCA9887_HW_1_0_BOARD_DATA_FILE,
147 .board_size = QCA9887_BOARD_DATA_SZ,
148 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ,
149 },
150 .hw_ops = &qca988x_ops,
151 .decap_align_bytes = 4,
152 .spectral_bin_discard = 0,
153 .spectral_bin_offset = 0,
154 .vht160_mcs_rx_highest = 0,
155 .vht160_mcs_tx_highest = 0,
156 .n_cipher_suites = 8,
157 .ast_skid_limit = 0x10,
158 .num_wds_entries = 0x20,
159 .target_64bit = false,
160 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
161 .shadow_reg_support = false,
162 .rri_on_ddr = false,
163 .hw_filter_reset_required = true,
164 .fw_diag_ce_download = false,
165 .credit_size_workaround = false,
166 .tx_stats_over_pktlog = false,
167 .dynamic_sar_support = false,
168 },
169 {
170 .id = QCA6174_HW_3_2_VERSION,
171 .dev_id = QCA6174_3_2_DEVICE_ID,
172 .bus = ATH10K_BUS_SDIO,
173 .name = "qca6174 hw3.2 sdio",
174 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
175 .uart_pin = 19,
176 .otp_exe_param = 0,
177 .channel_counters_freq_hz = 88000,
178 .max_probe_resp_desc_thres = 0,
179 .cal_data_len = 0,
180 .fw = {
181 .dir = QCA6174_HW_3_0_FW_DIR,
182 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
183 .board_size = QCA6174_BOARD_DATA_SZ,
184 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
185 },
186 .hw_ops = &qca6174_sdio_ops,
187 .hw_clk = qca6174_clk,
188 .target_cpu_freq = 176000000,
189 .decap_align_bytes = 4,
190 .n_cipher_suites = 8,
191 .num_peers = 10,
192 .ast_skid_limit = 0x10,
193 .num_wds_entries = 0x20,
194 .uart_pin_workaround = true,
195 .tx_stats_over_pktlog = false,
196 .credit_size_workaround = false,
197 .bmi_large_size_download = true,
198 .supports_peer_stats_info = true,
199 .dynamic_sar_support = true,
200 },
201 {
202 .id = QCA6174_HW_2_1_VERSION,
203 .dev_id = QCA6164_2_1_DEVICE_ID,
204 .bus = ATH10K_BUS_PCI,
205 .name = "qca6164 hw2.1",
206 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
207 .uart_pin = 6,
208 .otp_exe_param = 0,
209 .channel_counters_freq_hz = 88000,
210 .max_probe_resp_desc_thres = 0,
211 .cal_data_len = 8124,
212 .fw = {
213 .dir = QCA6174_HW_2_1_FW_DIR,
214 .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
215 .board_size = QCA6174_BOARD_DATA_SZ,
216 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
217 },
218 .hw_ops = &qca988x_ops,
219 .decap_align_bytes = 4,
220 .spectral_bin_discard = 0,
221 .spectral_bin_offset = 0,
222 .vht160_mcs_rx_highest = 0,
223 .vht160_mcs_tx_highest = 0,
224 .n_cipher_suites = 8,
225 .ast_skid_limit = 0x10,
226 .num_wds_entries = 0x20,
227 .target_64bit = false,
228 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
229 .shadow_reg_support = false,
230 .rri_on_ddr = false,
231 .hw_filter_reset_required = true,
232 .fw_diag_ce_download = false,
233 .credit_size_workaround = false,
234 .tx_stats_over_pktlog = false,
235 .dynamic_sar_support = false,
236 },
237 {
238 .id = QCA6174_HW_2_1_VERSION,
239 .dev_id = QCA6174_2_1_DEVICE_ID,
240 .bus = ATH10K_BUS_PCI,
241 .name = "qca6174 hw2.1",
242 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
243 .uart_pin = 6,
244 .otp_exe_param = 0,
245 .channel_counters_freq_hz = 88000,
246 .max_probe_resp_desc_thres = 0,
247 .cal_data_len = 8124,
248 .fw = {
249 .dir = QCA6174_HW_2_1_FW_DIR,
250 .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
251 .board_size = QCA6174_BOARD_DATA_SZ,
252 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
253 },
254 .hw_ops = &qca988x_ops,
255 .decap_align_bytes = 4,
256 .spectral_bin_discard = 0,
257 .spectral_bin_offset = 0,
258 .vht160_mcs_rx_highest = 0,
259 .vht160_mcs_tx_highest = 0,
260 .n_cipher_suites = 8,
261 .ast_skid_limit = 0x10,
262 .num_wds_entries = 0x20,
263 .target_64bit = false,
264 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
265 .shadow_reg_support = false,
266 .rri_on_ddr = false,
267 .hw_filter_reset_required = true,
268 .fw_diag_ce_download = false,
269 .credit_size_workaround = false,
270 .tx_stats_over_pktlog = false,
271 .dynamic_sar_support = false,
272 },
273 {
274 .id = QCA6174_HW_3_0_VERSION,
275 .dev_id = QCA6174_2_1_DEVICE_ID,
276 .bus = ATH10K_BUS_PCI,
277 .name = "qca6174 hw3.0",
278 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
279 .uart_pin = 6,
280 .otp_exe_param = 0,
281 .channel_counters_freq_hz = 88000,
282 .max_probe_resp_desc_thres = 0,
283 .cal_data_len = 8124,
284 .fw = {
285 .dir = QCA6174_HW_3_0_FW_DIR,
286 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
287 .board_size = QCA6174_BOARD_DATA_SZ,
288 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
289 },
290 .hw_ops = &qca988x_ops,
291 .decap_align_bytes = 4,
292 .spectral_bin_discard = 0,
293 .spectral_bin_offset = 0,
294 .vht160_mcs_rx_highest = 0,
295 .vht160_mcs_tx_highest = 0,
296 .n_cipher_suites = 8,
297 .ast_skid_limit = 0x10,
298 .num_wds_entries = 0x20,
299 .target_64bit = false,
300 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
301 .shadow_reg_support = false,
302 .rri_on_ddr = false,
303 .hw_filter_reset_required = true,
304 .fw_diag_ce_download = false,
305 .credit_size_workaround = false,
306 .tx_stats_over_pktlog = false,
307 .dynamic_sar_support = false,
308 },
309 {
310 .id = QCA6174_HW_3_2_VERSION,
311 .dev_id = QCA6174_2_1_DEVICE_ID,
312 .bus = ATH10K_BUS_PCI,
313 .name = "qca6174 hw3.2",
314 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
315 .uart_pin = 6,
316 .otp_exe_param = 0,
317 .channel_counters_freq_hz = 88000,
318 .max_probe_resp_desc_thres = 0,
319 .cal_data_len = 8124,
320 .fw = {
321 /* uses same binaries as hw3.0 */
322 .dir = QCA6174_HW_3_0_FW_DIR,
323 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
324 .board_size = QCA6174_BOARD_DATA_SZ,
325 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
326 },
327 .hw_ops = &qca6174_ops,
328 .hw_clk = qca6174_clk,
329 .target_cpu_freq = 176000000,
330 .decap_align_bytes = 4,
331 .spectral_bin_discard = 0,
332 .spectral_bin_offset = 0,
333 .vht160_mcs_rx_highest = 0,
334 .vht160_mcs_tx_highest = 0,
335 .n_cipher_suites = 8,
336 .ast_skid_limit = 0x10,
337 .num_wds_entries = 0x20,
338 .target_64bit = false,
339 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
340 .shadow_reg_support = false,
341 .rri_on_ddr = false,
342 .hw_filter_reset_required = true,
343 .fw_diag_ce_download = true,
344 .credit_size_workaround = false,
345 .tx_stats_over_pktlog = false,
346 .supports_peer_stats_info = true,
347 .dynamic_sar_support = true,
348 },
349 {
350 .id = QCA99X0_HW_2_0_DEV_VERSION,
351 .dev_id = QCA99X0_2_0_DEVICE_ID,
352 .bus = ATH10K_BUS_PCI,
353 .name = "qca99x0 hw2.0",
354 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
355 .uart_pin = 7,
356 .otp_exe_param = 0x00000700,
357 .continuous_frag_desc = true,
358 .cck_rate_map_rev2 = true,
359 .channel_counters_freq_hz = 150000,
360 .max_probe_resp_desc_thres = 24,
361 .tx_chain_mask = 0xf,
362 .rx_chain_mask = 0xf,
363 .max_spatial_stream = 4,
364 .cal_data_len = 12064,
365 .fw = {
366 .dir = QCA99X0_HW_2_0_FW_DIR,
367 .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
368 .board_size = QCA99X0_BOARD_DATA_SZ,
369 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
370 },
371 .sw_decrypt_mcast_mgmt = true,
372 .hw_ops = &qca99x0_ops,
373 .decap_align_bytes = 1,
374 .spectral_bin_discard = 4,
375 .spectral_bin_offset = 0,
376 .vht160_mcs_rx_highest = 0,
377 .vht160_mcs_tx_highest = 0,
378 .n_cipher_suites = 11,
379 .ast_skid_limit = 0x10,
380 .num_wds_entries = 0x20,
381 .target_64bit = false,
382 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
383 .shadow_reg_support = false,
384 .rri_on_ddr = false,
385 .hw_filter_reset_required = true,
386 .fw_diag_ce_download = false,
387 .credit_size_workaround = false,
388 .tx_stats_over_pktlog = false,
389 .dynamic_sar_support = false,
390 },
391 {
392 .id = QCA9984_HW_1_0_DEV_VERSION,
393 .dev_id = QCA9984_1_0_DEVICE_ID,
394 .bus = ATH10K_BUS_PCI,
395 .name = "qca9984/qca9994 hw1.0",
396 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
397 .uart_pin = 7,
398 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
399 .otp_exe_param = 0x00000700,
400 .continuous_frag_desc = true,
401 .cck_rate_map_rev2 = true,
402 .channel_counters_freq_hz = 150000,
403 .max_probe_resp_desc_thres = 24,
404 .tx_chain_mask = 0xf,
405 .rx_chain_mask = 0xf,
406 .max_spatial_stream = 4,
407 .cal_data_len = 12064,
408 .fw = {
409 .dir = QCA9984_HW_1_0_FW_DIR,
410 .board = QCA9984_HW_1_0_BOARD_DATA_FILE,
411 .eboard = QCA9984_HW_1_0_EBOARD_DATA_FILE,
412 .board_size = QCA99X0_BOARD_DATA_SZ,
413 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
414 .ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ,
415 },
416 .sw_decrypt_mcast_mgmt = true,
417 .hw_ops = &qca99x0_ops,
418 .decap_align_bytes = 1,
419 .spectral_bin_discard = 12,
420 .spectral_bin_offset = 8,
421
422 /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz
423 * or 2x2 160Mhz, long-guard-interval.
424 */
425 .vht160_mcs_rx_highest = 1560,
426 .vht160_mcs_tx_highest = 1560,
427 .n_cipher_suites = 11,
428 .ast_skid_limit = 0x10,
429 .num_wds_entries = 0x20,
430 .target_64bit = false,
431 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
432 .shadow_reg_support = false,
433 .rri_on_ddr = false,
434 .hw_filter_reset_required = true,
435 .fw_diag_ce_download = false,
436 .credit_size_workaround = false,
437 .tx_stats_over_pktlog = false,
438 .dynamic_sar_support = false,
439 },
440 {
441 .id = QCA9888_HW_2_0_DEV_VERSION,
442 .dev_id = QCA9888_2_0_DEVICE_ID,
443 .bus = ATH10K_BUS_PCI,
444 .name = "qca9888 hw2.0",
445 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
446 .uart_pin = 7,
447 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
448 .otp_exe_param = 0x00000700,
449 .continuous_frag_desc = true,
450 .channel_counters_freq_hz = 150000,
451 .max_probe_resp_desc_thres = 24,
452 .tx_chain_mask = 3,
453 .rx_chain_mask = 3,
454 .max_spatial_stream = 2,
455 .cal_data_len = 12064,
456 .fw = {
457 .dir = QCA9888_HW_2_0_FW_DIR,
458 .board = QCA9888_HW_2_0_BOARD_DATA_FILE,
459 .board_size = QCA99X0_BOARD_DATA_SZ,
460 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
461 },
462 .sw_decrypt_mcast_mgmt = true,
463 .hw_ops = &qca99x0_ops,
464 .decap_align_bytes = 1,
465 .spectral_bin_discard = 12,
466 .spectral_bin_offset = 8,
467
468 /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or
469 * 1x1 160Mhz, long-guard-interval.
470 */
471 .vht160_mcs_rx_highest = 780,
472 .vht160_mcs_tx_highest = 780,
473 .n_cipher_suites = 11,
474 .ast_skid_limit = 0x10,
475 .num_wds_entries = 0x20,
476 .target_64bit = false,
477 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
478 .shadow_reg_support = false,
479 .rri_on_ddr = false,
480 .hw_filter_reset_required = true,
481 .fw_diag_ce_download = false,
482 .credit_size_workaround = false,
483 .tx_stats_over_pktlog = false,
484 .dynamic_sar_support = false,
485 },
486 {
487 .id = QCA9377_HW_1_0_DEV_VERSION,
488 .dev_id = QCA9377_1_0_DEVICE_ID,
489 .bus = ATH10K_BUS_PCI,
490 .name = "qca9377 hw1.0",
491 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
492 .uart_pin = 6,
493 .otp_exe_param = 0,
494 .channel_counters_freq_hz = 88000,
495 .max_probe_resp_desc_thres = 0,
496 .cal_data_len = 8124,
497 .fw = {
498 .dir = QCA9377_HW_1_0_FW_DIR,
499 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
500 .board_size = QCA9377_BOARD_DATA_SZ,
501 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
502 },
503 .hw_ops = &qca988x_ops,
504 .decap_align_bytes = 4,
505 .spectral_bin_discard = 0,
506 .spectral_bin_offset = 0,
507 .vht160_mcs_rx_highest = 0,
508 .vht160_mcs_tx_highest = 0,
509 .n_cipher_suites = 8,
510 .ast_skid_limit = 0x10,
511 .num_wds_entries = 0x20,
512 .target_64bit = false,
513 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
514 .shadow_reg_support = false,
515 .rri_on_ddr = false,
516 .hw_filter_reset_required = true,
517 .fw_diag_ce_download = false,
518 .credit_size_workaround = false,
519 .tx_stats_over_pktlog = false,
520 .dynamic_sar_support = false,
521 },
522 {
523 .id = QCA9377_HW_1_1_DEV_VERSION,
524 .dev_id = QCA9377_1_0_DEVICE_ID,
525 .bus = ATH10K_BUS_PCI,
526 .name = "qca9377 hw1.1",
527 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
528 .uart_pin = 6,
529 .otp_exe_param = 0,
530 .channel_counters_freq_hz = 88000,
531 .max_probe_resp_desc_thres = 0,
532 .cal_data_len = 8124,
533 .fw = {
534 .dir = QCA9377_HW_1_0_FW_DIR,
535 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
536 .board_size = QCA9377_BOARD_DATA_SZ,
537 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
538 },
539 .hw_ops = &qca6174_ops,
540 .hw_clk = qca6174_clk,
541 .target_cpu_freq = 176000000,
542 .decap_align_bytes = 4,
543 .spectral_bin_discard = 0,
544 .spectral_bin_offset = 0,
545 .vht160_mcs_rx_highest = 0,
546 .vht160_mcs_tx_highest = 0,
547 .n_cipher_suites = 8,
548 .ast_skid_limit = 0x10,
549 .num_wds_entries = 0x20,
550 .target_64bit = false,
551 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
552 .shadow_reg_support = false,
553 .rri_on_ddr = false,
554 .hw_filter_reset_required = true,
555 .fw_diag_ce_download = true,
556 .credit_size_workaround = false,
557 .tx_stats_over_pktlog = false,
558 .dynamic_sar_support = false,
559 },
560 {
561 .id = QCA9377_HW_1_1_DEV_VERSION,
562 .dev_id = QCA9377_1_0_DEVICE_ID,
563 .bus = ATH10K_BUS_SDIO,
564 .name = "qca9377 hw1.1 sdio",
565 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
566 .uart_pin = 19,
567 .otp_exe_param = 0,
568 .channel_counters_freq_hz = 88000,
569 .max_probe_resp_desc_thres = 0,
570 .cal_data_len = 8124,
571 .fw = {
572 .dir = QCA9377_HW_1_0_FW_DIR,
573 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
574 .board_size = QCA9377_BOARD_DATA_SZ,
575 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
576 },
577 .hw_ops = &qca6174_ops,
578 .hw_clk = qca6174_clk,
579 .target_cpu_freq = 176000000,
580 .decap_align_bytes = 4,
581 .n_cipher_suites = 8,
582 .num_peers = TARGET_QCA9377_HL_NUM_PEERS,
583 .ast_skid_limit = 0x10,
584 .num_wds_entries = 0x20,
585 .uart_pin_workaround = true,
586 .credit_size_workaround = true,
587 .dynamic_sar_support = false,
588 },
589 {
590 .id = QCA4019_HW_1_0_DEV_VERSION,
591 .dev_id = 0,
592 .bus = ATH10K_BUS_AHB,
593 .name = "qca4019 hw1.0",
594 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
595 .uart_pin = 7,
596 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
597 .otp_exe_param = 0x0010000,
598 .continuous_frag_desc = true,
599 .cck_rate_map_rev2 = true,
600 .channel_counters_freq_hz = 125000,
601 .max_probe_resp_desc_thres = 24,
602 .tx_chain_mask = 0x3,
603 .rx_chain_mask = 0x3,
604 .max_spatial_stream = 2,
605 .cal_data_len = 12064,
606 .fw = {
607 .dir = QCA4019_HW_1_0_FW_DIR,
608 .board = QCA4019_HW_1_0_BOARD_DATA_FILE,
609 .board_size = QCA4019_BOARD_DATA_SZ,
610 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
611 },
612 .sw_decrypt_mcast_mgmt = true,
613 .hw_ops = &qca99x0_ops,
614 .decap_align_bytes = 1,
615 .spectral_bin_discard = 4,
616 .spectral_bin_offset = 0,
617 .vht160_mcs_rx_highest = 0,
618 .vht160_mcs_tx_highest = 0,
619 .n_cipher_suites = 11,
620 .ast_skid_limit = 0x10,
621 .num_wds_entries = 0x20,
622 .target_64bit = false,
623 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
624 .shadow_reg_support = false,
625 .rri_on_ddr = false,
626 .hw_filter_reset_required = true,
627 .fw_diag_ce_download = false,
628 .credit_size_workaround = false,
629 .tx_stats_over_pktlog = false,
630 .dynamic_sar_support = false,
631 },
632 {
633 .id = WCN3990_HW_1_0_DEV_VERSION,
634 .dev_id = 0,
635 .bus = ATH10K_BUS_SNOC,
636 .name = "wcn3990 hw1.0",
637 .continuous_frag_desc = true,
638 .tx_chain_mask = 0x7,
639 .rx_chain_mask = 0x7,
640 .max_spatial_stream = 4,
641 .fw = {
642 .dir = WCN3990_HW_1_0_FW_DIR,
643 },
644 .sw_decrypt_mcast_mgmt = true,
645 .hw_ops = &wcn3990_ops,
646 .decap_align_bytes = 1,
647 .num_peers = TARGET_HL_TLV_NUM_PEERS,
648 .n_cipher_suites = 11,
649 .ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT,
650 .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES,
651 .target_64bit = true,
652 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
653 .shadow_reg_support = true,
654 .rri_on_ddr = true,
655 .hw_filter_reset_required = false,
656 .fw_diag_ce_download = false,
657 .credit_size_workaround = false,
658 .tx_stats_over_pktlog = false,
659 .dynamic_sar_support = true,
660 },
661 };
662
663 static const char *const ath10k_core_fw_feature_str[] = {
664 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
665 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
666 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
667 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
668 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
669 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
670 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
671 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
672 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
673 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
674 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
675 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
676 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
677 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl",
678 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param",
679 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war",
680 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast",
681 [ATH10K_FW_FEATURE_NO_PS] = "no-ps",
682 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference",
683 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi",
684 [ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel",
685 [ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate",
686 [ATH10K_FW_FEATURE_IRAM_RECOVERY] = "iram-recovery",
687 };
688
ath10k_core_get_fw_feature_str(char * buf,size_t buf_len,enum ath10k_fw_features feat)689 static unsigned int ath10k_core_get_fw_feature_str(char *buf,
690 size_t buf_len,
691 enum ath10k_fw_features feat)
692 {
693 /* make sure that ath10k_core_fw_feature_str[] gets updated */
694 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
695 ATH10K_FW_FEATURE_COUNT);
696
697 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
698 WARN_ON(!ath10k_core_fw_feature_str[feat])) {
699 return scnprintf(buf, buf_len, "bit%d", feat);
700 }
701
702 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
703 }
704
ath10k_core_get_fw_features_str(struct ath10k * ar,char * buf,size_t buf_len)705 void ath10k_core_get_fw_features_str(struct ath10k *ar,
706 char *buf,
707 size_t buf_len)
708 {
709 size_t len = 0;
710 int i;
711
712 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
713 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) {
714 if (len > 0)
715 len += scnprintf(buf + len, buf_len - len, ",");
716
717 len += ath10k_core_get_fw_feature_str(buf + len,
718 buf_len - len,
719 i);
720 }
721 }
722 }
723
ath10k_send_suspend_complete(struct ath10k * ar)724 static void ath10k_send_suspend_complete(struct ath10k *ar)
725 {
726 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
727
728 complete(&ar->target_suspend);
729 }
730
ath10k_init_sdio(struct ath10k * ar,enum ath10k_firmware_mode mode)731 static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode)
732 {
733 bool mtu_workaround = ar->hw_params.credit_size_workaround;
734 int ret;
735 u32 param = 0;
736
737 ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256);
738 if (ret)
739 return ret;
740
741 ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99);
742 if (ret)
743 return ret;
744
745 ret = ath10k_bmi_read32(ar, hi_acs_flags, ¶m);
746 if (ret)
747 return ret;
748
749 param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET;
750
751 if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround)
752 param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
753 else
754 param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
755
756 if (mode == ATH10K_FIRMWARE_MODE_UTF)
757 param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET;
758 else
759 param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET;
760
761 ret = ath10k_bmi_write32(ar, hi_acs_flags, param);
762 if (ret)
763 return ret;
764
765 ret = ath10k_bmi_read32(ar, hi_option_flag2, ¶m);
766 if (ret)
767 return ret;
768
769 param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST;
770
771 ret = ath10k_bmi_write32(ar, hi_option_flag2, param);
772 if (ret)
773 return ret;
774
775 return 0;
776 }
777
ath10k_init_configure_target(struct ath10k * ar)778 static int ath10k_init_configure_target(struct ath10k *ar)
779 {
780 u32 param_host;
781 int ret;
782
783 /* tell target which HTC version it is used*/
784 ret = ath10k_bmi_write32(ar, hi_app_host_interest,
785 HTC_PROTOCOL_VERSION);
786 if (ret) {
787 ath10k_err(ar, "settings HTC version failed\n");
788 return ret;
789 }
790
791 /* set the firmware mode to STA/IBSS/AP */
792 ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host);
793 if (ret) {
794 ath10k_err(ar, "setting firmware mode (1/2) failed\n");
795 return ret;
796 }
797
798 /* TODO following parameters need to be re-visited. */
799 /* num_device */
800 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
801 /* Firmware mode */
802 /* FIXME: Why FW_MODE_AP ??.*/
803 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
804 /* mac_addr_method */
805 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
806 /* firmware_bridge */
807 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
808 /* fwsubmode */
809 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
810
811 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
812 if (ret) {
813 ath10k_err(ar, "setting firmware mode (2/2) failed\n");
814 return ret;
815 }
816
817 /* We do all byte-swapping on the host */
818 ret = ath10k_bmi_write32(ar, hi_be, 0);
819 if (ret) {
820 ath10k_err(ar, "setting host CPU BE mode failed\n");
821 return ret;
822 }
823
824 /* FW descriptor/Data swap flags */
825 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
826
827 if (ret) {
828 ath10k_err(ar, "setting FW data/desc swap flags failed\n");
829 return ret;
830 }
831
832 /* Some devices have a special sanity check that verifies the PCI
833 * Device ID is written to this host interest var. It is known to be
834 * required to boot QCA6164.
835 */
836 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
837 ar->dev_id);
838 if (ret) {
839 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
840 return ret;
841 }
842
843 return 0;
844 }
845
ath10k_fetch_fw_file(struct ath10k * ar,const char * dir,const char * file)846 static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
847 const char *dir,
848 const char *file)
849 {
850 char filename[100];
851 const struct firmware *fw;
852 int ret;
853
854 if (file == NULL)
855 return ERR_PTR(-ENOENT);
856
857 if (dir == NULL)
858 dir = ".";
859
860 snprintf(filename, sizeof(filename), "%s/%s", dir, file);
861 ret = firmware_request_nowarn(&fw, filename, ar->dev);
862 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n",
863 filename, ret);
864
865 if (ret)
866 return ERR_PTR(ret);
867
868 return fw;
869 }
870
ath10k_push_board_ext_data(struct ath10k * ar,const void * data,size_t data_len)871 static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
872 size_t data_len)
873 {
874 u32 board_data_size = ar->hw_params.fw.board_size;
875 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
876 u32 board_ext_data_addr;
877 int ret;
878
879 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
880 if (ret) {
881 ath10k_err(ar, "could not read board ext data addr (%d)\n",
882 ret);
883 return ret;
884 }
885
886 ath10k_dbg(ar, ATH10K_DBG_BOOT,
887 "boot push board extended data addr 0x%x\n",
888 board_ext_data_addr);
889
890 if (board_ext_data_addr == 0)
891 return 0;
892
893 if (data_len != (board_data_size + board_ext_data_size)) {
894 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
895 data_len, board_data_size, board_ext_data_size);
896 return -EINVAL;
897 }
898
899 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
900 data + board_data_size,
901 board_ext_data_size);
902 if (ret) {
903 ath10k_err(ar, "could not write board ext data (%d)\n", ret);
904 return ret;
905 }
906
907 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
908 (board_ext_data_size << 16) | 1);
909 if (ret) {
910 ath10k_err(ar, "could not write board ext data bit (%d)\n",
911 ret);
912 return ret;
913 }
914
915 return 0;
916 }
917
ath10k_core_get_board_id_from_otp(struct ath10k * ar)918 static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
919 {
920 u32 result, address;
921 u8 board_id, chip_id;
922 bool ext_bid_support;
923 int ret, bmi_board_id_param;
924
925 address = ar->hw_params.patch_load_addr;
926
927 if (!ar->normal_mode_fw.fw_file.otp_data ||
928 !ar->normal_mode_fw.fw_file.otp_len) {
929 ath10k_warn(ar,
930 "failed to retrieve board id because of invalid otp\n");
931 return -ENODATA;
932 }
933
934 if (ar->id.bmi_ids_valid) {
935 ath10k_dbg(ar, ATH10K_DBG_BOOT,
936 "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n",
937 ar->id.bmi_board_id, ar->id.bmi_chip_id);
938 goto skip_otp_download;
939 }
940
941 ath10k_dbg(ar, ATH10K_DBG_BOOT,
942 "boot upload otp to 0x%x len %zd for board id\n",
943 address, ar->normal_mode_fw.fw_file.otp_len);
944
945 ret = ath10k_bmi_fast_download(ar, address,
946 ar->normal_mode_fw.fw_file.otp_data,
947 ar->normal_mode_fw.fw_file.otp_len);
948 if (ret) {
949 ath10k_err(ar, "could not write otp for board id check: %d\n",
950 ret);
951 return ret;
952 }
953
954 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
955 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)
956 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID;
957 else
958 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID;
959
960 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result);
961 if (ret) {
962 ath10k_err(ar, "could not execute otp for board id check: %d\n",
963 ret);
964 return ret;
965 }
966
967 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
968 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
969 ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT);
970
971 ath10k_dbg(ar, ATH10K_DBG_BOOT,
972 "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n",
973 result, board_id, chip_id, ext_bid_support);
974
975 ar->id.ext_bid_supported = ext_bid_support;
976
977 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 ||
978 (board_id == 0)) {
979 ath10k_dbg(ar, ATH10K_DBG_BOOT,
980 "board id does not exist in otp, ignore it\n");
981 return -EOPNOTSUPP;
982 }
983
984 ar->id.bmi_ids_valid = true;
985 ar->id.bmi_board_id = board_id;
986 ar->id.bmi_chip_id = chip_id;
987
988 skip_otp_download:
989
990 return 0;
991 }
992
ath10k_core_check_bdfext(const struct dmi_header * hdr,void * data)993 static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data)
994 {
995 struct ath10k *ar = data;
996 const char *bdf_ext;
997 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC;
998 u8 bdf_enabled;
999 int i;
1000
1001 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE)
1002 return;
1003
1004 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) {
1005 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1006 "wrong smbios bdf ext type length (%d).\n",
1007 hdr->length);
1008 return;
1009 }
1010
1011 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET);
1012 if (!bdf_enabled) {
1013 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n");
1014 return;
1015 }
1016
1017 /* Only one string exists (per spec) */
1018 bdf_ext = (char *)hdr + hdr->length;
1019
1020 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) {
1021 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1022 "bdf variant magic does not match.\n");
1023 return;
1024 }
1025
1026 for (i = 0; i < strlen(bdf_ext); i++) {
1027 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) {
1028 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1029 "bdf variant name contains non ascii chars.\n");
1030 return;
1031 }
1032 }
1033
1034 /* Copy extension name without magic suffix */
1035 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic),
1036 sizeof(ar->id.bdf_ext)) < 0) {
1037 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1038 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1039 bdf_ext);
1040 return;
1041 }
1042
1043 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1044 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
1045 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext);
1046 }
1047
ath10k_core_check_smbios(struct ath10k * ar)1048 static int ath10k_core_check_smbios(struct ath10k *ar)
1049 {
1050 ar->id.bdf_ext[0] = '\0';
1051 dmi_walk(ath10k_core_check_bdfext, ar);
1052
1053 if (ar->id.bdf_ext[0] == '\0')
1054 return -ENODATA;
1055
1056 return 0;
1057 }
1058
ath10k_core_check_dt(struct ath10k * ar)1059 int ath10k_core_check_dt(struct ath10k *ar)
1060 {
1061 struct device_node *node;
1062 const char *variant = NULL;
1063
1064 node = ar->dev->of_node;
1065 if (!node)
1066 return -ENOENT;
1067
1068 of_property_read_string(node, "qcom,ath10k-calibration-variant",
1069 &variant);
1070 if (!variant)
1071 return -ENODATA;
1072
1073 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0)
1074 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1075 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1076 variant);
1077
1078 return 0;
1079 }
1080 EXPORT_SYMBOL(ath10k_core_check_dt);
1081
ath10k_download_fw(struct ath10k * ar)1082 static int ath10k_download_fw(struct ath10k *ar)
1083 {
1084 u32 address, data_len;
1085 const void *data;
1086 int ret;
1087 struct pm_qos_request latency_qos;
1088
1089 address = ar->hw_params.patch_load_addr;
1090
1091 data = ar->running_fw->fw_file.firmware_data;
1092 data_len = ar->running_fw->fw_file.firmware_len;
1093
1094 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file);
1095 if (ret) {
1096 ath10k_err(ar, "failed to configure fw code swap: %d\n",
1097 ret);
1098 return ret;
1099 }
1100
1101 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1102 "boot uploading firmware image %pK len %d\n",
1103 data, data_len);
1104
1105 /* Check if device supports to download firmware via
1106 * diag copy engine. Downloading firmware via diag CE
1107 * greatly reduces the time to download firmware.
1108 */
1109 if (ar->hw_params.fw_diag_ce_download) {
1110 ret = ath10k_hw_diag_fast_download(ar, address,
1111 data, data_len);
1112 if (ret == 0)
1113 /* firmware upload via diag ce was successful */
1114 return 0;
1115
1116 ath10k_warn(ar,
1117 "failed to upload firmware via diag ce, trying BMI: %d",
1118 ret);
1119 }
1120
1121 memset(&latency_qos, 0, sizeof(latency_qos));
1122 cpu_latency_qos_add_request(&latency_qos, 0);
1123
1124 ret = ath10k_bmi_fast_download(ar, address, data, data_len);
1125
1126 cpu_latency_qos_remove_request(&latency_qos);
1127
1128 return ret;
1129 }
1130
ath10k_core_free_board_files(struct ath10k * ar)1131 void ath10k_core_free_board_files(struct ath10k *ar)
1132 {
1133 if (!IS_ERR(ar->normal_mode_fw.board))
1134 release_firmware(ar->normal_mode_fw.board);
1135
1136 if (!IS_ERR(ar->normal_mode_fw.ext_board))
1137 release_firmware(ar->normal_mode_fw.ext_board);
1138
1139 ar->normal_mode_fw.board = NULL;
1140 ar->normal_mode_fw.board_data = NULL;
1141 ar->normal_mode_fw.board_len = 0;
1142 ar->normal_mode_fw.ext_board = NULL;
1143 ar->normal_mode_fw.ext_board_data = NULL;
1144 ar->normal_mode_fw.ext_board_len = 0;
1145 }
1146 EXPORT_SYMBOL(ath10k_core_free_board_files);
1147
ath10k_core_free_firmware_files(struct ath10k * ar)1148 static void ath10k_core_free_firmware_files(struct ath10k *ar)
1149 {
1150 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware))
1151 release_firmware(ar->normal_mode_fw.fw_file.firmware);
1152
1153 if (!IS_ERR(ar->cal_file))
1154 release_firmware(ar->cal_file);
1155
1156 if (!IS_ERR(ar->pre_cal_file))
1157 release_firmware(ar->pre_cal_file);
1158
1159 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file);
1160
1161 ar->normal_mode_fw.fw_file.otp_data = NULL;
1162 ar->normal_mode_fw.fw_file.otp_len = 0;
1163
1164 ar->normal_mode_fw.fw_file.firmware = NULL;
1165 ar->normal_mode_fw.fw_file.firmware_data = NULL;
1166 ar->normal_mode_fw.fw_file.firmware_len = 0;
1167
1168 ar->cal_file = NULL;
1169 ar->pre_cal_file = NULL;
1170 }
1171
ath10k_fetch_cal_file(struct ath10k * ar)1172 static int ath10k_fetch_cal_file(struct ath10k *ar)
1173 {
1174 char filename[100];
1175
1176 /* pre-cal-<bus>-<id>.bin */
1177 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin",
1178 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1179
1180 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
1181 if (!IS_ERR(ar->pre_cal_file))
1182 goto success;
1183
1184 /* cal-<bus>-<id>.bin */
1185 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
1186 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1187
1188 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
1189 if (IS_ERR(ar->cal_file))
1190 /* calibration file is optional, don't print any warnings */
1191 return PTR_ERR(ar->cal_file);
1192 success:
1193 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
1194 ATH10K_FW_DIR, filename);
1195
1196 return 0;
1197 }
1198
ath10k_core_fetch_board_data_api_1(struct ath10k * ar,int bd_ie_type)1199 static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type)
1200 {
1201 const struct firmware *fw;
1202
1203 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1204 if (!ar->hw_params.fw.board) {
1205 ath10k_err(ar, "failed to find board file fw entry\n");
1206 return -EINVAL;
1207 }
1208
1209 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
1210 ar->hw_params.fw.dir,
1211 ar->hw_params.fw.board);
1212 if (IS_ERR(ar->normal_mode_fw.board))
1213 return PTR_ERR(ar->normal_mode_fw.board);
1214
1215 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data;
1216 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size;
1217 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1218 if (!ar->hw_params.fw.eboard) {
1219 ath10k_err(ar, "failed to find eboard file fw entry\n");
1220 return -EINVAL;
1221 }
1222
1223 fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
1224 ar->hw_params.fw.eboard);
1225 ar->normal_mode_fw.ext_board = fw;
1226 if (IS_ERR(ar->normal_mode_fw.ext_board))
1227 return PTR_ERR(ar->normal_mode_fw.ext_board);
1228
1229 ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data;
1230 ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size;
1231 }
1232
1233 return 0;
1234 }
1235
ath10k_core_parse_bd_ie_board(struct ath10k * ar,const void * buf,size_t buf_len,const char * boardname,int bd_ie_type)1236 static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
1237 const void *buf, size_t buf_len,
1238 const char *boardname,
1239 int bd_ie_type)
1240 {
1241 const struct ath10k_fw_ie *hdr;
1242 bool name_match_found;
1243 int ret, board_ie_id;
1244 size_t board_ie_len;
1245 const void *board_ie_data;
1246
1247 name_match_found = false;
1248
1249 /* go through ATH10K_BD_IE_BOARD_ elements */
1250 while (buf_len > sizeof(struct ath10k_fw_ie)) {
1251 hdr = buf;
1252 board_ie_id = le32_to_cpu(hdr->id);
1253 board_ie_len = le32_to_cpu(hdr->len);
1254 board_ie_data = hdr->data;
1255
1256 buf_len -= sizeof(*hdr);
1257 buf += sizeof(*hdr);
1258
1259 if (buf_len < ALIGN(board_ie_len, 4)) {
1260 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
1261 buf_len, ALIGN(board_ie_len, 4));
1262 ret = -EINVAL;
1263 goto out;
1264 }
1265
1266 switch (board_ie_id) {
1267 case ATH10K_BD_IE_BOARD_NAME:
1268 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
1269 board_ie_data, board_ie_len);
1270
1271 if (board_ie_len != strlen(boardname))
1272 break;
1273
1274 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1275 if (ret)
1276 break;
1277
1278 name_match_found = true;
1279 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1280 "boot found match for name '%s'",
1281 boardname);
1282 break;
1283 case ATH10K_BD_IE_BOARD_DATA:
1284 if (!name_match_found)
1285 /* no match found */
1286 break;
1287
1288 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1289 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1290 "boot found board data for '%s'",
1291 boardname);
1292
1293 ar->normal_mode_fw.board_data = board_ie_data;
1294 ar->normal_mode_fw.board_len = board_ie_len;
1295 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1296 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1297 "boot found eboard data for '%s'",
1298 boardname);
1299
1300 ar->normal_mode_fw.ext_board_data = board_ie_data;
1301 ar->normal_mode_fw.ext_board_len = board_ie_len;
1302 }
1303
1304 ret = 0;
1305 goto out;
1306 default:
1307 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
1308 board_ie_id);
1309 break;
1310 }
1311
1312 /* jump over the padding */
1313 board_ie_len = ALIGN(board_ie_len, 4);
1314
1315 buf_len -= board_ie_len;
1316 buf += board_ie_len;
1317 }
1318
1319 /* no match found */
1320 ret = -ENOENT;
1321
1322 out:
1323 return ret;
1324 }
1325
ath10k_core_search_bd(struct ath10k * ar,const char * boardname,const u8 * data,size_t len)1326 static int ath10k_core_search_bd(struct ath10k *ar,
1327 const char *boardname,
1328 const u8 *data,
1329 size_t len)
1330 {
1331 size_t ie_len;
1332 struct ath10k_fw_ie *hdr;
1333 int ret = -ENOENT, ie_id;
1334
1335 while (len > sizeof(struct ath10k_fw_ie)) {
1336 hdr = (struct ath10k_fw_ie *)data;
1337 ie_id = le32_to_cpu(hdr->id);
1338 ie_len = le32_to_cpu(hdr->len);
1339
1340 len -= sizeof(*hdr);
1341 data = hdr->data;
1342
1343 if (len < ALIGN(ie_len, 4)) {
1344 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1345 ie_id, ie_len, len);
1346 return -EINVAL;
1347 }
1348
1349 switch (ie_id) {
1350 case ATH10K_BD_IE_BOARD:
1351 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
1352 boardname,
1353 ATH10K_BD_IE_BOARD);
1354 if (ret == -ENOENT)
1355 /* no match found, continue */
1356 break;
1357
1358 /* either found or error, so stop searching */
1359 goto out;
1360 case ATH10K_BD_IE_BOARD_EXT:
1361 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
1362 boardname,
1363 ATH10K_BD_IE_BOARD_EXT);
1364 if (ret == -ENOENT)
1365 /* no match found, continue */
1366 break;
1367
1368 /* either found or error, so stop searching */
1369 goto out;
1370 }
1371
1372 /* jump over the padding */
1373 ie_len = ALIGN(ie_len, 4);
1374
1375 len -= ie_len;
1376 data += ie_len;
1377 }
1378
1379 out:
1380 /* return result of parse_bd_ie_board() or -ENOENT */
1381 return ret;
1382 }
1383
ath10k_core_fetch_board_data_api_n(struct ath10k * ar,const char * boardname,const char * fallback_boardname1,const char * fallback_boardname2,const char * filename)1384 static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
1385 const char *boardname,
1386 const char *fallback_boardname1,
1387 const char *fallback_boardname2,
1388 const char *filename)
1389 {
1390 size_t len, magic_len;
1391 const u8 *data;
1392 int ret;
1393
1394 /* Skip if already fetched during board data download */
1395 if (!ar->normal_mode_fw.board)
1396 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
1397 ar->hw_params.fw.dir,
1398 filename);
1399 if (IS_ERR(ar->normal_mode_fw.board))
1400 return PTR_ERR(ar->normal_mode_fw.board);
1401
1402 data = ar->normal_mode_fw.board->data;
1403 len = ar->normal_mode_fw.board->size;
1404
1405 /* magic has extra null byte padded */
1406 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
1407 if (len < magic_len) {
1408 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
1409 ar->hw_params.fw.dir, filename, len);
1410 ret = -EINVAL;
1411 goto err;
1412 }
1413
1414 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
1415 ath10k_err(ar, "found invalid board magic\n");
1416 ret = -EINVAL;
1417 goto err;
1418 }
1419
1420 /* magic is padded to 4 bytes */
1421 magic_len = ALIGN(magic_len, 4);
1422 if (len < magic_len) {
1423 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
1424 ar->hw_params.fw.dir, filename, len);
1425 ret = -EINVAL;
1426 goto err;
1427 }
1428
1429 data += magic_len;
1430 len -= magic_len;
1431
1432 /* attempt to find boardname in the IE list */
1433 ret = ath10k_core_search_bd(ar, boardname, data, len);
1434
1435 /* if we didn't find it and have a fallback name, try that */
1436 if (ret == -ENOENT && fallback_boardname1)
1437 ret = ath10k_core_search_bd(ar, fallback_boardname1, data, len);
1438
1439 if (ret == -ENOENT && fallback_boardname2)
1440 ret = ath10k_core_search_bd(ar, fallback_boardname2, data, len);
1441
1442 if (ret == -ENOENT) {
1443 ath10k_err(ar,
1444 "failed to fetch board data for %s from %s/%s\n",
1445 boardname, ar->hw_params.fw.dir, filename);
1446 ret = -ENODATA;
1447 }
1448
1449 if (ret)
1450 goto err;
1451
1452 return 0;
1453
1454 err:
1455 ath10k_core_free_board_files(ar);
1456 return ret;
1457 }
1458
ath10k_core_create_board_name(struct ath10k * ar,char * name,size_t name_len,bool with_variant,bool with_chip_id)1459 static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
1460 size_t name_len, bool with_variant,
1461 bool with_chip_id)
1462 {
1463 /* strlen(',variant=') + strlen(ar->id.bdf_ext) */
1464 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 };
1465
1466 if (with_variant && ar->id.bdf_ext[0] != '\0')
1467 scnprintf(variant, sizeof(variant), ",variant=%s",
1468 ar->id.bdf_ext);
1469
1470 if (ar->id.bmi_ids_valid) {
1471 scnprintf(name, name_len,
1472 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s",
1473 ath10k_bus_str(ar->hif.bus),
1474 ar->id.bmi_chip_id,
1475 ar->id.bmi_board_id, variant);
1476 goto out;
1477 }
1478
1479 if (ar->id.qmi_ids_valid) {
1480 if (with_chip_id)
1481 scnprintf(name, name_len,
1482 "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s",
1483 ath10k_bus_str(ar->hif.bus),
1484 ar->id.qmi_board_id, ar->id.qmi_chip_id,
1485 variant);
1486 else
1487 scnprintf(name, name_len,
1488 "bus=%s,qmi-board-id=%x",
1489 ath10k_bus_str(ar->hif.bus),
1490 ar->id.qmi_board_id);
1491 goto out;
1492 }
1493
1494 scnprintf(name, name_len,
1495 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s",
1496 ath10k_bus_str(ar->hif.bus),
1497 ar->id.vendor, ar->id.device,
1498 ar->id.subsystem_vendor, ar->id.subsystem_device, variant);
1499 out:
1500 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
1501
1502 return 0;
1503 }
1504
ath10k_core_create_eboard_name(struct ath10k * ar,char * name,size_t name_len)1505 static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name,
1506 size_t name_len)
1507 {
1508 if (ar->id.bmi_ids_valid) {
1509 scnprintf(name, name_len,
1510 "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d",
1511 ath10k_bus_str(ar->hif.bus),
1512 ar->id.bmi_chip_id,
1513 ar->id.bmi_eboard_id);
1514
1515 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name);
1516 return 0;
1517 }
1518 /* Fallback if returned board id is zero */
1519 return -1;
1520 }
1521
ath10k_core_fetch_board_file(struct ath10k * ar,int bd_ie_type)1522 int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type)
1523 {
1524 char boardname[100], fallback_boardname1[100], fallback_boardname2[100];
1525 int ret;
1526
1527 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1528 /* With variant and chip id */
1529 ret = ath10k_core_create_board_name(ar, boardname,
1530 sizeof(boardname), true,
1531 true);
1532 if (ret) {
1533 ath10k_err(ar, "failed to create board name: %d", ret);
1534 return ret;
1535 }
1536
1537 /* Without variant and only chip-id */
1538 ret = ath10k_core_create_board_name(ar, fallback_boardname1,
1539 sizeof(boardname), false,
1540 true);
1541 if (ret) {
1542 ath10k_err(ar, "failed to create 1st fallback board name: %d",
1543 ret);
1544 return ret;
1545 }
1546
1547 /* Without variant and without chip-id */
1548 ret = ath10k_core_create_board_name(ar, fallback_boardname2,
1549 sizeof(boardname), false,
1550 false);
1551 if (ret) {
1552 ath10k_err(ar, "failed to create 2nd fallback board name: %d",
1553 ret);
1554 return ret;
1555 }
1556 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1557 ret = ath10k_core_create_eboard_name(ar, boardname,
1558 sizeof(boardname));
1559 if (ret) {
1560 ath10k_err(ar, "fallback to eboard.bin since board id 0");
1561 goto fallback;
1562 }
1563 }
1564
1565 ar->bd_api = 2;
1566 ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
1567 fallback_boardname1,
1568 fallback_boardname2,
1569 ATH10K_BOARD_API2_FILE);
1570 if (!ret)
1571 goto success;
1572
1573 fallback:
1574 ar->bd_api = 1;
1575 ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type);
1576 if (ret) {
1577 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n",
1578 ar->hw_params.fw.dir);
1579 return ret;
1580 }
1581
1582 success:
1583 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
1584 return 0;
1585 }
1586 EXPORT_SYMBOL(ath10k_core_fetch_board_file);
1587
ath10k_core_get_ext_board_id_from_otp(struct ath10k * ar)1588 static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar)
1589 {
1590 u32 result, address;
1591 u8 ext_board_id;
1592 int ret;
1593
1594 address = ar->hw_params.patch_load_addr;
1595
1596 if (!ar->normal_mode_fw.fw_file.otp_data ||
1597 !ar->normal_mode_fw.fw_file.otp_len) {
1598 ath10k_warn(ar,
1599 "failed to retrieve extended board id due to otp binary missing\n");
1600 return -ENODATA;
1601 }
1602
1603 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1604 "boot upload otp to 0x%x len %zd for ext board id\n",
1605 address, ar->normal_mode_fw.fw_file.otp_len);
1606
1607 ret = ath10k_bmi_fast_download(ar, address,
1608 ar->normal_mode_fw.fw_file.otp_data,
1609 ar->normal_mode_fw.fw_file.otp_len);
1610 if (ret) {
1611 ath10k_err(ar, "could not write otp for ext board id check: %d\n",
1612 ret);
1613 return ret;
1614 }
1615
1616 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result);
1617 if (ret) {
1618 ath10k_err(ar, "could not execute otp for ext board id check: %d\n",
1619 ret);
1620 return ret;
1621 }
1622
1623 if (!result) {
1624 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1625 "ext board id does not exist in otp, ignore it\n");
1626 return -EOPNOTSUPP;
1627 }
1628
1629 ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK;
1630
1631 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1632 "boot get otp ext board id result 0x%08x ext_board_id %d\n",
1633 result, ext_board_id);
1634
1635 ar->id.bmi_eboard_id = ext_board_id;
1636
1637 return 0;
1638 }
1639
ath10k_download_board_data(struct ath10k * ar,const void * data,size_t data_len)1640 static int ath10k_download_board_data(struct ath10k *ar, const void *data,
1641 size_t data_len)
1642 {
1643 u32 board_data_size = ar->hw_params.fw.board_size;
1644 u32 eboard_data_size = ar->hw_params.fw.ext_board_size;
1645 u32 board_address;
1646 u32 ext_board_address;
1647 int ret;
1648
1649 ret = ath10k_push_board_ext_data(ar, data, data_len);
1650 if (ret) {
1651 ath10k_err(ar, "could not push board ext data (%d)\n", ret);
1652 goto exit;
1653 }
1654
1655 ret = ath10k_bmi_read32(ar, hi_board_data, &board_address);
1656 if (ret) {
1657 ath10k_err(ar, "could not read board data addr (%d)\n", ret);
1658 goto exit;
1659 }
1660
1661 ret = ath10k_bmi_write_memory(ar, board_address, data,
1662 min_t(u32, board_data_size,
1663 data_len));
1664 if (ret) {
1665 ath10k_err(ar, "could not write board data (%d)\n", ret);
1666 goto exit;
1667 }
1668
1669 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
1670 if (ret) {
1671 ath10k_err(ar, "could not write board data bit (%d)\n", ret);
1672 goto exit;
1673 }
1674
1675 if (!ar->id.ext_bid_supported)
1676 goto exit;
1677
1678 /* Extended board data download */
1679 ret = ath10k_core_get_ext_board_id_from_otp(ar);
1680 if (ret == -EOPNOTSUPP) {
1681 /* Not fetching ext_board_data if ext board id is 0 */
1682 ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n");
1683 return 0;
1684 } else if (ret) {
1685 ath10k_err(ar, "failed to get extended board id: %d\n", ret);
1686 goto exit;
1687 }
1688
1689 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT);
1690 if (ret)
1691 goto exit;
1692
1693 if (ar->normal_mode_fw.ext_board_data) {
1694 ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET;
1695 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1696 "boot writing ext board data to addr 0x%x",
1697 ext_board_address);
1698 ret = ath10k_bmi_write_memory(ar, ext_board_address,
1699 ar->normal_mode_fw.ext_board_data,
1700 min_t(u32, eboard_data_size, data_len));
1701 if (ret)
1702 ath10k_err(ar, "failed to write ext board data: %d\n", ret);
1703 }
1704
1705 exit:
1706 return ret;
1707 }
1708
ath10k_download_and_run_otp(struct ath10k * ar)1709 static int ath10k_download_and_run_otp(struct ath10k *ar)
1710 {
1711 u32 result, address = ar->hw_params.patch_load_addr;
1712 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
1713 int ret;
1714
1715 ret = ath10k_download_board_data(ar,
1716 ar->running_fw->board_data,
1717 ar->running_fw->board_len);
1718 if (ret) {
1719 ath10k_err(ar, "failed to download board data: %d\n", ret);
1720 return ret;
1721 }
1722
1723 /* OTP is optional */
1724
1725 if (!ar->running_fw->fw_file.otp_data ||
1726 !ar->running_fw->fw_file.otp_len) {
1727 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n",
1728 ar->running_fw->fw_file.otp_data,
1729 ar->running_fw->fw_file.otp_len);
1730 return 0;
1731 }
1732
1733 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
1734 address, ar->running_fw->fw_file.otp_len);
1735
1736 ret = ath10k_bmi_fast_download(ar, address,
1737 ar->running_fw->fw_file.otp_data,
1738 ar->running_fw->fw_file.otp_len);
1739 if (ret) {
1740 ath10k_err(ar, "could not write otp (%d)\n", ret);
1741 return ret;
1742 }
1743
1744 /* As of now pre-cal is valid for 10_4 variants */
1745 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
1746 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)
1747 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL;
1748
1749 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
1750 if (ret) {
1751 ath10k_err(ar, "could not execute otp (%d)\n", ret);
1752 return ret;
1753 }
1754
1755 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
1756
1757 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
1758 ar->running_fw->fw_file.fw_features)) &&
1759 result != 0) {
1760 ath10k_err(ar, "otp calibration failed: %d", result);
1761 return -EINVAL;
1762 }
1763
1764 return 0;
1765 }
1766
ath10k_download_cal_file(struct ath10k * ar,const struct firmware * file)1767 static int ath10k_download_cal_file(struct ath10k *ar,
1768 const struct firmware *file)
1769 {
1770 int ret;
1771
1772 if (!file)
1773 return -ENOENT;
1774
1775 if (IS_ERR(file))
1776 return PTR_ERR(file);
1777
1778 ret = ath10k_download_board_data(ar, file->data, file->size);
1779 if (ret) {
1780 ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
1781 return ret;
1782 }
1783
1784 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
1785
1786 return 0;
1787 }
1788
ath10k_download_cal_dt(struct ath10k * ar,const char * dt_name)1789 static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name)
1790 {
1791 struct device_node *node;
1792 int data_len;
1793 void *data;
1794 int ret;
1795
1796 node = ar->dev->of_node;
1797 if (!node)
1798 /* Device Tree is optional, don't print any warnings if
1799 * there's no node for ath10k.
1800 */
1801 return -ENOENT;
1802
1803 if (!of_get_property(node, dt_name, &data_len)) {
1804 /* The calibration data node is optional */
1805 return -ENOENT;
1806 }
1807
1808 if (data_len != ar->hw_params.cal_data_len) {
1809 ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
1810 data_len);
1811 ret = -EMSGSIZE;
1812 goto out;
1813 }
1814
1815 data = kmalloc(data_len, GFP_KERNEL);
1816 if (!data) {
1817 ret = -ENOMEM;
1818 goto out;
1819 }
1820
1821 ret = of_property_read_u8_array(node, dt_name, data, data_len);
1822 if (ret) {
1823 ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
1824 ret);
1825 goto out_free;
1826 }
1827
1828 ret = ath10k_download_board_data(ar, data, data_len);
1829 if (ret) {
1830 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
1831 ret);
1832 goto out_free;
1833 }
1834
1835 ret = 0;
1836
1837 out_free:
1838 kfree(data);
1839
1840 out:
1841 return ret;
1842 }
1843
ath10k_download_cal_eeprom(struct ath10k * ar)1844 static int ath10k_download_cal_eeprom(struct ath10k *ar)
1845 {
1846 size_t data_len;
1847 void *data = NULL;
1848 int ret;
1849
1850 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len);
1851 if (ret) {
1852 if (ret != -EOPNOTSUPP)
1853 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n",
1854 ret);
1855 goto out_free;
1856 }
1857
1858 ret = ath10k_download_board_data(ar, data, data_len);
1859 if (ret) {
1860 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n",
1861 ret);
1862 goto out_free;
1863 }
1864
1865 ret = 0;
1866
1867 out_free:
1868 kfree(data);
1869
1870 return ret;
1871 }
1872
ath10k_core_fetch_firmware_api_n(struct ath10k * ar,const char * name,struct ath10k_fw_file * fw_file)1873 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
1874 struct ath10k_fw_file *fw_file)
1875 {
1876 size_t magic_len, len, ie_len;
1877 int ie_id, i, index, bit, ret;
1878 struct ath10k_fw_ie *hdr;
1879 const u8 *data;
1880 __le32 *timestamp, *version;
1881
1882 /* first fetch the firmware file (firmware-*.bin) */
1883 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
1884 name);
1885 if (IS_ERR(fw_file->firmware))
1886 return PTR_ERR(fw_file->firmware);
1887
1888 data = fw_file->firmware->data;
1889 len = fw_file->firmware->size;
1890
1891 /* magic also includes the null byte, check that as well */
1892 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
1893
1894 if (len < magic_len) {
1895 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
1896 ar->hw_params.fw.dir, name, len);
1897 ret = -EINVAL;
1898 goto err;
1899 }
1900
1901 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
1902 ath10k_err(ar, "invalid firmware magic\n");
1903 ret = -EINVAL;
1904 goto err;
1905 }
1906
1907 /* jump over the padding */
1908 magic_len = ALIGN(magic_len, 4);
1909
1910 len -= magic_len;
1911 data += magic_len;
1912
1913 /* loop elements */
1914 while (len > sizeof(struct ath10k_fw_ie)) {
1915 hdr = (struct ath10k_fw_ie *)data;
1916
1917 ie_id = le32_to_cpu(hdr->id);
1918 ie_len = le32_to_cpu(hdr->len);
1919
1920 len -= sizeof(*hdr);
1921 data += sizeof(*hdr);
1922
1923 if (len < ie_len) {
1924 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
1925 ie_id, len, ie_len);
1926 ret = -EINVAL;
1927 goto err;
1928 }
1929
1930 switch (ie_id) {
1931 case ATH10K_FW_IE_FW_VERSION:
1932 if (ie_len > sizeof(fw_file->fw_version) - 1)
1933 break;
1934
1935 memcpy(fw_file->fw_version, data, ie_len);
1936 fw_file->fw_version[ie_len] = '\0';
1937
1938 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1939 "found fw version %s\n",
1940 fw_file->fw_version);
1941 break;
1942 case ATH10K_FW_IE_TIMESTAMP:
1943 if (ie_len != sizeof(u32))
1944 break;
1945
1946 timestamp = (__le32 *)data;
1947
1948 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
1949 le32_to_cpup(timestamp));
1950 break;
1951 case ATH10K_FW_IE_FEATURES:
1952 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1953 "found firmware features ie (%zd B)\n",
1954 ie_len);
1955
1956 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
1957 index = i / 8;
1958 bit = i % 8;
1959
1960 if (index == ie_len)
1961 break;
1962
1963 if (data[index] & (1 << bit)) {
1964 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1965 "Enabling feature bit: %i\n",
1966 i);
1967 __set_bit(i, fw_file->fw_features);
1968 }
1969 }
1970
1971 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
1972 fw_file->fw_features,
1973 sizeof(fw_file->fw_features));
1974 break;
1975 case ATH10K_FW_IE_FW_IMAGE:
1976 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1977 "found fw image ie (%zd B)\n",
1978 ie_len);
1979
1980 fw_file->firmware_data = data;
1981 fw_file->firmware_len = ie_len;
1982
1983 break;
1984 case ATH10K_FW_IE_OTP_IMAGE:
1985 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1986 "found otp image ie (%zd B)\n",
1987 ie_len);
1988
1989 fw_file->otp_data = data;
1990 fw_file->otp_len = ie_len;
1991
1992 break;
1993 case ATH10K_FW_IE_WMI_OP_VERSION:
1994 if (ie_len != sizeof(u32))
1995 break;
1996
1997 version = (__le32 *)data;
1998
1999 fw_file->wmi_op_version = le32_to_cpup(version);
2000
2001 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
2002 fw_file->wmi_op_version);
2003 break;
2004 case ATH10K_FW_IE_HTT_OP_VERSION:
2005 if (ie_len != sizeof(u32))
2006 break;
2007
2008 version = (__le32 *)data;
2009
2010 fw_file->htt_op_version = le32_to_cpup(version);
2011
2012 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
2013 fw_file->htt_op_version);
2014 break;
2015 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
2016 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2017 "found fw code swap image ie (%zd B)\n",
2018 ie_len);
2019 fw_file->codeswap_data = data;
2020 fw_file->codeswap_len = ie_len;
2021 break;
2022 default:
2023 ath10k_warn(ar, "Unknown FW IE: %u\n",
2024 le32_to_cpu(hdr->id));
2025 break;
2026 }
2027
2028 /* jump over the padding */
2029 ie_len = ALIGN(ie_len, 4);
2030
2031 len -= ie_len;
2032 data += ie_len;
2033 }
2034
2035 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) &&
2036 (!fw_file->firmware_data || !fw_file->firmware_len)) {
2037 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
2038 ar->hw_params.fw.dir, name);
2039 ret = -ENOMEDIUM;
2040 goto err;
2041 }
2042
2043 return 0;
2044
2045 err:
2046 ath10k_core_free_firmware_files(ar);
2047 return ret;
2048 }
2049
ath10k_core_get_fw_name(struct ath10k * ar,char * fw_name,size_t fw_name_len,int fw_api)2050 static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name,
2051 size_t fw_name_len, int fw_api)
2052 {
2053 switch (ar->hif.bus) {
2054 case ATH10K_BUS_SDIO:
2055 case ATH10K_BUS_USB:
2056 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin",
2057 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus),
2058 fw_api);
2059 break;
2060 case ATH10K_BUS_PCI:
2061 case ATH10K_BUS_AHB:
2062 case ATH10K_BUS_SNOC:
2063 scnprintf(fw_name, fw_name_len, "%s-%d.bin",
2064 ATH10K_FW_FILE_BASE, fw_api);
2065 break;
2066 }
2067 }
2068
ath10k_core_fetch_firmware_files(struct ath10k * ar)2069 static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
2070 {
2071 int ret, i;
2072 char fw_name[100];
2073
2074 /* calibration file is optional, don't check for any errors */
2075 ath10k_fetch_cal_file(ar);
2076
2077 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) {
2078 ar->fw_api = i;
2079 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n",
2080 ar->fw_api);
2081
2082 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api);
2083 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name,
2084 &ar->normal_mode_fw.fw_file);
2085 if (!ret)
2086 goto success;
2087 }
2088
2089 /* we end up here if we couldn't fetch any firmware */
2090
2091 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d",
2092 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir,
2093 ret);
2094
2095 return ret;
2096
2097 success:
2098 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
2099
2100 return 0;
2101 }
2102
ath10k_core_pre_cal_download(struct ath10k * ar)2103 static int ath10k_core_pre_cal_download(struct ath10k *ar)
2104 {
2105 int ret;
2106
2107 ret = ath10k_download_cal_file(ar, ar->pre_cal_file);
2108 if (ret == 0) {
2109 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;
2110 goto success;
2111 }
2112
2113 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2114 "boot did not find a pre calibration file, try DT next: %d\n",
2115 ret);
2116
2117 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data");
2118 if (ret) {
2119 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2120 "unable to load pre cal data from DT: %d\n", ret);
2121 return ret;
2122 }
2123 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT;
2124
2125 success:
2126 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
2127 ath10k_cal_mode_str(ar->cal_mode));
2128
2129 return 0;
2130 }
2131
ath10k_core_pre_cal_config(struct ath10k * ar)2132 static int ath10k_core_pre_cal_config(struct ath10k *ar)
2133 {
2134 int ret;
2135
2136 ret = ath10k_core_pre_cal_download(ar);
2137 if (ret) {
2138 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2139 "failed to load pre cal data: %d\n", ret);
2140 return ret;
2141 }
2142
2143 ret = ath10k_core_get_board_id_from_otp(ar);
2144 if (ret) {
2145 ath10k_err(ar, "failed to get board id: %d\n", ret);
2146 return ret;
2147 }
2148
2149 ret = ath10k_download_and_run_otp(ar);
2150 if (ret) {
2151 ath10k_err(ar, "failed to run otp: %d\n", ret);
2152 return ret;
2153 }
2154
2155 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2156 "pre cal configuration done successfully\n");
2157
2158 return 0;
2159 }
2160
ath10k_download_cal_data(struct ath10k * ar)2161 static int ath10k_download_cal_data(struct ath10k *ar)
2162 {
2163 int ret;
2164
2165 ret = ath10k_core_pre_cal_config(ar);
2166 if (ret == 0)
2167 return 0;
2168
2169 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2170 "pre cal download procedure failed, try cal file: %d\n",
2171 ret);
2172
2173 ret = ath10k_download_cal_file(ar, ar->cal_file);
2174 if (ret == 0) {
2175 ar->cal_mode = ATH10K_CAL_MODE_FILE;
2176 goto done;
2177 }
2178
2179 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2180 "boot did not find a calibration file, try DT next: %d\n",
2181 ret);
2182
2183 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data");
2184 if (ret == 0) {
2185 ar->cal_mode = ATH10K_CAL_MODE_DT;
2186 goto done;
2187 }
2188
2189 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2190 "boot did not find DT entry, try target EEPROM next: %d\n",
2191 ret);
2192
2193 ret = ath10k_download_cal_eeprom(ar);
2194 if (ret == 0) {
2195 ar->cal_mode = ATH10K_CAL_MODE_EEPROM;
2196 goto done;
2197 }
2198
2199 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2200 "boot did not find target EEPROM entry, try OTP next: %d\n",
2201 ret);
2202
2203 ret = ath10k_download_and_run_otp(ar);
2204 if (ret) {
2205 ath10k_err(ar, "failed to run otp: %d\n", ret);
2206 return ret;
2207 }
2208
2209 ar->cal_mode = ATH10K_CAL_MODE_OTP;
2210
2211 done:
2212 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
2213 ath10k_cal_mode_str(ar->cal_mode));
2214 return 0;
2215 }
2216
ath10k_core_fetch_btcoex_dt(struct ath10k * ar)2217 static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar)
2218 {
2219 struct device_node *node;
2220 u8 coex_support = 0;
2221 int ret;
2222
2223 node = ar->dev->of_node;
2224 if (!node)
2225 goto out;
2226
2227 ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support);
2228 if (ret) {
2229 ar->coex_support = true;
2230 goto out;
2231 }
2232
2233 if (coex_support) {
2234 ar->coex_support = true;
2235 } else {
2236 ar->coex_support = false;
2237 ar->coex_gpio_pin = -1;
2238 goto out;
2239 }
2240
2241 ret = of_property_read_u32(node, "qcom,coexist-gpio-pin",
2242 &ar->coex_gpio_pin);
2243 if (ret)
2244 ar->coex_gpio_pin = -1;
2245
2246 out:
2247 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n",
2248 ar->coex_support, ar->coex_gpio_pin);
2249 }
2250
ath10k_init_uart(struct ath10k * ar)2251 static int ath10k_init_uart(struct ath10k *ar)
2252 {
2253 int ret;
2254
2255 /*
2256 * Explicitly setting UART prints to zero as target turns it on
2257 * based on scratch registers.
2258 */
2259 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
2260 if (ret) {
2261 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
2262 return ret;
2263 }
2264
2265 if (!uart_print) {
2266 if (ar->hw_params.uart_pin_workaround) {
2267 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin,
2268 ar->hw_params.uart_pin);
2269 if (ret) {
2270 ath10k_warn(ar, "failed to set UART TX pin: %d",
2271 ret);
2272 return ret;
2273 }
2274 }
2275
2276 return 0;
2277 }
2278
2279 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
2280 if (ret) {
2281 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
2282 return ret;
2283 }
2284
2285 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
2286 if (ret) {
2287 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
2288 return ret;
2289 }
2290
2291 /* Set the UART baud rate to 19200. */
2292 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
2293 if (ret) {
2294 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
2295 return ret;
2296 }
2297
2298 ath10k_info(ar, "UART prints enabled\n");
2299 return 0;
2300 }
2301
ath10k_init_hw_params(struct ath10k * ar)2302 static int ath10k_init_hw_params(struct ath10k *ar)
2303 {
2304 const struct ath10k_hw_params *hw_params;
2305 int i;
2306
2307 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
2308 hw_params = &ath10k_hw_params_list[i];
2309
2310 if (hw_params->bus == ar->hif.bus &&
2311 hw_params->id == ar->target_version &&
2312 hw_params->dev_id == ar->dev_id)
2313 break;
2314 }
2315
2316 if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
2317 ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
2318 ar->target_version);
2319 return -EINVAL;
2320 }
2321
2322 ar->hw_params = *hw_params;
2323
2324 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
2325 ar->hw_params.name, ar->target_version);
2326
2327 return 0;
2328 }
2329
ath10k_core_start_recovery(struct ath10k * ar)2330 void ath10k_core_start_recovery(struct ath10k *ar)
2331 {
2332 if (test_and_set_bit(ATH10K_FLAG_RESTARTING, &ar->dev_flags)) {
2333 ath10k_warn(ar, "already restarting\n");
2334 return;
2335 }
2336
2337 queue_work(ar->workqueue, &ar->restart_work);
2338 }
2339 EXPORT_SYMBOL(ath10k_core_start_recovery);
2340
ath10k_core_napi_enable(struct ath10k * ar)2341 void ath10k_core_napi_enable(struct ath10k *ar)
2342 {
2343 lockdep_assert_held(&ar->conf_mutex);
2344
2345 if (test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags))
2346 return;
2347
2348 napi_enable(&ar->napi);
2349 set_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags);
2350 }
2351 EXPORT_SYMBOL(ath10k_core_napi_enable);
2352
ath10k_core_napi_sync_disable(struct ath10k * ar)2353 void ath10k_core_napi_sync_disable(struct ath10k *ar)
2354 {
2355 lockdep_assert_held(&ar->conf_mutex);
2356
2357 if (!test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags))
2358 return;
2359
2360 napi_synchronize(&ar->napi);
2361 napi_disable(&ar->napi);
2362 clear_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags);
2363 }
2364 EXPORT_SYMBOL(ath10k_core_napi_sync_disable);
2365
ath10k_core_restart(struct work_struct * work)2366 static void ath10k_core_restart(struct work_struct *work)
2367 {
2368 struct ath10k *ar = container_of(work, struct ath10k, restart_work);
2369 int ret;
2370
2371 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
2372
2373 /* Place a barrier to make sure the compiler doesn't reorder
2374 * CRASH_FLUSH and calling other functions.
2375 */
2376 barrier();
2377
2378 ieee80211_stop_queues(ar->hw);
2379 ath10k_drain_tx(ar);
2380 complete(&ar->scan.started);
2381 complete(&ar->scan.completed);
2382 complete(&ar->scan.on_channel);
2383 complete(&ar->offchan_tx_completed);
2384 complete(&ar->install_key_done);
2385 complete(&ar->vdev_setup_done);
2386 complete(&ar->vdev_delete_done);
2387 complete(&ar->thermal.wmi_sync);
2388 complete(&ar->bss_survey_done);
2389 wake_up(&ar->htt.empty_tx_wq);
2390 wake_up(&ar->wmi.tx_credits_wq);
2391 wake_up(&ar->peer_mapping_wq);
2392
2393 /* TODO: We can have one instance of cancelling coverage_class_work by
2394 * moving it to ath10k_halt(), so that both stop() and restart() would
2395 * call that but it takes conf_mutex() and if we call cancel_work_sync()
2396 * with conf_mutex it will deadlock.
2397 */
2398 cancel_work_sync(&ar->set_coverage_class_work);
2399
2400 mutex_lock(&ar->conf_mutex);
2401
2402 switch (ar->state) {
2403 case ATH10K_STATE_ON:
2404 ar->state = ATH10K_STATE_RESTARTING;
2405 ath10k_halt(ar);
2406 ath10k_scan_finish(ar);
2407 ieee80211_restart_hw(ar->hw);
2408 break;
2409 case ATH10K_STATE_OFF:
2410 /* this can happen if driver is being unloaded
2411 * or if the crash happens during FW probing
2412 */
2413 ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
2414 break;
2415 case ATH10K_STATE_RESTARTING:
2416 /* hw restart might be requested from multiple places */
2417 break;
2418 case ATH10K_STATE_RESTARTED:
2419 ar->state = ATH10K_STATE_WEDGED;
2420 fallthrough;
2421 case ATH10K_STATE_WEDGED:
2422 ath10k_warn(ar, "device is wedged, will not restart\n");
2423 break;
2424 case ATH10K_STATE_UTF:
2425 ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
2426 break;
2427 }
2428
2429 mutex_unlock(&ar->conf_mutex);
2430
2431 ret = ath10k_coredump_submit(ar);
2432 if (ret)
2433 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d",
2434 ret);
2435
2436 complete(&ar->driver_recovery);
2437 }
2438
ath10k_core_set_coverage_class_work(struct work_struct * work)2439 static void ath10k_core_set_coverage_class_work(struct work_struct *work)
2440 {
2441 struct ath10k *ar = container_of(work, struct ath10k,
2442 set_coverage_class_work);
2443
2444 if (ar->hw_params.hw_ops->set_coverage_class)
2445 ar->hw_params.hw_ops->set_coverage_class(ar, -1);
2446 }
2447
ath10k_core_init_firmware_features(struct ath10k * ar)2448 static int ath10k_core_init_firmware_features(struct ath10k *ar)
2449 {
2450 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
2451 int max_num_peers;
2452
2453 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) &&
2454 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
2455 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
2456 return -EINVAL;
2457 }
2458
2459 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
2460 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
2461 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version);
2462 return -EINVAL;
2463 }
2464
2465 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
2466 switch (ath10k_cryptmode_param) {
2467 case ATH10K_CRYPT_MODE_HW:
2468 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2469 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
2470 break;
2471 case ATH10K_CRYPT_MODE_SW:
2472 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
2473 fw_file->fw_features)) {
2474 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
2475 return -EINVAL;
2476 }
2477
2478 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2479 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
2480 break;
2481 default:
2482 ath10k_info(ar, "invalid cryptmode: %d\n",
2483 ath10k_cryptmode_param);
2484 return -EINVAL;
2485 }
2486
2487 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
2488 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
2489
2490 if (rawmode) {
2491 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
2492 fw_file->fw_features)) {
2493 ath10k_err(ar, "rawmode = 1 requires support from firmware");
2494 return -EINVAL;
2495 }
2496 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2497 }
2498
2499 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
2500 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
2501
2502 /* Workaround:
2503 *
2504 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
2505 * and causes enormous performance issues (malformed frames,
2506 * etc).
2507 *
2508 * Disabling A-MSDU makes RAW mode stable with heavy traffic
2509 * albeit a bit slower compared to regular operation.
2510 */
2511 ar->htt.max_num_amsdu = 1;
2512 }
2513
2514 /* Backwards compatibility for firmwares without
2515 * ATH10K_FW_IE_WMI_OP_VERSION.
2516 */
2517 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
2518 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
2519 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
2520 fw_file->fw_features))
2521 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
2522 else
2523 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
2524 } else {
2525 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
2526 }
2527 }
2528
2529 switch (fw_file->wmi_op_version) {
2530 case ATH10K_FW_WMI_OP_VERSION_MAIN:
2531 max_num_peers = TARGET_NUM_PEERS;
2532 ar->max_num_stations = TARGET_NUM_STATIONS;
2533 ar->max_num_vdevs = TARGET_NUM_VDEVS;
2534 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
2535 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
2536 WMI_STAT_PEER;
2537 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2538 break;
2539 case ATH10K_FW_WMI_OP_VERSION_10_1:
2540 case ATH10K_FW_WMI_OP_VERSION_10_2:
2541 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2542 if (ath10k_peer_stats_enabled(ar)) {
2543 max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS;
2544 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS;
2545 } else {
2546 max_num_peers = TARGET_10X_NUM_PEERS;
2547 ar->max_num_stations = TARGET_10X_NUM_STATIONS;
2548 }
2549 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
2550 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
2551 ar->fw_stats_req_mask = WMI_STAT_PEER;
2552 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2553 break;
2554 case ATH10K_FW_WMI_OP_VERSION_TLV:
2555 max_num_peers = TARGET_TLV_NUM_PEERS;
2556 ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
2557 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
2558 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
2559 if (ar->hif.bus == ATH10K_BUS_SDIO)
2560 ar->htt.max_num_pending_tx =
2561 TARGET_TLV_NUM_MSDU_DESC_HL;
2562 else
2563 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
2564 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
2565 ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV |
2566 WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD;
2567 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2568 ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC;
2569 break;
2570 case ATH10K_FW_WMI_OP_VERSION_10_4:
2571 max_num_peers = TARGET_10_4_NUM_PEERS;
2572 ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
2573 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
2574 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
2575 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
2576 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER |
2577 WMI_10_4_STAT_PEER_EXTD |
2578 WMI_10_4_STAT_VDEV_EXTD;
2579 ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
2580 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS;
2581
2582 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
2583 fw_file->fw_features))
2584 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC;
2585 else
2586 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
2587 break;
2588 case ATH10K_FW_WMI_OP_VERSION_UNSET:
2589 case ATH10K_FW_WMI_OP_VERSION_MAX:
2590 default:
2591 WARN_ON(1);
2592 return -EINVAL;
2593 }
2594
2595 if (ar->hw_params.num_peers)
2596 ar->max_num_peers = ar->hw_params.num_peers;
2597 else
2598 ar->max_num_peers = max_num_peers;
2599
2600 /* Backwards compatibility for firmwares without
2601 * ATH10K_FW_IE_HTT_OP_VERSION.
2602 */
2603 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
2604 switch (fw_file->wmi_op_version) {
2605 case ATH10K_FW_WMI_OP_VERSION_MAIN:
2606 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
2607 break;
2608 case ATH10K_FW_WMI_OP_VERSION_10_1:
2609 case ATH10K_FW_WMI_OP_VERSION_10_2:
2610 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2611 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
2612 break;
2613 case ATH10K_FW_WMI_OP_VERSION_TLV:
2614 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
2615 break;
2616 case ATH10K_FW_WMI_OP_VERSION_10_4:
2617 case ATH10K_FW_WMI_OP_VERSION_UNSET:
2618 case ATH10K_FW_WMI_OP_VERSION_MAX:
2619 ath10k_err(ar, "htt op version not found from fw meta data");
2620 return -EINVAL;
2621 }
2622 }
2623
2624 return 0;
2625 }
2626
ath10k_core_reset_rx_filter(struct ath10k * ar)2627 static int ath10k_core_reset_rx_filter(struct ath10k *ar)
2628 {
2629 int ret;
2630 int vdev_id;
2631 int vdev_type;
2632 int vdev_subtype;
2633 const u8 *vdev_addr;
2634
2635 vdev_id = 0;
2636 vdev_type = WMI_VDEV_TYPE_STA;
2637 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE);
2638 vdev_addr = ar->mac_addr;
2639
2640 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype,
2641 vdev_addr);
2642 if (ret) {
2643 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret);
2644 return ret;
2645 }
2646
2647 ret = ath10k_wmi_vdev_delete(ar, vdev_id);
2648 if (ret) {
2649 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret);
2650 return ret;
2651 }
2652
2653 /* WMI and HTT may use separate HIF pipes and are not guaranteed to be
2654 * serialized properly implicitly.
2655 *
2656 * Moreover (most) WMI commands have no explicit acknowledges. It is
2657 * possible to infer it implicitly by poking firmware with echo
2658 * command - getting a reply means all preceding comments have been
2659 * (mostly) processed.
2660 *
2661 * In case of vdev create/delete this is sufficient.
2662 *
2663 * Without this it's possible to end up with a race when HTT Rx ring is
2664 * started before vdev create/delete hack is complete allowing a short
2665 * window of opportunity to receive (and Tx ACK) a bunch of frames.
2666 */
2667 ret = ath10k_wmi_barrier(ar);
2668 if (ret) {
2669 ath10k_err(ar, "failed to ping firmware: %d\n", ret);
2670 return ret;
2671 }
2672
2673 return 0;
2674 }
2675
ath10k_core_compat_services(struct ath10k * ar)2676 static int ath10k_core_compat_services(struct ath10k *ar)
2677 {
2678 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
2679
2680 /* all 10.x firmware versions support thermal throttling but don't
2681 * advertise the support via service flags so we have to hardcode
2682 * it here
2683 */
2684 switch (fw_file->wmi_op_version) {
2685 case ATH10K_FW_WMI_OP_VERSION_10_1:
2686 case ATH10K_FW_WMI_OP_VERSION_10_2:
2687 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2688 case ATH10K_FW_WMI_OP_VERSION_10_4:
2689 set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map);
2690 break;
2691 default:
2692 break;
2693 }
2694
2695 return 0;
2696 }
2697
2698 #define TGT_IRAM_READ_PER_ITR (8 * 1024)
2699
ath10k_core_copy_target_iram(struct ath10k * ar)2700 static int ath10k_core_copy_target_iram(struct ath10k *ar)
2701 {
2702 const struct ath10k_hw_mem_layout *hw_mem;
2703 const struct ath10k_mem_region *tmp, *mem_region = NULL;
2704 dma_addr_t paddr;
2705 void *vaddr = NULL;
2706 u8 num_read_itr;
2707 int i, ret;
2708 u32 len, remaining_len;
2709
2710 /* copy target iram feature must work also when
2711 * ATH10K_FW_CRASH_DUMP_RAM_DATA is disabled, so
2712 * _ath10k_coredump_get_mem_layout() to accomplist that
2713 */
2714 hw_mem = _ath10k_coredump_get_mem_layout(ar);
2715 if (!hw_mem)
2716 /* if CONFIG_DEV_COREDUMP is disabled we get NULL, then
2717 * just silently disable the feature by doing nothing
2718 */
2719 return 0;
2720
2721 for (i = 0; i < hw_mem->region_table.size; i++) {
2722 tmp = &hw_mem->region_table.regions[i];
2723 if (tmp->type == ATH10K_MEM_REGION_TYPE_REG) {
2724 mem_region = tmp;
2725 break;
2726 }
2727 }
2728
2729 if (!mem_region)
2730 return -ENOMEM;
2731
2732 for (i = 0; i < ar->wmi.num_mem_chunks; i++) {
2733 if (ar->wmi.mem_chunks[i].req_id ==
2734 WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID) {
2735 vaddr = ar->wmi.mem_chunks[i].vaddr;
2736 len = ar->wmi.mem_chunks[i].len;
2737 break;
2738 }
2739 }
2740
2741 if (!vaddr || !len) {
2742 ath10k_warn(ar, "No allocated memory for IRAM back up");
2743 return -ENOMEM;
2744 }
2745
2746 len = (len < mem_region->len) ? len : mem_region->len;
2747 paddr = mem_region->start;
2748 num_read_itr = len / TGT_IRAM_READ_PER_ITR;
2749 remaining_len = len % TGT_IRAM_READ_PER_ITR;
2750 for (i = 0; i < num_read_itr; i++) {
2751 ret = ath10k_hif_diag_read(ar, paddr, vaddr,
2752 TGT_IRAM_READ_PER_ITR);
2753 if (ret) {
2754 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d",
2755 ret);
2756 return ret;
2757 }
2758
2759 paddr += TGT_IRAM_READ_PER_ITR;
2760 vaddr += TGT_IRAM_READ_PER_ITR;
2761 }
2762
2763 if (remaining_len) {
2764 ret = ath10k_hif_diag_read(ar, paddr, vaddr, remaining_len);
2765 if (ret) {
2766 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d",
2767 ret);
2768 return ret;
2769 }
2770 }
2771
2772 ath10k_dbg(ar, ATH10K_DBG_BOOT, "target IRAM back up completed\n");
2773
2774 return 0;
2775 }
2776
ath10k_core_start(struct ath10k * ar,enum ath10k_firmware_mode mode,const struct ath10k_fw_components * fw)2777 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
2778 const struct ath10k_fw_components *fw)
2779 {
2780 int status;
2781 u32 val;
2782
2783 lockdep_assert_held(&ar->conf_mutex);
2784
2785 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
2786
2787 ar->running_fw = fw;
2788
2789 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
2790 ar->running_fw->fw_file.fw_features)) {
2791 ath10k_bmi_start(ar);
2792
2793 /* Enable hardware clock to speed up firmware download */
2794 if (ar->hw_params.hw_ops->enable_pll_clk) {
2795 status = ar->hw_params.hw_ops->enable_pll_clk(ar);
2796 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n",
2797 status);
2798 }
2799
2800 if (ath10k_init_configure_target(ar)) {
2801 status = -EINVAL;
2802 goto err;
2803 }
2804
2805 status = ath10k_download_cal_data(ar);
2806 if (status)
2807 goto err;
2808
2809 /* Some of qca988x solutions are having global reset issue
2810 * during target initialization. Bypassing PLL setting before
2811 * downloading firmware and letting the SoC run on REF_CLK is
2812 * fixing the problem. Corresponding firmware change is also
2813 * needed to set the clock source once the target is
2814 * initialized.
2815 */
2816 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
2817 ar->running_fw->fw_file.fw_features)) {
2818 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
2819 if (status) {
2820 ath10k_err(ar, "could not write to skip_clock_init: %d\n",
2821 status);
2822 goto err;
2823 }
2824 }
2825
2826 status = ath10k_download_fw(ar);
2827 if (status)
2828 goto err;
2829
2830 status = ath10k_init_uart(ar);
2831 if (status)
2832 goto err;
2833
2834 if (ar->hif.bus == ATH10K_BUS_SDIO) {
2835 status = ath10k_init_sdio(ar, mode);
2836 if (status) {
2837 ath10k_err(ar, "failed to init SDIO: %d\n", status);
2838 goto err;
2839 }
2840 }
2841 }
2842
2843 ar->htc.htc_ops.target_send_suspend_complete =
2844 ath10k_send_suspend_complete;
2845
2846 status = ath10k_htc_init(ar);
2847 if (status) {
2848 ath10k_err(ar, "could not init HTC (%d)\n", status);
2849 goto err;
2850 }
2851
2852 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
2853 ar->running_fw->fw_file.fw_features)) {
2854 status = ath10k_bmi_done(ar);
2855 if (status)
2856 goto err;
2857 }
2858
2859 status = ath10k_wmi_attach(ar);
2860 if (status) {
2861 ath10k_err(ar, "WMI attach failed: %d\n", status);
2862 goto err;
2863 }
2864
2865 status = ath10k_htt_init(ar);
2866 if (status) {
2867 ath10k_err(ar, "failed to init htt: %d\n", status);
2868 goto err_wmi_detach;
2869 }
2870
2871 status = ath10k_htt_tx_start(&ar->htt);
2872 if (status) {
2873 ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
2874 goto err_wmi_detach;
2875 }
2876
2877 /* If firmware indicates Full Rx Reorder support it must be used in a
2878 * slightly different manner. Let HTT code know.
2879 */
2880 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
2881 ar->wmi.svc_map));
2882
2883 status = ath10k_htt_rx_alloc(&ar->htt);
2884 if (status) {
2885 ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
2886 goto err_htt_tx_detach;
2887 }
2888
2889 status = ath10k_hif_start(ar);
2890 if (status) {
2891 ath10k_err(ar, "could not start HIF: %d\n", status);
2892 goto err_htt_rx_detach;
2893 }
2894
2895 status = ath10k_htc_wait_target(&ar->htc);
2896 if (status) {
2897 ath10k_err(ar, "failed to connect to HTC: %d\n", status);
2898 goto err_hif_stop;
2899 }
2900
2901 status = ath10k_hif_start_post(ar);
2902 if (status) {
2903 ath10k_err(ar, "failed to swap mailbox: %d\n", status);
2904 goto err_hif_stop;
2905 }
2906
2907 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
2908 status = ath10k_htt_connect(&ar->htt);
2909 if (status) {
2910 ath10k_err(ar, "failed to connect htt (%d)\n", status);
2911 goto err_hif_stop;
2912 }
2913 }
2914
2915 status = ath10k_wmi_connect(ar);
2916 if (status) {
2917 ath10k_err(ar, "could not connect wmi: %d\n", status);
2918 goto err_hif_stop;
2919 }
2920
2921 status = ath10k_htc_start(&ar->htc);
2922 if (status) {
2923 ath10k_err(ar, "failed to start htc: %d\n", status);
2924 goto err_hif_stop;
2925 }
2926
2927 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
2928 status = ath10k_wmi_wait_for_service_ready(ar);
2929 if (status) {
2930 ath10k_warn(ar, "wmi service ready event not received");
2931 goto err_hif_stop;
2932 }
2933 }
2934
2935 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
2936 ar->hw->wiphy->fw_version);
2937
2938 if (test_bit(ATH10K_FW_FEATURE_IRAM_RECOVERY,
2939 ar->running_fw->fw_file.fw_features)) {
2940 status = ath10k_core_copy_target_iram(ar);
2941 if (status) {
2942 ath10k_warn(ar, "failed to copy target iram contents: %d",
2943 status);
2944 goto err_hif_stop;
2945 }
2946 }
2947
2948 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) &&
2949 mode == ATH10K_FIRMWARE_MODE_NORMAL) {
2950 val = 0;
2951 if (ath10k_peer_stats_enabled(ar))
2952 val = WMI_10_4_PEER_STATS;
2953
2954 /* Enable vdev stats by default */
2955 val |= WMI_10_4_VDEV_STATS;
2956
2957 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map))
2958 val |= WMI_10_4_BSS_CHANNEL_INFO_64;
2959
2960 ath10k_core_fetch_btcoex_dt(ar);
2961
2962 /* 10.4 firmware supports BT-Coex without reloading firmware
2963 * via pdev param. To support Bluetooth coexistence pdev param,
2964 * WMI_COEX_GPIO_SUPPORT of extended resource config should be
2965 * enabled always.
2966 *
2967 * We can still enable BTCOEX if firmware has the support
2968 * eventhough btceox_support value is
2969 * ATH10K_DT_BTCOEX_NOT_FOUND
2970 */
2971
2972 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) &&
2973 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM,
2974 ar->running_fw->fw_file.fw_features) &&
2975 ar->coex_support)
2976 val |= WMI_10_4_COEX_GPIO_SUPPORT;
2977
2978 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY,
2979 ar->wmi.svc_map))
2980 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY;
2981
2982 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA,
2983 ar->wmi.svc_map))
2984 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA;
2985
2986 if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI,
2987 ar->wmi.svc_map))
2988 val |= WMI_10_4_TX_DATA_ACK_RSSI;
2989
2990 if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map))
2991 val |= WMI_10_4_REPORT_AIRTIME;
2992
2993 if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT,
2994 ar->wmi.svc_map))
2995 val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT;
2996
2997 status = ath10k_mac_ext_resource_config(ar, val);
2998 if (status) {
2999 ath10k_err(ar,
3000 "failed to send ext resource cfg command : %d\n",
3001 status);
3002 goto err_hif_stop;
3003 }
3004 }
3005
3006 status = ath10k_wmi_cmd_init(ar);
3007 if (status) {
3008 ath10k_err(ar, "could not send WMI init command (%d)\n",
3009 status);
3010 goto err_hif_stop;
3011 }
3012
3013 status = ath10k_wmi_wait_for_unified_ready(ar);
3014 if (status) {
3015 ath10k_err(ar, "wmi unified ready event not received\n");
3016 goto err_hif_stop;
3017 }
3018
3019 status = ath10k_core_compat_services(ar);
3020 if (status) {
3021 ath10k_err(ar, "compat services failed: %d\n", status);
3022 goto err_hif_stop;
3023 }
3024
3025 status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr);
3026 if (status && status != -EOPNOTSUPP) {
3027 ath10k_err(ar,
3028 "failed to set base mac address: %d\n", status);
3029 goto err_hif_stop;
3030 }
3031
3032 /* Some firmware revisions do not properly set up hardware rx filter
3033 * registers.
3034 *
3035 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK
3036 * is filled with 0s instead of 1s allowing HW to respond with ACKs to
3037 * any frames that matches MAC_PCU_RX_FILTER which is also
3038 * misconfigured to accept anything.
3039 *
3040 * The ADDR1 is programmed using internal firmware structure field and
3041 * can't be (easily/sanely) reached from the driver explicitly. It is
3042 * possible to implicitly make it correct by creating a dummy vdev and
3043 * then deleting it.
3044 */
3045 if (ar->hw_params.hw_filter_reset_required &&
3046 mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3047 status = ath10k_core_reset_rx_filter(ar);
3048 if (status) {
3049 ath10k_err(ar,
3050 "failed to reset rx filter: %d\n", status);
3051 goto err_hif_stop;
3052 }
3053 }
3054
3055 status = ath10k_htt_rx_ring_refill(ar);
3056 if (status) {
3057 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
3058 goto err_hif_stop;
3059 }
3060
3061 if (ar->max_num_vdevs >= 64)
3062 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL;
3063 else
3064 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
3065
3066 INIT_LIST_HEAD(&ar->arvifs);
3067
3068 /* we don't care about HTT in UTF mode */
3069 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3070 status = ath10k_htt_setup(&ar->htt);
3071 if (status) {
3072 ath10k_err(ar, "failed to setup htt: %d\n", status);
3073 goto err_hif_stop;
3074 }
3075 }
3076
3077 status = ath10k_debug_start(ar);
3078 if (status)
3079 goto err_hif_stop;
3080
3081 status = ath10k_hif_set_target_log_mode(ar, fw_diag_log);
3082 if (status && status != -EOPNOTSUPP) {
3083 ath10k_warn(ar, "set target log mode failed: %d\n", status);
3084 goto err_hif_stop;
3085 }
3086
3087 return 0;
3088
3089 err_hif_stop:
3090 ath10k_hif_stop(ar);
3091 err_htt_rx_detach:
3092 ath10k_htt_rx_free(&ar->htt);
3093 err_htt_tx_detach:
3094 ath10k_htt_tx_free(&ar->htt);
3095 err_wmi_detach:
3096 ath10k_wmi_detach(ar);
3097 err:
3098 return status;
3099 }
3100 EXPORT_SYMBOL(ath10k_core_start);
3101
ath10k_wait_for_suspend(struct ath10k * ar,u32 suspend_opt)3102 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
3103 {
3104 int ret;
3105 unsigned long time_left;
3106
3107 reinit_completion(&ar->target_suspend);
3108
3109 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
3110 if (ret) {
3111 ath10k_warn(ar, "could not suspend target (%d)\n", ret);
3112 return ret;
3113 }
3114
3115 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
3116
3117 if (!time_left) {
3118 ath10k_warn(ar, "suspend timed out - target pause event never came\n");
3119 return -ETIMEDOUT;
3120 }
3121
3122 return 0;
3123 }
3124
ath10k_core_stop(struct ath10k * ar)3125 void ath10k_core_stop(struct ath10k *ar)
3126 {
3127 lockdep_assert_held(&ar->conf_mutex);
3128 ath10k_debug_stop(ar);
3129
3130 /* try to suspend target */
3131 if (ar->state != ATH10K_STATE_RESTARTING &&
3132 ar->state != ATH10K_STATE_UTF)
3133 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
3134
3135 ath10k_hif_stop(ar);
3136 ath10k_htt_tx_stop(&ar->htt);
3137 ath10k_htt_rx_free(&ar->htt);
3138 ath10k_wmi_detach(ar);
3139
3140 ar->id.bmi_ids_valid = false;
3141 }
3142 EXPORT_SYMBOL(ath10k_core_stop);
3143
3144 /* mac80211 manages fw/hw initialization through start/stop hooks. However in
3145 * order to know what hw capabilities should be advertised to mac80211 it is
3146 * necessary to load the firmware (and tear it down immediately since start
3147 * hook will try to init it again) before registering
3148 */
ath10k_core_probe_fw(struct ath10k * ar)3149 static int ath10k_core_probe_fw(struct ath10k *ar)
3150 {
3151 struct bmi_target_info target_info;
3152 int ret = 0;
3153
3154 ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL);
3155 if (ret) {
3156 ath10k_err(ar, "could not power on hif bus (%d)\n", ret);
3157 return ret;
3158 }
3159
3160 switch (ar->hif.bus) {
3161 case ATH10K_BUS_SDIO:
3162 memset(&target_info, 0, sizeof(target_info));
3163 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info);
3164 if (ret) {
3165 ath10k_err(ar, "could not get target info (%d)\n", ret);
3166 goto err_power_down;
3167 }
3168 ar->target_version = target_info.version;
3169 ar->hw->wiphy->hw_version = target_info.version;
3170 break;
3171 case ATH10K_BUS_PCI:
3172 case ATH10K_BUS_AHB:
3173 case ATH10K_BUS_USB:
3174 memset(&target_info, 0, sizeof(target_info));
3175 ret = ath10k_bmi_get_target_info(ar, &target_info);
3176 if (ret) {
3177 ath10k_err(ar, "could not get target info (%d)\n", ret);
3178 goto err_power_down;
3179 }
3180 ar->target_version = target_info.version;
3181 ar->hw->wiphy->hw_version = target_info.version;
3182 break;
3183 case ATH10K_BUS_SNOC:
3184 memset(&target_info, 0, sizeof(target_info));
3185 ret = ath10k_hif_get_target_info(ar, &target_info);
3186 if (ret) {
3187 ath10k_err(ar, "could not get target info (%d)\n", ret);
3188 goto err_power_down;
3189 }
3190 ar->target_version = target_info.version;
3191 ar->hw->wiphy->hw_version = target_info.version;
3192 break;
3193 default:
3194 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus);
3195 }
3196
3197 ret = ath10k_init_hw_params(ar);
3198 if (ret) {
3199 ath10k_err(ar, "could not get hw params (%d)\n", ret);
3200 goto err_power_down;
3201 }
3202
3203 ret = ath10k_core_fetch_firmware_files(ar);
3204 if (ret) {
3205 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
3206 goto err_power_down;
3207 }
3208
3209 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) !=
3210 sizeof(ar->normal_mode_fw.fw_file.fw_version));
3211 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version,
3212 sizeof(ar->hw->wiphy->fw_version));
3213
3214 ath10k_debug_print_hwfw_info(ar);
3215
3216 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3217 ar->normal_mode_fw.fw_file.fw_features)) {
3218 ret = ath10k_core_pre_cal_download(ar);
3219 if (ret) {
3220 /* pre calibration data download is not necessary
3221 * for all the chipsets. Ignore failures and continue.
3222 */
3223 ath10k_dbg(ar, ATH10K_DBG_BOOT,
3224 "could not load pre cal data: %d\n", ret);
3225 }
3226
3227 ret = ath10k_core_get_board_id_from_otp(ar);
3228 if (ret && ret != -EOPNOTSUPP) {
3229 ath10k_err(ar, "failed to get board id from otp: %d\n",
3230 ret);
3231 goto err_free_firmware_files;
3232 }
3233
3234 ret = ath10k_core_check_smbios(ar);
3235 if (ret)
3236 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n");
3237
3238 ret = ath10k_core_check_dt(ar);
3239 if (ret)
3240 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n");
3241
3242 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD);
3243 if (ret) {
3244 ath10k_err(ar, "failed to fetch board file: %d\n", ret);
3245 goto err_free_firmware_files;
3246 }
3247
3248 ath10k_debug_print_board_info(ar);
3249 }
3250
3251 device_get_mac_address(ar->dev, ar->mac_addr, sizeof(ar->mac_addr));
3252
3253 ret = ath10k_core_init_firmware_features(ar);
3254 if (ret) {
3255 ath10k_err(ar, "fatal problem with firmware features: %d\n",
3256 ret);
3257 goto err_free_firmware_files;
3258 }
3259
3260 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3261 ar->normal_mode_fw.fw_file.fw_features)) {
3262 ret = ath10k_swap_code_seg_init(ar,
3263 &ar->normal_mode_fw.fw_file);
3264 if (ret) {
3265 ath10k_err(ar, "failed to initialize code swap segment: %d\n",
3266 ret);
3267 goto err_free_firmware_files;
3268 }
3269 }
3270
3271 mutex_lock(&ar->conf_mutex);
3272
3273 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL,
3274 &ar->normal_mode_fw);
3275 if (ret) {
3276 ath10k_err(ar, "could not init core (%d)\n", ret);
3277 goto err_unlock;
3278 }
3279
3280 ath10k_debug_print_boot_info(ar);
3281 ath10k_core_stop(ar);
3282
3283 mutex_unlock(&ar->conf_mutex);
3284
3285 ath10k_hif_power_down(ar);
3286 return 0;
3287
3288 err_unlock:
3289 mutex_unlock(&ar->conf_mutex);
3290
3291 err_free_firmware_files:
3292 ath10k_core_free_firmware_files(ar);
3293
3294 err_power_down:
3295 ath10k_hif_power_down(ar);
3296
3297 return ret;
3298 }
3299
ath10k_core_register_work(struct work_struct * work)3300 static void ath10k_core_register_work(struct work_struct *work)
3301 {
3302 struct ath10k *ar = container_of(work, struct ath10k, register_work);
3303 int status;
3304
3305 /* peer stats are enabled by default */
3306 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags);
3307
3308 status = ath10k_core_probe_fw(ar);
3309 if (status) {
3310 ath10k_err(ar, "could not probe fw (%d)\n", status);
3311 goto err;
3312 }
3313
3314 status = ath10k_mac_register(ar);
3315 if (status) {
3316 ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
3317 goto err_release_fw;
3318 }
3319
3320 status = ath10k_coredump_register(ar);
3321 if (status) {
3322 ath10k_err(ar, "unable to register coredump\n");
3323 goto err_unregister_mac;
3324 }
3325
3326 status = ath10k_debug_register(ar);
3327 if (status) {
3328 ath10k_err(ar, "unable to initialize debugfs\n");
3329 goto err_unregister_coredump;
3330 }
3331
3332 status = ath10k_spectral_create(ar);
3333 if (status) {
3334 ath10k_err(ar, "failed to initialize spectral\n");
3335 goto err_debug_destroy;
3336 }
3337
3338 status = ath10k_thermal_register(ar);
3339 if (status) {
3340 ath10k_err(ar, "could not register thermal device: %d\n",
3341 status);
3342 goto err_spectral_destroy;
3343 }
3344
3345 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
3346 return;
3347
3348 err_spectral_destroy:
3349 ath10k_spectral_destroy(ar);
3350 err_debug_destroy:
3351 ath10k_debug_destroy(ar);
3352 err_unregister_coredump:
3353 ath10k_coredump_unregister(ar);
3354 err_unregister_mac:
3355 ath10k_mac_unregister(ar);
3356 err_release_fw:
3357 ath10k_core_free_firmware_files(ar);
3358 err:
3359 /* TODO: It's probably a good idea to release device from the driver
3360 * but calling device_release_driver() here will cause a deadlock.
3361 */
3362 return;
3363 }
3364
ath10k_core_register(struct ath10k * ar,const struct ath10k_bus_params * bus_params)3365 int ath10k_core_register(struct ath10k *ar,
3366 const struct ath10k_bus_params *bus_params)
3367 {
3368 ar->bus_param = *bus_params;
3369
3370 queue_work(ar->workqueue, &ar->register_work);
3371
3372 return 0;
3373 }
3374 EXPORT_SYMBOL(ath10k_core_register);
3375
ath10k_core_unregister(struct ath10k * ar)3376 void ath10k_core_unregister(struct ath10k *ar)
3377 {
3378 cancel_work_sync(&ar->register_work);
3379
3380 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
3381 return;
3382
3383 ath10k_thermal_unregister(ar);
3384 /* Stop spectral before unregistering from mac80211 to remove the
3385 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
3386 * would be already be free'd recursively, leading to a double free.
3387 */
3388 ath10k_spectral_destroy(ar);
3389
3390 /* We must unregister from mac80211 before we stop HTC and HIF.
3391 * Otherwise we will fail to submit commands to FW and mac80211 will be
3392 * unhappy about callback failures.
3393 */
3394 ath10k_mac_unregister(ar);
3395
3396 ath10k_testmode_destroy(ar);
3397
3398 ath10k_core_free_firmware_files(ar);
3399 ath10k_core_free_board_files(ar);
3400
3401 ath10k_debug_unregister(ar);
3402 }
3403 EXPORT_SYMBOL(ath10k_core_unregister);
3404
ath10k_core_create(size_t priv_size,struct device * dev,enum ath10k_bus bus,enum ath10k_hw_rev hw_rev,const struct ath10k_hif_ops * hif_ops)3405 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
3406 enum ath10k_bus bus,
3407 enum ath10k_hw_rev hw_rev,
3408 const struct ath10k_hif_ops *hif_ops)
3409 {
3410 struct ath10k *ar;
3411 int ret;
3412
3413 ar = ath10k_mac_create(priv_size);
3414 if (!ar)
3415 return NULL;
3416
3417 ar->ath_common.priv = ar;
3418 ar->ath_common.hw = ar->hw;
3419 ar->dev = dev;
3420 ar->hw_rev = hw_rev;
3421 ar->hif.ops = hif_ops;
3422 ar->hif.bus = bus;
3423
3424 switch (hw_rev) {
3425 case ATH10K_HW_QCA988X:
3426 case ATH10K_HW_QCA9887:
3427 ar->regs = &qca988x_regs;
3428 ar->hw_ce_regs = &qcax_ce_regs;
3429 ar->hw_values = &qca988x_values;
3430 break;
3431 case ATH10K_HW_QCA6174:
3432 case ATH10K_HW_QCA9377:
3433 ar->regs = &qca6174_regs;
3434 ar->hw_ce_regs = &qcax_ce_regs;
3435 ar->hw_values = &qca6174_values;
3436 break;
3437 case ATH10K_HW_QCA99X0:
3438 case ATH10K_HW_QCA9984:
3439 ar->regs = &qca99x0_regs;
3440 ar->hw_ce_regs = &qcax_ce_regs;
3441 ar->hw_values = &qca99x0_values;
3442 break;
3443 case ATH10K_HW_QCA9888:
3444 ar->regs = &qca99x0_regs;
3445 ar->hw_ce_regs = &qcax_ce_regs;
3446 ar->hw_values = &qca9888_values;
3447 break;
3448 case ATH10K_HW_QCA4019:
3449 ar->regs = &qca4019_regs;
3450 ar->hw_ce_regs = &qcax_ce_regs;
3451 ar->hw_values = &qca4019_values;
3452 break;
3453 case ATH10K_HW_WCN3990:
3454 ar->regs = &wcn3990_regs;
3455 ar->hw_ce_regs = &wcn3990_ce_regs;
3456 ar->hw_values = &wcn3990_values;
3457 break;
3458 default:
3459 ath10k_err(ar, "unsupported core hardware revision %d\n",
3460 hw_rev);
3461 ret = -ENOTSUPP;
3462 goto err_free_mac;
3463 }
3464
3465 init_completion(&ar->scan.started);
3466 init_completion(&ar->scan.completed);
3467 init_completion(&ar->scan.on_channel);
3468 init_completion(&ar->target_suspend);
3469 init_completion(&ar->driver_recovery);
3470 init_completion(&ar->wow.wakeup_completed);
3471
3472 init_completion(&ar->install_key_done);
3473 init_completion(&ar->vdev_setup_done);
3474 init_completion(&ar->vdev_delete_done);
3475 init_completion(&ar->thermal.wmi_sync);
3476 init_completion(&ar->bss_survey_done);
3477 init_completion(&ar->peer_delete_done);
3478 init_completion(&ar->peer_stats_info_complete);
3479
3480 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
3481
3482 ar->workqueue = create_singlethread_workqueue("ath10k_wq");
3483 if (!ar->workqueue)
3484 goto err_free_mac;
3485
3486 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
3487 if (!ar->workqueue_aux)
3488 goto err_free_wq;
3489
3490 ar->workqueue_tx_complete =
3491 create_singlethread_workqueue("ath10k_tx_complete_wq");
3492 if (!ar->workqueue_tx_complete)
3493 goto err_free_aux_wq;
3494
3495 mutex_init(&ar->conf_mutex);
3496 mutex_init(&ar->dump_mutex);
3497 spin_lock_init(&ar->data_lock);
3498
3499 INIT_LIST_HEAD(&ar->peers);
3500 init_waitqueue_head(&ar->peer_mapping_wq);
3501 init_waitqueue_head(&ar->htt.empty_tx_wq);
3502 init_waitqueue_head(&ar->wmi.tx_credits_wq);
3503
3504 skb_queue_head_init(&ar->htt.rx_indication_head);
3505
3506 init_completion(&ar->offchan_tx_completed);
3507 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
3508 skb_queue_head_init(&ar->offchan_tx_queue);
3509
3510 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
3511 skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
3512
3513 INIT_WORK(&ar->register_work, ath10k_core_register_work);
3514 INIT_WORK(&ar->restart_work, ath10k_core_restart);
3515 INIT_WORK(&ar->set_coverage_class_work,
3516 ath10k_core_set_coverage_class_work);
3517
3518 init_dummy_netdev(&ar->napi_dev);
3519
3520 ret = ath10k_coredump_create(ar);
3521 if (ret)
3522 goto err_free_tx_complete;
3523
3524 ret = ath10k_debug_create(ar);
3525 if (ret)
3526 goto err_free_coredump;
3527
3528 return ar;
3529
3530 err_free_coredump:
3531 ath10k_coredump_destroy(ar);
3532 err_free_tx_complete:
3533 destroy_workqueue(ar->workqueue_tx_complete);
3534 err_free_aux_wq:
3535 destroy_workqueue(ar->workqueue_aux);
3536 err_free_wq:
3537 destroy_workqueue(ar->workqueue);
3538 err_free_mac:
3539 ath10k_mac_destroy(ar);
3540
3541 return NULL;
3542 }
3543 EXPORT_SYMBOL(ath10k_core_create);
3544
ath10k_core_destroy(struct ath10k * ar)3545 void ath10k_core_destroy(struct ath10k *ar)
3546 {
3547 flush_workqueue(ar->workqueue);
3548 destroy_workqueue(ar->workqueue);
3549
3550 flush_workqueue(ar->workqueue_aux);
3551 destroy_workqueue(ar->workqueue_aux);
3552
3553 flush_workqueue(ar->workqueue_tx_complete);
3554 destroy_workqueue(ar->workqueue_tx_complete);
3555
3556 ath10k_debug_destroy(ar);
3557 ath10k_coredump_destroy(ar);
3558 ath10k_htt_tx_destroy(&ar->htt);
3559 ath10k_wmi_free_host_mem(ar);
3560 ath10k_mac_destroy(ar);
3561 }
3562 EXPORT_SYMBOL(ath10k_core_destroy);
3563
3564 MODULE_AUTHOR("Qualcomm Atheros");
3565 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards.");
3566 MODULE_LICENSE("Dual BSD/GPL");
3567