1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 CGX driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/phy.h>
16 #include <linux/of.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
19
20 #include "cgx.h"
21 #include "rvu.h"
22 #include "lmac_common.h"
23
24 #define DRV_NAME "Marvell-CGX/RPM"
25 #define DRV_STRING "Marvell CGX/RPM Driver"
26
27 static LIST_HEAD(cgx_list);
28
29 /* Convert firmware speed encoding to user format(Mbps) */
30 static const u32 cgx_speed_mbps[CGX_LINK_SPEED_MAX] = {
31 [CGX_LINK_NONE] = 0,
32 [CGX_LINK_10M] = 10,
33 [CGX_LINK_100M] = 100,
34 [CGX_LINK_1G] = 1000,
35 [CGX_LINK_2HG] = 2500,
36 [CGX_LINK_5G] = 5000,
37 [CGX_LINK_10G] = 10000,
38 [CGX_LINK_20G] = 20000,
39 [CGX_LINK_25G] = 25000,
40 [CGX_LINK_40G] = 40000,
41 [CGX_LINK_50G] = 50000,
42 [CGX_LINK_80G] = 80000,
43 [CGX_LINK_100G] = 100000,
44 };
45
46 /* Convert firmware lmac type encoding to string */
47 static const char *cgx_lmactype_string[LMAC_MODE_MAX] = {
48 [LMAC_MODE_SGMII] = "SGMII",
49 [LMAC_MODE_XAUI] = "XAUI",
50 [LMAC_MODE_RXAUI] = "RXAUI",
51 [LMAC_MODE_10G_R] = "10G_R",
52 [LMAC_MODE_40G_R] = "40G_R",
53 [LMAC_MODE_QSGMII] = "QSGMII",
54 [LMAC_MODE_25G_R] = "25G_R",
55 [LMAC_MODE_50G_R] = "50G_R",
56 [LMAC_MODE_100G_R] = "100G_R",
57 [LMAC_MODE_USXGMII] = "USXGMII",
58 };
59
60 /* CGX PHY management internal APIs */
61 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en);
62
63 /* Supported devices */
64 static const struct pci_device_id cgx_id_table[] = {
65 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) },
66 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM) },
67 { 0, } /* end of table */
68 };
69
70 MODULE_DEVICE_TABLE(pci, cgx_id_table);
71
is_dev_rpm(void * cgxd)72 static bool is_dev_rpm(void *cgxd)
73 {
74 struct cgx *cgx = cgxd;
75
76 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM);
77 }
78
is_lmac_valid(struct cgx * cgx,int lmac_id)79 bool is_lmac_valid(struct cgx *cgx, int lmac_id)
80 {
81 if (!cgx || lmac_id < 0 || lmac_id >= MAX_LMAC_PER_CGX)
82 return false;
83 return test_bit(lmac_id, &cgx->lmac_bmap);
84 }
85
86 /* Helper function to get sequential index
87 * given the enabled LMAC of a CGX
88 */
get_sequence_id_of_lmac(struct cgx * cgx,int lmac_id)89 static int get_sequence_id_of_lmac(struct cgx *cgx, int lmac_id)
90 {
91 int tmp, id = 0;
92
93 for_each_set_bit(tmp, &cgx->lmac_bmap, MAX_LMAC_PER_CGX) {
94 if (tmp == lmac_id)
95 break;
96 id++;
97 }
98
99 return id;
100 }
101
get_mac_ops(void * cgxd)102 struct mac_ops *get_mac_ops(void *cgxd)
103 {
104 if (!cgxd)
105 return cgxd;
106
107 return ((struct cgx *)cgxd)->mac_ops;
108 }
109
cgx_write(struct cgx * cgx,u64 lmac,u64 offset,u64 val)110 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val)
111 {
112 writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +
113 offset);
114 }
115
cgx_read(struct cgx * cgx,u64 lmac,u64 offset)116 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset)
117 {
118 return readq(cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +
119 offset);
120 }
121
lmac_pdata(u8 lmac_id,struct cgx * cgx)122 struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx)
123 {
124 if (!cgx || lmac_id >= MAX_LMAC_PER_CGX)
125 return NULL;
126
127 return cgx->lmac_idmap[lmac_id];
128 }
129
cgx_get_cgxcnt_max(void)130 int cgx_get_cgxcnt_max(void)
131 {
132 struct cgx *cgx_dev;
133 int idmax = -ENODEV;
134
135 list_for_each_entry(cgx_dev, &cgx_list, cgx_list)
136 if (cgx_dev->cgx_id > idmax)
137 idmax = cgx_dev->cgx_id;
138
139 if (idmax < 0)
140 return 0;
141
142 return idmax + 1;
143 }
144
cgx_get_lmac_cnt(void * cgxd)145 int cgx_get_lmac_cnt(void *cgxd)
146 {
147 struct cgx *cgx = cgxd;
148
149 if (!cgx)
150 return -ENODEV;
151
152 return cgx->lmac_count;
153 }
154
cgx_get_pdata(int cgx_id)155 void *cgx_get_pdata(int cgx_id)
156 {
157 struct cgx *cgx_dev;
158
159 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) {
160 if (cgx_dev->cgx_id == cgx_id)
161 return cgx_dev;
162 }
163 return NULL;
164 }
165
cgx_lmac_write(int cgx_id,int lmac_id,u64 offset,u64 val)166 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val)
167 {
168 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
169
170 /* Software must not access disabled LMAC registers */
171 if (!is_lmac_valid(cgx_dev, lmac_id))
172 return;
173 cgx_write(cgx_dev, lmac_id, offset, val);
174 }
175
cgx_lmac_read(int cgx_id,int lmac_id,u64 offset)176 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset)
177 {
178 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
179
180 /* Software must not access disabled LMAC registers */
181 if (!is_lmac_valid(cgx_dev, lmac_id))
182 return 0;
183
184 return cgx_read(cgx_dev, lmac_id, offset);
185 }
186
cgx_get_cgxid(void * cgxd)187 int cgx_get_cgxid(void *cgxd)
188 {
189 struct cgx *cgx = cgxd;
190
191 if (!cgx)
192 return -EINVAL;
193
194 return cgx->cgx_id;
195 }
196
cgx_lmac_get_p2x(int cgx_id,int lmac_id)197 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id)
198 {
199 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
200 u64 cfg;
201
202 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG);
203
204 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT;
205 }
206
207 /* Ensure the required lock for event queue(where asynchronous events are
208 * posted) is acquired before calling this API. Else an asynchronous event(with
209 * latest link status) can reach the destination before this function returns
210 * and could make the link status appear wrong.
211 */
cgx_get_link_info(void * cgxd,int lmac_id,struct cgx_link_user_info * linfo)212 int cgx_get_link_info(void *cgxd, int lmac_id,
213 struct cgx_link_user_info *linfo)
214 {
215 struct lmac *lmac = lmac_pdata(lmac_id, cgxd);
216
217 if (!lmac)
218 return -ENODEV;
219
220 *linfo = lmac->link_info;
221 return 0;
222 }
223
mac2u64(u8 * mac_addr)224 static u64 mac2u64 (u8 *mac_addr)
225 {
226 u64 mac = 0;
227 int index;
228
229 for (index = ETH_ALEN - 1; index >= 0; index--)
230 mac |= ((u64)*mac_addr++) << (8 * index);
231 return mac;
232 }
233
cfg2mac(u64 cfg,u8 * mac_addr)234 static void cfg2mac(u64 cfg, u8 *mac_addr)
235 {
236 int i, index = 0;
237
238 for (i = ETH_ALEN - 1; i >= 0; i--, index++)
239 mac_addr[i] = (cfg >> (8 * index)) & 0xFF;
240 }
241
cgx_lmac_addr_set(u8 cgx_id,u8 lmac_id,u8 * mac_addr)242 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr)
243 {
244 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
245 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
246 struct mac_ops *mac_ops;
247 int index, id;
248 u64 cfg;
249
250 /* access mac_ops to know csr_offset */
251 mac_ops = cgx_dev->mac_ops;
252
253 /* copy 6bytes from macaddr */
254 /* memcpy(&cfg, mac_addr, 6); */
255
256 cfg = mac2u64 (mac_addr);
257
258 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
259
260 index = id * lmac->mac_to_index_bmap.max;
261
262 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)),
263 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49));
264
265 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
266 cfg |= (CGX_DMAC_CTL0_CAM_ENABLE | CGX_DMAC_BCAST_MODE |
267 CGX_DMAC_MCAST_MODE);
268 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
269
270 return 0;
271 }
272
cgx_read_dmac_ctrl(void * cgxd,int lmac_id)273 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id)
274 {
275 struct mac_ops *mac_ops;
276 struct cgx *cgx = cgxd;
277
278 if (!cgxd || !is_lmac_valid(cgxd, lmac_id))
279 return 0;
280
281 cgx = cgxd;
282 /* Get mac_ops to know csr offset */
283 mac_ops = cgx->mac_ops;
284
285 return cgx_read(cgxd, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
286 }
287
cgx_read_dmac_entry(void * cgxd,int index)288 u64 cgx_read_dmac_entry(void *cgxd, int index)
289 {
290 struct mac_ops *mac_ops;
291 struct cgx *cgx;
292
293 if (!cgxd)
294 return 0;
295
296 cgx = cgxd;
297 mac_ops = cgx->mac_ops;
298 return cgx_read(cgx, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 8)));
299 }
300
cgx_lmac_addr_add(u8 cgx_id,u8 lmac_id,u8 * mac_addr)301 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr)
302 {
303 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
304 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
305 struct mac_ops *mac_ops;
306 int index, idx;
307 u64 cfg = 0;
308 int id;
309
310 if (!lmac)
311 return -ENODEV;
312
313 mac_ops = cgx_dev->mac_ops;
314 /* Get available index where entry is to be installed */
315 idx = rvu_alloc_rsrc(&lmac->mac_to_index_bmap);
316 if (idx < 0)
317 return idx;
318
319 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
320
321 index = id * lmac->mac_to_index_bmap.max + idx;
322
323 cfg = mac2u64 (mac_addr);
324 cfg |= CGX_DMAC_CAM_ADDR_ENABLE;
325 cfg |= ((u64)lmac_id << 49);
326 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
327
328 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
329 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_CAM_ACCEPT);
330
331 if (is_multicast_ether_addr(mac_addr)) {
332 cfg &= ~GENMASK_ULL(2, 1);
333 cfg |= CGX_DMAC_MCAST_MODE_CAM;
334 lmac->mcast_filters_count++;
335 } else if (!lmac->mcast_filters_count) {
336 cfg |= CGX_DMAC_MCAST_MODE;
337 }
338
339 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
340
341 return idx;
342 }
343
cgx_lmac_addr_reset(u8 cgx_id,u8 lmac_id)344 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id)
345 {
346 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
347 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
348 struct mac_ops *mac_ops;
349 u8 index = 0, id;
350 u64 cfg;
351
352 if (!lmac)
353 return -ENODEV;
354
355 mac_ops = cgx_dev->mac_ops;
356 /* Restore index 0 to its default init value as done during
357 * cgx_lmac_init
358 */
359 set_bit(0, lmac->mac_to_index_bmap.bmap);
360
361 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
362
363 index = id * lmac->mac_to_index_bmap.max + index;
364 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
365
366 /* Reset CGXX_CMRX_RX_DMAC_CTL0 register to default state */
367 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
368 cfg &= ~CGX_DMAC_CAM_ACCEPT;
369 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE);
370 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
371
372 return 0;
373 }
374
375 /* Allows caller to change macaddress associated with index
376 * in dmac filter table including index 0 reserved for
377 * interface mac address
378 */
cgx_lmac_addr_update(u8 cgx_id,u8 lmac_id,u8 * mac_addr,u8 index)379 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index)
380 {
381 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
382 struct mac_ops *mac_ops;
383 struct lmac *lmac;
384 u64 cfg;
385 int id;
386
387 lmac = lmac_pdata(lmac_id, cgx_dev);
388 if (!lmac)
389 return -ENODEV;
390
391 mac_ops = cgx_dev->mac_ops;
392 /* Validate the index */
393 if (index >= lmac->mac_to_index_bmap.max)
394 return -EINVAL;
395
396 /* ensure index is already set */
397 if (!test_bit(index, lmac->mac_to_index_bmap.bmap))
398 return -EINVAL;
399
400 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
401
402 index = id * lmac->mac_to_index_bmap.max + index;
403
404 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)));
405 cfg &= ~CGX_RX_DMAC_ADR_MASK;
406 cfg |= mac2u64 (mac_addr);
407
408 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
409 return 0;
410 }
411
cgx_lmac_addr_del(u8 cgx_id,u8 lmac_id,u8 index)412 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index)
413 {
414 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
415 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
416 struct mac_ops *mac_ops;
417 u8 mac[ETH_ALEN];
418 u64 cfg;
419 int id;
420
421 if (!lmac)
422 return -ENODEV;
423
424 mac_ops = cgx_dev->mac_ops;
425 /* Validate the index */
426 if (index >= lmac->mac_to_index_bmap.max)
427 return -EINVAL;
428
429 /* Skip deletion for reserved index i.e. index 0 */
430 if (index == 0)
431 return 0;
432
433 rvu_free_rsrc(&lmac->mac_to_index_bmap, index);
434
435 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
436
437 index = id * lmac->mac_to_index_bmap.max + index;
438
439 /* Read MAC address to check whether it is ucast or mcast */
440 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)));
441
442 cfg2mac(cfg, mac);
443 if (is_multicast_ether_addr(mac))
444 lmac->mcast_filters_count--;
445
446 if (!lmac->mcast_filters_count) {
447 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
448 cfg &= ~GENMASK_ULL(2, 1);
449 cfg |= CGX_DMAC_MCAST_MODE;
450 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
451 }
452
453 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
454
455 return 0;
456 }
457
cgx_lmac_addr_max_entries_get(u8 cgx_id,u8 lmac_id)458 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id)
459 {
460 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
461 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
462
463 if (lmac)
464 return lmac->mac_to_index_bmap.max;
465
466 return 0;
467 }
468
cgx_lmac_addr_get(u8 cgx_id,u8 lmac_id)469 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id)
470 {
471 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
472 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
473 struct mac_ops *mac_ops;
474 int index;
475 u64 cfg;
476 int id;
477
478 mac_ops = cgx_dev->mac_ops;
479
480 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
481
482 index = id * lmac->mac_to_index_bmap.max;
483
484 cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8);
485 return cfg & CGX_RX_DMAC_ADR_MASK;
486 }
487
cgx_set_pkind(void * cgxd,u8 lmac_id,int pkind)488 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind)
489 {
490 struct cgx *cgx = cgxd;
491
492 if (!is_lmac_valid(cgx, lmac_id))
493 return -ENODEV;
494
495 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_ID_MAP, (pkind & 0x3F));
496 return 0;
497 }
498
cgx_get_lmac_type(void * cgxd,int lmac_id)499 static u8 cgx_get_lmac_type(void *cgxd, int lmac_id)
500 {
501 struct cgx *cgx = cgxd;
502 u64 cfg;
503
504 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
505 return (cfg >> CGX_LMAC_TYPE_SHIFT) & CGX_LMAC_TYPE_MASK;
506 }
507
cgx_get_lmac_fifo_len(void * cgxd,int lmac_id)508 static u32 cgx_get_lmac_fifo_len(void *cgxd, int lmac_id)
509 {
510 struct cgx *cgx = cgxd;
511 u8 num_lmacs;
512 u32 fifo_len;
513
514 fifo_len = cgx->mac_ops->fifo_len;
515 num_lmacs = cgx->mac_ops->get_nr_lmacs(cgx);
516
517 switch (num_lmacs) {
518 case 1:
519 return fifo_len;
520 case 2:
521 return fifo_len / 2;
522 case 3:
523 /* LMAC0 gets half of the FIFO, reset 1/4th */
524 if (lmac_id == 0)
525 return fifo_len / 2;
526 return fifo_len / 4;
527 case 4:
528 default:
529 return fifo_len / 4;
530 }
531 return 0;
532 }
533
534 /* Configure CGX LMAC in internal loopback mode */
cgx_lmac_internal_loopback(void * cgxd,int lmac_id,bool enable)535 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable)
536 {
537 struct cgx *cgx = cgxd;
538 u8 lmac_type;
539 u64 cfg;
540
541 if (!is_lmac_valid(cgx, lmac_id))
542 return -ENODEV;
543
544 lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac_id);
545 if (lmac_type == LMAC_MODE_SGMII || lmac_type == LMAC_MODE_QSGMII) {
546 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL);
547 if (enable)
548 cfg |= CGXX_GMP_PCS_MRX_CTL_LBK;
549 else
550 cfg &= ~CGXX_GMP_PCS_MRX_CTL_LBK;
551 cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg);
552 } else {
553 cfg = cgx_read(cgx, lmac_id, CGXX_SPUX_CONTROL1);
554 if (enable)
555 cfg |= CGXX_SPUX_CONTROL1_LBK;
556 else
557 cfg &= ~CGXX_SPUX_CONTROL1_LBK;
558 cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg);
559 }
560 return 0;
561 }
562
cgx_lmac_promisc_config(int cgx_id,int lmac_id,bool enable)563 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable)
564 {
565 struct cgx *cgx = cgx_get_pdata(cgx_id);
566 struct lmac *lmac = lmac_pdata(lmac_id, cgx);
567 u16 max_dmac = lmac->mac_to_index_bmap.max;
568 struct mac_ops *mac_ops;
569 int index, i;
570 u64 cfg = 0;
571 int id;
572
573 if (!cgx)
574 return;
575
576 id = get_sequence_id_of_lmac(cgx, lmac_id);
577
578 mac_ops = cgx->mac_ops;
579 if (enable) {
580 /* Enable promiscuous mode on LMAC */
581 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
582 cfg &= ~CGX_DMAC_CAM_ACCEPT;
583 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE);
584 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
585
586 for (i = 0; i < max_dmac; i++) {
587 index = id * max_dmac + i;
588 cfg = cgx_read(cgx, 0,
589 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8));
590 cfg &= ~CGX_DMAC_CAM_ADDR_ENABLE;
591 cgx_write(cgx, 0,
592 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8), cfg);
593 }
594 } else {
595 /* Disable promiscuous mode */
596 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
597 cfg |= CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE;
598 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
599 for (i = 0; i < max_dmac; i++) {
600 index = id * max_dmac + i;
601 cfg = cgx_read(cgx, 0,
602 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8));
603 if ((cfg & CGX_RX_DMAC_ADR_MASK) != 0) {
604 cfg |= CGX_DMAC_CAM_ADDR_ENABLE;
605 cgx_write(cgx, 0,
606 (CGXX_CMRX_RX_DMAC_CAM0 +
607 index * 0x8),
608 cfg);
609 }
610 }
611 }
612 }
613
614 /* Enable or disable forwarding received pause frames to Tx block */
cgx_lmac_enadis_rx_pause_fwding(void * cgxd,int lmac_id,bool enable)615 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable)
616 {
617 struct cgx *cgx = cgxd;
618 u64 cfg;
619
620 if (!cgx)
621 return;
622
623 if (enable) {
624 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
625 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
626 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
627
628 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
629 cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK;
630 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
631 } else {
632 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
633 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
634 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
635
636 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
637 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
638 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
639 }
640 }
641
cgx_get_rx_stats(void * cgxd,int lmac_id,int idx,u64 * rx_stat)642 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat)
643 {
644 struct cgx *cgx = cgxd;
645
646 if (!is_lmac_valid(cgx, lmac_id))
647 return -ENODEV;
648 *rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8));
649 return 0;
650 }
651
cgx_get_tx_stats(void * cgxd,int lmac_id,int idx,u64 * tx_stat)652 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat)
653 {
654 struct cgx *cgx = cgxd;
655
656 if (!is_lmac_valid(cgx, lmac_id))
657 return -ENODEV;
658 *tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8));
659 return 0;
660 }
661
cgx_features_get(void * cgxd)662 u64 cgx_features_get(void *cgxd)
663 {
664 return ((struct cgx *)cgxd)->hw_features;
665 }
666
cgx_set_fec_stats_count(struct cgx_link_user_info * linfo)667 static int cgx_set_fec_stats_count(struct cgx_link_user_info *linfo)
668 {
669 if (!linfo->fec)
670 return 0;
671
672 switch (linfo->lmac_type_id) {
673 case LMAC_MODE_SGMII:
674 case LMAC_MODE_XAUI:
675 case LMAC_MODE_RXAUI:
676 case LMAC_MODE_QSGMII:
677 return 0;
678 case LMAC_MODE_10G_R:
679 case LMAC_MODE_25G_R:
680 case LMAC_MODE_100G_R:
681 case LMAC_MODE_USXGMII:
682 return 1;
683 case LMAC_MODE_40G_R:
684 return 4;
685 case LMAC_MODE_50G_R:
686 if (linfo->fec == OTX2_FEC_BASER)
687 return 2;
688 else
689 return 1;
690 default:
691 return 0;
692 }
693 }
694
cgx_get_fec_stats(void * cgxd,int lmac_id,struct cgx_fec_stats_rsp * rsp)695 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp)
696 {
697 int stats, fec_stats_count = 0;
698 int corr_reg, uncorr_reg;
699 struct cgx *cgx = cgxd;
700
701 if (!cgx || lmac_id >= cgx->lmac_count)
702 return -ENODEV;
703 fec_stats_count =
704 cgx_set_fec_stats_count(&cgx->lmac_idmap[lmac_id]->link_info);
705 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) {
706 corr_reg = CGXX_SPUX_LNX_FEC_CORR_BLOCKS;
707 uncorr_reg = CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS;
708 } else {
709 corr_reg = CGXX_SPUX_RSFEC_CORR;
710 uncorr_reg = CGXX_SPUX_RSFEC_UNCORR;
711 }
712 for (stats = 0; stats < fec_stats_count; stats++) {
713 rsp->fec_corr_blks +=
714 cgx_read(cgx, lmac_id, corr_reg + (stats * 8));
715 rsp->fec_uncorr_blks +=
716 cgx_read(cgx, lmac_id, uncorr_reg + (stats * 8));
717 }
718 return 0;
719 }
720
cgx_lmac_rx_tx_enable(void * cgxd,int lmac_id,bool enable)721 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable)
722 {
723 struct cgx *cgx = cgxd;
724 u64 cfg;
725
726 if (!is_lmac_valid(cgx, lmac_id))
727 return -ENODEV;
728
729 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
730 if (enable)
731 cfg |= DATA_PKT_RX_EN | DATA_PKT_TX_EN;
732 else
733 cfg &= ~(DATA_PKT_RX_EN | DATA_PKT_TX_EN);
734 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
735 return 0;
736 }
737
cgx_lmac_tx_enable(void * cgxd,int lmac_id,bool enable)738 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable)
739 {
740 struct cgx *cgx = cgxd;
741 u64 cfg, last;
742
743 if (!is_lmac_valid(cgx, lmac_id))
744 return -ENODEV;
745
746 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
747 last = cfg;
748 if (enable)
749 cfg |= DATA_PKT_TX_EN;
750 else
751 cfg &= ~DATA_PKT_TX_EN;
752
753 if (cfg != last)
754 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
755 return !!(last & DATA_PKT_TX_EN);
756 }
757
cgx_lmac_get_pause_frm_status(void * cgxd,int lmac_id,u8 * tx_pause,u8 * rx_pause)758 static int cgx_lmac_get_pause_frm_status(void *cgxd, int lmac_id,
759 u8 *tx_pause, u8 *rx_pause)
760 {
761 struct cgx *cgx = cgxd;
762 u64 cfg;
763
764 if (is_dev_rpm(cgx))
765 return 0;
766
767 if (!is_lmac_valid(cgx, lmac_id))
768 return -ENODEV;
769
770 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
771 *rx_pause = !!(cfg & CGX_SMUX_RX_FRM_CTL_CTL_BCK);
772
773 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
774 *tx_pause = !!(cfg & CGX_SMUX_TX_CTL_L2P_BP_CONV);
775 return 0;
776 }
777
cgx_lmac_enadis_pause_frm(void * cgxd,int lmac_id,u8 tx_pause,u8 rx_pause)778 static int cgx_lmac_enadis_pause_frm(void *cgxd, int lmac_id,
779 u8 tx_pause, u8 rx_pause)
780 {
781 struct cgx *cgx = cgxd;
782 u64 cfg;
783
784 if (is_dev_rpm(cgx))
785 return 0;
786
787 if (!is_lmac_valid(cgx, lmac_id))
788 return -ENODEV;
789
790 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
791 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
792 cfg |= rx_pause ? CGX_SMUX_RX_FRM_CTL_CTL_BCK : 0x0;
793 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
794
795 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
796 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV;
797 cfg |= tx_pause ? CGX_SMUX_TX_CTL_L2P_BP_CONV : 0x0;
798 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
799
800 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP);
801 if (tx_pause) {
802 cfg &= ~CGX_CMR_RX_OVR_BP_EN(lmac_id);
803 } else {
804 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id);
805 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id);
806 }
807 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg);
808 return 0;
809 }
810
cgx_lmac_pause_frm_config(void * cgxd,int lmac_id,bool enable)811 static void cgx_lmac_pause_frm_config(void *cgxd, int lmac_id, bool enable)
812 {
813 struct cgx *cgx = cgxd;
814 u64 cfg;
815
816 if (!is_lmac_valid(cgx, lmac_id))
817 return;
818
819 if (enable) {
820 /* Set pause time and interval */
821 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_TIME,
822 DEFAULT_PAUSE_TIME);
823 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL);
824 cfg &= ~0xFFFFULL;
825 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL,
826 cfg | (DEFAULT_PAUSE_TIME / 2));
827
828 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_TIME,
829 DEFAULT_PAUSE_TIME);
830
831 cfg = cgx_read(cgx, lmac_id,
832 CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL);
833 cfg &= ~0xFFFFULL;
834 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL,
835 cfg | (DEFAULT_PAUSE_TIME / 2));
836 }
837
838 /* ALL pause frames received are completely ignored */
839 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
840 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
841 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
842
843 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
844 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
845 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
846
847 /* Disable pause frames transmission */
848 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
849 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV;
850 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
851 }
852
cgx_lmac_ptp_config(void * cgxd,int lmac_id,bool enable)853 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable)
854 {
855 struct cgx *cgx = cgxd;
856 u64 cfg;
857
858 if (!cgx)
859 return;
860
861 if (enable) {
862 /* Enable inbound PTP timestamping */
863 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
864 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE;
865 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
866
867 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
868 cfg |= CGX_SMUX_RX_FRM_CTL_PTP_MODE;
869 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
870 } else {
871 /* Disable inbound PTP stamping */
872 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
873 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE;
874 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
875
876 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
877 cfg &= ~CGX_SMUX_RX_FRM_CTL_PTP_MODE;
878 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
879 }
880 }
881
882 /* CGX Firmware interface low level support */
cgx_fwi_cmd_send(u64 req,u64 * resp,struct lmac * lmac)883 int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac)
884 {
885 struct cgx *cgx = lmac->cgx;
886 struct device *dev;
887 int err = 0;
888 u64 cmd;
889
890 /* Ensure no other command is in progress */
891 err = mutex_lock_interruptible(&lmac->cmd_lock);
892 if (err)
893 return err;
894
895 /* Ensure command register is free */
896 cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG);
897 if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) {
898 err = -EBUSY;
899 goto unlock;
900 }
901
902 /* Update ownership in command request */
903 req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req);
904
905 /* Mark this lmac as pending, before we start */
906 lmac->cmd_pend = true;
907
908 /* Start command in hardware */
909 cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req);
910
911 /* Ensure command is completed without errors */
912 if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend,
913 msecs_to_jiffies(CGX_CMD_TIMEOUT))) {
914 dev = &cgx->pdev->dev;
915 dev_err(dev, "cgx port %d:%d cmd timeout\n",
916 cgx->cgx_id, lmac->lmac_id);
917 err = -EIO;
918 goto unlock;
919 }
920
921 /* we have a valid command response */
922 smp_rmb(); /* Ensure the latest updates are visible */
923 *resp = lmac->resp;
924
925 unlock:
926 mutex_unlock(&lmac->cmd_lock);
927
928 return err;
929 }
930
cgx_fwi_cmd_generic(u64 req,u64 * resp,struct cgx * cgx,int lmac_id)931 int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id)
932 {
933 struct lmac *lmac;
934 int err;
935
936 lmac = lmac_pdata(lmac_id, cgx);
937 if (!lmac)
938 return -ENODEV;
939
940 err = cgx_fwi_cmd_send(req, resp, lmac);
941
942 /* Check for valid response */
943 if (!err) {
944 if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL)
945 return -EIO;
946 else
947 return 0;
948 }
949
950 return err;
951 }
952
cgx_link_usertable_index_map(int speed)953 static int cgx_link_usertable_index_map(int speed)
954 {
955 switch (speed) {
956 case SPEED_10:
957 return CGX_LINK_10M;
958 case SPEED_100:
959 return CGX_LINK_100M;
960 case SPEED_1000:
961 return CGX_LINK_1G;
962 case SPEED_2500:
963 return CGX_LINK_2HG;
964 case SPEED_5000:
965 return CGX_LINK_5G;
966 case SPEED_10000:
967 return CGX_LINK_10G;
968 case SPEED_20000:
969 return CGX_LINK_20G;
970 case SPEED_25000:
971 return CGX_LINK_25G;
972 case SPEED_40000:
973 return CGX_LINK_40G;
974 case SPEED_50000:
975 return CGX_LINK_50G;
976 case 80000:
977 return CGX_LINK_80G;
978 case SPEED_100000:
979 return CGX_LINK_100G;
980 case SPEED_UNKNOWN:
981 return CGX_LINK_NONE;
982 }
983 return CGX_LINK_NONE;
984 }
985
set_mod_args(struct cgx_set_link_mode_args * args,u32 speed,u8 duplex,u8 autoneg,u64 mode)986 static void set_mod_args(struct cgx_set_link_mode_args *args,
987 u32 speed, u8 duplex, u8 autoneg, u64 mode)
988 {
989 /* Fill default values incase of user did not pass
990 * valid parameters
991 */
992 if (args->duplex == DUPLEX_UNKNOWN)
993 args->duplex = duplex;
994 if (args->speed == SPEED_UNKNOWN)
995 args->speed = speed;
996 if (args->an == AUTONEG_UNKNOWN)
997 args->an = autoneg;
998 args->mode = mode;
999 args->ports = 0;
1000 }
1001
otx2_map_ethtool_link_modes(u64 bitmask,struct cgx_set_link_mode_args * args)1002 static void otx2_map_ethtool_link_modes(u64 bitmask,
1003 struct cgx_set_link_mode_args *args)
1004 {
1005 switch (bitmask) {
1006 case ETHTOOL_LINK_MODE_10baseT_Half_BIT:
1007 set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1008 break;
1009 case ETHTOOL_LINK_MODE_10baseT_Full_BIT:
1010 set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1011 break;
1012 case ETHTOOL_LINK_MODE_100baseT_Half_BIT:
1013 set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1014 break;
1015 case ETHTOOL_LINK_MODE_100baseT_Full_BIT:
1016 set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1017 break;
1018 case ETHTOOL_LINK_MODE_1000baseT_Half_BIT:
1019 set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1020 break;
1021 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT:
1022 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1023 break;
1024 case ETHTOOL_LINK_MODE_1000baseX_Full_BIT:
1025 set_mod_args(args, 1000, 0, 0, BIT_ULL(CGX_MODE_1000_BASEX));
1026 break;
1027 case ETHTOOL_LINK_MODE_10000baseT_Full_BIT:
1028 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_QSGMII));
1029 break;
1030 case ETHTOOL_LINK_MODE_10000baseSR_Full_BIT:
1031 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2C));
1032 break;
1033 case ETHTOOL_LINK_MODE_10000baseLR_Full_BIT:
1034 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2M));
1035 break;
1036 case ETHTOOL_LINK_MODE_10000baseKR_Full_BIT:
1037 set_mod_args(args, 10000, 0, 1, BIT_ULL(CGX_MODE_10G_KR));
1038 break;
1039 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
1040 set_mod_args(args, 25000, 0, 0, BIT_ULL(CGX_MODE_25G_C2C));
1041 break;
1042 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
1043 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_CR));
1044 break;
1045 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
1046 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_KR));
1047 break;
1048 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
1049 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2C));
1050 break;
1051 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
1052 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2M));
1053 break;
1054 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
1055 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_CR4));
1056 break;
1057 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
1058 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_KR4));
1059 break;
1060 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
1061 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2C));
1062 break;
1063 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
1064 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2M));
1065 break;
1066 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
1067 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_CR));
1068 break;
1069 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
1070 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_KR));
1071 break;
1072 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
1073 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2C));
1074 break;
1075 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
1076 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2M));
1077 break;
1078 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
1079 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_CR4));
1080 break;
1081 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
1082 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_KR4));
1083 break;
1084 default:
1085 set_mod_args(args, 0, 1, 0, BIT_ULL(CGX_MODE_MAX));
1086 break;
1087 }
1088 }
1089
link_status_user_format(u64 lstat,struct cgx_link_user_info * linfo,struct cgx * cgx,u8 lmac_id)1090 static inline void link_status_user_format(u64 lstat,
1091 struct cgx_link_user_info *linfo,
1092 struct cgx *cgx, u8 lmac_id)
1093 {
1094 const char *lmac_string;
1095
1096 linfo->link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat);
1097 linfo->full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat);
1098 linfo->speed = cgx_speed_mbps[FIELD_GET(RESP_LINKSTAT_SPEED, lstat)];
1099 linfo->an = FIELD_GET(RESP_LINKSTAT_AN, lstat);
1100 linfo->fec = FIELD_GET(RESP_LINKSTAT_FEC, lstat);
1101 linfo->lmac_type_id = cgx_get_lmac_type(cgx, lmac_id);
1102 lmac_string = cgx_lmactype_string[linfo->lmac_type_id];
1103 strncpy(linfo->lmac_type, lmac_string, LMACTYPE_STR_LEN - 1);
1104 }
1105
1106 /* Hardware event handlers */
cgx_link_change_handler(u64 lstat,struct lmac * lmac)1107 static inline void cgx_link_change_handler(u64 lstat,
1108 struct lmac *lmac)
1109 {
1110 struct cgx_link_user_info *linfo;
1111 struct cgx *cgx = lmac->cgx;
1112 struct cgx_link_event event;
1113 struct device *dev;
1114 int err_type;
1115
1116 dev = &cgx->pdev->dev;
1117
1118 link_status_user_format(lstat, &event.link_uinfo, cgx, lmac->lmac_id);
1119 err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat);
1120
1121 event.cgx_id = cgx->cgx_id;
1122 event.lmac_id = lmac->lmac_id;
1123
1124 /* update the local copy of link status */
1125 lmac->link_info = event.link_uinfo;
1126 linfo = &lmac->link_info;
1127
1128 if (err_type == CGX_ERR_SPEED_CHANGE_INVALID)
1129 return;
1130
1131 /* Ensure callback doesn't get unregistered until we finish it */
1132 spin_lock(&lmac->event_cb_lock);
1133
1134 if (!lmac->event_cb.notify_link_chg) {
1135 dev_dbg(dev, "cgx port %d:%d Link change handler null",
1136 cgx->cgx_id, lmac->lmac_id);
1137 if (err_type != CGX_ERR_NONE) {
1138 dev_err(dev, "cgx port %d:%d Link error %d\n",
1139 cgx->cgx_id, lmac->lmac_id, err_type);
1140 }
1141 dev_info(dev, "cgx port %d:%d Link is %s %d Mbps\n",
1142 cgx->cgx_id, lmac->lmac_id,
1143 linfo->link_up ? "UP" : "DOWN", linfo->speed);
1144 goto err;
1145 }
1146
1147 if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data))
1148 dev_err(dev, "event notification failure\n");
1149 err:
1150 spin_unlock(&lmac->event_cb_lock);
1151 }
1152
cgx_cmdresp_is_linkevent(u64 event)1153 static inline bool cgx_cmdresp_is_linkevent(u64 event)
1154 {
1155 u8 id;
1156
1157 id = FIELD_GET(EVTREG_ID, event);
1158 if (id == CGX_CMD_LINK_BRING_UP ||
1159 id == CGX_CMD_LINK_BRING_DOWN ||
1160 id == CGX_CMD_MODE_CHANGE)
1161 return true;
1162 else
1163 return false;
1164 }
1165
cgx_event_is_linkevent(u64 event)1166 static inline bool cgx_event_is_linkevent(u64 event)
1167 {
1168 if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE)
1169 return true;
1170 else
1171 return false;
1172 }
1173
cgx_fwi_event_handler(int irq,void * data)1174 static irqreturn_t cgx_fwi_event_handler(int irq, void *data)
1175 {
1176 u64 event, offset, clear_bit;
1177 struct lmac *lmac = data;
1178 struct cgx *cgx;
1179
1180 cgx = lmac->cgx;
1181
1182 /* Clear SW_INT for RPM and CMR_INT for CGX */
1183 offset = cgx->mac_ops->int_register;
1184 clear_bit = cgx->mac_ops->int_ena_bit;
1185
1186 event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG);
1187
1188 if (!FIELD_GET(EVTREG_ACK, event))
1189 return IRQ_NONE;
1190
1191 switch (FIELD_GET(EVTREG_EVT_TYPE, event)) {
1192 case CGX_EVT_CMD_RESP:
1193 /* Copy the response. Since only one command is active at a
1194 * time, there is no way a response can get overwritten
1195 */
1196 lmac->resp = event;
1197 /* Ensure response is updated before thread context starts */
1198 smp_wmb();
1199
1200 /* There wont be separate events for link change initiated from
1201 * software; Hence report the command responses as events
1202 */
1203 if (cgx_cmdresp_is_linkevent(event))
1204 cgx_link_change_handler(event, lmac);
1205
1206 /* Release thread waiting for completion */
1207 lmac->cmd_pend = false;
1208 wake_up_interruptible(&lmac->wq_cmd_cmplt);
1209 break;
1210 case CGX_EVT_ASYNC:
1211 if (cgx_event_is_linkevent(event))
1212 cgx_link_change_handler(event, lmac);
1213 break;
1214 }
1215
1216 /* Any new event or command response will be posted by firmware
1217 * only after the current status is acked.
1218 * Ack the interrupt register as well.
1219 */
1220 cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0);
1221 cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit);
1222
1223 return IRQ_HANDLED;
1224 }
1225
1226 /* APIs for PHY management using CGX firmware interface */
1227
1228 /* callback registration for hardware events like link change */
cgx_lmac_evh_register(struct cgx_event_cb * cb,void * cgxd,int lmac_id)1229 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id)
1230 {
1231 struct cgx *cgx = cgxd;
1232 struct lmac *lmac;
1233
1234 lmac = lmac_pdata(lmac_id, cgx);
1235 if (!lmac)
1236 return -ENODEV;
1237
1238 lmac->event_cb = *cb;
1239
1240 return 0;
1241 }
1242
cgx_lmac_evh_unregister(void * cgxd,int lmac_id)1243 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id)
1244 {
1245 struct lmac *lmac;
1246 unsigned long flags;
1247 struct cgx *cgx = cgxd;
1248
1249 lmac = lmac_pdata(lmac_id, cgx);
1250 if (!lmac)
1251 return -ENODEV;
1252
1253 spin_lock_irqsave(&lmac->event_cb_lock, flags);
1254 lmac->event_cb.notify_link_chg = NULL;
1255 lmac->event_cb.data = NULL;
1256 spin_unlock_irqrestore(&lmac->event_cb_lock, flags);
1257
1258 return 0;
1259 }
1260
cgx_get_fwdata_base(u64 * base)1261 int cgx_get_fwdata_base(u64 *base)
1262 {
1263 u64 req = 0, resp;
1264 struct cgx *cgx;
1265 int first_lmac;
1266 int err;
1267
1268 cgx = list_first_entry_or_null(&cgx_list, struct cgx, cgx_list);
1269 if (!cgx)
1270 return -ENXIO;
1271
1272 first_lmac = find_first_bit(&cgx->lmac_bmap, MAX_LMAC_PER_CGX);
1273 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FWD_BASE, req);
1274 err = cgx_fwi_cmd_generic(req, &resp, cgx, first_lmac);
1275 if (!err)
1276 *base = FIELD_GET(RESP_FWD_BASE, resp);
1277
1278 return err;
1279 }
1280
cgx_set_link_mode(void * cgxd,struct cgx_set_link_mode_args args,int cgx_id,int lmac_id)1281 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
1282 int cgx_id, int lmac_id)
1283 {
1284 struct cgx *cgx = cgxd;
1285 u64 req = 0, resp;
1286
1287 if (!cgx)
1288 return -ENODEV;
1289
1290 if (args.mode)
1291 otx2_map_ethtool_link_modes(args.mode, &args);
1292 if (!args.speed && args.duplex && !args.an)
1293 return -EINVAL;
1294
1295 req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req);
1296 req = FIELD_SET(CMDMODECHANGE_SPEED,
1297 cgx_link_usertable_index_map(args.speed), req);
1298 req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req);
1299 req = FIELD_SET(CMDMODECHANGE_AN, args.an, req);
1300 req = FIELD_SET(CMDMODECHANGE_PORT, args.ports, req);
1301 req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req);
1302
1303 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1304 }
cgx_set_fec(u64 fec,int cgx_id,int lmac_id)1305 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id)
1306 {
1307 u64 req = 0, resp;
1308 struct cgx *cgx;
1309 int err = 0;
1310
1311 cgx = cgx_get_pdata(cgx_id);
1312 if (!cgx)
1313 return -ENXIO;
1314
1315 req = FIELD_SET(CMDREG_ID, CGX_CMD_SET_FEC, req);
1316 req = FIELD_SET(CMDSETFEC, fec, req);
1317 err = cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1318 if (err)
1319 return err;
1320
1321 cgx->lmac_idmap[lmac_id]->link_info.fec =
1322 FIELD_GET(RESP_LINKSTAT_FEC, resp);
1323 return cgx->lmac_idmap[lmac_id]->link_info.fec;
1324 }
1325
cgx_get_phy_fec_stats(void * cgxd,int lmac_id)1326 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id)
1327 {
1328 struct cgx *cgx = cgxd;
1329 u64 req = 0, resp;
1330
1331 if (!cgx)
1332 return -ENODEV;
1333
1334 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_PHY_FEC_STATS, req);
1335 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1336 }
1337
cgx_fwi_link_change(struct cgx * cgx,int lmac_id,bool enable)1338 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable)
1339 {
1340 u64 req = 0;
1341 u64 resp;
1342
1343 if (enable)
1344 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req);
1345 else
1346 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req);
1347
1348 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1349 }
1350
cgx_fwi_read_version(u64 * resp,struct cgx * cgx)1351 static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx)
1352 {
1353 int first_lmac = find_first_bit(&cgx->lmac_bmap, MAX_LMAC_PER_CGX);
1354 u64 req = 0;
1355
1356 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req);
1357 return cgx_fwi_cmd_generic(req, resp, cgx, first_lmac);
1358 }
1359
cgx_lmac_verify_fwi_version(struct cgx * cgx)1360 static int cgx_lmac_verify_fwi_version(struct cgx *cgx)
1361 {
1362 struct device *dev = &cgx->pdev->dev;
1363 int major_ver, minor_ver;
1364 u64 resp;
1365 int err;
1366
1367 if (!cgx->lmac_count)
1368 return 0;
1369
1370 err = cgx_fwi_read_version(&resp, cgx);
1371 if (err)
1372 return err;
1373
1374 major_ver = FIELD_GET(RESP_MAJOR_VER, resp);
1375 minor_ver = FIELD_GET(RESP_MINOR_VER, resp);
1376 dev_dbg(dev, "Firmware command interface version = %d.%d\n",
1377 major_ver, minor_ver);
1378 if (major_ver != CGX_FIRMWARE_MAJOR_VER)
1379 return -EIO;
1380 else
1381 return 0;
1382 }
1383
cgx_lmac_linkup_work(struct work_struct * work)1384 static void cgx_lmac_linkup_work(struct work_struct *work)
1385 {
1386 struct cgx *cgx = container_of(work, struct cgx, cgx_cmd_work);
1387 struct device *dev = &cgx->pdev->dev;
1388 int i, err;
1389
1390 /* Do Link up for all the enabled lmacs */
1391 for_each_set_bit(i, &cgx->lmac_bmap, MAX_LMAC_PER_CGX) {
1392 err = cgx_fwi_link_change(cgx, i, true);
1393 if (err)
1394 dev_info(dev, "cgx port %d:%d Link up command failed\n",
1395 cgx->cgx_id, i);
1396 }
1397 }
1398
cgx_lmac_linkup_start(void * cgxd)1399 int cgx_lmac_linkup_start(void *cgxd)
1400 {
1401 struct cgx *cgx = cgxd;
1402
1403 if (!cgx)
1404 return -ENODEV;
1405
1406 queue_work(cgx->cgx_cmd_workq, &cgx->cgx_cmd_work);
1407
1408 return 0;
1409 }
1410
cgx_lmac_get_fifolen(struct cgx * cgx)1411 static void cgx_lmac_get_fifolen(struct cgx *cgx)
1412 {
1413 u64 cfg;
1414
1415 cfg = cgx_read(cgx, 0, CGX_CONST);
1416 cgx->mac_ops->fifo_len = FIELD_GET(CGX_CONST_RXFIFO_SIZE, cfg);
1417 }
1418
cgx_configure_interrupt(struct cgx * cgx,struct lmac * lmac,int cnt,bool req_free)1419 static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac,
1420 int cnt, bool req_free)
1421 {
1422 struct mac_ops *mac_ops = cgx->mac_ops;
1423 u64 offset, ena_bit;
1424 unsigned int irq;
1425 int err;
1426
1427 irq = pci_irq_vector(cgx->pdev, mac_ops->lmac_fwi +
1428 cnt * mac_ops->irq_offset);
1429 offset = mac_ops->int_set_reg;
1430 ena_bit = mac_ops->int_ena_bit;
1431
1432 if (req_free) {
1433 free_irq(irq, lmac);
1434 return 0;
1435 }
1436
1437 err = request_irq(irq, cgx_fwi_event_handler, 0, lmac->name, lmac);
1438 if (err)
1439 return err;
1440
1441 /* Enable interrupt */
1442 cgx_write(cgx, lmac->lmac_id, offset, ena_bit);
1443 return 0;
1444 }
1445
cgx_get_nr_lmacs(void * cgxd)1446 int cgx_get_nr_lmacs(void *cgxd)
1447 {
1448 struct cgx *cgx = cgxd;
1449
1450 return cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7ULL;
1451 }
1452
cgx_get_lmacid(void * cgxd,u8 lmac_index)1453 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index)
1454 {
1455 struct cgx *cgx = cgxd;
1456
1457 return cgx->lmac_idmap[lmac_index]->lmac_id;
1458 }
1459
cgx_get_lmac_bmap(void * cgxd)1460 unsigned long cgx_get_lmac_bmap(void *cgxd)
1461 {
1462 struct cgx *cgx = cgxd;
1463
1464 return cgx->lmac_bmap;
1465 }
1466
cgx_lmac_init(struct cgx * cgx)1467 static int cgx_lmac_init(struct cgx *cgx)
1468 {
1469 struct lmac *lmac;
1470 u64 lmac_list;
1471 int i, err;
1472
1473 cgx_lmac_get_fifolen(cgx);
1474
1475 cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx);
1476 /* lmac_list specifies which lmacs are enabled
1477 * when bit n is set to 1, LMAC[n] is enabled
1478 */
1479 if (cgx->mac_ops->non_contiguous_serdes_lane)
1480 lmac_list = cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0xFULL;
1481
1482 if (cgx->lmac_count > MAX_LMAC_PER_CGX)
1483 cgx->lmac_count = MAX_LMAC_PER_CGX;
1484
1485 for (i = 0; i < cgx->lmac_count; i++) {
1486 lmac = kzalloc(sizeof(struct lmac), GFP_KERNEL);
1487 if (!lmac)
1488 return -ENOMEM;
1489 lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL);
1490 if (!lmac->name) {
1491 err = -ENOMEM;
1492 goto err_lmac_free;
1493 }
1494 sprintf(lmac->name, "cgx_fwi_%d_%d", cgx->cgx_id, i);
1495 if (cgx->mac_ops->non_contiguous_serdes_lane) {
1496 lmac->lmac_id = __ffs64(lmac_list);
1497 lmac_list &= ~BIT_ULL(lmac->lmac_id);
1498 } else {
1499 lmac->lmac_id = i;
1500 }
1501
1502 lmac->cgx = cgx;
1503 lmac->mac_to_index_bmap.max =
1504 MAX_DMAC_ENTRIES_PER_CGX / cgx->lmac_count;
1505 err = rvu_alloc_bitmap(&lmac->mac_to_index_bmap);
1506 if (err)
1507 goto err_name_free;
1508
1509 /* Reserve first entry for default MAC address */
1510 set_bit(0, lmac->mac_to_index_bmap.bmap);
1511
1512 init_waitqueue_head(&lmac->wq_cmd_cmplt);
1513 mutex_init(&lmac->cmd_lock);
1514 spin_lock_init(&lmac->event_cb_lock);
1515 err = cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, false);
1516 if (err)
1517 goto err_bitmap_free;
1518
1519 /* Add reference */
1520 cgx->lmac_idmap[lmac->lmac_id] = lmac;
1521 set_bit(lmac->lmac_id, &cgx->lmac_bmap);
1522 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true);
1523 }
1524
1525 return cgx_lmac_verify_fwi_version(cgx);
1526
1527 err_bitmap_free:
1528 rvu_free_bitmap(&lmac->mac_to_index_bmap);
1529 err_name_free:
1530 kfree(lmac->name);
1531 err_lmac_free:
1532 kfree(lmac);
1533 return err;
1534 }
1535
cgx_lmac_exit(struct cgx * cgx)1536 static int cgx_lmac_exit(struct cgx *cgx)
1537 {
1538 struct lmac *lmac;
1539 int i;
1540
1541 if (cgx->cgx_cmd_workq) {
1542 flush_workqueue(cgx->cgx_cmd_workq);
1543 destroy_workqueue(cgx->cgx_cmd_workq);
1544 cgx->cgx_cmd_workq = NULL;
1545 }
1546
1547 /* Free all lmac related resources */
1548 for_each_set_bit(i, &cgx->lmac_bmap, MAX_LMAC_PER_CGX) {
1549 lmac = cgx->lmac_idmap[i];
1550 if (!lmac)
1551 continue;
1552 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, false);
1553 cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, true);
1554 kfree(lmac->mac_to_index_bmap.bmap);
1555 kfree(lmac->name);
1556 kfree(lmac);
1557 }
1558
1559 return 0;
1560 }
1561
cgx_populate_features(struct cgx * cgx)1562 static void cgx_populate_features(struct cgx *cgx)
1563 {
1564 if (is_dev_rpm(cgx))
1565 cgx->hw_features = (RVU_LMAC_FEAT_DMACF | RVU_MAC_RPM |
1566 RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP);
1567 else
1568 cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_HIGIG2 |
1569 RVU_LMAC_FEAT_PTP | RVU_LMAC_FEAT_DMACF);
1570 }
1571
1572 static struct mac_ops cgx_mac_ops = {
1573 .name = "cgx",
1574 .csr_offset = 0,
1575 .lmac_offset = 18,
1576 .int_register = CGXX_CMRX_INT,
1577 .int_set_reg = CGXX_CMRX_INT_ENA_W1S,
1578 .irq_offset = 9,
1579 .int_ena_bit = FW_CGX_INT,
1580 .lmac_fwi = CGX_LMAC_FWI,
1581 .non_contiguous_serdes_lane = false,
1582 .rx_stats_cnt = 9,
1583 .tx_stats_cnt = 18,
1584 .get_nr_lmacs = cgx_get_nr_lmacs,
1585 .get_lmac_type = cgx_get_lmac_type,
1586 .lmac_fifo_len = cgx_get_lmac_fifo_len,
1587 .mac_lmac_intl_lbk = cgx_lmac_internal_loopback,
1588 .mac_get_rx_stats = cgx_get_rx_stats,
1589 .mac_get_tx_stats = cgx_get_tx_stats,
1590 .mac_enadis_rx_pause_fwding = cgx_lmac_enadis_rx_pause_fwding,
1591 .mac_get_pause_frm_status = cgx_lmac_get_pause_frm_status,
1592 .mac_enadis_pause_frm = cgx_lmac_enadis_pause_frm,
1593 .mac_pause_frm_config = cgx_lmac_pause_frm_config,
1594 .mac_enadis_ptp_config = cgx_lmac_ptp_config,
1595 .mac_rx_tx_enable = cgx_lmac_rx_tx_enable,
1596 .mac_tx_enable = cgx_lmac_tx_enable,
1597 };
1598
cgx_probe(struct pci_dev * pdev,const struct pci_device_id * id)1599 static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1600 {
1601 struct device *dev = &pdev->dev;
1602 struct cgx *cgx;
1603 int err, nvec;
1604
1605 cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL);
1606 if (!cgx)
1607 return -ENOMEM;
1608 cgx->pdev = pdev;
1609
1610 pci_set_drvdata(pdev, cgx);
1611
1612 /* Use mac_ops to get MAC specific features */
1613 if (pdev->device == PCI_DEVID_CN10K_RPM)
1614 cgx->mac_ops = rpm_get_mac_ops();
1615 else
1616 cgx->mac_ops = &cgx_mac_ops;
1617
1618 err = pci_enable_device(pdev);
1619 if (err) {
1620 dev_err(dev, "Failed to enable PCI device\n");
1621 pci_set_drvdata(pdev, NULL);
1622 return err;
1623 }
1624
1625 err = pci_request_regions(pdev, DRV_NAME);
1626 if (err) {
1627 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1628 goto err_disable_device;
1629 }
1630
1631 /* MAP configuration registers */
1632 cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1633 if (!cgx->reg_base) {
1634 dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n");
1635 err = -ENOMEM;
1636 goto err_release_regions;
1637 }
1638
1639 nvec = pci_msix_vec_count(cgx->pdev);
1640 err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX);
1641 if (err < 0 || err != nvec) {
1642 dev_err(dev, "Request for %d msix vectors failed, err %d\n",
1643 nvec, err);
1644 goto err_release_regions;
1645 }
1646
1647 cgx->cgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24)
1648 & CGX_ID_MASK;
1649
1650 /* init wq for processing linkup requests */
1651 INIT_WORK(&cgx->cgx_cmd_work, cgx_lmac_linkup_work);
1652 cgx->cgx_cmd_workq = alloc_workqueue("cgx_cmd_workq", 0, 0);
1653 if (!cgx->cgx_cmd_workq) {
1654 dev_err(dev, "alloc workqueue failed for cgx cmd");
1655 err = -ENOMEM;
1656 goto err_free_irq_vectors;
1657 }
1658
1659 list_add(&cgx->cgx_list, &cgx_list);
1660
1661
1662 cgx_populate_features(cgx);
1663
1664 mutex_init(&cgx->lock);
1665
1666 err = cgx_lmac_init(cgx);
1667 if (err)
1668 goto err_release_lmac;
1669
1670 return 0;
1671
1672 err_release_lmac:
1673 cgx_lmac_exit(cgx);
1674 list_del(&cgx->cgx_list);
1675 err_free_irq_vectors:
1676 pci_free_irq_vectors(pdev);
1677 err_release_regions:
1678 pci_release_regions(pdev);
1679 err_disable_device:
1680 pci_disable_device(pdev);
1681 pci_set_drvdata(pdev, NULL);
1682 return err;
1683 }
1684
cgx_remove(struct pci_dev * pdev)1685 static void cgx_remove(struct pci_dev *pdev)
1686 {
1687 struct cgx *cgx = pci_get_drvdata(pdev);
1688
1689 if (cgx) {
1690 cgx_lmac_exit(cgx);
1691 list_del(&cgx->cgx_list);
1692 }
1693 pci_free_irq_vectors(pdev);
1694 pci_release_regions(pdev);
1695 pci_disable_device(pdev);
1696 pci_set_drvdata(pdev, NULL);
1697 }
1698
1699 struct pci_driver cgx_driver = {
1700 .name = DRV_NAME,
1701 .id_table = cgx_id_table,
1702 .probe = cgx_probe,
1703 .remove = cgx_remove,
1704 };
1705