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Searched defs:csr (Results 1 – 25 of 32) sorted by relevance

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/arch/mips/dec/
Dkn02-irq.c30 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq() local
39 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq() local
62 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs() local
Dkn01-berr.c49 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_ack() local
150 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_interrupt() local
177 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_init() local
Decc-berr.c227 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in dec_kn02_be_init() local
/arch/sparc/kernel/
Debus.c74 u32 csr = 0; in ebus_dma_irq() local
99 u32 csr; in ebus_dma_register() local
127 u32 csr; in ebus_dma_irq_enable() local
159 u32 csr; in ebus_dma_unregister() local
179 u32 csr; in ebus_dma_request() local
208 u32 csr; in ebus_dma_prepare() local
244 u32 orig_csr, csr; in ebus_dma_enable() local
Dpsycho_common.c256 u64 csr, csr_error_bits; in psycho_pcierr_intr_other() local
/arch/sh/kernel/cpu/
Dadc.c16 unsigned char csr; in adc_single() local
/arch/riscv/include/asm/
Dcsr.h166 #define csr_swap(csr, val) \ argument
175 #define csr_read(csr) \ argument
184 #define csr_write(csr, val) \ argument
192 #define csr_read_set(csr, val) \ argument
201 #define csr_set(csr, val) \ argument
209 #define csr_read_clear(csr, val) \ argument
218 #define csr_clear(csr, val) \ argument
/arch/mips/kernel/
Dsignal.c75 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in copy_fp_to_sigcontext() local
94 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in copy_fp_from_sigcontext() local
130 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in save_hw_fp_context() local
139 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in restore_hw_fp_context() local
213 unsigned int csr; in restore_msa_extcontext() local
329 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in protected_save_fp_context() local
382 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in protected_restore_fp_context() local
500 unsigned int csr, enabled; in fpcsr_pending() local
Dirq_txx9.c34 u32 csr; member
186 u32 csr = __raw_readl(&txx9_ircptr->csr); in txx9_irq() local
Dmips-r2-to-r6-emul.c201 u32 csr; in movf_func() local
224 u32 csr; in movt_func() local
/arch/mips/cavium-octeon/executive/
Dcvmx-interrupt-rsl.c53 union cvmx_asxx_int_en csr; in __cvmx_interrupt_asxx_enable() local
/arch/m68k/sun3x/
Dtime.h9 volatile unsigned char csr; member
/arch/sh/boards/mach-hp6xx/
Dpm.c40 u8 stbcr, csr; in pm_enter() local
/arch/mips/include/asm/sibyte/
Dsb1250_defs.h242 #define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) argument
243 #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr))) argument
/arch/mips/include/uapi/asm/
Ducontext.h40 unsigned int csr; member
/arch/powerpc/boot/
Dugecon.c43 u32 csr, data, cr; in ug_io_transaction() local
/arch/mips/txx9/generic/
Dirq_tx4939.c211 u32 csr = __raw_readl(&tx4939_ircptr->cs.r); in tx4939_irq() local
/arch/powerpc/platforms/embedded6xx/
Dusbgecko_udbg.c50 u32 csr, data, cr; in ug_io_transaction() local
/arch/alpha/kernel/
Dsys_marvel.c174 volatile unsigned long *csr, in io7_redirect_irq()
Dcore_tsunami.c181 volatile unsigned long *csr; in tsunami_pci_tbi() local
Dcore_titan.c207 volatile unsigned long *csr; in titan_pci_tbi() local
/arch/alpha/include/asm/
Dcore_wildfire.h37 volatile unsigned long csr __attribute__((aligned(64))); member
41 volatile unsigned long csr __attribute__((aligned(256))); member
45 volatile unsigned long csr __attribute__((aligned(2048))); member
Dcore_marvel.h30 volatile unsigned long csr __attribute__((aligned(16))); member
71 volatile unsigned long csr __attribute__((aligned(64))); member
/arch/arm/plat-omap/
Ddma.c815 u32 csr; in omap1_dma_handle_ch() local
/arch/mips/include/asm/txx9/
Dtx4939.h105 struct tx4939_le_reg csr; member
158 struct tx4939_le_reg csr; member

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