1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef MBOX_H
9 #define MBOX_H
10
11 #include <linux/etherdevice.h>
12 #include <linux/sizes.h>
13
14 #include "rvu_struct.h"
15 #include "common.h"
16
17 #define MBOX_SIZE SZ_64K
18
19 /* AF/PF: PF initiated, PF/VF VF initiated */
20 #define MBOX_DOWN_RX_START 0
21 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
22 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
23 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
24 /* AF/PF: AF initiated, PF/VF PF initiated */
25 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
26 #define MBOX_UP_RX_SIZE SZ_1K
27 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
28 #define MBOX_UP_TX_SIZE SZ_1K
29
30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
31 # error "incorrect mailbox area sizes"
32 #endif
33
34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
35
36 #define MBOX_RSP_TIMEOUT 3000 /* Time(ms) to wait for mbox response */
37
38 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
39
40 /* Mailbox directions */
41 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
42 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
43 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
44 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
45 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
46 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
47 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
48 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
49
50 struct otx2_mbox_dev {
51 void *mbase; /* This dev's mbox region */
52 void *hwbase;
53 spinlock_t mbox_lock;
54 u16 msg_size; /* Total msg size to be sent */
55 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
56 u16 num_msgs; /* No of msgs sent or waiting for response */
57 u16 msgs_acked; /* No of msgs for which response is received */
58 };
59
60 struct otx2_mbox {
61 struct pci_dev *pdev;
62 void *hwbase; /* Mbox region advertised by HW */
63 void *reg_base;/* CSR base for this dev */
64 u64 trigger; /* Trigger mbox notification */
65 u16 tr_shift; /* Mbox trigger shift */
66 u64 rx_start; /* Offset of Rx region in mbox memory */
67 u64 tx_start; /* Offset of Tx region in mbox memory */
68 u16 rx_size; /* Size of Rx region */
69 u16 tx_size; /* Size of Tx region */
70 u16 ndevs; /* The number of peers */
71 struct otx2_mbox_dev *dev;
72 };
73
74 /* Header which precedes all mbox messages */
75 struct mbox_hdr {
76 u64 msg_size; /* Total msgs size embedded */
77 u16 num_msgs; /* No of msgs embedded */
78 };
79
80 /* Header which precedes every msg and is also part of it */
81 struct mbox_msghdr {
82 u16 pcifunc; /* Who's sending this msg */
83 u16 id; /* Mbox message ID */
84 #define OTX2_MBOX_REQ_SIG (0xdead)
85 #define OTX2_MBOX_RSP_SIG (0xbeef)
86 u16 sig; /* Signature, for validating corrupted msgs */
87 #define OTX2_MBOX_VERSION (0x000a)
88 u16 ver; /* Version of msg's structure for this ID */
89 u16 next_msgoff; /* Offset of next msg within mailbox region */
90 int rc; /* Msg process'ed response code */
91 };
92
93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
95 void otx2_mbox_destroy(struct otx2_mbox *mbox);
96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
97 struct pci_dev *pdev, void __force *reg_base,
98 int direction, int ndevs);
99
100 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
101 struct pci_dev *pdev, void __force *reg_base,
102 int direction, int ndevs, unsigned long *bmap);
103 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
104 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
105 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
106 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
107 int size, int size_rsp);
108 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
109 struct mbox_msghdr *msg);
110 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
111 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
112 u16 pcifunc, u16 id);
113 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
114 const char *otx2_mbox_id2name(u16 id);
otx2_mbox_alloc_msg(struct otx2_mbox * mbox,int devid,int size)115 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
116 int devid, int size)
117 {
118 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
119 }
120
121 /* Mailbox message types */
122 #define MBOX_MSG_MASK 0xFFFF
123 #define MBOX_MSG_INVALID 0xFFFE
124 #define MBOX_MSG_MAX 0xFFFF
125
126 #define MBOX_MESSAGES \
127 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
128 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
129 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
130 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
131 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
132 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
133 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
134 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
135 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
136 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
137 msg_rsp) \
138 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \
139 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
140 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
141 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
142 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
143 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
144 cgx_mac_addr_set_or_get) \
145 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
146 cgx_mac_addr_set_or_get) \
147 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
148 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
149 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
150 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
151 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
152 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
153 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
154 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
155 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
156 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
157 cgx_pause_frm_cfg) \
158 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
159 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
160 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
161 cgx_mac_addr_add_rsp) \
162 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
163 msg_rsp) \
164 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
165 cgx_max_dmac_entries_get_rsp) \
166 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
167 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
168 cgx_set_link_mode_rsp) \
169 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
170 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \
171 cgx_features_info_msg) \
172 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
173 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, msg_req, msg_rsp) \
174 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
175 msg_rsp) \
176 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
177 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
178 npa_lf_alloc_req, npa_lf_alloc_rsp) \
179 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
180 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
181 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
182 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
183 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
184 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
185 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
186 msg_rsp) \
187 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
188 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
189 cpt_rd_wr_reg_msg) \
190 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \
191 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
192 msg_rsp) \
193 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
194 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
195 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
196 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
197 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
198 npc_mcam_alloc_entry_rsp) \
199 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
200 npc_mcam_free_entry_req, msg_rsp) \
201 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
202 npc_mcam_write_entry_req, msg_rsp) \
203 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
204 npc_mcam_ena_dis_entry_req, msg_rsp) \
205 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
206 npc_mcam_ena_dis_entry_req, msg_rsp) \
207 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
208 npc_mcam_shift_entry_rsp) \
209 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
210 npc_mcam_alloc_counter_req, \
211 npc_mcam_alloc_counter_rsp) \
212 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
213 npc_mcam_oper_counter_req, msg_rsp) \
214 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
215 npc_mcam_unmap_counter_req, msg_rsp) \
216 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
217 npc_mcam_oper_counter_req, msg_rsp) \
218 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
219 npc_mcam_oper_counter_req, \
220 npc_mcam_oper_counter_rsp) \
221 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
222 npc_mcam_alloc_and_write_entry_req, \
223 npc_mcam_alloc_and_write_entry_rsp) \
224 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
225 msg_req, npc_get_kex_cfg_rsp) \
226 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
227 npc_install_flow_req, npc_install_flow_rsp) \
228 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
229 npc_delete_flow_req, msg_rsp) \
230 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
231 npc_mcam_read_entry_req, \
232 npc_mcam_read_entry_rsp) \
233 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
234 npc_set_pkind, msg_rsp) \
235 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
236 msg_req, npc_mcam_read_base_rule_rsp) \
237 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
238 npc_mcam_get_stats_req, \
239 npc_mcam_get_stats_rsp) \
240 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
241 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
242 nix_lf_alloc_req, nix_lf_alloc_rsp) \
243 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
244 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
245 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
246 hwctx_disable_req, msg_rsp) \
247 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
248 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
249 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
250 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
251 nix_txschq_config) \
252 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
253 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
254 nix_vtag_config_rsp) \
255 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
256 nix_rss_flowkey_cfg, \
257 nix_rss_flowkey_cfg_rsp) \
258 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
259 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
260 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
261 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
262 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
263 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
264 nix_mark_format_cfg, \
265 nix_mark_format_cfg_rsp) \
266 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
267 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
268 nix_lso_format_cfg, \
269 nix_lso_format_cfg_rsp) \
270 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
271 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
272 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
273 nix_bp_cfg_rsp) \
274 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
275 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
276 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
277 nix_cn10k_aq_enq_rsp) \
278 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
279 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
280 nix_bandprof_alloc_rsp) \
281 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
282 msg_rsp) \
283 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
284 nix_bandprof_get_hwinfo_rsp)
285
286 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
287 #define MBOX_UP_CGX_MESSAGES \
288 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
289
290 enum {
291 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
292 MBOX_MESSAGES
293 MBOX_UP_CGX_MESSAGES
294 #undef M
295 };
296
297 /* Mailbox message formats */
298
299 #define RVU_DEFAULT_PF_FUNC 0xFFFF
300
301 /* Generic request msg used for those mbox messages which
302 * don't send any data in the request.
303 */
304 struct msg_req {
305 struct mbox_msghdr hdr;
306 };
307
308 /* Generic response msg used an ack or response for those mbox
309 * messages which don't have a specific rsp msg format.
310 */
311 struct msg_rsp {
312 struct mbox_msghdr hdr;
313 };
314
315 /* RVU mailbox error codes
316 * Range 256 - 300.
317 */
318 enum rvu_af_status {
319 RVU_INVALID_VF_ID = -256,
320 };
321
322 struct ready_msg_rsp {
323 struct mbox_msghdr hdr;
324 u16 sclk_freq; /* SCLK frequency (in MHz) */
325 u16 rclk_freq; /* RCLK frequency (in MHz) */
326 };
327
328 /* Structure for requesting resource provisioning.
329 * 'modify' flag to be used when either requesting more
330 * or to detach partial of a certain resource type.
331 * Rest of the fields specify how many of what type to
332 * be attached.
333 * To request LFs from two blocks of same type this mailbox
334 * can be sent twice as below:
335 * struct rsrc_attach *attach;
336 * .. Allocate memory for message ..
337 * attach->cptlfs = 3; <3 LFs from CPT0>
338 * .. Send message ..
339 * .. Allocate memory for message ..
340 * attach->modify = 1;
341 * attach->cpt_blkaddr = BLKADDR_CPT1;
342 * attach->cptlfs = 2; <2 LFs from CPT1>
343 * .. Send message ..
344 */
345 struct rsrc_attach {
346 struct mbox_msghdr hdr;
347 u8 modify:1;
348 u8 npalf:1;
349 u8 nixlf:1;
350 u16 sso;
351 u16 ssow;
352 u16 timlfs;
353 u16 cptlfs;
354 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
355 };
356
357 /* Structure for relinquishing resources.
358 * 'partial' flag to be used when relinquishing all resources
359 * but only of a certain type. If not set, all resources of all
360 * types provisioned to the RVU function will be detached.
361 */
362 struct rsrc_detach {
363 struct mbox_msghdr hdr;
364 u8 partial:1;
365 u8 npalf:1;
366 u8 nixlf:1;
367 u8 sso:1;
368 u8 ssow:1;
369 u8 timlfs:1;
370 u8 cptlfs:1;
371 };
372
373 /* Number of resources available to the caller.
374 * In reply to MBOX_MSG_FREE_RSRC_CNT.
375 */
376 struct free_rsrcs_rsp {
377 struct mbox_msghdr hdr;
378 u16 schq[NIX_TXSCH_LVL_CNT];
379 u16 sso;
380 u16 tim;
381 u16 ssow;
382 u16 cpt;
383 u8 npa;
384 u8 nix;
385 u16 schq_nix1[NIX_TXSCH_LVL_CNT];
386 u8 nix1;
387 u8 cpt1;
388 u8 ree0;
389 u8 ree1;
390 };
391
392 #define MSIX_VECTOR_INVALID 0xFFFF
393 #define MAX_RVU_BLKLF_CNT 256
394
395 struct msix_offset_rsp {
396 struct mbox_msghdr hdr;
397 u16 npa_msixoff;
398 u16 nix_msixoff;
399 u16 sso;
400 u16 ssow;
401 u16 timlfs;
402 u16 cptlfs;
403 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
404 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
405 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
406 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
407 u16 cpt1_lfs;
408 u16 ree0_lfs;
409 u16 ree1_lfs;
410 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
411 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
412 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
413 };
414
415 struct get_hw_cap_rsp {
416 struct mbox_msghdr hdr;
417 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
418 u8 nix_shaping; /* Is shaping and coloring supported */
419 };
420
421 /* CGX mbox message formats */
422
423 struct cgx_stats_rsp {
424 struct mbox_msghdr hdr;
425 #define CGX_RX_STATS_COUNT 9
426 #define CGX_TX_STATS_COUNT 18
427 u64 rx_stats[CGX_RX_STATS_COUNT];
428 u64 tx_stats[CGX_TX_STATS_COUNT];
429 };
430
431 struct cgx_fec_stats_rsp {
432 struct mbox_msghdr hdr;
433 u64 fec_corr_blks;
434 u64 fec_uncorr_blks;
435 };
436 /* Structure for requesting the operation for
437 * setting/getting mac address in the CGX interface
438 */
439 struct cgx_mac_addr_set_or_get {
440 struct mbox_msghdr hdr;
441 u8 mac_addr[ETH_ALEN];
442 };
443
444 /* Structure for requesting the operation to
445 * add DMAC filter entry into CGX interface
446 */
447 struct cgx_mac_addr_add_req {
448 struct mbox_msghdr hdr;
449 u8 mac_addr[ETH_ALEN];
450 };
451
452 /* Structure for response against the operation to
453 * add DMAC filter entry into CGX interface
454 */
455 struct cgx_mac_addr_add_rsp {
456 struct mbox_msghdr hdr;
457 u8 index;
458 };
459
460 /* Structure for requesting the operation to
461 * delete DMAC filter entry from CGX interface
462 */
463 struct cgx_mac_addr_del_req {
464 struct mbox_msghdr hdr;
465 u8 index;
466 };
467
468 /* Structure for response against the operation to
469 * get maximum supported DMAC filter entries
470 */
471 struct cgx_max_dmac_entries_get_rsp {
472 struct mbox_msghdr hdr;
473 u8 max_dmac_filters;
474 };
475
476 struct cgx_link_user_info {
477 uint64_t link_up:1;
478 uint64_t full_duplex:1;
479 uint64_t lmac_type_id:4;
480 uint64_t speed:20; /* speed in Mbps */
481 uint64_t an:1; /* AN supported or not */
482 uint64_t fec:2; /* FEC type if enabled else 0 */
483 #define LMACTYPE_STR_LEN 16
484 char lmac_type[LMACTYPE_STR_LEN];
485 };
486
487 struct cgx_link_info_msg {
488 struct mbox_msghdr hdr;
489 struct cgx_link_user_info link_info;
490 };
491
492 struct cgx_pause_frm_cfg {
493 struct mbox_msghdr hdr;
494 u8 set;
495 /* set = 1 if the request is to config pause frames */
496 /* set = 0 if the request is to fetch pause frames config */
497 u8 rx_pause;
498 u8 tx_pause;
499 };
500
501 enum fec_type {
502 OTX2_FEC_NONE,
503 OTX2_FEC_BASER,
504 OTX2_FEC_RS,
505 OTX2_FEC_STATS_CNT = 2,
506 OTX2_FEC_OFF,
507 };
508
509 struct fec_mode {
510 struct mbox_msghdr hdr;
511 int fec;
512 };
513
514 struct sfp_eeprom_s {
515 #define SFP_EEPROM_SIZE 256
516 u16 sff_id;
517 u8 buf[SFP_EEPROM_SIZE];
518 u64 reserved;
519 };
520
521 struct phy_s {
522 struct {
523 u64 can_change_mod_type:1;
524 u64 mod_type:1;
525 u64 has_fec_stats:1;
526 } misc;
527 struct fec_stats_s {
528 u32 rsfec_corr_cws;
529 u32 rsfec_uncorr_cws;
530 u32 brfec_corr_blks;
531 u32 brfec_uncorr_blks;
532 } fec_stats;
533 };
534
535 struct cgx_lmac_fwdata_s {
536 u16 rw_valid;
537 u64 supported_fec;
538 u64 supported_an;
539 u64 supported_link_modes;
540 /* only applicable if AN is supported */
541 u64 advertised_fec;
542 u64 advertised_link_modes;
543 /* Only applicable if SFP/QSFP slot is present */
544 struct sfp_eeprom_s sfp_eeprom;
545 struct phy_s phy;
546 #define LMAC_FWDATA_RESERVED_MEM 1021
547 u64 reserved[LMAC_FWDATA_RESERVED_MEM];
548 };
549
550 struct cgx_fw_data {
551 struct mbox_msghdr hdr;
552 struct cgx_lmac_fwdata_s fwdata;
553 };
554
555 struct cgx_set_link_mode_args {
556 u32 speed;
557 u8 duplex;
558 u8 an;
559 u8 ports;
560 u64 mode;
561 };
562
563 struct cgx_set_link_mode_req {
564 #define AUTONEG_UNKNOWN 0xff
565 struct mbox_msghdr hdr;
566 struct cgx_set_link_mode_args args;
567 };
568
569 struct cgx_set_link_mode_rsp {
570 struct mbox_msghdr hdr;
571 int status;
572 };
573
574 struct cgx_mac_addr_update_req {
575 struct mbox_msghdr hdr;
576 u8 mac_addr[ETH_ALEN];
577 u8 index;
578 };
579
580 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */
581 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1)
582 /* flow control from physical link higig2 messages */
583 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */
584 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */
585 #define RVU_MAC_VERSION BIT_ULL(4)
586 #define RVU_MAC_CGX BIT_ULL(5)
587 #define RVU_MAC_RPM BIT_ULL(6)
588
589 struct cgx_features_info_msg {
590 struct mbox_msghdr hdr;
591 u64 lmac_features;
592 };
593
594 struct rpm_stats_rsp {
595 struct mbox_msghdr hdr;
596 #define RPM_RX_STATS_COUNT 43
597 #define RPM_TX_STATS_COUNT 34
598 u64 rx_stats[RPM_RX_STATS_COUNT];
599 u64 tx_stats[RPM_TX_STATS_COUNT];
600 };
601
602 struct npc_set_pkind {
603 struct mbox_msghdr hdr;
604 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
605 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
606 u64 mode;
607 #define PKIND_TX BIT_ULL(0)
608 #define PKIND_RX BIT_ULL(1)
609 u8 dir;
610 u8 pkind; /* valid only in case custom flag */
611 u8 var_len_off; /* Offset of custom header length field.
612 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
613 */
614 u8 var_len_off_mask; /* Mask for length with in offset */
615 u8 shift_dir; /* shift direction to get length of the header at var_len_off */
616 };
617
618 /* NPA mbox message formats */
619
620 /* NPA mailbox error codes
621 * Range 301 - 400.
622 */
623 enum npa_af_status {
624 NPA_AF_ERR_PARAM = -301,
625 NPA_AF_ERR_AQ_FULL = -302,
626 NPA_AF_ERR_AQ_ENQUEUE = -303,
627 NPA_AF_ERR_AF_LF_INVALID = -304,
628 NPA_AF_ERR_AF_LF_ALLOC = -305,
629 NPA_AF_ERR_LF_RESET = -306,
630 };
631
632 /* For NPA LF context alloc and init */
633 struct npa_lf_alloc_req {
634 struct mbox_msghdr hdr;
635 int node;
636 int aura_sz; /* No of auras */
637 u32 nr_pools; /* No of pools */
638 u64 way_mask;
639 };
640
641 struct npa_lf_alloc_rsp {
642 struct mbox_msghdr hdr;
643 u32 stack_pg_ptrs; /* No of ptrs per stack page */
644 u32 stack_pg_bytes; /* Size of stack page */
645 u16 qints; /* NPA_AF_CONST::QINTS */
646 u8 cache_lines; /*BATCH ALLOC DMA */
647 };
648
649 /* NPA AQ enqueue msg */
650 struct npa_aq_enq_req {
651 struct mbox_msghdr hdr;
652 u32 aura_id;
653 u8 ctype;
654 u8 op;
655 union {
656 /* Valid when op == WRITE/INIT and ctype == AURA.
657 * LF fills the pool_id in aura.pool_addr. AF will translate
658 * the pool_id to pool context pointer.
659 */
660 struct npa_aura_s aura;
661 /* Valid when op == WRITE/INIT and ctype == POOL */
662 struct npa_pool_s pool;
663 };
664 /* Mask data when op == WRITE (1=write, 0=don't write) */
665 union {
666 /* Valid when op == WRITE and ctype == AURA */
667 struct npa_aura_s aura_mask;
668 /* Valid when op == WRITE and ctype == POOL */
669 struct npa_pool_s pool_mask;
670 };
671 };
672
673 struct npa_aq_enq_rsp {
674 struct mbox_msghdr hdr;
675 union {
676 /* Valid when op == READ and ctype == AURA */
677 struct npa_aura_s aura;
678 /* Valid when op == READ and ctype == POOL */
679 struct npa_pool_s pool;
680 };
681 };
682
683 /* Disable all contexts of type 'ctype' */
684 struct hwctx_disable_req {
685 struct mbox_msghdr hdr;
686 u8 ctype;
687 };
688
689 /* NIX mbox message formats */
690
691 /* NIX mailbox error codes
692 * Range 401 - 500.
693 */
694 enum nix_af_status {
695 NIX_AF_ERR_PARAM = -401,
696 NIX_AF_ERR_AQ_FULL = -402,
697 NIX_AF_ERR_AQ_ENQUEUE = -403,
698 NIX_AF_ERR_AF_LF_INVALID = -404,
699 NIX_AF_ERR_AF_LF_ALLOC = -405,
700 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
701 NIX_AF_ERR_TLX_INVALID = -407,
702 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
703 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
704 NIX_AF_ERR_FRS_INVALID = -410,
705 NIX_AF_ERR_RX_LINK_INVALID = -411,
706 NIX_AF_INVAL_TXSCHQ_CFG = -412,
707 NIX_AF_SMQ_FLUSH_FAILED = -413,
708 NIX_AF_ERR_LF_RESET = -414,
709 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
710 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
711 NIX_AF_ERR_MARK_CFG_FAIL = -417,
712 NIX_AF_ERR_LSO_CFG_FAIL = -418,
713 NIX_AF_INVAL_NPA_PF_FUNC = -419,
714 NIX_AF_INVAL_SSO_PF_FUNC = -420,
715 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
716 NIX_AF_ERR_RX_VTAG_INUSE = -422,
717 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
718 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
719 NIX_AF_ERR_INVALID_NIXBLK = -425,
720 NIX_AF_ERR_INVALID_BANDPROF = -426,
721 NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
722 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428,
723 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429,
724 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430,
725 NIX_AF_ERR_LINK_CREDITS = -431,
726 };
727
728 /* For NIX RX vtag action */
729 enum nix_rx_vtag0_type {
730 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
731 NIX_AF_LFX_RX_VTAG_TYPE1,
732 NIX_AF_LFX_RX_VTAG_TYPE2,
733 NIX_AF_LFX_RX_VTAG_TYPE3,
734 NIX_AF_LFX_RX_VTAG_TYPE4,
735 NIX_AF_LFX_RX_VTAG_TYPE5,
736 NIX_AF_LFX_RX_VTAG_TYPE6,
737 NIX_AF_LFX_RX_VTAG_TYPE7,
738 };
739
740 /* For NIX LF context alloc and init */
741 struct nix_lf_alloc_req {
742 struct mbox_msghdr hdr;
743 int node;
744 u32 rq_cnt; /* No of receive queues */
745 u32 sq_cnt; /* No of send queues */
746 u32 cq_cnt; /* No of completion queues */
747 u8 xqe_sz;
748 u16 rss_sz;
749 u8 rss_grps;
750 u16 npa_func;
751 u16 sso_func;
752 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
753 u64 way_mask;
754 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
755 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
756 u64 flags;
757 };
758
759 struct nix_lf_alloc_rsp {
760 struct mbox_msghdr hdr;
761 u16 sqb_size;
762 u16 rx_chan_base;
763 u16 tx_chan_base;
764 u8 rx_chan_cnt; /* total number of RX channels */
765 u8 tx_chan_cnt; /* total number of TX channels */
766 u8 lso_tsov4_idx;
767 u8 lso_tsov6_idx;
768 u8 mac_addr[ETH_ALEN];
769 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
770 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
771 u16 cints; /* NIX_AF_CONST2::CINTS */
772 u16 qints; /* NIX_AF_CONST2::QINTS */
773 u8 cgx_links; /* No. of CGX links present in HW */
774 u8 lbk_links; /* No. of LBK links present in HW */
775 u8 sdp_links; /* No. of SDP links present in HW */
776 u8 tx_link; /* Transmit channel link number */
777 };
778
779 struct nix_lf_free_req {
780 struct mbox_msghdr hdr;
781 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
782 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
783 u64 flags;
784 };
785
786 /* CN10K NIX AQ enqueue msg */
787 struct nix_cn10k_aq_enq_req {
788 struct mbox_msghdr hdr;
789 u32 qidx;
790 u8 ctype;
791 u8 op;
792 union {
793 struct nix_cn10k_rq_ctx_s rq;
794 struct nix_cn10k_sq_ctx_s sq;
795 struct nix_cq_ctx_s cq;
796 struct nix_rsse_s rss;
797 struct nix_rx_mce_s mce;
798 struct nix_bandprof_s prof;
799 };
800 union {
801 struct nix_cn10k_rq_ctx_s rq_mask;
802 struct nix_cn10k_sq_ctx_s sq_mask;
803 struct nix_cq_ctx_s cq_mask;
804 struct nix_rsse_s rss_mask;
805 struct nix_rx_mce_s mce_mask;
806 struct nix_bandprof_s prof_mask;
807 };
808 };
809
810 struct nix_cn10k_aq_enq_rsp {
811 struct mbox_msghdr hdr;
812 union {
813 struct nix_cn10k_rq_ctx_s rq;
814 struct nix_cn10k_sq_ctx_s sq;
815 struct nix_cq_ctx_s cq;
816 struct nix_rsse_s rss;
817 struct nix_rx_mce_s mce;
818 struct nix_bandprof_s prof;
819 };
820 };
821
822 /* NIX AQ enqueue msg */
823 struct nix_aq_enq_req {
824 struct mbox_msghdr hdr;
825 u32 qidx;
826 u8 ctype;
827 u8 op;
828 union {
829 struct nix_rq_ctx_s rq;
830 struct nix_sq_ctx_s sq;
831 struct nix_cq_ctx_s cq;
832 struct nix_rsse_s rss;
833 struct nix_rx_mce_s mce;
834 u64 prof;
835 };
836 union {
837 struct nix_rq_ctx_s rq_mask;
838 struct nix_sq_ctx_s sq_mask;
839 struct nix_cq_ctx_s cq_mask;
840 struct nix_rsse_s rss_mask;
841 struct nix_rx_mce_s mce_mask;
842 u64 prof_mask;
843 };
844 };
845
846 struct nix_aq_enq_rsp {
847 struct mbox_msghdr hdr;
848 union {
849 struct nix_rq_ctx_s rq;
850 struct nix_sq_ctx_s sq;
851 struct nix_cq_ctx_s cq;
852 struct nix_rsse_s rss;
853 struct nix_rx_mce_s mce;
854 struct nix_bandprof_s prof;
855 };
856 };
857
858 /* Tx scheduler/shaper mailbox messages */
859
860 #define MAX_TXSCHQ_PER_FUNC 128
861
862 struct nix_txsch_alloc_req {
863 struct mbox_msghdr hdr;
864 /* Scheduler queue count request at each level */
865 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
866 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
867 };
868
869 struct nix_txsch_alloc_rsp {
870 struct mbox_msghdr hdr;
871 /* Scheduler queue count allocated at each level */
872 u16 schq_contig[NIX_TXSCH_LVL_CNT];
873 u16 schq[NIX_TXSCH_LVL_CNT];
874 /* Scheduler queue list allocated at each level */
875 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
876 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
877 u8 aggr_level; /* Traffic aggregation scheduler level */
878 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
879 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
880 };
881
882 struct nix_txsch_free_req {
883 struct mbox_msghdr hdr;
884 #define TXSCHQ_FREE_ALL BIT_ULL(0)
885 u16 flags;
886 /* Scheduler queue level to be freed */
887 u16 schq_lvl;
888 /* List of scheduler queues to be freed */
889 u16 schq;
890 };
891
892 struct nix_txschq_config {
893 struct mbox_msghdr hdr;
894 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
895 u8 read;
896 #define TXSCHQ_IDX_SHIFT 16
897 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
898 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
899 u8 num_regs;
900 #define MAX_REGS_PER_MBOX_MSG 20
901 u64 reg[MAX_REGS_PER_MBOX_MSG];
902 u64 regval[MAX_REGS_PER_MBOX_MSG];
903 /* All 0's => overwrite with new value */
904 u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
905 };
906
907 struct nix_vtag_config {
908 struct mbox_msghdr hdr;
909 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
910 u8 vtag_size;
911 /* cfg_type is '0' for tx vlan cfg
912 * cfg_type is '1' for rx vlan cfg
913 */
914 u8 cfg_type;
915 union {
916 /* valid when cfg_type is '0' */
917 struct {
918 u64 vtag0;
919 u64 vtag1;
920
921 /* cfg_vtag0 & cfg_vtag1 fields are valid
922 * when free_vtag0 & free_vtag1 are '0's.
923 */
924 /* cfg_vtag0 = 1 to configure vtag0 */
925 u8 cfg_vtag0 :1;
926 /* cfg_vtag1 = 1 to configure vtag1 */
927 u8 cfg_vtag1 :1;
928
929 /* vtag0_idx & vtag1_idx are only valid when
930 * both cfg_vtag0 & cfg_vtag1 are '0's,
931 * these fields are used along with free_vtag0
932 * & free_vtag1 to free the nix lf's tx_vlan
933 * configuration.
934 *
935 * Denotes the indices of tx_vtag def registers
936 * that needs to be cleared and freed.
937 */
938 int vtag0_idx;
939 int vtag1_idx;
940
941 /* free_vtag0 & free_vtag1 fields are valid
942 * when cfg_vtag0 & cfg_vtag1 are '0's.
943 */
944 /* free_vtag0 = 1 clears vtag0 configuration
945 * vtag0_idx denotes the index to be cleared.
946 */
947 u8 free_vtag0 :1;
948 /* free_vtag1 = 1 clears vtag1 configuration
949 * vtag1_idx denotes the index to be cleared.
950 */
951 u8 free_vtag1 :1;
952 } tx;
953
954 /* valid when cfg_type is '1' */
955 struct {
956 /* rx vtag type index, valid values are in 0..7 range */
957 u8 vtag_type;
958 /* rx vtag strip */
959 u8 strip_vtag :1;
960 /* rx vtag capture */
961 u8 capture_vtag :1;
962 } rx;
963 };
964 };
965
966 struct nix_vtag_config_rsp {
967 struct mbox_msghdr hdr;
968 int vtag0_idx;
969 int vtag1_idx;
970 /* Indices of tx_vtag def registers used to configure
971 * tx vtag0 & vtag1 headers, these indices are valid
972 * when nix_vtag_config mbox requested for vtag0 and/
973 * or vtag1 configuration.
974 */
975 };
976
977 struct nix_rss_flowkey_cfg {
978 struct mbox_msghdr hdr;
979 int mcam_index; /* MCAM entry index to modify */
980 #define NIX_FLOW_KEY_TYPE_PORT BIT(0)
981 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
982 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
983 #define NIX_FLOW_KEY_TYPE_TCP BIT(3)
984 #define NIX_FLOW_KEY_TYPE_UDP BIT(4)
985 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
986 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
987 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
988 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
989 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
990 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
991 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
992 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
993 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
994 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
995 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
996 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
997 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
998 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20)
999 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21)
1000 #define NIX_FLOW_KEY_TYPE_AH BIT(22)
1001 #define NIX_FLOW_KEY_TYPE_ESP BIT(23)
1002 u32 flowkey_cfg; /* Flowkey types selected */
1003 u8 group; /* RSS context or group */
1004 };
1005
1006 struct nix_rss_flowkey_cfg_rsp {
1007 struct mbox_msghdr hdr;
1008 u8 alg_idx; /* Selected algo index */
1009 };
1010
1011 struct nix_set_mac_addr {
1012 struct mbox_msghdr hdr;
1013 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1014 };
1015
1016 struct nix_get_mac_addr_rsp {
1017 struct mbox_msghdr hdr;
1018 u8 mac_addr[ETH_ALEN];
1019 };
1020
1021 struct nix_mark_format_cfg {
1022 struct mbox_msghdr hdr;
1023 u8 offset;
1024 u8 y_mask;
1025 u8 y_val;
1026 u8 r_mask;
1027 u8 r_val;
1028 };
1029
1030 struct nix_mark_format_cfg_rsp {
1031 struct mbox_msghdr hdr;
1032 u8 mark_format_idx;
1033 };
1034
1035 struct nix_rx_mode {
1036 struct mbox_msghdr hdr;
1037 #define NIX_RX_MODE_UCAST BIT(0)
1038 #define NIX_RX_MODE_PROMISC BIT(1)
1039 #define NIX_RX_MODE_ALLMULTI BIT(2)
1040 #define NIX_RX_MODE_USE_MCE BIT(3)
1041 u16 mode;
1042 };
1043
1044 struct nix_rx_cfg {
1045 struct mbox_msghdr hdr;
1046 #define NIX_RX_OL3_VERIFY BIT(0)
1047 #define NIX_RX_OL4_VERIFY BIT(1)
1048 u8 len_verify; /* Outer L3/L4 len check */
1049 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1050 u8 csum_verify; /* Outer L4 checksum verification */
1051 };
1052
1053 struct nix_frs_cfg {
1054 struct mbox_msghdr hdr;
1055 u8 update_smq; /* Update SMQ's min/max lens */
1056 u8 update_minlen; /* Set minlen also */
1057 u8 sdp_link; /* Set SDP RX link */
1058 u16 maxlen;
1059 u16 minlen;
1060 };
1061
1062 struct nix_lso_format_cfg {
1063 struct mbox_msghdr hdr;
1064 u64 field_mask;
1065 #define NIX_LSO_FIELD_MAX 8
1066 u64 fields[NIX_LSO_FIELD_MAX];
1067 };
1068
1069 struct nix_lso_format_cfg_rsp {
1070 struct mbox_msghdr hdr;
1071 u8 lso_format_idx;
1072 };
1073
1074 struct nix_bp_cfg_req {
1075 struct mbox_msghdr hdr;
1076 u16 chan_base; /* Starting channel number */
1077 u8 chan_cnt; /* Number of channels */
1078 u8 bpid_per_chan;
1079 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1080 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1081 };
1082
1083 /* PF can be mapped to either CGX or LBK interface,
1084 * so maximum 64 channels are possible.
1085 */
1086 #define NIX_MAX_BPID_CHAN 64
1087 struct nix_bp_cfg_rsp {
1088 struct mbox_msghdr hdr;
1089 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1090 u8 chan_cnt; /* Number of channel for which bpids are assigned */
1091 };
1092
1093 struct nix_hw_info {
1094 struct mbox_msghdr hdr;
1095 u16 rsvs16;
1096 u16 max_mtu;
1097 u16 min_mtu;
1098 u32 rpm_dwrr_mtu;
1099 u32 sdp_dwrr_mtu;
1100 u64 rsvd[16]; /* Add reserved fields for future expansion */
1101 };
1102
1103 struct nix_bandprof_alloc_req {
1104 struct mbox_msghdr hdr;
1105 /* Count of profiles needed per layer */
1106 u16 prof_count[BAND_PROF_NUM_LAYERS];
1107 };
1108
1109 struct nix_bandprof_alloc_rsp {
1110 struct mbox_msghdr hdr;
1111 u16 prof_count[BAND_PROF_NUM_LAYERS];
1112
1113 /* There is no need to allocate morethan 1 bandwidth profile
1114 * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1115 * profiles to 64 per PF_FUNC.
1116 */
1117 #define MAX_BANDPROF_PER_PFFUNC 64
1118 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1119 };
1120
1121 struct nix_bandprof_free_req {
1122 struct mbox_msghdr hdr;
1123 u8 free_all;
1124 u16 prof_count[BAND_PROF_NUM_LAYERS];
1125 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1126 };
1127
1128 struct nix_bandprof_get_hwinfo_rsp {
1129 struct mbox_msghdr hdr;
1130 u16 prof_count[BAND_PROF_NUM_LAYERS];
1131 u32 policer_timeunit;
1132 };
1133
1134 /* NPC mbox message structs */
1135
1136 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1137 #define NPC_MCAM_INVALID_MAP 0xFFFF
1138
1139 /* NPC mailbox error codes
1140 * Range 701 - 800.
1141 */
1142 enum npc_af_status {
1143 NPC_MCAM_INVALID_REQ = -701,
1144 NPC_MCAM_ALLOC_DENIED = -702,
1145 NPC_MCAM_ALLOC_FAILED = -703,
1146 NPC_MCAM_PERM_DENIED = -704,
1147 NPC_FLOW_INTF_INVALID = -707,
1148 NPC_FLOW_CHAN_INVALID = -708,
1149 NPC_FLOW_NO_NIXLF = -709,
1150 NPC_FLOW_NOT_SUPPORTED = -710,
1151 NPC_FLOW_VF_PERM_DENIED = -711,
1152 NPC_FLOW_VF_NOT_INIT = -712,
1153 NPC_FLOW_VF_OVERLAP = -713,
1154 };
1155
1156 struct npc_mcam_alloc_entry_req {
1157 struct mbox_msghdr hdr;
1158 #define NPC_MAX_NONCONTIG_ENTRIES 256
1159 u8 contig; /* Contiguous entries ? */
1160 #define NPC_MCAM_ANY_PRIO 0
1161 #define NPC_MCAM_LOWER_PRIO 1
1162 #define NPC_MCAM_HIGHER_PRIO 2
1163 u8 priority; /* Lower or higher w.r.t ref_entry */
1164 u16 ref_entry;
1165 u16 count; /* Number of entries requested */
1166 };
1167
1168 struct npc_mcam_alloc_entry_rsp {
1169 struct mbox_msghdr hdr;
1170 u16 entry; /* Entry allocated or start index if contiguous.
1171 * Invalid incase of non-contiguous.
1172 */
1173 u16 count; /* Number of entries allocated */
1174 u16 free_count; /* Number of entries available */
1175 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1176 };
1177
1178 struct npc_mcam_free_entry_req {
1179 struct mbox_msghdr hdr;
1180 u16 entry; /* Entry index to be freed */
1181 u8 all; /* If all entries allocated to this PFVF to be freed */
1182 };
1183
1184 struct mcam_entry {
1185 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
1186 u64 kw[NPC_MAX_KWS_IN_KEY];
1187 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
1188 u64 action;
1189 u64 vtag_action;
1190 };
1191
1192 struct npc_mcam_write_entry_req {
1193 struct mbox_msghdr hdr;
1194 struct mcam_entry entry_data;
1195 u16 entry; /* MCAM entry to write this match key */
1196 u16 cntr; /* Counter for this MCAM entry */
1197 u8 intf; /* Rx or Tx interface */
1198 u8 enable_entry;/* Enable this MCAM entry ? */
1199 u8 set_cntr; /* Set counter for this entry ? */
1200 };
1201
1202 /* Enable/Disable a given entry */
1203 struct npc_mcam_ena_dis_entry_req {
1204 struct mbox_msghdr hdr;
1205 u16 entry;
1206 };
1207
1208 struct npc_mcam_shift_entry_req {
1209 struct mbox_msghdr hdr;
1210 #define NPC_MCAM_MAX_SHIFTS 64
1211 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1212 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1213 u16 shift_count; /* Number of entries to shift */
1214 };
1215
1216 struct npc_mcam_shift_entry_rsp {
1217 struct mbox_msghdr hdr;
1218 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1219 };
1220
1221 struct npc_mcam_alloc_counter_req {
1222 struct mbox_msghdr hdr;
1223 u8 contig; /* Contiguous counters ? */
1224 #define NPC_MAX_NONCONTIG_COUNTERS 64
1225 u16 count; /* Number of counters requested */
1226 };
1227
1228 struct npc_mcam_alloc_counter_rsp {
1229 struct mbox_msghdr hdr;
1230 u16 cntr; /* Counter allocated or start index if contiguous.
1231 * Invalid incase of non-contiguous.
1232 */
1233 u16 count; /* Number of counters allocated */
1234 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1235 };
1236
1237 struct npc_mcam_oper_counter_req {
1238 struct mbox_msghdr hdr;
1239 u16 cntr; /* Free a counter or clear/fetch it's stats */
1240 };
1241
1242 struct npc_mcam_oper_counter_rsp {
1243 struct mbox_msghdr hdr;
1244 u64 stat; /* valid only while fetching counter's stats */
1245 };
1246
1247 struct npc_mcam_unmap_counter_req {
1248 struct mbox_msghdr hdr;
1249 u16 cntr;
1250 u16 entry; /* Entry and counter to be unmapped */
1251 u8 all; /* Unmap all entries using this counter ? */
1252 };
1253
1254 struct npc_mcam_alloc_and_write_entry_req {
1255 struct mbox_msghdr hdr;
1256 struct mcam_entry entry_data;
1257 u16 ref_entry;
1258 u8 priority; /* Lower or higher w.r.t ref_entry */
1259 u8 intf; /* Rx or Tx interface */
1260 u8 enable_entry;/* Enable this MCAM entry ? */
1261 u8 alloc_cntr; /* Allocate counter and map ? */
1262 };
1263
1264 struct npc_mcam_alloc_and_write_entry_rsp {
1265 struct mbox_msghdr hdr;
1266 u16 entry;
1267 u16 cntr;
1268 };
1269
1270 struct npc_get_kex_cfg_rsp {
1271 struct mbox_msghdr hdr;
1272 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1273 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1274 #define NPC_MAX_INTF 2
1275 #define NPC_MAX_LID 8
1276 #define NPC_MAX_LT 16
1277 #define NPC_MAX_LD 2
1278 #define NPC_MAX_LFL 16
1279 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1280 u64 kex_ld_flags[NPC_MAX_LD];
1281 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1282 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1283 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1284 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1285 #define MKEX_NAME_LEN 128
1286 u8 mkex_pfl_name[MKEX_NAME_LEN];
1287 };
1288
1289 struct flow_msg {
1290 unsigned char dmac[6];
1291 unsigned char smac[6];
1292 __be16 etype;
1293 __be16 vlan_etype;
1294 __be16 vlan_tci;
1295 union {
1296 __be32 ip4src;
1297 __be32 ip6src[4];
1298 };
1299 union {
1300 __be32 ip4dst;
1301 __be32 ip6dst[4];
1302 };
1303 u8 tos;
1304 u8 ip_ver;
1305 u8 ip_proto;
1306 u8 tc;
1307 __be16 sport;
1308 __be16 dport;
1309 };
1310
1311 struct npc_install_flow_req {
1312 struct mbox_msghdr hdr;
1313 struct flow_msg packet;
1314 struct flow_msg mask;
1315 u64 features;
1316 u16 entry;
1317 u16 channel;
1318 u16 chan_mask;
1319 u8 intf;
1320 u8 set_cntr; /* If counter is available set counter for this entry ? */
1321 u8 default_rule;
1322 u8 append; /* overwrite(0) or append(1) flow to default rule? */
1323 u16 vf;
1324 /* action */
1325 u32 index;
1326 u16 match_id;
1327 u8 flow_key_alg;
1328 u8 op;
1329 /* vtag rx action */
1330 u8 vtag0_type;
1331 u8 vtag0_valid;
1332 u8 vtag1_type;
1333 u8 vtag1_valid;
1334 /* vtag tx action */
1335 u16 vtag0_def;
1336 u8 vtag0_op;
1337 u16 vtag1_def;
1338 u8 vtag1_op;
1339 };
1340
1341 struct npc_install_flow_rsp {
1342 struct mbox_msghdr hdr;
1343 int counter; /* negative if no counter else counter number */
1344 };
1345
1346 struct npc_delete_flow_req {
1347 struct mbox_msghdr hdr;
1348 u16 entry;
1349 u16 start;/*Disable range of entries */
1350 u16 end;
1351 u8 all; /* PF + VFs */
1352 };
1353
1354 struct npc_mcam_read_entry_req {
1355 struct mbox_msghdr hdr;
1356 u16 entry; /* MCAM entry to read */
1357 };
1358
1359 struct npc_mcam_read_entry_rsp {
1360 struct mbox_msghdr hdr;
1361 struct mcam_entry entry_data;
1362 u8 intf;
1363 u8 enable;
1364 };
1365
1366 struct npc_mcam_read_base_rule_rsp {
1367 struct mbox_msghdr hdr;
1368 struct mcam_entry entry;
1369 };
1370
1371 struct npc_mcam_get_stats_req {
1372 struct mbox_msghdr hdr;
1373 u16 entry; /* mcam entry */
1374 };
1375
1376 struct npc_mcam_get_stats_rsp {
1377 struct mbox_msghdr hdr;
1378 u64 stat; /* counter stats */
1379 u8 stat_ena; /* enabled */
1380 };
1381
1382 enum ptp_op {
1383 PTP_OP_ADJFINE = 0,
1384 PTP_OP_GET_CLOCK = 1,
1385 };
1386
1387 struct ptp_req {
1388 struct mbox_msghdr hdr;
1389 u8 op;
1390 s64 scaled_ppm;
1391 };
1392
1393 struct ptp_rsp {
1394 struct mbox_msghdr hdr;
1395 u64 clk;
1396 };
1397
1398 struct set_vf_perm {
1399 struct mbox_msghdr hdr;
1400 u16 vf;
1401 #define RESET_VF_PERM BIT_ULL(0)
1402 #define VF_TRUSTED BIT_ULL(1)
1403 u64 flags;
1404 };
1405
1406 struct lmtst_tbl_setup_req {
1407 struct mbox_msghdr hdr;
1408 u64 dis_sched_early_comp :1;
1409 u64 sch_ena :1;
1410 u64 dis_line_pref :1;
1411 u64 ssow_pf_func :13;
1412 u16 base_pcifunc;
1413 u8 use_local_lmt_region;
1414 u64 lmt_iova;
1415 u64 rsvd[4];
1416 };
1417
1418 /* CPT mailbox error codes
1419 * Range 901 - 1000.
1420 */
1421 enum cpt_af_status {
1422 CPT_AF_ERR_PARAM = -901,
1423 CPT_AF_ERR_GRP_INVALID = -902,
1424 CPT_AF_ERR_LF_INVALID = -903,
1425 CPT_AF_ERR_ACCESS_DENIED = -904,
1426 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1427 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906
1428 };
1429
1430 /* CPT mbox message formats */
1431 struct cpt_rd_wr_reg_msg {
1432 struct mbox_msghdr hdr;
1433 u64 reg_offset;
1434 u64 *ret_val;
1435 u64 val;
1436 u8 is_write;
1437 int blkaddr;
1438 };
1439
1440 struct cpt_lf_alloc_req_msg {
1441 struct mbox_msghdr hdr;
1442 u16 nix_pf_func;
1443 u16 sso_pf_func;
1444 u16 eng_grpmsk;
1445 int blkaddr;
1446 };
1447
1448 /* Mailbox message request and response format for CPT stats. */
1449 struct cpt_sts_req {
1450 struct mbox_msghdr hdr;
1451 u8 blkaddr;
1452 };
1453
1454 struct cpt_sts_rsp {
1455 struct mbox_msghdr hdr;
1456 u64 inst_req_pc;
1457 u64 inst_lat_pc;
1458 u64 rd_req_pc;
1459 u64 rd_lat_pc;
1460 u64 rd_uc_pc;
1461 u64 active_cycles_pc;
1462 u64 ctx_mis_pc;
1463 u64 ctx_hit_pc;
1464 u64 ctx_aop_pc;
1465 u64 ctx_aop_lat_pc;
1466 u64 ctx_ifetch_pc;
1467 u64 ctx_ifetch_lat_pc;
1468 u64 ctx_ffetch_pc;
1469 u64 ctx_ffetch_lat_pc;
1470 u64 ctx_wback_pc;
1471 u64 ctx_wback_lat_pc;
1472 u64 ctx_psh_pc;
1473 u64 ctx_psh_lat_pc;
1474 u64 ctx_err;
1475 u64 ctx_enc_id;
1476 u64 ctx_flush_timer;
1477 u64 rxc_time;
1478 u64 rxc_time_cfg;
1479 u64 rxc_active_sts;
1480 u64 rxc_zombie_sts;
1481 u64 busy_sts_ae;
1482 u64 free_sts_ae;
1483 u64 busy_sts_se;
1484 u64 free_sts_se;
1485 u64 busy_sts_ie;
1486 u64 free_sts_ie;
1487 u64 exe_err_info;
1488 u64 cptclk_cnt;
1489 u64 diag;
1490 u64 rxc_dfrg;
1491 u64 x2p_link_cfg0;
1492 u64 x2p_link_cfg1;
1493 };
1494
1495 /* Mailbox message request format to configure reassembly timeout. */
1496 struct cpt_rxc_time_cfg_req {
1497 struct mbox_msghdr hdr;
1498 int blkaddr;
1499 u32 step;
1500 u16 zombie_thres;
1501 u16 zombie_limit;
1502 u16 active_thres;
1503 u16 active_limit;
1504 };
1505
1506 struct sdp_node_info {
1507 /* Node to which this PF belons to */
1508 u8 node_id;
1509 u8 max_vfs;
1510 u8 num_pf_rings;
1511 u8 pf_srn;
1512 #define SDP_MAX_VFS 128
1513 u8 vf_rings[SDP_MAX_VFS];
1514 };
1515
1516 struct sdp_chan_info_msg {
1517 struct mbox_msghdr hdr;
1518 struct sdp_node_info info;
1519 };
1520
1521 struct sdp_get_chan_info_msg {
1522 struct mbox_msghdr hdr;
1523 u16 chan_base;
1524 u16 num_chan;
1525 };
1526
1527 /* CGX mailbox error codes
1528 * Range 1101 - 1200.
1529 */
1530 enum cgx_af_status {
1531 LMAC_AF_ERR_INVALID_PARAM = -1101,
1532 LMAC_AF_ERR_PF_NOT_MAPPED = -1102,
1533 LMAC_AF_ERR_PERM_DENIED = -1103,
1534 };
1535
1536 #endif /* MBOX_H */
1537