1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #include "dpu_hwio.h"
6 #include "dpu_hw_catalog.h"
7 #include "dpu_hw_intf.h"
8 #include "dpu_kms.h"
9
10 #define INTF_TIMING_ENGINE_EN 0x000
11 #define INTF_CONFIG 0x004
12 #define INTF_HSYNC_CTL 0x008
13 #define INTF_VSYNC_PERIOD_F0 0x00C
14 #define INTF_VSYNC_PERIOD_F1 0x010
15 #define INTF_VSYNC_PULSE_WIDTH_F0 0x014
16 #define INTF_VSYNC_PULSE_WIDTH_F1 0x018
17 #define INTF_DISPLAY_V_START_F0 0x01C
18 #define INTF_DISPLAY_V_START_F1 0x020
19 #define INTF_DISPLAY_V_END_F0 0x024
20 #define INTF_DISPLAY_V_END_F1 0x028
21 #define INTF_ACTIVE_V_START_F0 0x02C
22 #define INTF_ACTIVE_V_START_F1 0x030
23 #define INTF_ACTIVE_V_END_F0 0x034
24 #define INTF_ACTIVE_V_END_F1 0x038
25 #define INTF_DISPLAY_HCTL 0x03C
26 #define INTF_ACTIVE_HCTL 0x040
27 #define INTF_BORDER_COLOR 0x044
28 #define INTF_UNDERFLOW_COLOR 0x048
29 #define INTF_HSYNC_SKEW 0x04C
30 #define INTF_POLARITY_CTL 0x050
31 #define INTF_TEST_CTL 0x054
32 #define INTF_TP_COLOR0 0x058
33 #define INTF_TP_COLOR1 0x05C
34 #define INTF_CONFIG2 0x060
35 #define INTF_DISPLAY_DATA_HCTL 0x064
36 #define INTF_FRAME_LINE_COUNT_EN 0x0A8
37 #define INTF_FRAME_COUNT 0x0AC
38 #define INTF_LINE_COUNT 0x0B0
39
40 #define INTF_DEFLICKER_CONFIG 0x0F0
41 #define INTF_DEFLICKER_STRNG_COEFF 0x0F4
42 #define INTF_DEFLICKER_WEAK_COEFF 0x0F8
43
44 #define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084
45 #define INTF_PANEL_FORMAT 0x090
46 #define INTF_TPG_ENABLE 0x100
47 #define INTF_TPG_MAIN_CONTROL 0x104
48 #define INTF_TPG_VIDEO_CONFIG 0x108
49 #define INTF_TPG_COMPONENT_LIMITS 0x10C
50 #define INTF_TPG_RECTANGLE 0x110
51 #define INTF_TPG_INITIAL_VALUE 0x114
52 #define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118
53 #define INTF_TPG_RGB_MAPPING 0x11C
54 #define INTF_PROG_FETCH_START 0x170
55 #define INTF_PROG_ROT_START 0x174
56 #define INTF_MUX 0x25C
57 #define INTF_STATUS 0x26C
58
_intf_offset(enum dpu_intf intf,const struct dpu_mdss_cfg * m,void __iomem * addr,struct dpu_hw_blk_reg_map * b)59 static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
60 const struct dpu_mdss_cfg *m,
61 void __iomem *addr,
62 struct dpu_hw_blk_reg_map *b)
63 {
64 int i;
65
66 for (i = 0; i < m->intf_count; i++) {
67 if ((intf == m->intf[i].id) &&
68 (m->intf[i].type != INTF_NONE)) {
69 b->base_off = addr;
70 b->blk_off = m->intf[i].base;
71 b->length = m->intf[i].len;
72 b->hwversion = m->hwversion;
73 b->log_mask = DPU_DBG_MASK_INTF;
74 return &m->intf[i];
75 }
76 }
77
78 return ERR_PTR(-EINVAL);
79 }
80
dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf * ctx,const struct intf_timing_params * p,const struct dpu_format * fmt)81 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
82 const struct intf_timing_params *p,
83 const struct dpu_format *fmt)
84 {
85 struct dpu_hw_blk_reg_map *c = &ctx->hw;
86 u32 hsync_period, vsync_period;
87 u32 display_v_start, display_v_end;
88 u32 hsync_start_x, hsync_end_x;
89 u32 active_h_start, active_h_end;
90 u32 active_v_start, active_v_end;
91 u32 active_hctl, display_hctl, hsync_ctl;
92 u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity;
93 u32 panel_format;
94 u32 intf_cfg, intf_cfg2 = 0, display_data_hctl = 0;
95
96 /* read interface_cfg */
97 intf_cfg = DPU_REG_READ(c, INTF_CONFIG);
98 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width +
99 p->h_front_porch;
100 vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height +
101 p->v_front_porch;
102
103 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) *
104 hsync_period) + p->hsync_skew;
105 display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
106 p->hsync_skew - 1;
107
108 hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
109 hsync_end_x = hsync_period - p->h_front_porch - 1;
110
111 if (p->width != p->xres) {
112 active_h_start = hsync_start_x;
113 active_h_end = active_h_start + p->xres - 1;
114 } else {
115 active_h_start = 0;
116 active_h_end = 0;
117 }
118
119 if (p->height != p->yres) {
120 active_v_start = display_v_start;
121 active_v_end = active_v_start + (p->yres * hsync_period) - 1;
122 } else {
123 active_v_start = 0;
124 active_v_end = 0;
125 }
126
127 if (active_h_end) {
128 active_hctl = (active_h_end << 16) | active_h_start;
129 intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */
130 } else {
131 active_hctl = 0;
132 }
133
134 if (active_v_end)
135 intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */
136
137 hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
138 display_hctl = (hsync_end_x << 16) | hsync_start_x;
139
140 if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
141 active_h_start = hsync_start_x;
142 active_h_end = active_h_start + p->xres - 1;
143 active_v_start = display_v_start;
144 active_v_end = active_v_start + (p->yres * hsync_period) - 1;
145
146 display_v_start += p->hsync_pulse_width + p->h_back_porch;
147 display_v_end -= p->h_front_porch;
148
149 active_hctl = (active_h_end << 16) | active_h_start;
150 display_hctl = active_hctl;
151 }
152
153 den_polarity = 0;
154 if (ctx->cap->type == INTF_HDMI) {
155 hsync_polarity = p->yres >= 720 ? 0 : 1;
156 vsync_polarity = p->yres >= 720 ? 0 : 1;
157 } else if (ctx->cap->type == INTF_DP) {
158 hsync_polarity = p->hsync_polarity;
159 vsync_polarity = p->vsync_polarity;
160 } else {
161 hsync_polarity = 0;
162 vsync_polarity = 0;
163 }
164 polarity_ctl = (den_polarity << 2) | /* DEN Polarity */
165 (vsync_polarity << 1) | /* VSYNC Polarity */
166 (hsync_polarity << 0); /* HSYNC Polarity */
167
168 if (!DPU_FORMAT_IS_YUV(fmt))
169 panel_format = (fmt->bits[C0_G_Y] |
170 (fmt->bits[C1_B_Cb] << 2) |
171 (fmt->bits[C2_R_Cr] << 4) |
172 (0x21 << 8));
173 else
174 /* Interface treats all the pixel data in RGB888 format */
175 panel_format = (COLOR_8BIT |
176 (COLOR_8BIT << 2) |
177 (COLOR_8BIT << 4) |
178 (0x21 << 8));
179
180 if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) {
181 intf_cfg2 |= BIT(4);
182 display_data_hctl = display_hctl;
183 DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);
184 DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);
185 }
186
187 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
188 DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period);
189 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0,
190 p->vsync_pulse_width * hsync_period);
191 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl);
192 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start);
193 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end);
194 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl);
195 DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start);
196 DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end);
197 DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr);
198 DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr);
199 DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew);
200 DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl);
201 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
202 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);
203 DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
204 }
205
dpu_hw_intf_enable_timing_engine(struct dpu_hw_intf * intf,u8 enable)206 static void dpu_hw_intf_enable_timing_engine(
207 struct dpu_hw_intf *intf,
208 u8 enable)
209 {
210 struct dpu_hw_blk_reg_map *c = &intf->hw;
211 /* Note: Display interface select is handled in top block hw layer */
212 DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0);
213 }
214
dpu_hw_intf_setup_prg_fetch(struct dpu_hw_intf * intf,const struct intf_prog_fetch * fetch)215 static void dpu_hw_intf_setup_prg_fetch(
216 struct dpu_hw_intf *intf,
217 const struct intf_prog_fetch *fetch)
218 {
219 struct dpu_hw_blk_reg_map *c = &intf->hw;
220 int fetch_enable;
221
222 /*
223 * Fetch should always be outside the active lines. If the fetching
224 * is programmed within active region, hardware behavior is unknown.
225 */
226
227 fetch_enable = DPU_REG_READ(c, INTF_CONFIG);
228 if (fetch->enable) {
229 fetch_enable |= BIT(31);
230 DPU_REG_WRITE(c, INTF_PROG_FETCH_START,
231 fetch->fetch_start);
232 } else {
233 fetch_enable &= ~BIT(31);
234 }
235
236 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable);
237 }
238
dpu_hw_intf_bind_pingpong_blk(struct dpu_hw_intf * intf,bool enable,const enum dpu_pingpong pp)239 static void dpu_hw_intf_bind_pingpong_blk(
240 struct dpu_hw_intf *intf,
241 bool enable,
242 const enum dpu_pingpong pp)
243 {
244 struct dpu_hw_blk_reg_map *c = &intf->hw;
245 u32 mux_cfg;
246
247 mux_cfg = DPU_REG_READ(c, INTF_MUX);
248 mux_cfg &= ~0xf;
249
250 if (enable)
251 mux_cfg |= (pp - PINGPONG_0) & 0x7;
252 else
253 mux_cfg |= 0xf;
254
255 DPU_REG_WRITE(c, INTF_MUX, mux_cfg);
256 }
257
dpu_hw_intf_get_status(struct dpu_hw_intf * intf,struct intf_status * s)258 static void dpu_hw_intf_get_status(
259 struct dpu_hw_intf *intf,
260 struct intf_status *s)
261 {
262 struct dpu_hw_blk_reg_map *c = &intf->hw;
263 unsigned long cap = intf->cap->features;
264
265 if (cap & BIT(DPU_INTF_STATUS_SUPPORTED))
266 s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0);
267 else
268 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
269
270 s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31));
271 if (s->is_en) {
272 s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);
273 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT);
274 } else {
275 s->line_count = 0;
276 s->frame_count = 0;
277 }
278 }
279
dpu_hw_intf_get_line_count(struct dpu_hw_intf * intf)280 static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
281 {
282 struct dpu_hw_blk_reg_map *c;
283
284 if (!intf)
285 return 0;
286
287 c = &intf->hw;
288
289 return DPU_REG_READ(c, INTF_LINE_COUNT);
290 }
291
_setup_intf_ops(struct dpu_hw_intf_ops * ops,unsigned long cap)292 static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
293 unsigned long cap)
294 {
295 ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine;
296 ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch;
297 ops->get_status = dpu_hw_intf_get_status;
298 ops->enable_timing = dpu_hw_intf_enable_timing_engine;
299 ops->get_line_count = dpu_hw_intf_get_line_count;
300 if (cap & BIT(DPU_INTF_INPUT_CTRL))
301 ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
302 }
303
dpu_hw_intf_init(enum dpu_intf idx,void __iomem * addr,const struct dpu_mdss_cfg * m)304 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
305 void __iomem *addr,
306 const struct dpu_mdss_cfg *m)
307 {
308 struct dpu_hw_intf *c;
309 const struct dpu_intf_cfg *cfg;
310
311 c = kzalloc(sizeof(*c), GFP_KERNEL);
312 if (!c)
313 return ERR_PTR(-ENOMEM);
314
315 cfg = _intf_offset(idx, m, addr, &c->hw);
316 if (IS_ERR_OR_NULL(cfg)) {
317 kfree(c);
318 pr_err("failed to create dpu_hw_intf %d\n", idx);
319 return ERR_PTR(-EINVAL);
320 }
321
322 /*
323 * Assign ops
324 */
325 c->idx = idx;
326 c->cap = cfg;
327 c->mdss = m;
328 _setup_intf_ops(&c->ops, c->cap->features);
329
330 return c;
331 }
332
dpu_hw_intf_destroy(struct dpu_hw_intf * intf)333 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf)
334 {
335 kfree(intf);
336 }
337
338