1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/iommu.h>
13 #include <linux/iopoll.h>
14 #include <linux/irq.h>
15 #include <linux/log2.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/slab.h>
19 #include <linux/dmi.h>
20 #include <linux/dma-mapping.h>
21 #include <trace/hooks/usb.h>
22
23 #include "xhci.h"
24 #include "xhci-trace.h"
25 #include "xhci-debugfs.h"
26 #include "xhci-dbgcap.h"
27
28 #define DRIVER_AUTHOR "Sarah Sharp"
29 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
30
31 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
32
33 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
34 static int link_quirk;
35 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
36 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
37
38 static unsigned long long quirks;
39 module_param(quirks, ullong, S_IRUGO);
40 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
41
td_on_ring(struct xhci_td * td,struct xhci_ring * ring)42 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
43 {
44 struct xhci_segment *seg = ring->first_seg;
45
46 if (!td || !td->start_seg)
47 return false;
48 do {
49 if (seg == td->start_seg)
50 return true;
51 seg = seg->next;
52 } while (seg && seg != ring->first_seg);
53
54 return false;
55 }
56
57 /*
58 * xhci_handshake - spin reading hc until handshake completes or fails
59 * @ptr: address of hc register to be read
60 * @mask: bits to look at in result of read
61 * @done: value of those bits when handshake succeeds
62 * @usec: timeout in microseconds
63 *
64 * Returns negative errno, or zero on success
65 *
66 * Success happens when the "mask" bits have the specified value (hardware
67 * handshake done). There are two failure modes: "usec" have passed (major
68 * hardware flakeout), or the register reads as all-ones (hardware removed).
69 */
xhci_handshake(void __iomem * ptr,u32 mask,u32 done,u64 timeout_us)70 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
71 {
72 u32 result;
73 int ret;
74
75 ret = readl_poll_timeout_atomic(ptr, result,
76 (result & mask) == done ||
77 result == U32_MAX,
78 1, timeout_us);
79 if (result == U32_MAX) /* card removed */
80 return -ENODEV;
81
82 return ret;
83 }
84
85 /*
86 * Disable interrupts and begin the xHCI halting process.
87 */
xhci_quiesce(struct xhci_hcd * xhci)88 void xhci_quiesce(struct xhci_hcd *xhci)
89 {
90 u32 halted;
91 u32 cmd;
92 u32 mask;
93
94 mask = ~(XHCI_IRQS);
95 halted = readl(&xhci->op_regs->status) & STS_HALT;
96 if (!halted)
97 mask &= ~CMD_RUN;
98
99 cmd = readl(&xhci->op_regs->command);
100 cmd &= mask;
101 writel(cmd, &xhci->op_regs->command);
102 }
103
104 /*
105 * Force HC into halt state.
106 *
107 * Disable any IRQs and clear the run/stop bit.
108 * HC will complete any current and actively pipelined transactions, and
109 * should halt within 16 ms of the run/stop bit being cleared.
110 * Read HC Halted bit in the status register to see when the HC is finished.
111 */
xhci_halt(struct xhci_hcd * xhci)112 int xhci_halt(struct xhci_hcd *xhci)
113 {
114 int ret;
115 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
116 xhci_quiesce(xhci);
117
118 ret = xhci_handshake(&xhci->op_regs->status,
119 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
120 if (ret) {
121 xhci_warn(xhci, "Host halt failed, %d\n", ret);
122 return ret;
123 }
124 xhci->xhc_state |= XHCI_STATE_HALTED;
125 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
126 return ret;
127 }
128
129 /*
130 * Set the run bit and wait for the host to be running.
131 */
xhci_start(struct xhci_hcd * xhci)132 int xhci_start(struct xhci_hcd *xhci)
133 {
134 u32 temp;
135 int ret;
136
137 temp = readl(&xhci->op_regs->command);
138 temp |= (CMD_RUN);
139 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
140 temp);
141 writel(temp, &xhci->op_regs->command);
142
143 /*
144 * Wait for the HCHalted Status bit to be 0 to indicate the host is
145 * running.
146 */
147 ret = xhci_handshake(&xhci->op_regs->status,
148 STS_HALT, 0, XHCI_MAX_HALT_USEC);
149 if (ret == -ETIMEDOUT)
150 xhci_err(xhci, "Host took too long to start, "
151 "waited %u microseconds.\n",
152 XHCI_MAX_HALT_USEC);
153 if (!ret) {
154 /* clear state flags. Including dying, halted or removing */
155 xhci->xhc_state = 0;
156 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
157 }
158
159 return ret;
160 }
161
162 /*
163 * Reset a halted HC.
164 *
165 * This resets pipelines, timers, counters, state machines, etc.
166 * Transactions will be terminated immediately, and operational registers
167 * will be set to their defaults.
168 */
xhci_reset(struct xhci_hcd * xhci,u64 timeout_us)169 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
170 {
171 u32 command;
172 u32 state;
173 int ret;
174
175 state = readl(&xhci->op_regs->status);
176
177 if (state == ~(u32)0) {
178 xhci_warn(xhci, "Host not accessible, reset failed.\n");
179 return -ENODEV;
180 }
181
182 if ((state & STS_HALT) == 0) {
183 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
184 return 0;
185 }
186
187 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
188 command = readl(&xhci->op_regs->command);
189 command |= CMD_RESET;
190 writel(command, &xhci->op_regs->command);
191
192 /* Existing Intel xHCI controllers require a delay of 1 mS,
193 * after setting the CMD_RESET bit, and before accessing any
194 * HC registers. This allows the HC to complete the
195 * reset operation and be ready for HC register access.
196 * Without this delay, the subsequent HC register access,
197 * may result in a system hang very rarely.
198 */
199 if (xhci->quirks & XHCI_INTEL_HOST)
200 udelay(1000);
201
202 ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
203 if (ret)
204 return ret;
205
206 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
207 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
208
209 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
210 "Wait for controller to be ready for doorbell rings");
211 /*
212 * xHCI cannot write to any doorbells or operational registers other
213 * than status until the "Controller Not Ready" flag is cleared.
214 */
215 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
216
217 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
218 xhci->usb2_rhub.bus_state.suspended_ports = 0;
219 xhci->usb2_rhub.bus_state.resuming_ports = 0;
220 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
221 xhci->usb3_rhub.bus_state.suspended_ports = 0;
222 xhci->usb3_rhub.bus_state.resuming_ports = 0;
223
224 return ret;
225 }
226
xhci_zero_64b_regs(struct xhci_hcd * xhci)227 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
228 {
229 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
230 struct iommu_domain *domain;
231 int err, i;
232 u64 val;
233 u32 intrs;
234
235 /*
236 * Some Renesas controllers get into a weird state if they are
237 * reset while programmed with 64bit addresses (they will preserve
238 * the top half of the address in internal, non visible
239 * registers). You end up with half the address coming from the
240 * kernel, and the other half coming from the firmware. Also,
241 * changing the programming leads to extra accesses even if the
242 * controller is supposed to be halted. The controller ends up with
243 * a fatal fault, and is then ripe for being properly reset.
244 *
245 * Special care is taken to only apply this if the device is behind
246 * an iommu. Doing anything when there is no iommu is definitely
247 * unsafe...
248 */
249 domain = iommu_get_domain_for_dev(dev);
250 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !domain ||
251 domain->type == IOMMU_DOMAIN_IDENTITY)
252 return;
253
254 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
255
256 /* Clear HSEIE so that faults do not get signaled */
257 val = readl(&xhci->op_regs->command);
258 val &= ~CMD_HSEIE;
259 writel(val, &xhci->op_regs->command);
260
261 /* Clear HSE (aka FATAL) */
262 val = readl(&xhci->op_regs->status);
263 val |= STS_FATAL;
264 writel(val, &xhci->op_regs->status);
265
266 /* Now zero the registers, and brace for impact */
267 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
268 if (upper_32_bits(val))
269 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
270 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
271 if (upper_32_bits(val))
272 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
273
274 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
275 ARRAY_SIZE(xhci->run_regs->ir_set));
276
277 for (i = 0; i < intrs; i++) {
278 struct xhci_intr_reg __iomem *ir;
279
280 ir = &xhci->run_regs->ir_set[i];
281 val = xhci_read_64(xhci, &ir->erst_base);
282 if (upper_32_bits(val))
283 xhci_write_64(xhci, 0, &ir->erst_base);
284 val= xhci_read_64(xhci, &ir->erst_dequeue);
285 if (upper_32_bits(val))
286 xhci_write_64(xhci, 0, &ir->erst_dequeue);
287 }
288
289 /* Wait for the fault to appear. It will be cleared on reset */
290 err = xhci_handshake(&xhci->op_regs->status,
291 STS_FATAL, STS_FATAL,
292 XHCI_MAX_HALT_USEC);
293 if (!err)
294 xhci_info(xhci, "Fault detected\n");
295 }
296
297 #ifdef CONFIG_USB_PCI
298 /*
299 * Set up MSI
300 */
xhci_setup_msi(struct xhci_hcd * xhci)301 static int xhci_setup_msi(struct xhci_hcd *xhci)
302 {
303 int ret;
304 /*
305 * TODO:Check with MSI Soc for sysdev
306 */
307 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
308
309 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
310 if (ret < 0) {
311 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
312 "failed to allocate MSI entry");
313 return ret;
314 }
315
316 ret = request_irq(pdev->irq, xhci_msi_irq,
317 0, "xhci_hcd", xhci_to_hcd(xhci));
318 if (ret) {
319 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
320 "disable MSI interrupt");
321 pci_free_irq_vectors(pdev);
322 }
323
324 return ret;
325 }
326
327 /*
328 * Set up MSI-X
329 */
xhci_setup_msix(struct xhci_hcd * xhci)330 static int xhci_setup_msix(struct xhci_hcd *xhci)
331 {
332 int i, ret = 0;
333 struct usb_hcd *hcd = xhci_to_hcd(xhci);
334 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
335
336 /*
337 * calculate number of msi-x vectors supported.
338 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
339 * with max number of interrupters based on the xhci HCSPARAMS1.
340 * - num_online_cpus: maximum msi-x vectors per CPUs core.
341 * Add additional 1 vector to ensure always available interrupt.
342 */
343 xhci->msix_count = min(num_online_cpus() + 1,
344 HCS_MAX_INTRS(xhci->hcs_params1));
345
346 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
347 PCI_IRQ_MSIX);
348 if (ret < 0) {
349 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
350 "Failed to enable MSI-X");
351 return ret;
352 }
353
354 for (i = 0; i < xhci->msix_count; i++) {
355 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
356 "xhci_hcd", xhci_to_hcd(xhci));
357 if (ret)
358 goto disable_msix;
359 }
360
361 hcd->msix_enabled = 1;
362 return ret;
363
364 disable_msix:
365 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
366 while (--i >= 0)
367 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
368 pci_free_irq_vectors(pdev);
369 return ret;
370 }
371
372 /* Free any IRQs and disable MSI-X */
xhci_cleanup_msix(struct xhci_hcd * xhci)373 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
374 {
375 struct usb_hcd *hcd = xhci_to_hcd(xhci);
376 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
377
378 if (xhci->quirks & XHCI_PLAT)
379 return;
380
381 /* return if using legacy interrupt */
382 if (hcd->irq > 0)
383 return;
384
385 if (hcd->msix_enabled) {
386 int i;
387
388 for (i = 0; i < xhci->msix_count; i++)
389 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
390 } else {
391 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
392 }
393
394 pci_free_irq_vectors(pdev);
395 hcd->msix_enabled = 0;
396 }
397
xhci_msix_sync_irqs(struct xhci_hcd * xhci)398 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
399 {
400 struct usb_hcd *hcd = xhci_to_hcd(xhci);
401
402 if (hcd->msix_enabled) {
403 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
404 int i;
405
406 for (i = 0; i < xhci->msix_count; i++)
407 synchronize_irq(pci_irq_vector(pdev, i));
408 }
409 }
410
xhci_try_enable_msi(struct usb_hcd * hcd)411 static int xhci_try_enable_msi(struct usb_hcd *hcd)
412 {
413 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
414 struct pci_dev *pdev;
415 int ret;
416
417 /* The xhci platform device has set up IRQs through usb_add_hcd. */
418 if (xhci->quirks & XHCI_PLAT)
419 return 0;
420
421 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
422 /*
423 * Some Fresco Logic host controllers advertise MSI, but fail to
424 * generate interrupts. Don't even try to enable MSI.
425 */
426 if (xhci->quirks & XHCI_BROKEN_MSI)
427 goto legacy_irq;
428
429 /* unregister the legacy interrupt */
430 if (hcd->irq)
431 free_irq(hcd->irq, hcd);
432 hcd->irq = 0;
433
434 ret = xhci_setup_msix(xhci);
435 if (ret)
436 /* fall back to msi*/
437 ret = xhci_setup_msi(xhci);
438
439 if (!ret) {
440 hcd->msi_enabled = 1;
441 return 0;
442 }
443
444 if (!pdev->irq) {
445 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
446 return -EINVAL;
447 }
448
449 legacy_irq:
450 if (!strlen(hcd->irq_descr))
451 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
452 hcd->driver->description, hcd->self.busnum);
453
454 /* fall back to legacy interrupt*/
455 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
456 hcd->irq_descr, hcd);
457 if (ret) {
458 xhci_err(xhci, "request interrupt %d failed\n",
459 pdev->irq);
460 return ret;
461 }
462 hcd->irq = pdev->irq;
463 return 0;
464 }
465
466 #else
467
xhci_try_enable_msi(struct usb_hcd * hcd)468 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
469 {
470 return 0;
471 }
472
xhci_cleanup_msix(struct xhci_hcd * xhci)473 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
474 {
475 }
476
xhci_msix_sync_irqs(struct xhci_hcd * xhci)477 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
478 {
479 }
480
481 #endif
482
compliance_mode_recovery(struct timer_list * t)483 static void compliance_mode_recovery(struct timer_list *t)
484 {
485 struct xhci_hcd *xhci;
486 struct usb_hcd *hcd;
487 struct xhci_hub *rhub;
488 u32 temp;
489 int i;
490
491 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
492 rhub = &xhci->usb3_rhub;
493
494 for (i = 0; i < rhub->num_ports; i++) {
495 temp = readl(rhub->ports[i]->addr);
496 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
497 /*
498 * Compliance Mode Detected. Letting USB Core
499 * handle the Warm Reset
500 */
501 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
502 "Compliance mode detected->port %d",
503 i + 1);
504 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
505 "Attempting compliance mode recovery");
506 hcd = xhci->shared_hcd;
507
508 if (hcd->state == HC_STATE_SUSPENDED)
509 usb_hcd_resume_root_hub(hcd);
510
511 usb_hcd_poll_rh_status(hcd);
512 }
513 }
514
515 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
516 mod_timer(&xhci->comp_mode_recovery_timer,
517 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
518 }
519
520 /*
521 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
522 * that causes ports behind that hardware to enter compliance mode sometimes.
523 * The quirk creates a timer that polls every 2 seconds the link state of
524 * each host controller's port and recovers it by issuing a Warm reset
525 * if Compliance mode is detected, otherwise the port will become "dead" (no
526 * device connections or disconnections will be detected anymore). Becasue no
527 * status event is generated when entering compliance mode (per xhci spec),
528 * this quirk is needed on systems that have the failing hardware installed.
529 */
compliance_mode_recovery_timer_init(struct xhci_hcd * xhci)530 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
531 {
532 xhci->port_status_u0 = 0;
533 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
534 0);
535 xhci->comp_mode_recovery_timer.expires = jiffies +
536 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
537
538 add_timer(&xhci->comp_mode_recovery_timer);
539 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
540 "Compliance mode recovery timer initialized");
541 }
542
543 /*
544 * This function identifies the systems that have installed the SN65LVPE502CP
545 * USB3.0 re-driver and that need the Compliance Mode Quirk.
546 * Systems:
547 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
548 */
xhci_compliance_mode_recovery_timer_quirk_check(void)549 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
550 {
551 const char *dmi_product_name, *dmi_sys_vendor;
552
553 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
554 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
555 if (!dmi_product_name || !dmi_sys_vendor)
556 return false;
557
558 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
559 return false;
560
561 if (strstr(dmi_product_name, "Z420") ||
562 strstr(dmi_product_name, "Z620") ||
563 strstr(dmi_product_name, "Z820") ||
564 strstr(dmi_product_name, "Z1 Workstation"))
565 return true;
566
567 return false;
568 }
569
xhci_all_ports_seen_u0(struct xhci_hcd * xhci)570 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
571 {
572 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
573 }
574
575
576 /*
577 * Initialize memory for HCD and xHC (one-time init).
578 *
579 * Program the PAGESIZE register, initialize the device context array, create
580 * device contexts (?), set up a command ring segment (or two?), create event
581 * ring (one for now).
582 */
xhci_init(struct usb_hcd * hcd)583 static int xhci_init(struct usb_hcd *hcd)
584 {
585 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
586 int retval = 0;
587
588 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
589 spin_lock_init(&xhci->lock);
590 if (xhci->hci_version == 0x95 && link_quirk) {
591 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
592 "QUIRK: Not clearing Link TRB chain bits.");
593 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
594 } else {
595 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
596 "xHCI doesn't need link TRB QUIRK");
597 }
598 retval = xhci_mem_init(xhci, GFP_KERNEL);
599 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
600
601 /* Initializing Compliance Mode Recovery Data If Needed */
602 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
603 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
604 compliance_mode_recovery_timer_init(xhci);
605 }
606
607 return retval;
608 }
609
610 /*-------------------------------------------------------------------------*/
611
612
xhci_run_finished(struct xhci_hcd * xhci)613 static int xhci_run_finished(struct xhci_hcd *xhci)
614 {
615 unsigned long flags;
616 u32 temp;
617
618 /*
619 * Enable interrupts before starting the host (xhci 4.2 and 5.5.2).
620 * Protect the short window before host is running with a lock
621 */
622 spin_lock_irqsave(&xhci->lock, flags);
623
624 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts");
625 temp = readl(&xhci->op_regs->command);
626 temp |= (CMD_EIE);
627 writel(temp, &xhci->op_regs->command);
628
629 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter");
630 temp = readl(&xhci->ir_set->irq_pending);
631 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
632
633 if (xhci_start(xhci)) {
634 xhci_halt(xhci);
635 spin_unlock_irqrestore(&xhci->lock, flags);
636 return -ENODEV;
637 }
638 xhci->shared_hcd->state = HC_STATE_RUNNING;
639 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
640
641 if (xhci->quirks & XHCI_NEC_HOST)
642 xhci_ring_cmd_db(xhci);
643
644 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
645 "Finished xhci_run for USB3 roothub");
646
647 spin_unlock_irqrestore(&xhci->lock, flags);
648
649 return 0;
650 }
651
652 /*
653 * Start the HC after it was halted.
654 *
655 * This function is called by the USB core when the HC driver is added.
656 * Its opposite is xhci_stop().
657 *
658 * xhci_init() must be called once before this function can be called.
659 * Reset the HC, enable device slot contexts, program DCBAAP, and
660 * set command ring pointer and event ring pointer.
661 *
662 * Setup MSI-X vectors and enable interrupts.
663 */
xhci_run(struct usb_hcd * hcd)664 int xhci_run(struct usb_hcd *hcd)
665 {
666 u32 temp;
667 u64 temp_64;
668 int ret;
669 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
670
671 /* Start the xHCI host controller running only after the USB 2.0 roothub
672 * is setup.
673 */
674
675 hcd->uses_new_polling = 1;
676 if (!usb_hcd_is_primary_hcd(hcd))
677 return xhci_run_finished(xhci);
678
679 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
680
681 ret = xhci_try_enable_msi(hcd);
682 if (ret)
683 return ret;
684
685 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
686 temp_64 &= ~ERST_PTR_MASK;
687 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
688 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
689
690 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
691 "// Set the interrupt modulation register");
692 temp = readl(&xhci->ir_set->irq_control);
693 temp &= ~ER_IRQ_INTERVAL_MASK;
694 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
695 writel(temp, &xhci->ir_set->irq_control);
696
697 if (xhci->quirks & XHCI_NEC_HOST) {
698 struct xhci_command *command;
699
700 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
701 if (!command)
702 return -ENOMEM;
703
704 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
705 TRB_TYPE(TRB_NEC_GET_FW));
706 if (ret)
707 xhci_free_command(xhci, command);
708 }
709 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
710 "Finished xhci_run for USB2 roothub");
711
712 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
713
714 xhci_create_dbc_dev(xhci);
715
716 xhci_debugfs_init(xhci);
717
718 return 0;
719 }
720 EXPORT_SYMBOL_GPL(xhci_run);
721
722 /*
723 * Stop xHCI driver.
724 *
725 * This function is called by the USB core when the HC driver is removed.
726 * Its opposite is xhci_run().
727 *
728 * Disable device contexts, disable IRQs, and quiesce the HC.
729 * Reset the HC, finish any completed transactions, and cleanup memory.
730 */
xhci_stop(struct usb_hcd * hcd)731 static void xhci_stop(struct usb_hcd *hcd)
732 {
733 u32 temp;
734 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
735
736 mutex_lock(&xhci->mutex);
737
738 /* Only halt host and free memory after both hcds are removed */
739 if (!usb_hcd_is_primary_hcd(hcd)) {
740 mutex_unlock(&xhci->mutex);
741 return;
742 }
743
744 xhci_remove_dbc_dev(xhci);
745
746 spin_lock_irq(&xhci->lock);
747 xhci->xhc_state |= XHCI_STATE_HALTED;
748 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
749 xhci_halt(xhci);
750 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
751 spin_unlock_irq(&xhci->lock);
752
753 xhci_cleanup_msix(xhci);
754
755 /* Deleting Compliance Mode Recovery Timer */
756 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
757 (!(xhci_all_ports_seen_u0(xhci)))) {
758 del_timer_sync(&xhci->comp_mode_recovery_timer);
759 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
760 "%s: compliance mode recovery timer deleted",
761 __func__);
762 }
763
764 if (xhci->quirks & XHCI_AMD_PLL_FIX)
765 usb_amd_dev_put();
766
767 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
768 "// Disabling event ring interrupts");
769 temp = readl(&xhci->op_regs->status);
770 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
771 temp = readl(&xhci->ir_set->irq_pending);
772 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
773
774 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
775 xhci_mem_cleanup(xhci);
776 xhci_debugfs_exit(xhci);
777 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
778 "xhci_stop completed - status = %x",
779 readl(&xhci->op_regs->status));
780 mutex_unlock(&xhci->mutex);
781 }
782
783 /*
784 * Shutdown HC (not bus-specific)
785 *
786 * This is called when the machine is rebooting or halting. We assume that the
787 * machine will be powered off, and the HC's internal state will be reset.
788 * Don't bother to free memory.
789 *
790 * This will only ever be called with the main usb_hcd (the USB3 roothub).
791 */
xhci_shutdown(struct usb_hcd * hcd)792 void xhci_shutdown(struct usb_hcd *hcd)
793 {
794 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
795
796 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
797 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
798
799 /* Don't poll the roothubs after shutdown. */
800 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
801 __func__, hcd->self.busnum);
802 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
803 del_timer_sync(&hcd->rh_timer);
804
805 if (xhci->shared_hcd) {
806 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
807 del_timer_sync(&xhci->shared_hcd->rh_timer);
808 }
809
810 spin_lock_irq(&xhci->lock);
811 xhci_halt(xhci);
812
813 /*
814 * Workaround for spurious wakeps at shutdown with HSW, and for boot
815 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
816 */
817 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
818 xhci->quirks & XHCI_RESET_TO_DEFAULT)
819 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
820
821 spin_unlock_irq(&xhci->lock);
822
823 xhci_cleanup_msix(xhci);
824
825 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
826 "xhci_shutdown completed - status = %x",
827 readl(&xhci->op_regs->status));
828 }
829 EXPORT_SYMBOL_GPL(xhci_shutdown);
830
831 #ifdef CONFIG_PM
xhci_save_registers(struct xhci_hcd * xhci)832 static void xhci_save_registers(struct xhci_hcd *xhci)
833 {
834 xhci->s3.command = readl(&xhci->op_regs->command);
835 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
836 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
837 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
838 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
839 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
840 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
841 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
842 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
843 }
844
xhci_restore_registers(struct xhci_hcd * xhci)845 static void xhci_restore_registers(struct xhci_hcd *xhci)
846 {
847 writel(xhci->s3.command, &xhci->op_regs->command);
848 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
849 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
850 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
851 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
852 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
853 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
854 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
855 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
856 }
857
xhci_set_cmd_ring_deq(struct xhci_hcd * xhci)858 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
859 {
860 u64 val_64;
861
862 /* step 2: initialize command ring buffer */
863 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
864 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
865 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
866 xhci->cmd_ring->dequeue) &
867 (u64) ~CMD_RING_RSVD_BITS) |
868 xhci->cmd_ring->cycle_state;
869 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
870 "// Setting command ring address to 0x%llx",
871 (long unsigned long) val_64);
872 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
873 }
874
875 /*
876 * The whole command ring must be cleared to zero when we suspend the host.
877 *
878 * The host doesn't save the command ring pointer in the suspend well, so we
879 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
880 * aligned, because of the reserved bits in the command ring dequeue pointer
881 * register. Therefore, we can't just set the dequeue pointer back in the
882 * middle of the ring (TRBs are 16-byte aligned).
883 */
xhci_clear_command_ring(struct xhci_hcd * xhci)884 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
885 {
886 struct xhci_ring *ring;
887 struct xhci_segment *seg;
888
889 ring = xhci->cmd_ring;
890 seg = ring->deq_seg;
891 do {
892 memset(seg->trbs, 0,
893 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
894 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
895 cpu_to_le32(~TRB_CYCLE);
896 seg = seg->next;
897 } while (seg != ring->deq_seg);
898
899 /* Reset the software enqueue and dequeue pointers */
900 ring->deq_seg = ring->first_seg;
901 ring->dequeue = ring->first_seg->trbs;
902 ring->enq_seg = ring->deq_seg;
903 ring->enqueue = ring->dequeue;
904
905 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
906 /*
907 * Ring is now zeroed, so the HW should look for change of ownership
908 * when the cycle bit is set to 1.
909 */
910 ring->cycle_state = 1;
911
912 /*
913 * Reset the hardware dequeue pointer.
914 * Yes, this will need to be re-written after resume, but we're paranoid
915 * and want to make sure the hardware doesn't access bogus memory
916 * because, say, the BIOS or an SMI started the host without changing
917 * the command ring pointers.
918 */
919 xhci_set_cmd_ring_deq(xhci);
920 }
921
922 /*
923 * Disable port wake bits if do_wakeup is not set.
924 *
925 * Also clear a possible internal port wake state left hanging for ports that
926 * detected termination but never successfully enumerated (trained to 0U).
927 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
928 * at enumeration clears this wake, force one here as well for unconnected ports
929 */
930
xhci_disable_hub_port_wake(struct xhci_hcd * xhci,struct xhci_hub * rhub,bool do_wakeup)931 static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
932 struct xhci_hub *rhub,
933 bool do_wakeup)
934 {
935 unsigned long flags;
936 u32 t1, t2, portsc;
937 int i;
938
939 spin_lock_irqsave(&xhci->lock, flags);
940
941 for (i = 0; i < rhub->num_ports; i++) {
942 portsc = readl(rhub->ports[i]->addr);
943 t1 = xhci_port_state_to_neutral(portsc);
944 t2 = t1;
945
946 /* clear wake bits if do_wake is not set */
947 if (!do_wakeup)
948 t2 &= ~PORT_WAKE_BITS;
949
950 /* Don't touch csc bit if connected or connect change is set */
951 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
952 t2 |= PORT_CSC;
953
954 if (t1 != t2) {
955 writel(t2, rhub->ports[i]->addr);
956 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
957 rhub->hcd->self.busnum, i + 1, portsc, t2);
958 }
959 }
960 spin_unlock_irqrestore(&xhci->lock, flags);
961 }
962
xhci_pending_portevent(struct xhci_hcd * xhci)963 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
964 {
965 struct xhci_port **ports;
966 int port_index;
967 u32 status;
968 u32 portsc;
969
970 status = readl(&xhci->op_regs->status);
971 if (status & STS_EINT)
972 return true;
973 /*
974 * Checking STS_EINT is not enough as there is a lag between a change
975 * bit being set and the Port Status Change Event that it generated
976 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
977 */
978
979 port_index = xhci->usb2_rhub.num_ports;
980 ports = xhci->usb2_rhub.ports;
981 while (port_index--) {
982 portsc = readl(ports[port_index]->addr);
983 if (portsc & PORT_CHANGE_MASK ||
984 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
985 return true;
986 }
987 port_index = xhci->usb3_rhub.num_ports;
988 ports = xhci->usb3_rhub.ports;
989 while (port_index--) {
990 portsc = readl(ports[port_index]->addr);
991 if (portsc & PORT_CHANGE_MASK ||
992 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
993 return true;
994 }
995 return false;
996 }
997
998 /*
999 * Stop HC (not bus-specific)
1000 *
1001 * This is called when the machine transition into S3/S4 mode.
1002 *
1003 */
xhci_suspend(struct xhci_hcd * xhci,bool do_wakeup)1004 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
1005 {
1006 int rc = 0;
1007 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
1008 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1009 u32 command;
1010 u32 res;
1011
1012 if (!hcd->state)
1013 return 0;
1014
1015 if (hcd->state != HC_STATE_SUSPENDED ||
1016 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
1017 return -EINVAL;
1018
1019 /* Clear root port wake on bits if wakeup not allowed. */
1020 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
1021 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
1022
1023 if (!HCD_HW_ACCESSIBLE(hcd))
1024 return 0;
1025
1026 xhci_dbc_suspend(xhci);
1027
1028 /* Don't poll the roothubs on bus suspend. */
1029 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
1030 __func__, hcd->self.busnum);
1031 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1032 del_timer_sync(&hcd->rh_timer);
1033 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1034 del_timer_sync(&xhci->shared_hcd->rh_timer);
1035
1036 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1037 usleep_range(1000, 1500);
1038
1039 spin_lock_irq(&xhci->lock);
1040 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1041 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1042 /* step 1: stop endpoint */
1043 /* skipped assuming that port suspend has done */
1044
1045 /* step 2: clear Run/Stop bit */
1046 command = readl(&xhci->op_regs->command);
1047 command &= ~CMD_RUN;
1048 writel(command, &xhci->op_regs->command);
1049
1050 /* Some chips from Fresco Logic need an extraordinary delay */
1051 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1052
1053 if (xhci_handshake(&xhci->op_regs->status,
1054 STS_HALT, STS_HALT, delay)) {
1055 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1056 spin_unlock_irq(&xhci->lock);
1057 return -ETIMEDOUT;
1058 }
1059 xhci_clear_command_ring(xhci);
1060
1061 /* step 3: save registers */
1062 xhci_save_registers(xhci);
1063
1064 /* step 4: set CSS flag */
1065 command = readl(&xhci->op_regs->command);
1066 command |= CMD_CSS;
1067 writel(command, &xhci->op_regs->command);
1068 xhci->broken_suspend = 0;
1069 if (xhci_handshake(&xhci->op_regs->status,
1070 STS_SAVE, 0, 20 * 1000)) {
1071 /*
1072 * AMD SNPS xHC 3.0 occasionally does not clear the
1073 * SSS bit of USBSTS and when driver tries to poll
1074 * to see if the xHC clears BIT(8) which never happens
1075 * and driver assumes that controller is not responding
1076 * and times out. To workaround this, its good to check
1077 * if SRE and HCE bits are not set (as per xhci
1078 * Section 5.4.2) and bypass the timeout.
1079 */
1080 res = readl(&xhci->op_regs->status);
1081 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1082 (((res & STS_SRE) == 0) &&
1083 ((res & STS_HCE) == 0))) {
1084 xhci->broken_suspend = 1;
1085 } else {
1086 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1087 spin_unlock_irq(&xhci->lock);
1088 return -ETIMEDOUT;
1089 }
1090 }
1091 spin_unlock_irq(&xhci->lock);
1092
1093 /*
1094 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1095 * is about to be suspended.
1096 */
1097 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1098 (!(xhci_all_ports_seen_u0(xhci)))) {
1099 del_timer_sync(&xhci->comp_mode_recovery_timer);
1100 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1101 "%s: compliance mode recovery timer deleted",
1102 __func__);
1103 }
1104
1105 /* step 5: remove core well power */
1106 /* synchronize irq when using MSI-X */
1107 xhci_msix_sync_irqs(xhci);
1108
1109 return rc;
1110 }
1111 EXPORT_SYMBOL_GPL(xhci_suspend);
1112
1113 /*
1114 * start xHC (not bus-specific)
1115 *
1116 * This is called when the machine transition from S3/S4 mode.
1117 *
1118 */
xhci_resume(struct xhci_hcd * xhci,bool hibernated)1119 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1120 {
1121 u32 command, temp = 0;
1122 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1123 struct usb_hcd *secondary_hcd;
1124 int retval = 0;
1125 bool comp_timer_running = false;
1126 bool pending_portevent = false;
1127 bool reinit_xhc = false;
1128
1129 if (!hcd->state)
1130 return 0;
1131
1132 /* Wait a bit if either of the roothubs need to settle from the
1133 * transition into bus suspend.
1134 */
1135
1136 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1137 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1138 msleep(100);
1139
1140 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1141 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1142
1143 spin_lock_irq(&xhci->lock);
1144
1145 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1146 reinit_xhc = true;
1147
1148 if (!reinit_xhc) {
1149 /*
1150 * Some controllers might lose power during suspend, so wait
1151 * for controller not ready bit to clear, just as in xHC init.
1152 */
1153 retval = xhci_handshake(&xhci->op_regs->status,
1154 STS_CNR, 0, 10 * 1000 * 1000);
1155 if (retval) {
1156 xhci_warn(xhci, "Controller not ready at resume %d\n",
1157 retval);
1158 spin_unlock_irq(&xhci->lock);
1159 return retval;
1160 }
1161 /* step 1: restore register */
1162 xhci_restore_registers(xhci);
1163 /* step 2: initialize command ring buffer */
1164 xhci_set_cmd_ring_deq(xhci);
1165 /* step 3: restore state and start state*/
1166 /* step 3: set CRS flag */
1167 command = readl(&xhci->op_regs->command);
1168 command |= CMD_CRS;
1169 writel(command, &xhci->op_regs->command);
1170 /*
1171 * Some controllers take up to 55+ ms to complete the controller
1172 * restore so setting the timeout to 100ms. Xhci specification
1173 * doesn't mention any timeout value.
1174 */
1175 if (xhci_handshake(&xhci->op_regs->status,
1176 STS_RESTORE, 0, 100 * 1000)) {
1177 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1178 spin_unlock_irq(&xhci->lock);
1179 return -ETIMEDOUT;
1180 }
1181 }
1182
1183 temp = readl(&xhci->op_regs->status);
1184
1185 /* re-initialize the HC on Restore Error, or Host Controller Error */
1186 if (temp & (STS_SRE | STS_HCE)) {
1187 reinit_xhc = true;
1188 if (!xhci->broken_suspend)
1189 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1190 }
1191
1192 if (reinit_xhc) {
1193 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1194 !(xhci_all_ports_seen_u0(xhci))) {
1195 del_timer_sync(&xhci->comp_mode_recovery_timer);
1196 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1197 "Compliance Mode Recovery Timer deleted!");
1198 }
1199
1200 /* Let the USB core know _both_ roothubs lost power. */
1201 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1202 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1203
1204 xhci_dbg(xhci, "Stop HCD\n");
1205 xhci_halt(xhci);
1206 xhci_zero_64b_regs(xhci);
1207 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1208 spin_unlock_irq(&xhci->lock);
1209 if (retval)
1210 return retval;
1211 xhci_cleanup_msix(xhci);
1212
1213 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1214 temp = readl(&xhci->op_regs->status);
1215 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1216 temp = readl(&xhci->ir_set->irq_pending);
1217 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1218
1219 xhci_dbg(xhci, "cleaning up memory\n");
1220 xhci_mem_cleanup(xhci);
1221 xhci_debugfs_exit(xhci);
1222 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1223 readl(&xhci->op_regs->status));
1224
1225 /* USB core calls the PCI reinit and start functions twice:
1226 * first with the primary HCD, and then with the secondary HCD.
1227 * If we don't do the same, the host will never be started.
1228 */
1229 if (!usb_hcd_is_primary_hcd(hcd))
1230 secondary_hcd = hcd;
1231 else
1232 secondary_hcd = xhci->shared_hcd;
1233
1234 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1235 retval = xhci_init(hcd->primary_hcd);
1236 if (retval)
1237 return retval;
1238 comp_timer_running = true;
1239
1240 xhci_dbg(xhci, "Start the primary HCD\n");
1241 retval = xhci_run(hcd->primary_hcd);
1242 if (!retval) {
1243 xhci_dbg(xhci, "Start the secondary HCD\n");
1244 retval = xhci_run(secondary_hcd);
1245 }
1246 hcd->state = HC_STATE_SUSPENDED;
1247 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1248 goto done;
1249 }
1250
1251 /* step 4: set Run/Stop bit */
1252 command = readl(&xhci->op_regs->command);
1253 command |= CMD_RUN;
1254 writel(command, &xhci->op_regs->command);
1255 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1256 0, 250 * 1000);
1257
1258 /* step 5: walk topology and initialize portsc,
1259 * portpmsc and portli
1260 */
1261 /* this is done in bus_resume */
1262
1263 /* step 6: restart each of the previously
1264 * Running endpoints by ringing their doorbells
1265 */
1266
1267 spin_unlock_irq(&xhci->lock);
1268
1269 xhci_dbc_resume(xhci);
1270
1271 done:
1272 if (retval == 0) {
1273 /*
1274 * Resume roothubs only if there are pending events.
1275 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1276 * the first wake signalling failed, give it that chance.
1277 */
1278 pending_portevent = xhci_pending_portevent(xhci);
1279 if (!pending_portevent) {
1280 msleep(120);
1281 pending_portevent = xhci_pending_portevent(xhci);
1282 }
1283
1284 if (pending_portevent) {
1285 usb_hcd_resume_root_hub(xhci->shared_hcd);
1286 usb_hcd_resume_root_hub(hcd);
1287 }
1288 }
1289 /*
1290 * If system is subject to the Quirk, Compliance Mode Timer needs to
1291 * be re-initialized Always after a system resume. Ports are subject
1292 * to suffer the Compliance Mode issue again. It doesn't matter if
1293 * ports have entered previously to U0 before system's suspension.
1294 */
1295 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1296 compliance_mode_recovery_timer_init(xhci);
1297
1298 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1299 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1300
1301 /* Re-enable port polling. */
1302 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1303 __func__, hcd->self.busnum);
1304 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1305 usb_hcd_poll_rh_status(xhci->shared_hcd);
1306 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1307 usb_hcd_poll_rh_status(hcd);
1308
1309 return retval;
1310 }
1311 EXPORT_SYMBOL_GPL(xhci_resume);
1312 #endif /* CONFIG_PM */
1313
1314 /*-------------------------------------------------------------------------*/
1315
xhci_map_temp_buffer(struct usb_hcd * hcd,struct urb * urb)1316 static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1317 {
1318 void *temp;
1319 int ret = 0;
1320 unsigned int buf_len;
1321 enum dma_data_direction dir;
1322
1323 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1324 buf_len = urb->transfer_buffer_length;
1325
1326 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1327 dev_to_node(hcd->self.sysdev));
1328
1329 if (usb_urb_dir_out(urb))
1330 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1331 temp, buf_len, 0);
1332
1333 urb->transfer_buffer = temp;
1334 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1335 urb->transfer_buffer,
1336 urb->transfer_buffer_length,
1337 dir);
1338
1339 if (dma_mapping_error(hcd->self.sysdev,
1340 urb->transfer_dma)) {
1341 ret = -EAGAIN;
1342 kfree(temp);
1343 } else {
1344 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1345 }
1346
1347 return ret;
1348 }
1349
xhci_urb_temp_buffer_required(struct usb_hcd * hcd,struct urb * urb)1350 static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1351 struct urb *urb)
1352 {
1353 bool ret = false;
1354 unsigned int i;
1355 unsigned int len = 0;
1356 unsigned int trb_size;
1357 unsigned int max_pkt;
1358 struct scatterlist *sg;
1359 struct scatterlist *tail_sg;
1360
1361 tail_sg = urb->sg;
1362 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1363
1364 if (!urb->num_sgs)
1365 return ret;
1366
1367 if (urb->dev->speed >= USB_SPEED_SUPER)
1368 trb_size = TRB_CACHE_SIZE_SS;
1369 else
1370 trb_size = TRB_CACHE_SIZE_HS;
1371
1372 if (urb->transfer_buffer_length != 0 &&
1373 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1374 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1375 len = len + sg->length;
1376 if (i > trb_size - 2) {
1377 len = len - tail_sg->length;
1378 if (len < max_pkt) {
1379 ret = true;
1380 break;
1381 }
1382
1383 tail_sg = sg_next(tail_sg);
1384 }
1385 }
1386 }
1387 return ret;
1388 }
1389
xhci_unmap_temp_buf(struct usb_hcd * hcd,struct urb * urb)1390 static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1391 {
1392 unsigned int len;
1393 unsigned int buf_len;
1394 enum dma_data_direction dir;
1395
1396 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1397
1398 buf_len = urb->transfer_buffer_length;
1399
1400 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1401 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1402 dma_unmap_single(hcd->self.sysdev,
1403 urb->transfer_dma,
1404 urb->transfer_buffer_length,
1405 dir);
1406
1407 if (usb_urb_dir_in(urb)) {
1408 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1409 urb->transfer_buffer,
1410 buf_len,
1411 0);
1412 if (len != buf_len) {
1413 xhci_dbg(hcd_to_xhci(hcd),
1414 "Copy from tmp buf to urb sg list failed\n");
1415 urb->actual_length = len;
1416 }
1417 }
1418 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1419 kfree(urb->transfer_buffer);
1420 urb->transfer_buffer = NULL;
1421 }
1422
_trace_android_vh_xhci_urb_suitable_bypass(struct urb * urb,int * ret)1423 void _trace_android_vh_xhci_urb_suitable_bypass(struct urb *urb, int *ret)
1424 {
1425 trace_android_vh_xhci_urb_suitable_bypass(urb, ret);
1426 }
1427
1428 /*
1429 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1430 * we'll copy the actual data into the TRB address register. This is limited to
1431 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1432 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1433 */
xhci_map_urb_for_dma(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)1434 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1435 gfp_t mem_flags)
1436 {
1437 struct xhci_hcd *xhci;
1438
1439 xhci = hcd_to_xhci(hcd);
1440
1441 if (xhci_urb_suitable_for_idt(urb))
1442 return 0;
1443
1444 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1445 if (xhci_urb_temp_buffer_required(hcd, urb))
1446 return xhci_map_temp_buffer(hcd, urb);
1447 }
1448 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1449 }
1450
xhci_unmap_urb_for_dma(struct usb_hcd * hcd,struct urb * urb)1451 static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1452 {
1453 struct xhci_hcd *xhci;
1454 bool unmap_temp_buf = false;
1455
1456 xhci = hcd_to_xhci(hcd);
1457
1458 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1459 unmap_temp_buf = true;
1460
1461 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1462 xhci_unmap_temp_buf(hcd, urb);
1463 else
1464 usb_hcd_unmap_urb_for_dma(hcd, urb);
1465 }
1466
1467 /**
1468 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1469 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1470 * value to right shift 1 for the bitmask.
1471 *
1472 * Index = (epnum * 2) + direction - 1,
1473 * where direction = 0 for OUT, 1 for IN.
1474 * For control endpoints, the IN index is used (OUT index is unused), so
1475 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1476 */
xhci_get_endpoint_index(struct usb_endpoint_descriptor * desc)1477 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1478 {
1479 unsigned int index;
1480 if (usb_endpoint_xfer_control(desc))
1481 index = (unsigned int) (usb_endpoint_num(desc)*2);
1482 else
1483 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1484 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1485 return index;
1486 }
1487 EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1488
1489 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1490 * address from the XHCI endpoint index.
1491 */
xhci_get_endpoint_address(unsigned int ep_index)1492 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1493 {
1494 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1495 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1496 return direction | number;
1497 }
1498
1499 /* Find the flag for this endpoint (for use in the control context). Use the
1500 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1501 * bit 1, etc.
1502 */
xhci_get_endpoint_flag(struct usb_endpoint_descriptor * desc)1503 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1504 {
1505 return 1 << (xhci_get_endpoint_index(desc) + 1);
1506 }
1507
1508 /* Compute the last valid endpoint context index. Basically, this is the
1509 * endpoint index plus one. For slot contexts with more than valid endpoint,
1510 * we find the most significant bit set in the added contexts flags.
1511 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1512 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1513 */
xhci_last_valid_endpoint(u32 added_ctxs)1514 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1515 {
1516 return fls(added_ctxs) - 1;
1517 }
1518
1519 /* Returns 1 if the arguments are OK;
1520 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1521 */
xhci_check_args(struct usb_hcd * hcd,struct usb_device * udev,struct usb_host_endpoint * ep,int check_ep,bool check_virt_dev,const char * func)1522 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1523 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1524 const char *func) {
1525 struct xhci_hcd *xhci;
1526 struct xhci_virt_device *virt_dev;
1527
1528 if (!hcd || (check_ep && !ep) || !udev) {
1529 pr_debug("xHCI %s called with invalid args\n", func);
1530 return -EINVAL;
1531 }
1532 if (!udev->parent) {
1533 pr_debug("xHCI %s called for root hub\n", func);
1534 return 0;
1535 }
1536
1537 xhci = hcd_to_xhci(hcd);
1538 if (check_virt_dev) {
1539 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1540 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1541 func);
1542 return -EINVAL;
1543 }
1544
1545 virt_dev = xhci->devs[udev->slot_id];
1546 if (virt_dev->udev != udev) {
1547 xhci_dbg(xhci, "xHCI %s called with udev and "
1548 "virt_dev does not match\n", func);
1549 return -EINVAL;
1550 }
1551 }
1552
1553 if (xhci->xhc_state & XHCI_STATE_HALTED)
1554 return -ENODEV;
1555
1556 return 1;
1557 }
1558
1559 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1560 struct usb_device *udev, struct xhci_command *command,
1561 bool ctx_change, bool must_succeed);
1562
1563 /*
1564 * Full speed devices may have a max packet size greater than 8 bytes, but the
1565 * USB core doesn't know that until it reads the first 8 bytes of the
1566 * descriptor. If the usb_device's max packet size changes after that point,
1567 * we need to issue an evaluate context command and wait on it.
1568 */
xhci_check_maxpacket(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,struct urb * urb,gfp_t mem_flags)1569 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1570 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1571 {
1572 struct xhci_container_ctx *out_ctx;
1573 struct xhci_input_control_ctx *ctrl_ctx;
1574 struct xhci_ep_ctx *ep_ctx;
1575 struct xhci_command *command;
1576 int max_packet_size;
1577 int hw_max_packet_size;
1578 int ret = 0;
1579
1580 out_ctx = xhci->devs[slot_id]->out_ctx;
1581 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1582 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1583 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1584 if (hw_max_packet_size != max_packet_size) {
1585 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1586 "Max Packet Size for ep 0 changed.");
1587 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1588 "Max packet size in usb_device = %d",
1589 max_packet_size);
1590 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1591 "Max packet size in xHCI HW = %d",
1592 hw_max_packet_size);
1593 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1594 "Issuing evaluate context command.");
1595
1596 /* Set up the input context flags for the command */
1597 /* FIXME: This won't work if a non-default control endpoint
1598 * changes max packet sizes.
1599 */
1600
1601 command = xhci_alloc_command(xhci, true, mem_flags);
1602 if (!command)
1603 return -ENOMEM;
1604
1605 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1606 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1607 if (!ctrl_ctx) {
1608 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1609 __func__);
1610 ret = -ENOMEM;
1611 goto command_cleanup;
1612 }
1613 /* Set up the modified control endpoint 0 */
1614 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1615 xhci->devs[slot_id]->out_ctx, ep_index);
1616
1617 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1618 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1619 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1620 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1621
1622 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1623 ctrl_ctx->drop_flags = 0;
1624
1625 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1626 true, false);
1627
1628 /* Clean up the input context for later use by bandwidth
1629 * functions.
1630 */
1631 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1632 command_cleanup:
1633 kfree(command->completion);
1634 kfree(command);
1635 }
1636 return ret;
1637 }
1638
1639 /*
1640 * non-error returns are a promise to giveback() the urb later
1641 * we drop ownership so next owner (or urb unlink) can get it
1642 */
xhci_urb_enqueue(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)1643 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1644 {
1645 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1646 unsigned long flags;
1647 int ret = 0;
1648 unsigned int slot_id, ep_index;
1649 unsigned int *ep_state;
1650 struct urb_priv *urb_priv;
1651 int num_tds;
1652
1653 if (!urb)
1654 return -EINVAL;
1655 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1656 true, true, __func__);
1657 if (ret <= 0)
1658 return ret ? ret : -EINVAL;
1659
1660 slot_id = urb->dev->slot_id;
1661 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1662 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1663
1664 if (!HCD_HW_ACCESSIBLE(hcd))
1665 return -ESHUTDOWN;
1666
1667 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1668 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1669 return -ENODEV;
1670 }
1671
1672 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1673 num_tds = urb->number_of_packets;
1674 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1675 urb->transfer_buffer_length > 0 &&
1676 urb->transfer_flags & URB_ZERO_PACKET &&
1677 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1678 num_tds = 2;
1679 else
1680 num_tds = 1;
1681
1682 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1683 if (!urb_priv)
1684 return -ENOMEM;
1685
1686 urb_priv->num_tds = num_tds;
1687 urb_priv->num_tds_done = 0;
1688 urb->hcpriv = urb_priv;
1689
1690 trace_xhci_urb_enqueue(urb);
1691
1692 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1693 /* Check to see if the max packet size for the default control
1694 * endpoint changed during FS device enumeration
1695 */
1696 if (urb->dev->speed == USB_SPEED_FULL) {
1697 ret = xhci_check_maxpacket(xhci, slot_id,
1698 ep_index, urb, mem_flags);
1699 if (ret < 0) {
1700 xhci_urb_free_priv(urb_priv);
1701 urb->hcpriv = NULL;
1702 return ret;
1703 }
1704 }
1705 }
1706
1707 spin_lock_irqsave(&xhci->lock, flags);
1708
1709 if (xhci->xhc_state & XHCI_STATE_DYING) {
1710 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1711 urb->ep->desc.bEndpointAddress, urb);
1712 ret = -ESHUTDOWN;
1713 goto free_priv;
1714 }
1715 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1716 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1717 *ep_state);
1718 ret = -EINVAL;
1719 goto free_priv;
1720 }
1721 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1722 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1723 ret = -EINVAL;
1724 goto free_priv;
1725 }
1726
1727 switch (usb_endpoint_type(&urb->ep->desc)) {
1728
1729 case USB_ENDPOINT_XFER_CONTROL:
1730 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1731 slot_id, ep_index);
1732 break;
1733 case USB_ENDPOINT_XFER_BULK:
1734 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1735 slot_id, ep_index);
1736 break;
1737 case USB_ENDPOINT_XFER_INT:
1738 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1739 slot_id, ep_index);
1740 break;
1741 case USB_ENDPOINT_XFER_ISOC:
1742 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1743 slot_id, ep_index);
1744 }
1745
1746 if (ret) {
1747 free_priv:
1748 xhci_urb_free_priv(urb_priv);
1749 urb->hcpriv = NULL;
1750 }
1751 spin_unlock_irqrestore(&xhci->lock, flags);
1752 return ret;
1753 }
1754
1755 /*
1756 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1757 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1758 * should pick up where it left off in the TD, unless a Set Transfer Ring
1759 * Dequeue Pointer is issued.
1760 *
1761 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1762 * the ring. Since the ring is a contiguous structure, they can't be physically
1763 * removed. Instead, there are two options:
1764 *
1765 * 1) If the HC is in the middle of processing the URB to be canceled, we
1766 * simply move the ring's dequeue pointer past those TRBs using the Set
1767 * Transfer Ring Dequeue Pointer command. This will be the common case,
1768 * when drivers timeout on the last submitted URB and attempt to cancel.
1769 *
1770 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1771 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1772 * HC will need to invalidate the any TRBs it has cached after the stop
1773 * endpoint command, as noted in the xHCI 0.95 errata.
1774 *
1775 * 3) The TD may have completed by the time the Stop Endpoint Command
1776 * completes, so software needs to handle that case too.
1777 *
1778 * This function should protect against the TD enqueueing code ringing the
1779 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1780 * It also needs to account for multiple cancellations on happening at the same
1781 * time for the same endpoint.
1782 *
1783 * Note that this function can be called in any context, or so says
1784 * usb_hcd_unlink_urb()
1785 */
xhci_urb_dequeue(struct usb_hcd * hcd,struct urb * urb,int status)1786 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1787 {
1788 unsigned long flags;
1789 int ret, i;
1790 u32 temp;
1791 struct xhci_hcd *xhci;
1792 struct urb_priv *urb_priv;
1793 struct xhci_td *td;
1794 unsigned int ep_index;
1795 struct xhci_ring *ep_ring;
1796 struct xhci_virt_ep *ep;
1797 struct xhci_command *command;
1798 struct xhci_virt_device *vdev;
1799
1800 xhci = hcd_to_xhci(hcd);
1801 spin_lock_irqsave(&xhci->lock, flags);
1802
1803 trace_xhci_urb_dequeue(urb);
1804
1805 /* Make sure the URB hasn't completed or been unlinked already */
1806 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1807 if (ret)
1808 goto done;
1809
1810 /* give back URB now if we can't queue it for cancel */
1811 vdev = xhci->devs[urb->dev->slot_id];
1812 urb_priv = urb->hcpriv;
1813 if (!vdev || !urb_priv)
1814 goto err_giveback;
1815
1816 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1817 ep = &vdev->eps[ep_index];
1818 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1819 if (!ep || !ep_ring)
1820 goto err_giveback;
1821
1822 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1823 temp = readl(&xhci->op_regs->status);
1824 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1825 xhci_hc_died(xhci);
1826 goto done;
1827 }
1828
1829 /*
1830 * check ring is not re-allocated since URB was enqueued. If it is, then
1831 * make sure none of the ring related pointers in this URB private data
1832 * are touched, such as td_list, otherwise we overwrite freed data
1833 */
1834 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1835 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1836 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1837 td = &urb_priv->td[i];
1838 if (!list_empty(&td->cancelled_td_list))
1839 list_del_init(&td->cancelled_td_list);
1840 }
1841 goto err_giveback;
1842 }
1843
1844 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1845 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1846 "HC halted, freeing TD manually.");
1847 for (i = urb_priv->num_tds_done;
1848 i < urb_priv->num_tds;
1849 i++) {
1850 td = &urb_priv->td[i];
1851 if (!list_empty(&td->td_list))
1852 list_del_init(&td->td_list);
1853 if (!list_empty(&td->cancelled_td_list))
1854 list_del_init(&td->cancelled_td_list);
1855 }
1856 goto err_giveback;
1857 }
1858
1859 i = urb_priv->num_tds_done;
1860 if (i < urb_priv->num_tds)
1861 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1862 "Cancel URB %p, dev %s, ep 0x%x, "
1863 "starting at offset 0x%llx",
1864 urb, urb->dev->devpath,
1865 urb->ep->desc.bEndpointAddress,
1866 (unsigned long long) xhci_trb_virt_to_dma(
1867 urb_priv->td[i].start_seg,
1868 urb_priv->td[i].first_trb));
1869
1870 for (; i < urb_priv->num_tds; i++) {
1871 td = &urb_priv->td[i];
1872 /* TD can already be on cancelled list if ep halted on it */
1873 if (list_empty(&td->cancelled_td_list)) {
1874 td->cancel_status = TD_DIRTY;
1875 list_add_tail(&td->cancelled_td_list,
1876 &ep->cancelled_td_list);
1877 }
1878 }
1879
1880 /* Queue a stop endpoint command, but only if this is
1881 * the first cancellation to be handled.
1882 */
1883 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1884 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1885 if (!command) {
1886 ret = -ENOMEM;
1887 goto done;
1888 }
1889 ep->ep_state |= EP_STOP_CMD_PENDING;
1890 ep->stop_cmd_timer.expires = jiffies +
1891 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1892 add_timer(&ep->stop_cmd_timer);
1893 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1894 ep_index, 0);
1895 xhci_ring_cmd_db(xhci);
1896 }
1897 done:
1898 spin_unlock_irqrestore(&xhci->lock, flags);
1899 return ret;
1900
1901 err_giveback:
1902 if (urb_priv)
1903 xhci_urb_free_priv(urb_priv);
1904 usb_hcd_unlink_urb_from_ep(hcd, urb);
1905 spin_unlock_irqrestore(&xhci->lock, flags);
1906 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1907 return ret;
1908 }
1909
1910 /* Drop an endpoint from a new bandwidth configuration for this device.
1911 * Only one call to this function is allowed per endpoint before
1912 * check_bandwidth() or reset_bandwidth() must be called.
1913 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1914 * add the endpoint to the schedule with possibly new parameters denoted by a
1915 * different endpoint descriptor in usb_host_endpoint.
1916 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1917 * not allowed.
1918 *
1919 * The USB core will not allow URBs to be queued to an endpoint that is being
1920 * disabled, so there's no need for mutual exclusion to protect
1921 * the xhci->devs[slot_id] structure.
1922 */
xhci_drop_endpoint(struct usb_hcd * hcd,struct usb_device * udev,struct usb_host_endpoint * ep)1923 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1924 struct usb_host_endpoint *ep)
1925 {
1926 struct xhci_hcd *xhci;
1927 struct xhci_container_ctx *in_ctx, *out_ctx;
1928 struct xhci_input_control_ctx *ctrl_ctx;
1929 unsigned int ep_index;
1930 struct xhci_ep_ctx *ep_ctx;
1931 u32 drop_flag;
1932 u32 new_add_flags, new_drop_flags;
1933 int ret;
1934
1935 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1936 if (ret <= 0)
1937 return ret;
1938 xhci = hcd_to_xhci(hcd);
1939 if (xhci->xhc_state & XHCI_STATE_DYING)
1940 return -ENODEV;
1941
1942 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1943 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1944 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1945 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1946 __func__, drop_flag);
1947 return 0;
1948 }
1949
1950 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1951 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1952 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1953 if (!ctrl_ctx) {
1954 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1955 __func__);
1956 return 0;
1957 }
1958
1959 ep_index = xhci_get_endpoint_index(&ep->desc);
1960 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1961 /* If the HC already knows the endpoint is disabled,
1962 * or the HCD has noted it is disabled, ignore this request
1963 */
1964 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1965 le32_to_cpu(ctrl_ctx->drop_flags) &
1966 xhci_get_endpoint_flag(&ep->desc)) {
1967 /* Do not warn when called after a usb_device_reset */
1968 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1969 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1970 __func__, ep);
1971 return 0;
1972 }
1973
1974 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1975 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1976
1977 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1978 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1979
1980 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1981
1982 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1983
1984 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1985 (unsigned int) ep->desc.bEndpointAddress,
1986 udev->slot_id,
1987 (unsigned int) new_drop_flags,
1988 (unsigned int) new_add_flags);
1989 return 0;
1990 }
1991 EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1992
1993 /* Add an endpoint to a new possible bandwidth configuration for this device.
1994 * Only one call to this function is allowed per endpoint before
1995 * check_bandwidth() or reset_bandwidth() must be called.
1996 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1997 * add the endpoint to the schedule with possibly new parameters denoted by a
1998 * different endpoint descriptor in usb_host_endpoint.
1999 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
2000 * not allowed.
2001 *
2002 * The USB core will not allow URBs to be queued to an endpoint until the
2003 * configuration or alt setting is installed in the device, so there's no need
2004 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
2005 */
xhci_add_endpoint(struct usb_hcd * hcd,struct usb_device * udev,struct usb_host_endpoint * ep)2006 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2007 struct usb_host_endpoint *ep)
2008 {
2009 struct xhci_hcd *xhci;
2010 struct xhci_container_ctx *in_ctx;
2011 unsigned int ep_index;
2012 struct xhci_input_control_ctx *ctrl_ctx;
2013 struct xhci_ep_ctx *ep_ctx;
2014 u32 added_ctxs;
2015 u32 new_add_flags, new_drop_flags;
2016 struct xhci_virt_device *virt_dev;
2017 int ret = 0;
2018
2019 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
2020 if (ret <= 0) {
2021 /* So we won't queue a reset ep command for a root hub */
2022 ep->hcpriv = NULL;
2023 return ret;
2024 }
2025 xhci = hcd_to_xhci(hcd);
2026 if (xhci->xhc_state & XHCI_STATE_DYING)
2027 return -ENODEV;
2028
2029 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
2030 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
2031 /* FIXME when we have to issue an evaluate endpoint command to
2032 * deal with ep0 max packet size changing once we get the
2033 * descriptors
2034 */
2035 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
2036 __func__, added_ctxs);
2037 return 0;
2038 }
2039
2040 virt_dev = xhci->devs[udev->slot_id];
2041 in_ctx = virt_dev->in_ctx;
2042 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2043 if (!ctrl_ctx) {
2044 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2045 __func__);
2046 return 0;
2047 }
2048
2049 ep_index = xhci_get_endpoint_index(&ep->desc);
2050 /* If this endpoint is already in use, and the upper layers are trying
2051 * to add it again without dropping it, reject the addition.
2052 */
2053 if (virt_dev->eps[ep_index].ring &&
2054 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
2055 xhci_warn(xhci, "Trying to add endpoint 0x%x "
2056 "without dropping it.\n",
2057 (unsigned int) ep->desc.bEndpointAddress);
2058 return -EINVAL;
2059 }
2060
2061 /* If the HCD has already noted the endpoint is enabled,
2062 * ignore this request.
2063 */
2064 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
2065 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
2066 __func__, ep);
2067 return 0;
2068 }
2069
2070 /*
2071 * Configuration and alternate setting changes must be done in
2072 * process context, not interrupt context (or so documenation
2073 * for usb_set_interface() and usb_set_configuration() claim).
2074 */
2075 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
2076 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
2077 __func__, ep->desc.bEndpointAddress);
2078 return -ENOMEM;
2079 }
2080
2081 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
2082 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2083
2084 /* If xhci_endpoint_disable() was called for this endpoint, but the
2085 * xHC hasn't been notified yet through the check_bandwidth() call,
2086 * this re-adds a new state for the endpoint from the new endpoint
2087 * descriptors. We must drop and re-add this endpoint, so we leave the
2088 * drop flags alone.
2089 */
2090 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2091
2092 /* Store the usb_device pointer for later use */
2093 ep->hcpriv = udev;
2094
2095 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
2096 trace_xhci_add_endpoint(ep_ctx);
2097
2098 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2099 (unsigned int) ep->desc.bEndpointAddress,
2100 udev->slot_id,
2101 (unsigned int) new_drop_flags,
2102 (unsigned int) new_add_flags);
2103 return 0;
2104 }
2105 EXPORT_SYMBOL_GPL(xhci_add_endpoint);
2106
xhci_zero_in_ctx(struct xhci_hcd * xhci,struct xhci_virt_device * virt_dev)2107 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2108 {
2109 struct xhci_input_control_ctx *ctrl_ctx;
2110 struct xhci_ep_ctx *ep_ctx;
2111 struct xhci_slot_ctx *slot_ctx;
2112 int i;
2113
2114 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2115 if (!ctrl_ctx) {
2116 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2117 __func__);
2118 return;
2119 }
2120
2121 /* When a device's add flag and drop flag are zero, any subsequent
2122 * configure endpoint command will leave that endpoint's state
2123 * untouched. Make sure we don't leave any old state in the input
2124 * endpoint contexts.
2125 */
2126 ctrl_ctx->drop_flags = 0;
2127 ctrl_ctx->add_flags = 0;
2128 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2129 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2130 /* Endpoint 0 is always valid */
2131 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2132 for (i = 1; i < 31; i++) {
2133 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2134 ep_ctx->ep_info = 0;
2135 ep_ctx->ep_info2 = 0;
2136 ep_ctx->deq = 0;
2137 ep_ctx->tx_info = 0;
2138 }
2139 }
2140
xhci_configure_endpoint_result(struct xhci_hcd * xhci,struct usb_device * udev,u32 * cmd_status)2141 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2142 struct usb_device *udev, u32 *cmd_status)
2143 {
2144 int ret;
2145
2146 switch (*cmd_status) {
2147 case COMP_COMMAND_ABORTED:
2148 case COMP_COMMAND_RING_STOPPED:
2149 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2150 ret = -ETIME;
2151 break;
2152 case COMP_RESOURCE_ERROR:
2153 dev_warn(&udev->dev,
2154 "Not enough host controller resources for new device state.\n");
2155 ret = -ENOMEM;
2156 /* FIXME: can we allocate more resources for the HC? */
2157 break;
2158 case COMP_BANDWIDTH_ERROR:
2159 case COMP_SECONDARY_BANDWIDTH_ERROR:
2160 dev_warn(&udev->dev,
2161 "Not enough bandwidth for new device state.\n");
2162 ret = -ENOSPC;
2163 /* FIXME: can we go back to the old state? */
2164 break;
2165 case COMP_TRB_ERROR:
2166 /* the HCD set up something wrong */
2167 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2168 "add flag = 1, "
2169 "and endpoint is not disabled.\n");
2170 ret = -EINVAL;
2171 break;
2172 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2173 dev_warn(&udev->dev,
2174 "ERROR: Incompatible device for endpoint configure command.\n");
2175 ret = -ENODEV;
2176 break;
2177 case COMP_SUCCESS:
2178 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2179 "Successful Endpoint Configure command");
2180 ret = 0;
2181 break;
2182 default:
2183 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2184 *cmd_status);
2185 ret = -EINVAL;
2186 break;
2187 }
2188 return ret;
2189 }
2190
xhci_evaluate_context_result(struct xhci_hcd * xhci,struct usb_device * udev,u32 * cmd_status)2191 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2192 struct usb_device *udev, u32 *cmd_status)
2193 {
2194 int ret;
2195
2196 switch (*cmd_status) {
2197 case COMP_COMMAND_ABORTED:
2198 case COMP_COMMAND_RING_STOPPED:
2199 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2200 ret = -ETIME;
2201 break;
2202 case COMP_PARAMETER_ERROR:
2203 dev_warn(&udev->dev,
2204 "WARN: xHCI driver setup invalid evaluate context command.\n");
2205 ret = -EINVAL;
2206 break;
2207 case COMP_SLOT_NOT_ENABLED_ERROR:
2208 dev_warn(&udev->dev,
2209 "WARN: slot not enabled for evaluate context command.\n");
2210 ret = -EINVAL;
2211 break;
2212 case COMP_CONTEXT_STATE_ERROR:
2213 dev_warn(&udev->dev,
2214 "WARN: invalid context state for evaluate context command.\n");
2215 ret = -EINVAL;
2216 break;
2217 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2218 dev_warn(&udev->dev,
2219 "ERROR: Incompatible device for evaluate context command.\n");
2220 ret = -ENODEV;
2221 break;
2222 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2223 /* Max Exit Latency too large error */
2224 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2225 ret = -EINVAL;
2226 break;
2227 case COMP_SUCCESS:
2228 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2229 "Successful evaluate context command");
2230 ret = 0;
2231 break;
2232 default:
2233 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2234 *cmd_status);
2235 ret = -EINVAL;
2236 break;
2237 }
2238 return ret;
2239 }
2240
xhci_count_num_new_endpoints(struct xhci_hcd * xhci,struct xhci_input_control_ctx * ctrl_ctx)2241 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2242 struct xhci_input_control_ctx *ctrl_ctx)
2243 {
2244 u32 valid_add_flags;
2245 u32 valid_drop_flags;
2246
2247 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2248 * (bit 1). The default control endpoint is added during the Address
2249 * Device command and is never removed until the slot is disabled.
2250 */
2251 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2252 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2253
2254 /* Use hweight32 to count the number of ones in the add flags, or
2255 * number of endpoints added. Don't count endpoints that are changed
2256 * (both added and dropped).
2257 */
2258 return hweight32(valid_add_flags) -
2259 hweight32(valid_add_flags & valid_drop_flags);
2260 }
2261
xhci_count_num_dropped_endpoints(struct xhci_hcd * xhci,struct xhci_input_control_ctx * ctrl_ctx)2262 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2263 struct xhci_input_control_ctx *ctrl_ctx)
2264 {
2265 u32 valid_add_flags;
2266 u32 valid_drop_flags;
2267
2268 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2269 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2270
2271 return hweight32(valid_drop_flags) -
2272 hweight32(valid_add_flags & valid_drop_flags);
2273 }
2274
2275 /*
2276 * We need to reserve the new number of endpoints before the configure endpoint
2277 * command completes. We can't subtract the dropped endpoints from the number
2278 * of active endpoints until the command completes because we can oversubscribe
2279 * the host in this case:
2280 *
2281 * - the first configure endpoint command drops more endpoints than it adds
2282 * - a second configure endpoint command that adds more endpoints is queued
2283 * - the first configure endpoint command fails, so the config is unchanged
2284 * - the second command may succeed, even though there isn't enough resources
2285 *
2286 * Must be called with xhci->lock held.
2287 */
xhci_reserve_host_resources(struct xhci_hcd * xhci,struct xhci_input_control_ctx * ctrl_ctx)2288 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2289 struct xhci_input_control_ctx *ctrl_ctx)
2290 {
2291 u32 added_eps;
2292
2293 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2294 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2295 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2296 "Not enough ep ctxs: "
2297 "%u active, need to add %u, limit is %u.",
2298 xhci->num_active_eps, added_eps,
2299 xhci->limit_active_eps);
2300 return -ENOMEM;
2301 }
2302 xhci->num_active_eps += added_eps;
2303 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2304 "Adding %u ep ctxs, %u now active.", added_eps,
2305 xhci->num_active_eps);
2306 return 0;
2307 }
2308
2309 /*
2310 * The configure endpoint was failed by the xHC for some other reason, so we
2311 * need to revert the resources that failed configuration would have used.
2312 *
2313 * Must be called with xhci->lock held.
2314 */
xhci_free_host_resources(struct xhci_hcd * xhci,struct xhci_input_control_ctx * ctrl_ctx)2315 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2316 struct xhci_input_control_ctx *ctrl_ctx)
2317 {
2318 u32 num_failed_eps;
2319
2320 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2321 xhci->num_active_eps -= num_failed_eps;
2322 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2323 "Removing %u failed ep ctxs, %u now active.",
2324 num_failed_eps,
2325 xhci->num_active_eps);
2326 }
2327
2328 /*
2329 * Now that the command has completed, clean up the active endpoint count by
2330 * subtracting out the endpoints that were dropped (but not changed).
2331 *
2332 * Must be called with xhci->lock held.
2333 */
xhci_finish_resource_reservation(struct xhci_hcd * xhci,struct xhci_input_control_ctx * ctrl_ctx)2334 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2335 struct xhci_input_control_ctx *ctrl_ctx)
2336 {
2337 u32 num_dropped_eps;
2338
2339 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2340 xhci->num_active_eps -= num_dropped_eps;
2341 if (num_dropped_eps)
2342 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2343 "Removing %u dropped ep ctxs, %u now active.",
2344 num_dropped_eps,
2345 xhci->num_active_eps);
2346 }
2347
xhci_get_block_size(struct usb_device * udev)2348 static unsigned int xhci_get_block_size(struct usb_device *udev)
2349 {
2350 switch (udev->speed) {
2351 case USB_SPEED_LOW:
2352 case USB_SPEED_FULL:
2353 return FS_BLOCK;
2354 case USB_SPEED_HIGH:
2355 return HS_BLOCK;
2356 case USB_SPEED_SUPER:
2357 case USB_SPEED_SUPER_PLUS:
2358 return SS_BLOCK;
2359 case USB_SPEED_UNKNOWN:
2360 case USB_SPEED_WIRELESS:
2361 default:
2362 /* Should never happen */
2363 return 1;
2364 }
2365 }
2366
2367 static unsigned int
xhci_get_largest_overhead(struct xhci_interval_bw * interval_bw)2368 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2369 {
2370 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2371 return LS_OVERHEAD;
2372 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2373 return FS_OVERHEAD;
2374 return HS_OVERHEAD;
2375 }
2376
2377 /* If we are changing a LS/FS device under a HS hub,
2378 * make sure (if we are activating a new TT) that the HS bus has enough
2379 * bandwidth for this new TT.
2380 */
xhci_check_tt_bw_table(struct xhci_hcd * xhci,struct xhci_virt_device * virt_dev,int old_active_eps)2381 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2382 struct xhci_virt_device *virt_dev,
2383 int old_active_eps)
2384 {
2385 struct xhci_interval_bw_table *bw_table;
2386 struct xhci_tt_bw_info *tt_info;
2387
2388 /* Find the bandwidth table for the root port this TT is attached to. */
2389 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2390 tt_info = virt_dev->tt_info;
2391 /* If this TT already had active endpoints, the bandwidth for this TT
2392 * has already been added. Removing all periodic endpoints (and thus
2393 * making the TT enactive) will only decrease the bandwidth used.
2394 */
2395 if (old_active_eps)
2396 return 0;
2397 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2398 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2399 return -ENOMEM;
2400 return 0;
2401 }
2402 /* Not sure why we would have no new active endpoints...
2403 *
2404 * Maybe because of an Evaluate Context change for a hub update or a
2405 * control endpoint 0 max packet size change?
2406 * FIXME: skip the bandwidth calculation in that case.
2407 */
2408 return 0;
2409 }
2410
xhci_check_ss_bw(struct xhci_hcd * xhci,struct xhci_virt_device * virt_dev)2411 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2412 struct xhci_virt_device *virt_dev)
2413 {
2414 unsigned int bw_reserved;
2415
2416 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2417 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2418 return -ENOMEM;
2419
2420 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2421 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2422 return -ENOMEM;
2423
2424 return 0;
2425 }
2426
2427 /*
2428 * This algorithm is a very conservative estimate of the worst-case scheduling
2429 * scenario for any one interval. The hardware dynamically schedules the
2430 * packets, so we can't tell which microframe could be the limiting factor in
2431 * the bandwidth scheduling. This only takes into account periodic endpoints.
2432 *
2433 * Obviously, we can't solve an NP complete problem to find the minimum worst
2434 * case scenario. Instead, we come up with an estimate that is no less than
2435 * the worst case bandwidth used for any one microframe, but may be an
2436 * over-estimate.
2437 *
2438 * We walk the requirements for each endpoint by interval, starting with the
2439 * smallest interval, and place packets in the schedule where there is only one
2440 * possible way to schedule packets for that interval. In order to simplify
2441 * this algorithm, we record the largest max packet size for each interval, and
2442 * assume all packets will be that size.
2443 *
2444 * For interval 0, we obviously must schedule all packets for each interval.
2445 * The bandwidth for interval 0 is just the amount of data to be transmitted
2446 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2447 * the number of packets).
2448 *
2449 * For interval 1, we have two possible microframes to schedule those packets
2450 * in. For this algorithm, if we can schedule the same number of packets for
2451 * each possible scheduling opportunity (each microframe), we will do so. The
2452 * remaining number of packets will be saved to be transmitted in the gaps in
2453 * the next interval's scheduling sequence.
2454 *
2455 * As we move those remaining packets to be scheduled with interval 2 packets,
2456 * we have to double the number of remaining packets to transmit. This is
2457 * because the intervals are actually powers of 2, and we would be transmitting
2458 * the previous interval's packets twice in this interval. We also have to be
2459 * sure that when we look at the largest max packet size for this interval, we
2460 * also look at the largest max packet size for the remaining packets and take
2461 * the greater of the two.
2462 *
2463 * The algorithm continues to evenly distribute packets in each scheduling
2464 * opportunity, and push the remaining packets out, until we get to the last
2465 * interval. Then those packets and their associated overhead are just added
2466 * to the bandwidth used.
2467 */
xhci_check_bw_table(struct xhci_hcd * xhci,struct xhci_virt_device * virt_dev,int old_active_eps)2468 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2469 struct xhci_virt_device *virt_dev,
2470 int old_active_eps)
2471 {
2472 unsigned int bw_reserved;
2473 unsigned int max_bandwidth;
2474 unsigned int bw_used;
2475 unsigned int block_size;
2476 struct xhci_interval_bw_table *bw_table;
2477 unsigned int packet_size = 0;
2478 unsigned int overhead = 0;
2479 unsigned int packets_transmitted = 0;
2480 unsigned int packets_remaining = 0;
2481 unsigned int i;
2482
2483 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2484 return xhci_check_ss_bw(xhci, virt_dev);
2485
2486 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2487 max_bandwidth = HS_BW_LIMIT;
2488 /* Convert percent of bus BW reserved to blocks reserved */
2489 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2490 } else {
2491 max_bandwidth = FS_BW_LIMIT;
2492 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2493 }
2494
2495 bw_table = virt_dev->bw_table;
2496 /* We need to translate the max packet size and max ESIT payloads into
2497 * the units the hardware uses.
2498 */
2499 block_size = xhci_get_block_size(virt_dev->udev);
2500
2501 /* If we are manipulating a LS/FS device under a HS hub, double check
2502 * that the HS bus has enough bandwidth if we are activing a new TT.
2503 */
2504 if (virt_dev->tt_info) {
2505 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2506 "Recalculating BW for rootport %u",
2507 virt_dev->real_port);
2508 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2509 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2510 "newly activated TT.\n");
2511 return -ENOMEM;
2512 }
2513 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2514 "Recalculating BW for TT slot %u port %u",
2515 virt_dev->tt_info->slot_id,
2516 virt_dev->tt_info->ttport);
2517 } else {
2518 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2519 "Recalculating BW for rootport %u",
2520 virt_dev->real_port);
2521 }
2522
2523 /* Add in how much bandwidth will be used for interval zero, or the
2524 * rounded max ESIT payload + number of packets * largest overhead.
2525 */
2526 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2527 bw_table->interval_bw[0].num_packets *
2528 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2529
2530 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2531 unsigned int bw_added;
2532 unsigned int largest_mps;
2533 unsigned int interval_overhead;
2534
2535 /*
2536 * How many packets could we transmit in this interval?
2537 * If packets didn't fit in the previous interval, we will need
2538 * to transmit that many packets twice within this interval.
2539 */
2540 packets_remaining = 2 * packets_remaining +
2541 bw_table->interval_bw[i].num_packets;
2542
2543 /* Find the largest max packet size of this or the previous
2544 * interval.
2545 */
2546 if (list_empty(&bw_table->interval_bw[i].endpoints))
2547 largest_mps = 0;
2548 else {
2549 struct xhci_virt_ep *virt_ep;
2550 struct list_head *ep_entry;
2551
2552 ep_entry = bw_table->interval_bw[i].endpoints.next;
2553 virt_ep = list_entry(ep_entry,
2554 struct xhci_virt_ep, bw_endpoint_list);
2555 /* Convert to blocks, rounding up */
2556 largest_mps = DIV_ROUND_UP(
2557 virt_ep->bw_info.max_packet_size,
2558 block_size);
2559 }
2560 if (largest_mps > packet_size)
2561 packet_size = largest_mps;
2562
2563 /* Use the larger overhead of this or the previous interval. */
2564 interval_overhead = xhci_get_largest_overhead(
2565 &bw_table->interval_bw[i]);
2566 if (interval_overhead > overhead)
2567 overhead = interval_overhead;
2568
2569 /* How many packets can we evenly distribute across
2570 * (1 << (i + 1)) possible scheduling opportunities?
2571 */
2572 packets_transmitted = packets_remaining >> (i + 1);
2573
2574 /* Add in the bandwidth used for those scheduled packets */
2575 bw_added = packets_transmitted * (overhead + packet_size);
2576
2577 /* How many packets do we have remaining to transmit? */
2578 packets_remaining = packets_remaining % (1 << (i + 1));
2579
2580 /* What largest max packet size should those packets have? */
2581 /* If we've transmitted all packets, don't carry over the
2582 * largest packet size.
2583 */
2584 if (packets_remaining == 0) {
2585 packet_size = 0;
2586 overhead = 0;
2587 } else if (packets_transmitted > 0) {
2588 /* Otherwise if we do have remaining packets, and we've
2589 * scheduled some packets in this interval, take the
2590 * largest max packet size from endpoints with this
2591 * interval.
2592 */
2593 packet_size = largest_mps;
2594 overhead = interval_overhead;
2595 }
2596 /* Otherwise carry over packet_size and overhead from the last
2597 * time we had a remainder.
2598 */
2599 bw_used += bw_added;
2600 if (bw_used > max_bandwidth) {
2601 xhci_warn(xhci, "Not enough bandwidth. "
2602 "Proposed: %u, Max: %u\n",
2603 bw_used, max_bandwidth);
2604 return -ENOMEM;
2605 }
2606 }
2607 /*
2608 * Ok, we know we have some packets left over after even-handedly
2609 * scheduling interval 15. We don't know which microframes they will
2610 * fit into, so we over-schedule and say they will be scheduled every
2611 * microframe.
2612 */
2613 if (packets_remaining > 0)
2614 bw_used += overhead + packet_size;
2615
2616 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2617 unsigned int port_index = virt_dev->real_port - 1;
2618
2619 /* OK, we're manipulating a HS device attached to a
2620 * root port bandwidth domain. Include the number of active TTs
2621 * in the bandwidth used.
2622 */
2623 bw_used += TT_HS_OVERHEAD *
2624 xhci->rh_bw[port_index].num_active_tts;
2625 }
2626
2627 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2628 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2629 "Available: %u " "percent",
2630 bw_used, max_bandwidth, bw_reserved,
2631 (max_bandwidth - bw_used - bw_reserved) * 100 /
2632 max_bandwidth);
2633
2634 bw_used += bw_reserved;
2635 if (bw_used > max_bandwidth) {
2636 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2637 bw_used, max_bandwidth);
2638 return -ENOMEM;
2639 }
2640
2641 bw_table->bw_used = bw_used;
2642 return 0;
2643 }
2644
xhci_is_async_ep(unsigned int ep_type)2645 static bool xhci_is_async_ep(unsigned int ep_type)
2646 {
2647 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2648 ep_type != ISOC_IN_EP &&
2649 ep_type != INT_IN_EP);
2650 }
2651
xhci_is_sync_in_ep(unsigned int ep_type)2652 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2653 {
2654 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2655 }
2656
xhci_get_ss_bw_consumed(struct xhci_bw_info * ep_bw)2657 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2658 {
2659 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2660
2661 if (ep_bw->ep_interval == 0)
2662 return SS_OVERHEAD_BURST +
2663 (ep_bw->mult * ep_bw->num_packets *
2664 (SS_OVERHEAD + mps));
2665 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2666 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2667 1 << ep_bw->ep_interval);
2668
2669 }
2670
xhci_drop_ep_from_interval_table(struct xhci_hcd * xhci,struct xhci_bw_info * ep_bw,struct xhci_interval_bw_table * bw_table,struct usb_device * udev,struct xhci_virt_ep * virt_ep,struct xhci_tt_bw_info * tt_info)2671 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2672 struct xhci_bw_info *ep_bw,
2673 struct xhci_interval_bw_table *bw_table,
2674 struct usb_device *udev,
2675 struct xhci_virt_ep *virt_ep,
2676 struct xhci_tt_bw_info *tt_info)
2677 {
2678 struct xhci_interval_bw *interval_bw;
2679 int normalized_interval;
2680
2681 if (xhci_is_async_ep(ep_bw->type))
2682 return;
2683
2684 if (udev->speed >= USB_SPEED_SUPER) {
2685 if (xhci_is_sync_in_ep(ep_bw->type))
2686 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2687 xhci_get_ss_bw_consumed(ep_bw);
2688 else
2689 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2690 xhci_get_ss_bw_consumed(ep_bw);
2691 return;
2692 }
2693
2694 /* SuperSpeed endpoints never get added to intervals in the table, so
2695 * this check is only valid for HS/FS/LS devices.
2696 */
2697 if (list_empty(&virt_ep->bw_endpoint_list))
2698 return;
2699 /* For LS/FS devices, we need to translate the interval expressed in
2700 * microframes to frames.
2701 */
2702 if (udev->speed == USB_SPEED_HIGH)
2703 normalized_interval = ep_bw->ep_interval;
2704 else
2705 normalized_interval = ep_bw->ep_interval - 3;
2706
2707 if (normalized_interval == 0)
2708 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2709 interval_bw = &bw_table->interval_bw[normalized_interval];
2710 interval_bw->num_packets -= ep_bw->num_packets;
2711 switch (udev->speed) {
2712 case USB_SPEED_LOW:
2713 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2714 break;
2715 case USB_SPEED_FULL:
2716 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2717 break;
2718 case USB_SPEED_HIGH:
2719 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2720 break;
2721 case USB_SPEED_SUPER:
2722 case USB_SPEED_SUPER_PLUS:
2723 case USB_SPEED_UNKNOWN:
2724 case USB_SPEED_WIRELESS:
2725 /* Should never happen because only LS/FS/HS endpoints will get
2726 * added to the endpoint list.
2727 */
2728 return;
2729 }
2730 if (tt_info)
2731 tt_info->active_eps -= 1;
2732 list_del_init(&virt_ep->bw_endpoint_list);
2733 }
2734
xhci_add_ep_to_interval_table(struct xhci_hcd * xhci,struct xhci_bw_info * ep_bw,struct xhci_interval_bw_table * bw_table,struct usb_device * udev,struct xhci_virt_ep * virt_ep,struct xhci_tt_bw_info * tt_info)2735 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2736 struct xhci_bw_info *ep_bw,
2737 struct xhci_interval_bw_table *bw_table,
2738 struct usb_device *udev,
2739 struct xhci_virt_ep *virt_ep,
2740 struct xhci_tt_bw_info *tt_info)
2741 {
2742 struct xhci_interval_bw *interval_bw;
2743 struct xhci_virt_ep *smaller_ep;
2744 int normalized_interval;
2745
2746 if (xhci_is_async_ep(ep_bw->type))
2747 return;
2748
2749 if (udev->speed == USB_SPEED_SUPER) {
2750 if (xhci_is_sync_in_ep(ep_bw->type))
2751 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2752 xhci_get_ss_bw_consumed(ep_bw);
2753 else
2754 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2755 xhci_get_ss_bw_consumed(ep_bw);
2756 return;
2757 }
2758
2759 /* For LS/FS devices, we need to translate the interval expressed in
2760 * microframes to frames.
2761 */
2762 if (udev->speed == USB_SPEED_HIGH)
2763 normalized_interval = ep_bw->ep_interval;
2764 else
2765 normalized_interval = ep_bw->ep_interval - 3;
2766
2767 if (normalized_interval == 0)
2768 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2769 interval_bw = &bw_table->interval_bw[normalized_interval];
2770 interval_bw->num_packets += ep_bw->num_packets;
2771 switch (udev->speed) {
2772 case USB_SPEED_LOW:
2773 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2774 break;
2775 case USB_SPEED_FULL:
2776 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2777 break;
2778 case USB_SPEED_HIGH:
2779 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2780 break;
2781 case USB_SPEED_SUPER:
2782 case USB_SPEED_SUPER_PLUS:
2783 case USB_SPEED_UNKNOWN:
2784 case USB_SPEED_WIRELESS:
2785 /* Should never happen because only LS/FS/HS endpoints will get
2786 * added to the endpoint list.
2787 */
2788 return;
2789 }
2790
2791 if (tt_info)
2792 tt_info->active_eps += 1;
2793 /* Insert the endpoint into the list, largest max packet size first. */
2794 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2795 bw_endpoint_list) {
2796 if (ep_bw->max_packet_size >=
2797 smaller_ep->bw_info.max_packet_size) {
2798 /* Add the new ep before the smaller endpoint */
2799 list_add_tail(&virt_ep->bw_endpoint_list,
2800 &smaller_ep->bw_endpoint_list);
2801 return;
2802 }
2803 }
2804 /* Add the new endpoint at the end of the list. */
2805 list_add_tail(&virt_ep->bw_endpoint_list,
2806 &interval_bw->endpoints);
2807 }
2808
xhci_update_tt_active_eps(struct xhci_hcd * xhci,struct xhci_virt_device * virt_dev,int old_active_eps)2809 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2810 struct xhci_virt_device *virt_dev,
2811 int old_active_eps)
2812 {
2813 struct xhci_root_port_bw_info *rh_bw_info;
2814 if (!virt_dev->tt_info)
2815 return;
2816
2817 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2818 if (old_active_eps == 0 &&
2819 virt_dev->tt_info->active_eps != 0) {
2820 rh_bw_info->num_active_tts += 1;
2821 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2822 } else if (old_active_eps != 0 &&
2823 virt_dev->tt_info->active_eps == 0) {
2824 rh_bw_info->num_active_tts -= 1;
2825 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2826 }
2827 }
2828
xhci_reserve_bandwidth(struct xhci_hcd * xhci,struct xhci_virt_device * virt_dev,struct xhci_container_ctx * in_ctx)2829 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2830 struct xhci_virt_device *virt_dev,
2831 struct xhci_container_ctx *in_ctx)
2832 {
2833 struct xhci_bw_info ep_bw_info[31];
2834 int i;
2835 struct xhci_input_control_ctx *ctrl_ctx;
2836 int old_active_eps = 0;
2837
2838 if (virt_dev->tt_info)
2839 old_active_eps = virt_dev->tt_info->active_eps;
2840
2841 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2842 if (!ctrl_ctx) {
2843 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2844 __func__);
2845 return -ENOMEM;
2846 }
2847
2848 for (i = 0; i < 31; i++) {
2849 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2850 continue;
2851
2852 /* Make a copy of the BW info in case we need to revert this */
2853 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2854 sizeof(ep_bw_info[i]));
2855 /* Drop the endpoint from the interval table if the endpoint is
2856 * being dropped or changed.
2857 */
2858 if (EP_IS_DROPPED(ctrl_ctx, i))
2859 xhci_drop_ep_from_interval_table(xhci,
2860 &virt_dev->eps[i].bw_info,
2861 virt_dev->bw_table,
2862 virt_dev->udev,
2863 &virt_dev->eps[i],
2864 virt_dev->tt_info);
2865 }
2866 /* Overwrite the information stored in the endpoints' bw_info */
2867 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2868 for (i = 0; i < 31; i++) {
2869 /* Add any changed or added endpoints to the interval table */
2870 if (EP_IS_ADDED(ctrl_ctx, i))
2871 xhci_add_ep_to_interval_table(xhci,
2872 &virt_dev->eps[i].bw_info,
2873 virt_dev->bw_table,
2874 virt_dev->udev,
2875 &virt_dev->eps[i],
2876 virt_dev->tt_info);
2877 }
2878
2879 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2880 /* Ok, this fits in the bandwidth we have.
2881 * Update the number of active TTs.
2882 */
2883 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2884 return 0;
2885 }
2886
2887 /* We don't have enough bandwidth for this, revert the stored info. */
2888 for (i = 0; i < 31; i++) {
2889 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2890 continue;
2891
2892 /* Drop the new copies of any added or changed endpoints from
2893 * the interval table.
2894 */
2895 if (EP_IS_ADDED(ctrl_ctx, i)) {
2896 xhci_drop_ep_from_interval_table(xhci,
2897 &virt_dev->eps[i].bw_info,
2898 virt_dev->bw_table,
2899 virt_dev->udev,
2900 &virt_dev->eps[i],
2901 virt_dev->tt_info);
2902 }
2903 /* Revert the endpoint back to its old information */
2904 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2905 sizeof(ep_bw_info[i]));
2906 /* Add any changed or dropped endpoints back into the table */
2907 if (EP_IS_DROPPED(ctrl_ctx, i))
2908 xhci_add_ep_to_interval_table(xhci,
2909 &virt_dev->eps[i].bw_info,
2910 virt_dev->bw_table,
2911 virt_dev->udev,
2912 &virt_dev->eps[i],
2913 virt_dev->tt_info);
2914 }
2915 return -ENOMEM;
2916 }
2917
2918
2919 /* Issue a configure endpoint command or evaluate context command
2920 * and wait for it to finish.
2921 */
xhci_configure_endpoint(struct xhci_hcd * xhci,struct usb_device * udev,struct xhci_command * command,bool ctx_change,bool must_succeed)2922 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2923 struct usb_device *udev,
2924 struct xhci_command *command,
2925 bool ctx_change, bool must_succeed)
2926 {
2927 int ret;
2928 unsigned long flags;
2929 struct xhci_input_control_ctx *ctrl_ctx;
2930 struct xhci_virt_device *virt_dev;
2931 struct xhci_slot_ctx *slot_ctx;
2932
2933 if (!command)
2934 return -EINVAL;
2935
2936 spin_lock_irqsave(&xhci->lock, flags);
2937
2938 if (xhci->xhc_state & XHCI_STATE_DYING) {
2939 spin_unlock_irqrestore(&xhci->lock, flags);
2940 return -ESHUTDOWN;
2941 }
2942
2943 virt_dev = xhci->devs[udev->slot_id];
2944
2945 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2946 if (!ctrl_ctx) {
2947 spin_unlock_irqrestore(&xhci->lock, flags);
2948 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2949 __func__);
2950 return -ENOMEM;
2951 }
2952
2953 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2954 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2955 spin_unlock_irqrestore(&xhci->lock, flags);
2956 xhci_warn(xhci, "Not enough host resources, "
2957 "active endpoint contexts = %u\n",
2958 xhci->num_active_eps);
2959 return -ENOMEM;
2960 }
2961 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2962 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2963 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2964 xhci_free_host_resources(xhci, ctrl_ctx);
2965 spin_unlock_irqrestore(&xhci->lock, flags);
2966 xhci_warn(xhci, "Not enough bandwidth\n");
2967 return -ENOMEM;
2968 }
2969
2970 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2971
2972 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2973 trace_xhci_configure_endpoint(slot_ctx);
2974
2975 if (!ctx_change)
2976 ret = xhci_queue_configure_endpoint(xhci, command,
2977 command->in_ctx->dma,
2978 udev->slot_id, must_succeed);
2979 else
2980 ret = xhci_queue_evaluate_context(xhci, command,
2981 command->in_ctx->dma,
2982 udev->slot_id, must_succeed);
2983 if (ret < 0) {
2984 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2985 xhci_free_host_resources(xhci, ctrl_ctx);
2986 spin_unlock_irqrestore(&xhci->lock, flags);
2987 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2988 "FIXME allocate a new ring segment");
2989 return -ENOMEM;
2990 }
2991 xhci_ring_cmd_db(xhci);
2992 spin_unlock_irqrestore(&xhci->lock, flags);
2993
2994 /* Wait for the configure endpoint command to complete */
2995 wait_for_completion(command->completion);
2996
2997 if (!ctx_change)
2998 ret = xhci_configure_endpoint_result(xhci, udev,
2999 &command->status);
3000 else
3001 ret = xhci_evaluate_context_result(xhci, udev,
3002 &command->status);
3003
3004 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3005 spin_lock_irqsave(&xhci->lock, flags);
3006 /* If the command failed, remove the reserved resources.
3007 * Otherwise, clean up the estimate to include dropped eps.
3008 */
3009 if (ret)
3010 xhci_free_host_resources(xhci, ctrl_ctx);
3011 else
3012 xhci_finish_resource_reservation(xhci, ctrl_ctx);
3013 spin_unlock_irqrestore(&xhci->lock, flags);
3014 }
3015 return ret;
3016 }
3017
xhci_check_bw_drop_ep_streams(struct xhci_hcd * xhci,struct xhci_virt_device * vdev,int i)3018 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
3019 struct xhci_virt_device *vdev, int i)
3020 {
3021 struct xhci_virt_ep *ep = &vdev->eps[i];
3022
3023 if (ep->ep_state & EP_HAS_STREAMS) {
3024 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
3025 xhci_get_endpoint_address(i));
3026 xhci_free_stream_info(xhci, ep->stream_info);
3027 ep->stream_info = NULL;
3028 ep->ep_state &= ~EP_HAS_STREAMS;
3029 }
3030 }
3031
3032 /* Called after one or more calls to xhci_add_endpoint() or
3033 * xhci_drop_endpoint(). If this call fails, the USB core is expected
3034 * to call xhci_reset_bandwidth().
3035 *
3036 * Since we are in the middle of changing either configuration or
3037 * installing a new alt setting, the USB core won't allow URBs to be
3038 * enqueued for any endpoint on the old config or interface. Nothing
3039 * else should be touching the xhci->devs[slot_id] structure, so we
3040 * don't need to take the xhci->lock for manipulating that.
3041 */
xhci_check_bandwidth(struct usb_hcd * hcd,struct usb_device * udev)3042 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3043 {
3044 int i;
3045 int ret = 0;
3046 struct xhci_hcd *xhci;
3047 struct xhci_virt_device *virt_dev;
3048 struct xhci_input_control_ctx *ctrl_ctx;
3049 struct xhci_slot_ctx *slot_ctx;
3050 struct xhci_command *command;
3051
3052 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3053 if (ret <= 0)
3054 return ret;
3055 xhci = hcd_to_xhci(hcd);
3056 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3057 (xhci->xhc_state & XHCI_STATE_REMOVING))
3058 return -ENODEV;
3059
3060 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3061 virt_dev = xhci->devs[udev->slot_id];
3062
3063 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3064 if (!command)
3065 return -ENOMEM;
3066
3067 command->in_ctx = virt_dev->in_ctx;
3068
3069 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3070 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3071 if (!ctrl_ctx) {
3072 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3073 __func__);
3074 ret = -ENOMEM;
3075 goto command_cleanup;
3076 }
3077 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3078 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3079 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3080
3081 /* Don't issue the command if there's no endpoints to update. */
3082 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3083 ctrl_ctx->drop_flags == 0) {
3084 ret = 0;
3085 goto command_cleanup;
3086 }
3087 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3088 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3089 for (i = 31; i >= 1; i--) {
3090 __le32 le32 = cpu_to_le32(BIT(i));
3091
3092 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3093 || (ctrl_ctx->add_flags & le32) || i == 1) {
3094 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3095 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3096 break;
3097 }
3098 }
3099
3100 ret = xhci_configure_endpoint(xhci, udev, command,
3101 false, false);
3102 if (ret)
3103 /* Callee should call reset_bandwidth() */
3104 goto command_cleanup;
3105
3106 /* Free any rings that were dropped, but not changed. */
3107 for (i = 1; i < 31; i++) {
3108 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3109 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3110 xhci_free_endpoint_ring(xhci, virt_dev, i);
3111 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3112 }
3113 }
3114 xhci_zero_in_ctx(xhci, virt_dev);
3115 /*
3116 * Install any rings for completely new endpoints or changed endpoints,
3117 * and free any old rings from changed endpoints.
3118 */
3119 for (i = 1; i < 31; i++) {
3120 if (!virt_dev->eps[i].new_ring)
3121 continue;
3122 /* Only free the old ring if it exists.
3123 * It may not if this is the first add of an endpoint.
3124 */
3125 if (virt_dev->eps[i].ring) {
3126 xhci_free_endpoint_ring(xhci, virt_dev, i);
3127 }
3128 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3129 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3130 virt_dev->eps[i].new_ring = NULL;
3131 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3132 }
3133 command_cleanup:
3134 kfree(command->completion);
3135 kfree(command);
3136
3137 return ret;
3138 }
3139 EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3140
xhci_reset_bandwidth(struct usb_hcd * hcd,struct usb_device * udev)3141 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3142 {
3143 struct xhci_hcd *xhci;
3144 struct xhci_virt_device *virt_dev;
3145 int i, ret;
3146
3147 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3148 if (ret <= 0)
3149 return;
3150 xhci = hcd_to_xhci(hcd);
3151
3152 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3153 virt_dev = xhci->devs[udev->slot_id];
3154 /* Free any rings allocated for added endpoints */
3155 for (i = 0; i < 31; i++) {
3156 if (virt_dev->eps[i].new_ring) {
3157 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3158 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3159 virt_dev->eps[i].new_ring = NULL;
3160 }
3161 }
3162 xhci_zero_in_ctx(xhci, virt_dev);
3163 }
3164 EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3165
xhci_setup_input_ctx_for_config_ep(struct xhci_hcd * xhci,struct xhci_container_ctx * in_ctx,struct xhci_container_ctx * out_ctx,struct xhci_input_control_ctx * ctrl_ctx,u32 add_flags,u32 drop_flags)3166 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3167 struct xhci_container_ctx *in_ctx,
3168 struct xhci_container_ctx *out_ctx,
3169 struct xhci_input_control_ctx *ctrl_ctx,
3170 u32 add_flags, u32 drop_flags)
3171 {
3172 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3173 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3174 xhci_slot_copy(xhci, in_ctx, out_ctx);
3175 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3176 }
3177
xhci_endpoint_disable(struct usb_hcd * hcd,struct usb_host_endpoint * host_ep)3178 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3179 struct usb_host_endpoint *host_ep)
3180 {
3181 struct xhci_hcd *xhci;
3182 struct xhci_virt_device *vdev;
3183 struct xhci_virt_ep *ep;
3184 struct usb_device *udev;
3185 unsigned long flags;
3186 unsigned int ep_index;
3187
3188 xhci = hcd_to_xhci(hcd);
3189 rescan:
3190 spin_lock_irqsave(&xhci->lock, flags);
3191
3192 udev = (struct usb_device *)host_ep->hcpriv;
3193 if (!udev || !udev->slot_id)
3194 goto done;
3195
3196 vdev = xhci->devs[udev->slot_id];
3197 if (!vdev)
3198 goto done;
3199
3200 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3201 ep = &vdev->eps[ep_index];
3202 if (!ep)
3203 goto done;
3204
3205 /* wait for hub_tt_work to finish clearing hub TT */
3206 if (ep->ep_state & EP_CLEARING_TT) {
3207 spin_unlock_irqrestore(&xhci->lock, flags);
3208 schedule_timeout_uninterruptible(1);
3209 goto rescan;
3210 }
3211
3212 if (ep->ep_state)
3213 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3214 ep->ep_state);
3215 done:
3216 host_ep->hcpriv = NULL;
3217 spin_unlock_irqrestore(&xhci->lock, flags);
3218 }
3219
3220 /*
3221 * Called after usb core issues a clear halt control message.
3222 * The host side of the halt should already be cleared by a reset endpoint
3223 * command issued when the STALL event was received.
3224 *
3225 * The reset endpoint command may only be issued to endpoints in the halted
3226 * state. For software that wishes to reset the data toggle or sequence number
3227 * of an endpoint that isn't in the halted state this function will issue a
3228 * configure endpoint command with the Drop and Add bits set for the target
3229 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3230 */
3231
xhci_endpoint_reset(struct usb_hcd * hcd,struct usb_host_endpoint * host_ep)3232 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3233 struct usb_host_endpoint *host_ep)
3234 {
3235 struct xhci_hcd *xhci;
3236 struct usb_device *udev;
3237 struct xhci_virt_device *vdev;
3238 struct xhci_virt_ep *ep;
3239 struct xhci_input_control_ctx *ctrl_ctx;
3240 struct xhci_command *stop_cmd, *cfg_cmd;
3241 unsigned int ep_index;
3242 unsigned long flags;
3243 u32 ep_flag;
3244 int err;
3245
3246 xhci = hcd_to_xhci(hcd);
3247 if (!host_ep->hcpriv)
3248 return;
3249 udev = (struct usb_device *) host_ep->hcpriv;
3250 vdev = xhci->devs[udev->slot_id];
3251
3252 /*
3253 * vdev may be lost due to xHC restore error and re-initialization
3254 * during S3/S4 resume. A new vdev will be allocated later by
3255 * xhci_discover_or_reset_device()
3256 */
3257 if (!udev->slot_id || !vdev)
3258 return;
3259 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3260 ep = &vdev->eps[ep_index];
3261 if (!ep)
3262 return;
3263
3264 /* Bail out if toggle is already being cleared by a endpoint reset */
3265 spin_lock_irqsave(&xhci->lock, flags);
3266 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3267 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3268 spin_unlock_irqrestore(&xhci->lock, flags);
3269 return;
3270 }
3271 spin_unlock_irqrestore(&xhci->lock, flags);
3272 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3273 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3274 usb_endpoint_xfer_isoc(&host_ep->desc))
3275 return;
3276
3277 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3278
3279 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3280 return;
3281
3282 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3283 if (!stop_cmd)
3284 return;
3285
3286 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3287 if (!cfg_cmd)
3288 goto cleanup;
3289
3290 spin_lock_irqsave(&xhci->lock, flags);
3291
3292 /* block queuing new trbs and ringing ep doorbell */
3293 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3294
3295 /*
3296 * Make sure endpoint ring is empty before resetting the toggle/seq.
3297 * Driver is required to synchronously cancel all transfer request.
3298 * Stop the endpoint to force xHC to update the output context
3299 */
3300
3301 if (!list_empty(&ep->ring->td_list)) {
3302 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3303 spin_unlock_irqrestore(&xhci->lock, flags);
3304 xhci_free_command(xhci, cfg_cmd);
3305 goto cleanup;
3306 }
3307
3308 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3309 ep_index, 0);
3310 if (err < 0) {
3311 spin_unlock_irqrestore(&xhci->lock, flags);
3312 xhci_free_command(xhci, cfg_cmd);
3313 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3314 __func__, err);
3315 goto cleanup;
3316 }
3317
3318 xhci_ring_cmd_db(xhci);
3319 spin_unlock_irqrestore(&xhci->lock, flags);
3320
3321 wait_for_completion(stop_cmd->completion);
3322
3323 spin_lock_irqsave(&xhci->lock, flags);
3324
3325 /* config ep command clears toggle if add and drop ep flags are set */
3326 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3327 if (!ctrl_ctx) {
3328 spin_unlock_irqrestore(&xhci->lock, flags);
3329 xhci_free_command(xhci, cfg_cmd);
3330 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3331 __func__);
3332 goto cleanup;
3333 }
3334
3335 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3336 ctrl_ctx, ep_flag, ep_flag);
3337 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3338
3339 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3340 udev->slot_id, false);
3341 if (err < 0) {
3342 spin_unlock_irqrestore(&xhci->lock, flags);
3343 xhci_free_command(xhci, cfg_cmd);
3344 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3345 __func__, err);
3346 goto cleanup;
3347 }
3348
3349 xhci_ring_cmd_db(xhci);
3350 spin_unlock_irqrestore(&xhci->lock, flags);
3351
3352 wait_for_completion(cfg_cmd->completion);
3353
3354 xhci_free_command(xhci, cfg_cmd);
3355 cleanup:
3356 xhci_free_command(xhci, stop_cmd);
3357 spin_lock_irqsave(&xhci->lock, flags);
3358 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3359 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3360 spin_unlock_irqrestore(&xhci->lock, flags);
3361 }
3362
xhci_check_streams_endpoint(struct xhci_hcd * xhci,struct usb_device * udev,struct usb_host_endpoint * ep,unsigned int slot_id)3363 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3364 struct usb_device *udev, struct usb_host_endpoint *ep,
3365 unsigned int slot_id)
3366 {
3367 int ret;
3368 unsigned int ep_index;
3369 unsigned int ep_state;
3370
3371 if (!ep)
3372 return -EINVAL;
3373 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3374 if (ret <= 0)
3375 return ret ? ret : -EINVAL;
3376 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3377 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3378 " descriptor for ep 0x%x does not support streams\n",
3379 ep->desc.bEndpointAddress);
3380 return -EINVAL;
3381 }
3382
3383 ep_index = xhci_get_endpoint_index(&ep->desc);
3384 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3385 if (ep_state & EP_HAS_STREAMS ||
3386 ep_state & EP_GETTING_STREAMS) {
3387 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3388 "already has streams set up.\n",
3389 ep->desc.bEndpointAddress);
3390 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3391 "dynamic stream context array reallocation.\n");
3392 return -EINVAL;
3393 }
3394 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3395 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3396 "endpoint 0x%x; URBs are pending.\n",
3397 ep->desc.bEndpointAddress);
3398 return -EINVAL;
3399 }
3400 return 0;
3401 }
3402
xhci_calculate_streams_entries(struct xhci_hcd * xhci,unsigned int * num_streams,unsigned int * num_stream_ctxs)3403 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3404 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3405 {
3406 unsigned int max_streams;
3407
3408 /* The stream context array size must be a power of two */
3409 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3410 /*
3411 * Find out how many primary stream array entries the host controller
3412 * supports. Later we may use secondary stream arrays (similar to 2nd
3413 * level page entries), but that's an optional feature for xHCI host
3414 * controllers. xHCs must support at least 4 stream IDs.
3415 */
3416 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3417 if (*num_stream_ctxs > max_streams) {
3418 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3419 max_streams);
3420 *num_stream_ctxs = max_streams;
3421 *num_streams = max_streams;
3422 }
3423 }
3424
3425 /* Returns an error code if one of the endpoint already has streams.
3426 * This does not change any data structures, it only checks and gathers
3427 * information.
3428 */
xhci_calculate_streams_and_bitmask(struct xhci_hcd * xhci,struct usb_device * udev,struct usb_host_endpoint ** eps,unsigned int num_eps,unsigned int * num_streams,u32 * changed_ep_bitmask)3429 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3430 struct usb_device *udev,
3431 struct usb_host_endpoint **eps, unsigned int num_eps,
3432 unsigned int *num_streams, u32 *changed_ep_bitmask)
3433 {
3434 unsigned int max_streams;
3435 unsigned int endpoint_flag;
3436 int i;
3437 int ret;
3438
3439 for (i = 0; i < num_eps; i++) {
3440 ret = xhci_check_streams_endpoint(xhci, udev,
3441 eps[i], udev->slot_id);
3442 if (ret < 0)
3443 return ret;
3444
3445 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3446 if (max_streams < (*num_streams - 1)) {
3447 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3448 eps[i]->desc.bEndpointAddress,
3449 max_streams);
3450 *num_streams = max_streams+1;
3451 }
3452
3453 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3454 if (*changed_ep_bitmask & endpoint_flag)
3455 return -EINVAL;
3456 *changed_ep_bitmask |= endpoint_flag;
3457 }
3458 return 0;
3459 }
3460
xhci_calculate_no_streams_bitmask(struct xhci_hcd * xhci,struct usb_device * udev,struct usb_host_endpoint ** eps,unsigned int num_eps)3461 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3462 struct usb_device *udev,
3463 struct usb_host_endpoint **eps, unsigned int num_eps)
3464 {
3465 u32 changed_ep_bitmask = 0;
3466 unsigned int slot_id;
3467 unsigned int ep_index;
3468 unsigned int ep_state;
3469 int i;
3470
3471 slot_id = udev->slot_id;
3472 if (!xhci->devs[slot_id])
3473 return 0;
3474
3475 for (i = 0; i < num_eps; i++) {
3476 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3477 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3478 /* Are streams already being freed for the endpoint? */
3479 if (ep_state & EP_GETTING_NO_STREAMS) {
3480 xhci_warn(xhci, "WARN Can't disable streams for "
3481 "endpoint 0x%x, "
3482 "streams are being disabled already\n",
3483 eps[i]->desc.bEndpointAddress);
3484 return 0;
3485 }
3486 /* Are there actually any streams to free? */
3487 if (!(ep_state & EP_HAS_STREAMS) &&
3488 !(ep_state & EP_GETTING_STREAMS)) {
3489 xhci_warn(xhci, "WARN Can't disable streams for "
3490 "endpoint 0x%x, "
3491 "streams are already disabled!\n",
3492 eps[i]->desc.bEndpointAddress);
3493 xhci_warn(xhci, "WARN xhci_free_streams() called "
3494 "with non-streams endpoint\n");
3495 return 0;
3496 }
3497 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3498 }
3499 return changed_ep_bitmask;
3500 }
3501
3502 /*
3503 * The USB device drivers use this function (through the HCD interface in USB
3504 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3505 * coordinate mass storage command queueing across multiple endpoints (basically
3506 * a stream ID == a task ID).
3507 *
3508 * Setting up streams involves allocating the same size stream context array
3509 * for each endpoint and issuing a configure endpoint command for all endpoints.
3510 *
3511 * Don't allow the call to succeed if one endpoint only supports one stream
3512 * (which means it doesn't support streams at all).
3513 *
3514 * Drivers may get less stream IDs than they asked for, if the host controller
3515 * hardware or endpoints claim they can't support the number of requested
3516 * stream IDs.
3517 */
xhci_alloc_streams(struct usb_hcd * hcd,struct usb_device * udev,struct usb_host_endpoint ** eps,unsigned int num_eps,unsigned int num_streams,gfp_t mem_flags)3518 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3519 struct usb_host_endpoint **eps, unsigned int num_eps,
3520 unsigned int num_streams, gfp_t mem_flags)
3521 {
3522 int i, ret;
3523 struct xhci_hcd *xhci;
3524 struct xhci_virt_device *vdev;
3525 struct xhci_command *config_cmd;
3526 struct xhci_input_control_ctx *ctrl_ctx;
3527 unsigned int ep_index;
3528 unsigned int num_stream_ctxs;
3529 unsigned int max_packet;
3530 unsigned long flags;
3531 u32 changed_ep_bitmask = 0;
3532
3533 if (!eps)
3534 return -EINVAL;
3535
3536 /* Add one to the number of streams requested to account for
3537 * stream 0 that is reserved for xHCI usage.
3538 */
3539 num_streams += 1;
3540 xhci = hcd_to_xhci(hcd);
3541 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3542 num_streams);
3543
3544 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3545 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3546 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3547 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3548 return -ENOSYS;
3549 }
3550
3551 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3552 if (!config_cmd)
3553 return -ENOMEM;
3554
3555 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3556 if (!ctrl_ctx) {
3557 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3558 __func__);
3559 xhci_free_command(xhci, config_cmd);
3560 return -ENOMEM;
3561 }
3562
3563 /* Check to make sure all endpoints are not already configured for
3564 * streams. While we're at it, find the maximum number of streams that
3565 * all the endpoints will support and check for duplicate endpoints.
3566 */
3567 spin_lock_irqsave(&xhci->lock, flags);
3568 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3569 num_eps, &num_streams, &changed_ep_bitmask);
3570 if (ret < 0) {
3571 xhci_free_command(xhci, config_cmd);
3572 spin_unlock_irqrestore(&xhci->lock, flags);
3573 return ret;
3574 }
3575 if (num_streams <= 1) {
3576 xhci_warn(xhci, "WARN: endpoints can't handle "
3577 "more than one stream.\n");
3578 xhci_free_command(xhci, config_cmd);
3579 spin_unlock_irqrestore(&xhci->lock, flags);
3580 return -EINVAL;
3581 }
3582 vdev = xhci->devs[udev->slot_id];
3583 /* Mark each endpoint as being in transition, so
3584 * xhci_urb_enqueue() will reject all URBs.
3585 */
3586 for (i = 0; i < num_eps; i++) {
3587 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3588 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3589 }
3590 spin_unlock_irqrestore(&xhci->lock, flags);
3591
3592 /* Setup internal data structures and allocate HW data structures for
3593 * streams (but don't install the HW structures in the input context
3594 * until we're sure all memory allocation succeeded).
3595 */
3596 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3597 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3598 num_stream_ctxs, num_streams);
3599
3600 for (i = 0; i < num_eps; i++) {
3601 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3602 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3603 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3604 num_stream_ctxs,
3605 num_streams,
3606 max_packet, mem_flags);
3607 if (!vdev->eps[ep_index].stream_info)
3608 goto cleanup;
3609 /* Set maxPstreams in endpoint context and update deq ptr to
3610 * point to stream context array. FIXME
3611 */
3612 }
3613
3614 /* Set up the input context for a configure endpoint command. */
3615 for (i = 0; i < num_eps; i++) {
3616 struct xhci_ep_ctx *ep_ctx;
3617
3618 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3619 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3620
3621 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3622 vdev->out_ctx, ep_index);
3623 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3624 vdev->eps[ep_index].stream_info);
3625 }
3626 /* Tell the HW to drop its old copy of the endpoint context info
3627 * and add the updated copy from the input context.
3628 */
3629 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3630 vdev->out_ctx, ctrl_ctx,
3631 changed_ep_bitmask, changed_ep_bitmask);
3632
3633 /* Issue and wait for the configure endpoint command */
3634 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3635 false, false);
3636
3637 /* xHC rejected the configure endpoint command for some reason, so we
3638 * leave the old ring intact and free our internal streams data
3639 * structure.
3640 */
3641 if (ret < 0)
3642 goto cleanup;
3643
3644 spin_lock_irqsave(&xhci->lock, flags);
3645 for (i = 0; i < num_eps; i++) {
3646 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3647 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3648 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3649 udev->slot_id, ep_index);
3650 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3651 }
3652 xhci_free_command(xhci, config_cmd);
3653 spin_unlock_irqrestore(&xhci->lock, flags);
3654
3655 for (i = 0; i < num_eps; i++) {
3656 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3657 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3658 }
3659 /* Subtract 1 for stream 0, which drivers can't use */
3660 return num_streams - 1;
3661
3662 cleanup:
3663 /* If it didn't work, free the streams! */
3664 for (i = 0; i < num_eps; i++) {
3665 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3666 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3667 vdev->eps[ep_index].stream_info = NULL;
3668 /* FIXME Unset maxPstreams in endpoint context and
3669 * update deq ptr to point to normal string ring.
3670 */
3671 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3672 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3673 xhci_endpoint_zero(xhci, vdev, eps[i]);
3674 }
3675 xhci_free_command(xhci, config_cmd);
3676 return -ENOMEM;
3677 }
3678
3679 /* Transition the endpoint from using streams to being a "normal" endpoint
3680 * without streams.
3681 *
3682 * Modify the endpoint context state, submit a configure endpoint command,
3683 * and free all endpoint rings for streams if that completes successfully.
3684 */
xhci_free_streams(struct usb_hcd * hcd,struct usb_device * udev,struct usb_host_endpoint ** eps,unsigned int num_eps,gfp_t mem_flags)3685 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3686 struct usb_host_endpoint **eps, unsigned int num_eps,
3687 gfp_t mem_flags)
3688 {
3689 int i, ret;
3690 struct xhci_hcd *xhci;
3691 struct xhci_virt_device *vdev;
3692 struct xhci_command *command;
3693 struct xhci_input_control_ctx *ctrl_ctx;
3694 unsigned int ep_index;
3695 unsigned long flags;
3696 u32 changed_ep_bitmask;
3697
3698 xhci = hcd_to_xhci(hcd);
3699 vdev = xhci->devs[udev->slot_id];
3700
3701 /* Set up a configure endpoint command to remove the streams rings */
3702 spin_lock_irqsave(&xhci->lock, flags);
3703 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3704 udev, eps, num_eps);
3705 if (changed_ep_bitmask == 0) {
3706 spin_unlock_irqrestore(&xhci->lock, flags);
3707 return -EINVAL;
3708 }
3709
3710 /* Use the xhci_command structure from the first endpoint. We may have
3711 * allocated too many, but the driver may call xhci_free_streams() for
3712 * each endpoint it grouped into one call to xhci_alloc_streams().
3713 */
3714 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3715 command = vdev->eps[ep_index].stream_info->free_streams_command;
3716 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3717 if (!ctrl_ctx) {
3718 spin_unlock_irqrestore(&xhci->lock, flags);
3719 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3720 __func__);
3721 return -EINVAL;
3722 }
3723
3724 for (i = 0; i < num_eps; i++) {
3725 struct xhci_ep_ctx *ep_ctx;
3726
3727 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3728 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3729 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3730 EP_GETTING_NO_STREAMS;
3731
3732 xhci_endpoint_copy(xhci, command->in_ctx,
3733 vdev->out_ctx, ep_index);
3734 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3735 &vdev->eps[ep_index]);
3736 }
3737 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3738 vdev->out_ctx, ctrl_ctx,
3739 changed_ep_bitmask, changed_ep_bitmask);
3740 spin_unlock_irqrestore(&xhci->lock, flags);
3741
3742 /* Issue and wait for the configure endpoint command,
3743 * which must succeed.
3744 */
3745 ret = xhci_configure_endpoint(xhci, udev, command,
3746 false, true);
3747
3748 /* xHC rejected the configure endpoint command for some reason, so we
3749 * leave the streams rings intact.
3750 */
3751 if (ret < 0)
3752 return ret;
3753
3754 spin_lock_irqsave(&xhci->lock, flags);
3755 for (i = 0; i < num_eps; i++) {
3756 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3757 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3758 vdev->eps[ep_index].stream_info = NULL;
3759 /* FIXME Unset maxPstreams in endpoint context and
3760 * update deq ptr to point to normal string ring.
3761 */
3762 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3763 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3764 }
3765 spin_unlock_irqrestore(&xhci->lock, flags);
3766
3767 return 0;
3768 }
3769
3770 /*
3771 * Deletes endpoint resources for endpoints that were active before a Reset
3772 * Device command, or a Disable Slot command. The Reset Device command leaves
3773 * the control endpoint intact, whereas the Disable Slot command deletes it.
3774 *
3775 * Must be called with xhci->lock held.
3776 */
xhci_free_device_endpoint_resources(struct xhci_hcd * xhci,struct xhci_virt_device * virt_dev,bool drop_control_ep)3777 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3778 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3779 {
3780 int i;
3781 unsigned int num_dropped_eps = 0;
3782 unsigned int drop_flags = 0;
3783
3784 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3785 if (virt_dev->eps[i].ring) {
3786 drop_flags |= 1 << i;
3787 num_dropped_eps++;
3788 }
3789 }
3790 xhci->num_active_eps -= num_dropped_eps;
3791 if (num_dropped_eps)
3792 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3793 "Dropped %u ep ctxs, flags = 0x%x, "
3794 "%u now active.",
3795 num_dropped_eps, drop_flags,
3796 xhci->num_active_eps);
3797 }
3798
3799 /*
3800 * This submits a Reset Device Command, which will set the device state to 0,
3801 * set the device address to 0, and disable all the endpoints except the default
3802 * control endpoint. The USB core should come back and call
3803 * xhci_address_device(), and then re-set up the configuration. If this is
3804 * called because of a usb_reset_and_verify_device(), then the old alternate
3805 * settings will be re-installed through the normal bandwidth allocation
3806 * functions.
3807 *
3808 * Wait for the Reset Device command to finish. Remove all structures
3809 * associated with the endpoints that were disabled. Clear the input device
3810 * structure? Reset the control endpoint 0 max packet size?
3811 *
3812 * If the virt_dev to be reset does not exist or does not match the udev,
3813 * it means the device is lost, possibly due to the xHC restore error and
3814 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3815 * re-allocate the device.
3816 */
xhci_discover_or_reset_device(struct usb_hcd * hcd,struct usb_device * udev)3817 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3818 struct usb_device *udev)
3819 {
3820 int ret, i;
3821 unsigned long flags;
3822 struct xhci_hcd *xhci;
3823 unsigned int slot_id;
3824 struct xhci_virt_device *virt_dev;
3825 struct xhci_command *reset_device_cmd;
3826 struct xhci_slot_ctx *slot_ctx;
3827 int old_active_eps = 0;
3828
3829 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3830 if (ret <= 0)
3831 return ret;
3832 xhci = hcd_to_xhci(hcd);
3833 slot_id = udev->slot_id;
3834 virt_dev = xhci->devs[slot_id];
3835 if (!virt_dev) {
3836 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3837 "not exist. Re-allocate the device\n", slot_id);
3838 ret = xhci_alloc_dev(hcd, udev);
3839 if (ret == 1)
3840 return 0;
3841 else
3842 return -EINVAL;
3843 }
3844
3845 if (virt_dev->tt_info)
3846 old_active_eps = virt_dev->tt_info->active_eps;
3847
3848 if (virt_dev->udev != udev) {
3849 /* If the virt_dev and the udev does not match, this virt_dev
3850 * may belong to another udev.
3851 * Re-allocate the device.
3852 */
3853 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3854 "not match the udev. Re-allocate the device\n",
3855 slot_id);
3856 ret = xhci_alloc_dev(hcd, udev);
3857 if (ret == 1)
3858 return 0;
3859 else
3860 return -EINVAL;
3861 }
3862
3863 /* If device is not setup, there is no point in resetting it */
3864 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3865 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3866 SLOT_STATE_DISABLED)
3867 return 0;
3868
3869 trace_xhci_discover_or_reset_device(slot_ctx);
3870
3871 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3872 /* Allocate the command structure that holds the struct completion.
3873 * Assume we're in process context, since the normal device reset
3874 * process has to wait for the device anyway. Storage devices are
3875 * reset as part of error handling, so use GFP_NOIO instead of
3876 * GFP_KERNEL.
3877 */
3878 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3879 if (!reset_device_cmd) {
3880 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3881 return -ENOMEM;
3882 }
3883
3884 /* Attempt to submit the Reset Device command to the command ring */
3885 spin_lock_irqsave(&xhci->lock, flags);
3886
3887 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3888 if (ret) {
3889 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3890 spin_unlock_irqrestore(&xhci->lock, flags);
3891 goto command_cleanup;
3892 }
3893 xhci_ring_cmd_db(xhci);
3894 spin_unlock_irqrestore(&xhci->lock, flags);
3895
3896 /* Wait for the Reset Device command to finish */
3897 wait_for_completion(reset_device_cmd->completion);
3898
3899 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3900 * unless we tried to reset a slot ID that wasn't enabled,
3901 * or the device wasn't in the addressed or configured state.
3902 */
3903 ret = reset_device_cmd->status;
3904 switch (ret) {
3905 case COMP_COMMAND_ABORTED:
3906 case COMP_COMMAND_RING_STOPPED:
3907 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3908 ret = -ETIME;
3909 goto command_cleanup;
3910 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3911 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3912 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3913 slot_id,
3914 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3915 xhci_dbg(xhci, "Not freeing device rings.\n");
3916 /* Don't treat this as an error. May change my mind later. */
3917 ret = 0;
3918 goto command_cleanup;
3919 case COMP_SUCCESS:
3920 xhci_dbg(xhci, "Successful reset device command.\n");
3921 break;
3922 default:
3923 if (xhci_is_vendor_info_code(xhci, ret))
3924 break;
3925 xhci_warn(xhci, "Unknown completion code %u for "
3926 "reset device command.\n", ret);
3927 ret = -EINVAL;
3928 goto command_cleanup;
3929 }
3930
3931 /* Free up host controller endpoint resources */
3932 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3933 spin_lock_irqsave(&xhci->lock, flags);
3934 /* Don't delete the default control endpoint resources */
3935 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3936 spin_unlock_irqrestore(&xhci->lock, flags);
3937 }
3938
3939 /* Everything but endpoint 0 is disabled, so free the rings. */
3940 for (i = 1; i < 31; i++) {
3941 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3942
3943 if (ep->ep_state & EP_HAS_STREAMS) {
3944 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3945 xhci_get_endpoint_address(i));
3946 xhci_free_stream_info(xhci, ep->stream_info);
3947 ep->stream_info = NULL;
3948 ep->ep_state &= ~EP_HAS_STREAMS;
3949 }
3950
3951 if (ep->ring) {
3952 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3953 xhci_free_endpoint_ring(xhci, virt_dev, i);
3954 }
3955 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3956 xhci_drop_ep_from_interval_table(xhci,
3957 &virt_dev->eps[i].bw_info,
3958 virt_dev->bw_table,
3959 udev,
3960 &virt_dev->eps[i],
3961 virt_dev->tt_info);
3962 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3963 }
3964 /* If necessary, update the number of active TTs on this root port */
3965 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3966 virt_dev->flags = 0;
3967 ret = 0;
3968
3969 command_cleanup:
3970 xhci_free_command(xhci, reset_device_cmd);
3971 return ret;
3972 }
3973
3974 /*
3975 * At this point, the struct usb_device is about to go away, the device has
3976 * disconnected, and all traffic has been stopped and the endpoints have been
3977 * disabled. Free any HC data structures associated with that device.
3978 */
xhci_free_dev(struct usb_hcd * hcd,struct usb_device * udev)3979 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3980 {
3981 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3982 struct xhci_virt_device *virt_dev;
3983 struct xhci_slot_ctx *slot_ctx;
3984 unsigned long flags;
3985 int i, ret;
3986
3987 /*
3988 * We called pm_runtime_get_noresume when the device was attached.
3989 * Decrement the counter here to allow controller to runtime suspend
3990 * if no devices remain.
3991 */
3992 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3993 pm_runtime_put_noidle(hcd->self.controller);
3994
3995 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3996 /* If the host is halted due to driver unload, we still need to free the
3997 * device.
3998 */
3999 if (ret <= 0 && ret != -ENODEV)
4000 return;
4001
4002 virt_dev = xhci->devs[udev->slot_id];
4003 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4004 trace_xhci_free_dev(slot_ctx);
4005
4006 /* Stop any wayward timer functions (which may grab the lock) */
4007 for (i = 0; i < 31; i++) {
4008 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
4009 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
4010 }
4011 virt_dev->udev = NULL;
4012 xhci_disable_slot(xhci, udev->slot_id);
4013
4014 spin_lock_irqsave(&xhci->lock, flags);
4015 xhci_free_virt_device(xhci, udev->slot_id);
4016 spin_unlock_irqrestore(&xhci->lock, flags);
4017
4018 }
4019
xhci_disable_slot(struct xhci_hcd * xhci,u32 slot_id)4020 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
4021 {
4022 struct xhci_command *command;
4023 unsigned long flags;
4024 u32 state;
4025 int ret = 0;
4026
4027 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4028 if (!command)
4029 return -ENOMEM;
4030
4031 xhci_debugfs_remove_slot(xhci, slot_id);
4032
4033 spin_lock_irqsave(&xhci->lock, flags);
4034 /* Don't disable the slot if the host controller is dead. */
4035 state = readl(&xhci->op_regs->status);
4036 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
4037 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4038 spin_unlock_irqrestore(&xhci->lock, flags);
4039 kfree(command);
4040 return -ENODEV;
4041 }
4042
4043 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
4044 slot_id);
4045 if (ret) {
4046 spin_unlock_irqrestore(&xhci->lock, flags);
4047 kfree(command);
4048 return ret;
4049 }
4050 xhci_ring_cmd_db(xhci);
4051 spin_unlock_irqrestore(&xhci->lock, flags);
4052
4053 wait_for_completion(command->completion);
4054
4055 if (command->status != COMP_SUCCESS)
4056 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
4057 slot_id, command->status);
4058
4059 xhci_free_command(xhci, command);
4060
4061 return ret;
4062 }
4063
4064 /*
4065 * Checks if we have enough host controller resources for the default control
4066 * endpoint.
4067 *
4068 * Must be called with xhci->lock held.
4069 */
xhci_reserve_host_control_ep_resources(struct xhci_hcd * xhci)4070 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4071 {
4072 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4073 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4074 "Not enough ep ctxs: "
4075 "%u active, need to add 1, limit is %u.",
4076 xhci->num_active_eps, xhci->limit_active_eps);
4077 return -ENOMEM;
4078 }
4079 xhci->num_active_eps += 1;
4080 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4081 "Adding 1 ep ctx, %u now active.",
4082 xhci->num_active_eps);
4083 return 0;
4084 }
4085
4086
4087 /*
4088 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4089 * timed out, or allocating memory failed. Returns 1 on success.
4090 */
xhci_alloc_dev(struct usb_hcd * hcd,struct usb_device * udev)4091 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4092 {
4093 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4094 struct xhci_virt_device *vdev;
4095 struct xhci_slot_ctx *slot_ctx;
4096 unsigned long flags;
4097 int ret, slot_id;
4098 struct xhci_command *command;
4099
4100 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4101 if (!command)
4102 return 0;
4103
4104 spin_lock_irqsave(&xhci->lock, flags);
4105 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4106 if (ret) {
4107 spin_unlock_irqrestore(&xhci->lock, flags);
4108 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4109 xhci_free_command(xhci, command);
4110 return 0;
4111 }
4112 xhci_ring_cmd_db(xhci);
4113 spin_unlock_irqrestore(&xhci->lock, flags);
4114
4115 wait_for_completion(command->completion);
4116 slot_id = command->slot_id;
4117
4118 if (!slot_id || command->status != COMP_SUCCESS) {
4119 xhci_err(xhci, "Error while assigning device slot ID\n");
4120 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4121 HCS_MAX_SLOTS(
4122 readl(&xhci->cap_regs->hcs_params1)));
4123 xhci_free_command(xhci, command);
4124 return 0;
4125 }
4126
4127 xhci_free_command(xhci, command);
4128
4129 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4130 spin_lock_irqsave(&xhci->lock, flags);
4131 ret = xhci_reserve_host_control_ep_resources(xhci);
4132 if (ret) {
4133 spin_unlock_irqrestore(&xhci->lock, flags);
4134 xhci_warn(xhci, "Not enough host resources, "
4135 "active endpoint contexts = %u\n",
4136 xhci->num_active_eps);
4137 goto disable_slot;
4138 }
4139 spin_unlock_irqrestore(&xhci->lock, flags);
4140 }
4141 /* Use GFP_NOIO, since this function can be called from
4142 * xhci_discover_or_reset_device(), which may be called as part of
4143 * mass storage driver error handling.
4144 */
4145 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4146 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4147 goto disable_slot;
4148 }
4149 vdev = xhci->devs[slot_id];
4150 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4151 trace_xhci_alloc_dev(slot_ctx);
4152
4153 udev->slot_id = slot_id;
4154
4155 xhci_debugfs_create_slot(xhci, slot_id);
4156
4157 /*
4158 * If resetting upon resume, we can't put the controller into runtime
4159 * suspend if there is a device attached.
4160 */
4161 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4162 pm_runtime_get_noresume(hcd->self.controller);
4163
4164 /* Is this a LS or FS device under a HS hub? */
4165 /* Hub or peripherial? */
4166 return 1;
4167
4168 disable_slot:
4169 xhci_disable_slot(xhci, udev->slot_id);
4170 xhci_free_virt_device(xhci, udev->slot_id);
4171
4172 return 0;
4173 }
4174
4175 /*
4176 * Issue an Address Device command and optionally send a corresponding
4177 * SetAddress request to the device.
4178 */
xhci_setup_device(struct usb_hcd * hcd,struct usb_device * udev,enum xhci_setup_dev setup)4179 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4180 enum xhci_setup_dev setup)
4181 {
4182 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4183 unsigned long flags;
4184 struct xhci_virt_device *virt_dev;
4185 int ret = 0;
4186 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4187 struct xhci_slot_ctx *slot_ctx;
4188 struct xhci_input_control_ctx *ctrl_ctx;
4189 u64 temp_64;
4190 struct xhci_command *command = NULL;
4191
4192 mutex_lock(&xhci->mutex);
4193
4194 if (xhci->xhc_state) { /* dying, removing or halted */
4195 ret = -ESHUTDOWN;
4196 goto out;
4197 }
4198
4199 if (!udev->slot_id) {
4200 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4201 "Bad Slot ID %d", udev->slot_id);
4202 ret = -EINVAL;
4203 goto out;
4204 }
4205
4206 virt_dev = xhci->devs[udev->slot_id];
4207
4208 if (WARN_ON(!virt_dev)) {
4209 /*
4210 * In plug/unplug torture test with an NEC controller,
4211 * a zero-dereference was observed once due to virt_dev = 0.
4212 * Print useful debug rather than crash if it is observed again!
4213 */
4214 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4215 udev->slot_id);
4216 ret = -EINVAL;
4217 goto out;
4218 }
4219 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4220 trace_xhci_setup_device_slot(slot_ctx);
4221
4222 if (setup == SETUP_CONTEXT_ONLY) {
4223 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4224 SLOT_STATE_DEFAULT) {
4225 xhci_dbg(xhci, "Slot already in default state\n");
4226 goto out;
4227 }
4228 }
4229
4230 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4231 if (!command) {
4232 ret = -ENOMEM;
4233 goto out;
4234 }
4235
4236 command->in_ctx = virt_dev->in_ctx;
4237
4238 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4239 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4240 if (!ctrl_ctx) {
4241 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4242 __func__);
4243 ret = -EINVAL;
4244 goto out;
4245 }
4246 /*
4247 * If this is the first Set Address since device plug-in or
4248 * virt_device realloaction after a resume with an xHCI power loss,
4249 * then set up the slot context.
4250 */
4251 if (!slot_ctx->dev_info)
4252 xhci_setup_addressable_virt_dev(xhci, udev);
4253 /* Otherwise, update the control endpoint ring enqueue pointer. */
4254 else
4255 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4256 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4257 ctrl_ctx->drop_flags = 0;
4258
4259 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4260 le32_to_cpu(slot_ctx->dev_info) >> 27);
4261
4262 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4263 spin_lock_irqsave(&xhci->lock, flags);
4264 trace_xhci_setup_device(virt_dev);
4265 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4266 udev->slot_id, setup);
4267 if (ret) {
4268 spin_unlock_irqrestore(&xhci->lock, flags);
4269 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4270 "FIXME: allocate a command ring segment");
4271 goto out;
4272 }
4273 xhci_ring_cmd_db(xhci);
4274 spin_unlock_irqrestore(&xhci->lock, flags);
4275
4276 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4277 wait_for_completion(command->completion);
4278
4279 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4280 * the SetAddress() "recovery interval" required by USB and aborting the
4281 * command on a timeout.
4282 */
4283 switch (command->status) {
4284 case COMP_COMMAND_ABORTED:
4285 case COMP_COMMAND_RING_STOPPED:
4286 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4287 ret = -ETIME;
4288 break;
4289 case COMP_CONTEXT_STATE_ERROR:
4290 case COMP_SLOT_NOT_ENABLED_ERROR:
4291 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4292 act, udev->slot_id);
4293 ret = -EINVAL;
4294 break;
4295 case COMP_USB_TRANSACTION_ERROR:
4296 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4297
4298 mutex_unlock(&xhci->mutex);
4299 ret = xhci_disable_slot(xhci, udev->slot_id);
4300 xhci_free_virt_device(xhci, udev->slot_id);
4301 if (!ret)
4302 xhci_alloc_dev(hcd, udev);
4303 kfree(command->completion);
4304 kfree(command);
4305 return -EPROTO;
4306 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4307 dev_warn(&udev->dev,
4308 "ERROR: Incompatible device for setup %s command\n", act);
4309 ret = -ENODEV;
4310 break;
4311 case COMP_SUCCESS:
4312 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4313 "Successful setup %s command", act);
4314 break;
4315 default:
4316 xhci_err(xhci,
4317 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4318 act, command->status);
4319 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4320 ret = -EINVAL;
4321 break;
4322 }
4323 if (ret)
4324 goto out;
4325 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4326 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4327 "Op regs DCBAA ptr = %#016llx", temp_64);
4328 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4329 "Slot ID %d dcbaa entry @%p = %#016llx",
4330 udev->slot_id,
4331 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4332 (unsigned long long)
4333 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4334 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4335 "Output Context DMA address = %#08llx",
4336 (unsigned long long)virt_dev->out_ctx->dma);
4337 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4338 le32_to_cpu(slot_ctx->dev_info) >> 27);
4339 /*
4340 * USB core uses address 1 for the roothubs, so we add one to the
4341 * address given back to us by the HC.
4342 */
4343 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4344 le32_to_cpu(slot_ctx->dev_info) >> 27);
4345 /* Zero the input context control for later use */
4346 ctrl_ctx->add_flags = 0;
4347 ctrl_ctx->drop_flags = 0;
4348 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4349 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4350
4351 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4352 "Internal device address = %d",
4353 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4354 out:
4355 mutex_unlock(&xhci->mutex);
4356 if (command) {
4357 kfree(command->completion);
4358 kfree(command);
4359 }
4360 return ret;
4361 }
4362
xhci_address_device(struct usb_hcd * hcd,struct usb_device * udev)4363 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4364 {
4365 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4366 }
4367
xhci_enable_device(struct usb_hcd * hcd,struct usb_device * udev)4368 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4369 {
4370 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4371 }
4372
4373 /*
4374 * Transfer the port index into real index in the HW port status
4375 * registers. Caculate offset between the port's PORTSC register
4376 * and port status base. Divide the number of per port register
4377 * to get the real index. The raw port number bases 1.
4378 */
xhci_find_raw_port_number(struct usb_hcd * hcd,int port1)4379 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4380 {
4381 struct xhci_hub *rhub;
4382
4383 rhub = xhci_get_rhub(hcd);
4384 return rhub->ports[port1 - 1]->hw_portnum + 1;
4385 }
4386
4387 /*
4388 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4389 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4390 */
xhci_change_max_exit_latency(struct xhci_hcd * xhci,struct usb_device * udev,u16 max_exit_latency)4391 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4392 struct usb_device *udev, u16 max_exit_latency)
4393 {
4394 struct xhci_virt_device *virt_dev;
4395 struct xhci_command *command;
4396 struct xhci_input_control_ctx *ctrl_ctx;
4397 struct xhci_slot_ctx *slot_ctx;
4398 unsigned long flags;
4399 int ret;
4400
4401 spin_lock_irqsave(&xhci->lock, flags);
4402
4403 virt_dev = xhci->devs[udev->slot_id];
4404
4405 /*
4406 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4407 * xHC was re-initialized. Exit latency will be set later after
4408 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4409 */
4410
4411 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4412 spin_unlock_irqrestore(&xhci->lock, flags);
4413 return 0;
4414 }
4415
4416 /* Attempt to issue an Evaluate Context command to change the MEL. */
4417 command = xhci->lpm_command;
4418 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4419 if (!ctrl_ctx) {
4420 spin_unlock_irqrestore(&xhci->lock, flags);
4421 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4422 __func__);
4423 return -ENOMEM;
4424 }
4425
4426 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4427 spin_unlock_irqrestore(&xhci->lock, flags);
4428
4429 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4430 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4431 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4432 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4433 slot_ctx->dev_state = 0;
4434
4435 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4436 "Set up evaluate context for LPM MEL change.");
4437
4438 /* Issue and wait for the evaluate context command. */
4439 ret = xhci_configure_endpoint(xhci, udev, command,
4440 true, true);
4441
4442 if (!ret) {
4443 spin_lock_irqsave(&xhci->lock, flags);
4444 virt_dev->current_mel = max_exit_latency;
4445 spin_unlock_irqrestore(&xhci->lock, flags);
4446 }
4447 return ret;
4448 }
4449
4450 #ifdef CONFIG_PM
4451
4452 /* BESL to HIRD Encoding array for USB2 LPM */
4453 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4454 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4455
4456 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
xhci_calculate_hird_besl(struct xhci_hcd * xhci,struct usb_device * udev)4457 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4458 struct usb_device *udev)
4459 {
4460 int u2del, besl, besl_host;
4461 int besl_device = 0;
4462 u32 field;
4463
4464 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4465 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4466
4467 if (field & USB_BESL_SUPPORT) {
4468 for (besl_host = 0; besl_host < 16; besl_host++) {
4469 if (xhci_besl_encoding[besl_host] >= u2del)
4470 break;
4471 }
4472 /* Use baseline BESL value as default */
4473 if (field & USB_BESL_BASELINE_VALID)
4474 besl_device = USB_GET_BESL_BASELINE(field);
4475 else if (field & USB_BESL_DEEP_VALID)
4476 besl_device = USB_GET_BESL_DEEP(field);
4477 } else {
4478 if (u2del <= 50)
4479 besl_host = 0;
4480 else
4481 besl_host = (u2del - 51) / 75 + 1;
4482 }
4483
4484 besl = besl_host + besl_device;
4485 if (besl > 15)
4486 besl = 15;
4487
4488 return besl;
4489 }
4490
4491 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
xhci_calculate_usb2_hw_lpm_params(struct usb_device * udev)4492 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4493 {
4494 u32 field;
4495 int l1;
4496 int besld = 0;
4497 int hirdm = 0;
4498
4499 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4500
4501 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4502 l1 = udev->l1_params.timeout / 256;
4503
4504 /* device has preferred BESLD */
4505 if (field & USB_BESL_DEEP_VALID) {
4506 besld = USB_GET_BESL_DEEP(field);
4507 hirdm = 1;
4508 }
4509
4510 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4511 }
4512
xhci_set_usb2_hardware_lpm(struct usb_hcd * hcd,struct usb_device * udev,int enable)4513 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4514 struct usb_device *udev, int enable)
4515 {
4516 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4517 struct xhci_port **ports;
4518 __le32 __iomem *pm_addr, *hlpm_addr;
4519 u32 pm_val, hlpm_val, field;
4520 unsigned int port_num;
4521 unsigned long flags;
4522 int hird, exit_latency;
4523 int ret;
4524
4525 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4526 return -EPERM;
4527
4528 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4529 !udev->lpm_capable)
4530 return -EPERM;
4531
4532 if (!udev->parent || udev->parent->parent ||
4533 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4534 return -EPERM;
4535
4536 if (udev->usb2_hw_lpm_capable != 1)
4537 return -EPERM;
4538
4539 spin_lock_irqsave(&xhci->lock, flags);
4540
4541 ports = xhci->usb2_rhub.ports;
4542 port_num = udev->portnum - 1;
4543 pm_addr = ports[port_num]->addr + PORTPMSC;
4544 pm_val = readl(pm_addr);
4545 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4546
4547 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4548 enable ? "enable" : "disable", port_num + 1);
4549
4550 if (enable) {
4551 /* Host supports BESL timeout instead of HIRD */
4552 if (udev->usb2_hw_lpm_besl_capable) {
4553 /* if device doesn't have a preferred BESL value use a
4554 * default one which works with mixed HIRD and BESL
4555 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4556 */
4557 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4558 if ((field & USB_BESL_SUPPORT) &&
4559 (field & USB_BESL_BASELINE_VALID))
4560 hird = USB_GET_BESL_BASELINE(field);
4561 else
4562 hird = udev->l1_params.besl;
4563
4564 exit_latency = xhci_besl_encoding[hird];
4565 spin_unlock_irqrestore(&xhci->lock, flags);
4566
4567 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4568 * input context for link powermanagement evaluate
4569 * context commands. It is protected by hcd->bandwidth
4570 * mutex and is shared by all devices. We need to set
4571 * the max ext latency in USB 2 BESL LPM as well, so
4572 * use the same mutex and xhci_change_max_exit_latency()
4573 */
4574 mutex_lock(hcd->bandwidth_mutex);
4575 ret = xhci_change_max_exit_latency(xhci, udev,
4576 exit_latency);
4577 mutex_unlock(hcd->bandwidth_mutex);
4578
4579 if (ret < 0)
4580 return ret;
4581 spin_lock_irqsave(&xhci->lock, flags);
4582
4583 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4584 writel(hlpm_val, hlpm_addr);
4585 /* flush write */
4586 readl(hlpm_addr);
4587 } else {
4588 hird = xhci_calculate_hird_besl(xhci, udev);
4589 }
4590
4591 pm_val &= ~PORT_HIRD_MASK;
4592 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4593 writel(pm_val, pm_addr);
4594 pm_val = readl(pm_addr);
4595 pm_val |= PORT_HLE;
4596 writel(pm_val, pm_addr);
4597 /* flush write */
4598 readl(pm_addr);
4599 } else {
4600 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4601 writel(pm_val, pm_addr);
4602 /* flush write */
4603 readl(pm_addr);
4604 if (udev->usb2_hw_lpm_besl_capable) {
4605 spin_unlock_irqrestore(&xhci->lock, flags);
4606 mutex_lock(hcd->bandwidth_mutex);
4607 xhci_change_max_exit_latency(xhci, udev, 0);
4608 mutex_unlock(hcd->bandwidth_mutex);
4609 readl_poll_timeout(ports[port_num]->addr, pm_val,
4610 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4611 100, 10000);
4612 return 0;
4613 }
4614 }
4615
4616 spin_unlock_irqrestore(&xhci->lock, flags);
4617 return 0;
4618 }
4619
4620 /* check if a usb2 port supports a given extened capability protocol
4621 * only USB2 ports extended protocol capability values are cached.
4622 * Return 1 if capability is supported
4623 */
xhci_check_usb2_port_capability(struct xhci_hcd * xhci,int port,unsigned capability)4624 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4625 unsigned capability)
4626 {
4627 u32 port_offset, port_count;
4628 int i;
4629
4630 for (i = 0; i < xhci->num_ext_caps; i++) {
4631 if (xhci->ext_caps[i] & capability) {
4632 /* port offsets starts at 1 */
4633 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4634 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4635 if (port >= port_offset &&
4636 port < port_offset + port_count)
4637 return 1;
4638 }
4639 }
4640 return 0;
4641 }
4642
xhci_update_device(struct usb_hcd * hcd,struct usb_device * udev)4643 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4644 {
4645 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4646 int portnum = udev->portnum - 1;
4647
4648 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4649 return 0;
4650
4651 /* we only support lpm for non-hub device connected to root hub yet */
4652 if (!udev->parent || udev->parent->parent ||
4653 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4654 return 0;
4655
4656 if (xhci->hw_lpm_support == 1 &&
4657 xhci_check_usb2_port_capability(
4658 xhci, portnum, XHCI_HLC)) {
4659 udev->usb2_hw_lpm_capable = 1;
4660 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4661 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4662 if (xhci_check_usb2_port_capability(xhci, portnum,
4663 XHCI_BLC))
4664 udev->usb2_hw_lpm_besl_capable = 1;
4665 }
4666
4667 return 0;
4668 }
4669
4670 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4671
4672 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
xhci_service_interval_to_ns(struct usb_endpoint_descriptor * desc)4673 static unsigned long long xhci_service_interval_to_ns(
4674 struct usb_endpoint_descriptor *desc)
4675 {
4676 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4677 }
4678
xhci_get_timeout_no_hub_lpm(struct usb_device * udev,enum usb3_link_state state)4679 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4680 enum usb3_link_state state)
4681 {
4682 unsigned long long sel;
4683 unsigned long long pel;
4684 unsigned int max_sel_pel;
4685 char *state_name;
4686
4687 switch (state) {
4688 case USB3_LPM_U1:
4689 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4690 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4691 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4692 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4693 state_name = "U1";
4694 break;
4695 case USB3_LPM_U2:
4696 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4697 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4698 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4699 state_name = "U2";
4700 break;
4701 default:
4702 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4703 __func__);
4704 return USB3_LPM_DISABLED;
4705 }
4706
4707 if (sel <= max_sel_pel && pel <= max_sel_pel)
4708 return USB3_LPM_DEVICE_INITIATED;
4709
4710 if (sel > max_sel_pel)
4711 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4712 "due to long SEL %llu ms\n",
4713 state_name, sel);
4714 else
4715 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4716 "due to long PEL %llu ms\n",
4717 state_name, pel);
4718 return USB3_LPM_DISABLED;
4719 }
4720
4721 /* The U1 timeout should be the maximum of the following values:
4722 * - For control endpoints, U1 system exit latency (SEL) * 3
4723 * - For bulk endpoints, U1 SEL * 5
4724 * - For interrupt endpoints:
4725 * - Notification EPs, U1 SEL * 3
4726 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4727 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4728 */
xhci_calculate_intel_u1_timeout(struct usb_device * udev,struct usb_endpoint_descriptor * desc)4729 static unsigned long long xhci_calculate_intel_u1_timeout(
4730 struct usb_device *udev,
4731 struct usb_endpoint_descriptor *desc)
4732 {
4733 unsigned long long timeout_ns;
4734 int ep_type;
4735 int intr_type;
4736
4737 ep_type = usb_endpoint_type(desc);
4738 switch (ep_type) {
4739 case USB_ENDPOINT_XFER_CONTROL:
4740 timeout_ns = udev->u1_params.sel * 3;
4741 break;
4742 case USB_ENDPOINT_XFER_BULK:
4743 timeout_ns = udev->u1_params.sel * 5;
4744 break;
4745 case USB_ENDPOINT_XFER_INT:
4746 intr_type = usb_endpoint_interrupt_type(desc);
4747 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4748 timeout_ns = udev->u1_params.sel * 3;
4749 break;
4750 }
4751 /* Otherwise the calculation is the same as isoc eps */
4752 fallthrough;
4753 case USB_ENDPOINT_XFER_ISOC:
4754 timeout_ns = xhci_service_interval_to_ns(desc);
4755 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4756 if (timeout_ns < udev->u1_params.sel * 2)
4757 timeout_ns = udev->u1_params.sel * 2;
4758 break;
4759 default:
4760 return 0;
4761 }
4762
4763 return timeout_ns;
4764 }
4765
4766 /* Returns the hub-encoded U1 timeout value. */
xhci_calculate_u1_timeout(struct xhci_hcd * xhci,struct usb_device * udev,struct usb_endpoint_descriptor * desc)4767 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4768 struct usb_device *udev,
4769 struct usb_endpoint_descriptor *desc)
4770 {
4771 unsigned long long timeout_ns;
4772
4773 /* Prevent U1 if service interval is shorter than U1 exit latency */
4774 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4775 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4776 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4777 return USB3_LPM_DISABLED;
4778 }
4779 }
4780
4781 if (xhci->quirks & XHCI_INTEL_HOST)
4782 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4783 else
4784 timeout_ns = udev->u1_params.sel;
4785
4786 /* The U1 timeout is encoded in 1us intervals.
4787 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4788 */
4789 if (timeout_ns == USB3_LPM_DISABLED)
4790 timeout_ns = 1;
4791 else
4792 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4793
4794 /* If the necessary timeout value is bigger than what we can set in the
4795 * USB 3.0 hub, we have to disable hub-initiated U1.
4796 */
4797 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4798 return timeout_ns;
4799 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4800 "due to long timeout %llu ms\n", timeout_ns);
4801 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4802 }
4803
4804 /* The U2 timeout should be the maximum of:
4805 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4806 * - largest bInterval of any active periodic endpoint (to avoid going
4807 * into lower power link states between intervals).
4808 * - the U2 Exit Latency of the device
4809 */
xhci_calculate_intel_u2_timeout(struct usb_device * udev,struct usb_endpoint_descriptor * desc)4810 static unsigned long long xhci_calculate_intel_u2_timeout(
4811 struct usb_device *udev,
4812 struct usb_endpoint_descriptor *desc)
4813 {
4814 unsigned long long timeout_ns;
4815 unsigned long long u2_del_ns;
4816
4817 timeout_ns = 10 * 1000 * 1000;
4818
4819 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4820 (xhci_service_interval_to_ns(desc) > timeout_ns))
4821 timeout_ns = xhci_service_interval_to_ns(desc);
4822
4823 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4824 if (u2_del_ns > timeout_ns)
4825 timeout_ns = u2_del_ns;
4826
4827 return timeout_ns;
4828 }
4829
4830 /* Returns the hub-encoded U2 timeout value. */
xhci_calculate_u2_timeout(struct xhci_hcd * xhci,struct usb_device * udev,struct usb_endpoint_descriptor * desc)4831 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4832 struct usb_device *udev,
4833 struct usb_endpoint_descriptor *desc)
4834 {
4835 unsigned long long timeout_ns;
4836
4837 /* Prevent U2 if service interval is shorter than U2 exit latency */
4838 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4839 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4840 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4841 return USB3_LPM_DISABLED;
4842 }
4843 }
4844
4845 if (xhci->quirks & XHCI_INTEL_HOST)
4846 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4847 else
4848 timeout_ns = udev->u2_params.sel;
4849
4850 /* The U2 timeout is encoded in 256us intervals */
4851 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4852 /* If the necessary timeout value is bigger than what we can set in the
4853 * USB 3.0 hub, we have to disable hub-initiated U2.
4854 */
4855 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4856 return timeout_ns;
4857 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4858 "due to long timeout %llu ms\n", timeout_ns);
4859 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4860 }
4861
xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd * xhci,struct usb_device * udev,struct usb_endpoint_descriptor * desc,enum usb3_link_state state,u16 * timeout)4862 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4863 struct usb_device *udev,
4864 struct usb_endpoint_descriptor *desc,
4865 enum usb3_link_state state,
4866 u16 *timeout)
4867 {
4868 if (state == USB3_LPM_U1)
4869 return xhci_calculate_u1_timeout(xhci, udev, desc);
4870 else if (state == USB3_LPM_U2)
4871 return xhci_calculate_u2_timeout(xhci, udev, desc);
4872
4873 return USB3_LPM_DISABLED;
4874 }
4875
xhci_update_timeout_for_endpoint(struct xhci_hcd * xhci,struct usb_device * udev,struct usb_endpoint_descriptor * desc,enum usb3_link_state state,u16 * timeout)4876 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4877 struct usb_device *udev,
4878 struct usb_endpoint_descriptor *desc,
4879 enum usb3_link_state state,
4880 u16 *timeout)
4881 {
4882 u16 alt_timeout;
4883
4884 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4885 desc, state, timeout);
4886
4887 /* If we found we can't enable hub-initiated LPM, and
4888 * the U1 or U2 exit latency was too high to allow
4889 * device-initiated LPM as well, then we will disable LPM
4890 * for this device, so stop searching any further.
4891 */
4892 if (alt_timeout == USB3_LPM_DISABLED) {
4893 *timeout = alt_timeout;
4894 return -E2BIG;
4895 }
4896 if (alt_timeout > *timeout)
4897 *timeout = alt_timeout;
4898 return 0;
4899 }
4900
xhci_update_timeout_for_interface(struct xhci_hcd * xhci,struct usb_device * udev,struct usb_host_interface * alt,enum usb3_link_state state,u16 * timeout)4901 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4902 struct usb_device *udev,
4903 struct usb_host_interface *alt,
4904 enum usb3_link_state state,
4905 u16 *timeout)
4906 {
4907 int j;
4908
4909 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4910 if (xhci_update_timeout_for_endpoint(xhci, udev,
4911 &alt->endpoint[j].desc, state, timeout))
4912 return -E2BIG;
4913 }
4914 return 0;
4915 }
4916
xhci_check_intel_tier_policy(struct usb_device * udev,enum usb3_link_state state)4917 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4918 enum usb3_link_state state)
4919 {
4920 struct usb_device *parent;
4921 unsigned int num_hubs;
4922
4923 if (state == USB3_LPM_U2)
4924 return 0;
4925
4926 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4927 for (parent = udev->parent, num_hubs = 0; parent->parent;
4928 parent = parent->parent)
4929 num_hubs++;
4930
4931 if (num_hubs < 2)
4932 return 0;
4933
4934 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4935 " below second-tier hub.\n");
4936 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4937 "to decrease power consumption.\n");
4938 return -E2BIG;
4939 }
4940
xhci_check_tier_policy(struct xhci_hcd * xhci,struct usb_device * udev,enum usb3_link_state state)4941 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4942 struct usb_device *udev,
4943 enum usb3_link_state state)
4944 {
4945 if (xhci->quirks & XHCI_INTEL_HOST)
4946 return xhci_check_intel_tier_policy(udev, state);
4947 else
4948 return 0;
4949 }
4950
4951 /* Returns the U1 or U2 timeout that should be enabled.
4952 * If the tier check or timeout setting functions return with a non-zero exit
4953 * code, that means the timeout value has been finalized and we shouldn't look
4954 * at any more endpoints.
4955 */
xhci_calculate_lpm_timeout(struct usb_hcd * hcd,struct usb_device * udev,enum usb3_link_state state)4956 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4957 struct usb_device *udev, enum usb3_link_state state)
4958 {
4959 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4960 struct usb_host_config *config;
4961 char *state_name;
4962 int i;
4963 u16 timeout = USB3_LPM_DISABLED;
4964
4965 if (state == USB3_LPM_U1)
4966 state_name = "U1";
4967 else if (state == USB3_LPM_U2)
4968 state_name = "U2";
4969 else {
4970 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4971 state);
4972 return timeout;
4973 }
4974
4975 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4976 return timeout;
4977
4978 /* Gather some information about the currently installed configuration
4979 * and alternate interface settings.
4980 */
4981 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4982 state, &timeout))
4983 return timeout;
4984
4985 config = udev->actconfig;
4986 if (!config)
4987 return timeout;
4988
4989 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4990 struct usb_driver *driver;
4991 struct usb_interface *intf = config->interface[i];
4992
4993 if (!intf)
4994 continue;
4995
4996 /* Check if any currently bound drivers want hub-initiated LPM
4997 * disabled.
4998 */
4999 if (intf->dev.driver) {
5000 driver = to_usb_driver(intf->dev.driver);
5001 if (driver && driver->disable_hub_initiated_lpm) {
5002 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
5003 state_name, driver->name);
5004 timeout = xhci_get_timeout_no_hub_lpm(udev,
5005 state);
5006 if (timeout == USB3_LPM_DISABLED)
5007 return timeout;
5008 }
5009 }
5010
5011 /* Not sure how this could happen... */
5012 if (!intf->cur_altsetting)
5013 continue;
5014
5015 if (xhci_update_timeout_for_interface(xhci, udev,
5016 intf->cur_altsetting,
5017 state, &timeout))
5018 return timeout;
5019 }
5020 return timeout;
5021 }
5022
calculate_max_exit_latency(struct usb_device * udev,enum usb3_link_state state_changed,u16 hub_encoded_timeout)5023 static int calculate_max_exit_latency(struct usb_device *udev,
5024 enum usb3_link_state state_changed,
5025 u16 hub_encoded_timeout)
5026 {
5027 unsigned long long u1_mel_us = 0;
5028 unsigned long long u2_mel_us = 0;
5029 unsigned long long mel_us = 0;
5030 bool disabling_u1;
5031 bool disabling_u2;
5032 bool enabling_u1;
5033 bool enabling_u2;
5034
5035 disabling_u1 = (state_changed == USB3_LPM_U1 &&
5036 hub_encoded_timeout == USB3_LPM_DISABLED);
5037 disabling_u2 = (state_changed == USB3_LPM_U2 &&
5038 hub_encoded_timeout == USB3_LPM_DISABLED);
5039
5040 enabling_u1 = (state_changed == USB3_LPM_U1 &&
5041 hub_encoded_timeout != USB3_LPM_DISABLED);
5042 enabling_u2 = (state_changed == USB3_LPM_U2 &&
5043 hub_encoded_timeout != USB3_LPM_DISABLED);
5044
5045 /* If U1 was already enabled and we're not disabling it,
5046 * or we're going to enable U1, account for the U1 max exit latency.
5047 */
5048 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
5049 enabling_u1)
5050 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
5051 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
5052 enabling_u2)
5053 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5054
5055 if (u1_mel_us > u2_mel_us)
5056 mel_us = u1_mel_us;
5057 else
5058 mel_us = u2_mel_us;
5059 /* xHCI host controller max exit latency field is only 16 bits wide. */
5060 if (mel_us > MAX_EXIT) {
5061 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5062 "is too big.\n", mel_us);
5063 return -E2BIG;
5064 }
5065 return mel_us;
5066 }
5067
5068 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
xhci_enable_usb3_lpm_timeout(struct usb_hcd * hcd,struct usb_device * udev,enum usb3_link_state state)5069 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5070 struct usb_device *udev, enum usb3_link_state state)
5071 {
5072 struct xhci_hcd *xhci;
5073 struct xhci_port *port;
5074 u16 hub_encoded_timeout;
5075 int mel;
5076 int ret;
5077
5078 xhci = hcd_to_xhci(hcd);
5079 /* The LPM timeout values are pretty host-controller specific, so don't
5080 * enable hub-initiated timeouts unless the vendor has provided
5081 * information about their timeout algorithm.
5082 */
5083 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5084 !xhci->devs[udev->slot_id])
5085 return USB3_LPM_DISABLED;
5086
5087 /* If connected to root port then check port can handle lpm */
5088 if (udev->parent && !udev->parent->parent) {
5089 port = xhci->usb3_rhub.ports[udev->portnum - 1];
5090 if (port->lpm_incapable)
5091 return USB3_LPM_DISABLED;
5092 }
5093
5094 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5095 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5096 if (mel < 0) {
5097 /* Max Exit Latency is too big, disable LPM. */
5098 hub_encoded_timeout = USB3_LPM_DISABLED;
5099 mel = 0;
5100 }
5101
5102 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5103 if (ret)
5104 return ret;
5105 return hub_encoded_timeout;
5106 }
5107
xhci_disable_usb3_lpm_timeout(struct usb_hcd * hcd,struct usb_device * udev,enum usb3_link_state state)5108 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5109 struct usb_device *udev, enum usb3_link_state state)
5110 {
5111 struct xhci_hcd *xhci;
5112 u16 mel;
5113
5114 xhci = hcd_to_xhci(hcd);
5115 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5116 !xhci->devs[udev->slot_id])
5117 return 0;
5118
5119 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5120 return xhci_change_max_exit_latency(xhci, udev, mel);
5121 }
5122 #else /* CONFIG_PM */
5123
xhci_set_usb2_hardware_lpm(struct usb_hcd * hcd,struct usb_device * udev,int enable)5124 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5125 struct usb_device *udev, int enable)
5126 {
5127 return 0;
5128 }
5129
xhci_update_device(struct usb_hcd * hcd,struct usb_device * udev)5130 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5131 {
5132 return 0;
5133 }
5134
xhci_enable_usb3_lpm_timeout(struct usb_hcd * hcd,struct usb_device * udev,enum usb3_link_state state)5135 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5136 struct usb_device *udev, enum usb3_link_state state)
5137 {
5138 return USB3_LPM_DISABLED;
5139 }
5140
xhci_disable_usb3_lpm_timeout(struct usb_hcd * hcd,struct usb_device * udev,enum usb3_link_state state)5141 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5142 struct usb_device *udev, enum usb3_link_state state)
5143 {
5144 return 0;
5145 }
5146 #endif /* CONFIG_PM */
5147
5148 /*-------------------------------------------------------------------------*/
5149
5150 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5151 * internal data structures for the device.
5152 */
xhci_update_hub_device(struct usb_hcd * hcd,struct usb_device * hdev,struct usb_tt * tt,gfp_t mem_flags)5153 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5154 struct usb_tt *tt, gfp_t mem_flags)
5155 {
5156 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5157 struct xhci_virt_device *vdev;
5158 struct xhci_command *config_cmd;
5159 struct xhci_input_control_ctx *ctrl_ctx;
5160 struct xhci_slot_ctx *slot_ctx;
5161 unsigned long flags;
5162 unsigned think_time;
5163 int ret;
5164
5165 /* Ignore root hubs */
5166 if (!hdev->parent)
5167 return 0;
5168
5169 vdev = xhci->devs[hdev->slot_id];
5170 if (!vdev) {
5171 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5172 return -EINVAL;
5173 }
5174
5175 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5176 if (!config_cmd)
5177 return -ENOMEM;
5178
5179 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5180 if (!ctrl_ctx) {
5181 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5182 __func__);
5183 xhci_free_command(xhci, config_cmd);
5184 return -ENOMEM;
5185 }
5186
5187 spin_lock_irqsave(&xhci->lock, flags);
5188 if (hdev->speed == USB_SPEED_HIGH &&
5189 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5190 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5191 xhci_free_command(xhci, config_cmd);
5192 spin_unlock_irqrestore(&xhci->lock, flags);
5193 return -ENOMEM;
5194 }
5195
5196 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5197 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5198 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5199 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5200 /*
5201 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5202 * but it may be already set to 1 when setup an xHCI virtual
5203 * device, so clear it anyway.
5204 */
5205 if (tt->multi)
5206 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5207 else if (hdev->speed == USB_SPEED_FULL)
5208 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5209
5210 if (xhci->hci_version > 0x95) {
5211 xhci_dbg(xhci, "xHCI version %x needs hub "
5212 "TT think time and number of ports\n",
5213 (unsigned int) xhci->hci_version);
5214 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5215 /* Set TT think time - convert from ns to FS bit times.
5216 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5217 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5218 *
5219 * xHCI 1.0: this field shall be 0 if the device is not a
5220 * High-spped hub.
5221 */
5222 think_time = tt->think_time;
5223 if (think_time != 0)
5224 think_time = (think_time / 666) - 1;
5225 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5226 slot_ctx->tt_info |=
5227 cpu_to_le32(TT_THINK_TIME(think_time));
5228 } else {
5229 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5230 "TT think time or number of ports\n",
5231 (unsigned int) xhci->hci_version);
5232 }
5233 slot_ctx->dev_state = 0;
5234 spin_unlock_irqrestore(&xhci->lock, flags);
5235
5236 xhci_dbg(xhci, "Set up %s for hub device.\n",
5237 (xhci->hci_version > 0x95) ?
5238 "configure endpoint" : "evaluate context");
5239
5240 /* Issue and wait for the configure endpoint or
5241 * evaluate context command.
5242 */
5243 if (xhci->hci_version > 0x95)
5244 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5245 false, false);
5246 else
5247 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5248 true, false);
5249
5250 xhci_free_command(xhci, config_cmd);
5251 return ret;
5252 }
5253 EXPORT_SYMBOL_GPL(xhci_update_hub_device);
5254
xhci_get_frame(struct usb_hcd * hcd)5255 static int xhci_get_frame(struct usb_hcd *hcd)
5256 {
5257 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5258 /* EHCI mods by the periodic size. Why? */
5259 return readl(&xhci->run_regs->microframe_index) >> 3;
5260 }
5261
xhci_gen_setup(struct usb_hcd * hcd,xhci_get_quirks_t get_quirks)5262 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5263 {
5264 struct xhci_hcd *xhci;
5265 /*
5266 * TODO: Check with DWC3 clients for sysdev according to
5267 * quirks
5268 */
5269 struct device *dev = hcd->self.sysdev;
5270 unsigned int minor_rev;
5271 int retval;
5272
5273 /* Accept arbitrarily long scatter-gather lists */
5274 hcd->self.sg_tablesize = ~0;
5275
5276 /* support to build packet from discontinuous buffers */
5277 hcd->self.no_sg_constraint = 1;
5278
5279 /* XHCI controllers don't stop the ep queue on short packets :| */
5280 hcd->self.no_stop_on_short = 1;
5281
5282 xhci = hcd_to_xhci(hcd);
5283
5284 if (usb_hcd_is_primary_hcd(hcd)) {
5285 xhci->main_hcd = hcd;
5286 xhci->usb2_rhub.hcd = hcd;
5287 /* Mark the first roothub as being USB 2.0.
5288 * The xHCI driver will register the USB 3.0 roothub.
5289 */
5290 hcd->speed = HCD_USB2;
5291 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5292 /*
5293 * USB 2.0 roothub under xHCI has an integrated TT,
5294 * (rate matching hub) as opposed to having an OHCI/UHCI
5295 * companion controller.
5296 */
5297 hcd->has_tt = 1;
5298 } else {
5299 /*
5300 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5301 * should return 0x31 for sbrn, or that the minor revision
5302 * is a two digit BCD containig minor and sub-minor numbers.
5303 * This was later clarified in xHCI 1.2.
5304 *
5305 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5306 * minor revision set to 0x1 instead of 0x10.
5307 */
5308 if (xhci->usb3_rhub.min_rev == 0x1)
5309 minor_rev = 1;
5310 else
5311 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5312
5313 switch (minor_rev) {
5314 case 2:
5315 hcd->speed = HCD_USB32;
5316 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5317 hcd->self.root_hub->rx_lanes = 2;
5318 hcd->self.root_hub->tx_lanes = 2;
5319 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5320 break;
5321 case 1:
5322 hcd->speed = HCD_USB31;
5323 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5324 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5325 break;
5326 }
5327 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5328 minor_rev,
5329 minor_rev ? "Enhanced " : "");
5330
5331 xhci->usb3_rhub.hcd = hcd;
5332 /* xHCI private pointer was set in xhci_pci_probe for the second
5333 * registered roothub.
5334 */
5335 return 0;
5336 }
5337
5338 mutex_init(&xhci->mutex);
5339 xhci->cap_regs = hcd->regs;
5340 xhci->op_regs = hcd->regs +
5341 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5342 xhci->run_regs = hcd->regs +
5343 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5344 /* Cache read-only capability registers */
5345 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5346 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5347 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5348 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5349 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5350 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5351 if (xhci->hci_version > 0x100)
5352 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5353
5354 xhci->quirks |= quirks;
5355
5356 get_quirks(dev, xhci);
5357
5358 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5359 * success event after a short transfer. This quirk will ignore such
5360 * spurious event.
5361 */
5362 if (xhci->hci_version > 0x96)
5363 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5364
5365 /* Make sure the HC is halted. */
5366 retval = xhci_halt(xhci);
5367 if (retval)
5368 return retval;
5369
5370 xhci_zero_64b_regs(xhci);
5371
5372 xhci_dbg(xhci, "Resetting HCD\n");
5373 /* Reset the internal HC memory state and registers. */
5374 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5375 if (retval)
5376 return retval;
5377 xhci_dbg(xhci, "Reset complete\n");
5378
5379 /*
5380 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5381 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5382 * address memory pointers actually. So, this driver clears the AC64
5383 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5384 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5385 */
5386 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5387 xhci->hcc_params &= ~BIT(0);
5388
5389 /* Set dma_mask and coherent_dma_mask to 64-bits,
5390 * if xHC supports 64-bit addressing */
5391 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5392 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5393 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5394 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5395 } else {
5396 /*
5397 * This is to avoid error in cases where a 32-bit USB
5398 * controller is used on a 64-bit capable system.
5399 */
5400 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5401 if (retval)
5402 return retval;
5403 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5404 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5405 }
5406
5407 xhci_dbg(xhci, "Calling HCD init\n");
5408 /* Initialize HCD and host controller data structures. */
5409 retval = xhci_init(hcd);
5410 if (retval)
5411 return retval;
5412 xhci_dbg(xhci, "Called HCD init\n");
5413
5414 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5415 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5416
5417 return 0;
5418 }
5419 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5420
xhci_clear_tt_buffer_complete(struct usb_hcd * hcd,struct usb_host_endpoint * ep)5421 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5422 struct usb_host_endpoint *ep)
5423 {
5424 struct xhci_hcd *xhci;
5425 struct usb_device *udev;
5426 unsigned int slot_id;
5427 unsigned int ep_index;
5428 unsigned long flags;
5429
5430 xhci = hcd_to_xhci(hcd);
5431
5432 spin_lock_irqsave(&xhci->lock, flags);
5433 udev = (struct usb_device *)ep->hcpriv;
5434 slot_id = udev->slot_id;
5435 ep_index = xhci_get_endpoint_index(&ep->desc);
5436
5437 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5438 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5439 spin_unlock_irqrestore(&xhci->lock, flags);
5440 }
5441
5442 static const struct hc_driver xhci_hc_driver = {
5443 .description = "xhci-hcd",
5444 .product_desc = "xHCI Host Controller",
5445 .hcd_priv_size = sizeof(struct xhci_hcd),
5446
5447 /*
5448 * generic hardware linkage
5449 */
5450 .irq = xhci_irq,
5451 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5452 HCD_BH,
5453
5454 /*
5455 * basic lifecycle operations
5456 */
5457 .reset = NULL, /* set in xhci_init_driver() */
5458 .start = xhci_run,
5459 .stop = xhci_stop,
5460 .shutdown = xhci_shutdown,
5461
5462 /*
5463 * managing i/o requests and associated device resources
5464 */
5465 .map_urb_for_dma = xhci_map_urb_for_dma,
5466 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5467 .urb_enqueue = xhci_urb_enqueue,
5468 .urb_dequeue = xhci_urb_dequeue,
5469 .alloc_dev = xhci_alloc_dev,
5470 .free_dev = xhci_free_dev,
5471 .alloc_streams = xhci_alloc_streams,
5472 .free_streams = xhci_free_streams,
5473 .add_endpoint = xhci_add_endpoint,
5474 .drop_endpoint = xhci_drop_endpoint,
5475 .endpoint_disable = xhci_endpoint_disable,
5476 .endpoint_reset = xhci_endpoint_reset,
5477 .check_bandwidth = xhci_check_bandwidth,
5478 .reset_bandwidth = xhci_reset_bandwidth,
5479 .address_device = xhci_address_device,
5480 .enable_device = xhci_enable_device,
5481 .update_hub_device = xhci_update_hub_device,
5482 .reset_device = xhci_discover_or_reset_device,
5483
5484 /*
5485 * scheduling support
5486 */
5487 .get_frame_number = xhci_get_frame,
5488
5489 /*
5490 * root hub support
5491 */
5492 .hub_control = xhci_hub_control,
5493 .hub_status_data = xhci_hub_status_data,
5494 .bus_suspend = xhci_bus_suspend,
5495 .bus_resume = xhci_bus_resume,
5496 .get_resuming_ports = xhci_get_resuming_ports,
5497
5498 /*
5499 * call back when device connected and addressed
5500 */
5501 .update_device = xhci_update_device,
5502 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5503 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5504 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5505 .find_raw_port_number = xhci_find_raw_port_number,
5506 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5507 };
5508
xhci_init_driver(struct hc_driver * drv,const struct xhci_driver_overrides * over)5509 void xhci_init_driver(struct hc_driver *drv,
5510 const struct xhci_driver_overrides *over)
5511 {
5512 BUG_ON(!over);
5513
5514 /* Copy the generic table to drv then apply the overrides */
5515 *drv = xhci_hc_driver;
5516
5517 if (over) {
5518 drv->hcd_priv_size += over->extra_priv_size;
5519 if (over->reset)
5520 drv->reset = over->reset;
5521 if (over->start)
5522 drv->start = over->start;
5523 if (over->add_endpoint)
5524 drv->add_endpoint = over->add_endpoint;
5525 if (over->drop_endpoint)
5526 drv->drop_endpoint = over->drop_endpoint;
5527 if (over->check_bandwidth)
5528 drv->check_bandwidth = over->check_bandwidth;
5529 if (over->reset_bandwidth)
5530 drv->reset_bandwidth = over->reset_bandwidth;
5531 if (over->update_hub_device)
5532 drv->update_hub_device = over->update_hub_device;
5533 }
5534 }
5535 EXPORT_SYMBOL_GPL(xhci_init_driver);
5536
5537 MODULE_DESCRIPTION(DRIVER_DESC);
5538 MODULE_AUTHOR(DRIVER_AUTHOR);
5539 MODULE_LICENSE("GPL");
5540
xhci_hcd_init(void)5541 static int __init xhci_hcd_init(void)
5542 {
5543 /*
5544 * Check the compiler generated sizes of structures that must be laid
5545 * out in specific ways for hardware access.
5546 */
5547 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5548 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5549 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5550 /* xhci_device_control has eight fields, and also
5551 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5552 */
5553 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5554 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5555 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5556 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5557 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5558 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5559 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5560
5561 if (usb_disabled())
5562 return -ENODEV;
5563
5564 xhci_debugfs_create_root();
5565
5566 return 0;
5567 }
5568
5569 /*
5570 * If an init function is provided, an exit function must also be provided
5571 * to allow module unload.
5572 */
xhci_hcd_fini(void)5573 static void __exit xhci_hcd_fini(void)
5574 {
5575 xhci_debugfs_remove_root();
5576 }
5577
5578 module_init(xhci_hcd_init);
5579 module_exit(xhci_hcd_fini);
5580