1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Synopsys DesignWare Multimedia Card Interface driver
4 * (Based on NXP driver for lpc 31xx)
5 *
6 * Copyright (C) 2009 NXP Semiconductors
7 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 */
9
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/iopoll.h>
19 #include <linux/ioport.h>
20 #include <linux/ktime.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/prandom.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/bitops.h>
36 #include <linux/regulator/consumer.h>
37 #include <linux/of.h>
38 #include <linux/of_gpio.h>
39 #include <linux/mmc/slot-gpio.h>
40
41 #include "dw_mmc.h"
42
43 /* Common flag combinations */
44 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
45 SDMMC_INT_HTO | SDMMC_INT_SBE | \
46 SDMMC_INT_EBE | SDMMC_INT_HLE)
47 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
48 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
49 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
50 DW_MCI_CMD_ERROR_FLAGS)
51 #define DW_MCI_SEND_STATUS 1
52 #define DW_MCI_RECV_STATUS 2
53 #define DW_MCI_DMA_THRESHOLD 16
54
55 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
56 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
57
58 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
59 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
60 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
61 SDMMC_IDMAC_INT_TI)
62
63 #define DESC_RING_BUF_SZ PAGE_SIZE
64
65 struct idmac_desc_64addr {
66 u32 des0; /* Control Descriptor */
67 #define IDMAC_OWN_CLR64(x) \
68 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
69
70 u32 des1; /* Reserved */
71
72 u32 des2; /*Buffer sizes */
73 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
74 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
75 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
76
77 u32 des3; /* Reserved */
78
79 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
80 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
81
82 u32 des6; /* Lower 32-bits of Next Descriptor Address */
83 u32 des7; /* Upper 32-bits of Next Descriptor Address */
84 };
85
86 struct idmac_desc {
87 __le32 des0; /* Control Descriptor */
88 #define IDMAC_DES0_DIC BIT(1)
89 #define IDMAC_DES0_LD BIT(2)
90 #define IDMAC_DES0_FD BIT(3)
91 #define IDMAC_DES0_CH BIT(4)
92 #define IDMAC_DES0_ER BIT(5)
93 #define IDMAC_DES0_CES BIT(30)
94 #define IDMAC_DES0_OWN BIT(31)
95
96 __le32 des1; /* Buffer sizes */
97 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
98 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
99
100 __le32 des2; /* buffer 1 physical address */
101
102 __le32 des3; /* buffer 2 physical address */
103 };
104
105 /* Each descriptor can transfer up to 4KB of data in chained mode */
106 #define DW_MCI_DESC_DATA_LENGTH 0x1000
107
108 #if defined(CONFIG_DEBUG_FS)
dw_mci_req_show(struct seq_file * s,void * v)109 static int dw_mci_req_show(struct seq_file *s, void *v)
110 {
111 struct dw_mci_slot *slot = s->private;
112 struct mmc_request *mrq;
113 struct mmc_command *cmd;
114 struct mmc_command *stop;
115 struct mmc_data *data;
116
117 /* Make sure we get a consistent snapshot */
118 spin_lock_bh(&slot->host->lock);
119 mrq = slot->mrq;
120
121 if (mrq) {
122 cmd = mrq->cmd;
123 data = mrq->data;
124 stop = mrq->stop;
125
126 if (cmd)
127 seq_printf(s,
128 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
129 cmd->opcode, cmd->arg, cmd->flags,
130 cmd->resp[0], cmd->resp[1], cmd->resp[2],
131 cmd->resp[2], cmd->error);
132 if (data)
133 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
134 data->bytes_xfered, data->blocks,
135 data->blksz, data->flags, data->error);
136 if (stop)
137 seq_printf(s,
138 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
139 stop->opcode, stop->arg, stop->flags,
140 stop->resp[0], stop->resp[1], stop->resp[2],
141 stop->resp[2], stop->error);
142 }
143
144 spin_unlock_bh(&slot->host->lock);
145
146 return 0;
147 }
148 DEFINE_SHOW_ATTRIBUTE(dw_mci_req);
149
dw_mci_regs_show(struct seq_file * s,void * v)150 static int dw_mci_regs_show(struct seq_file *s, void *v)
151 {
152 struct dw_mci *host = s->private;
153
154 pm_runtime_get_sync(host->dev);
155
156 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
157 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
158 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
159 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
160 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
161 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
162
163 pm_runtime_put_autosuspend(host->dev);
164
165 return 0;
166 }
167 DEFINE_SHOW_ATTRIBUTE(dw_mci_regs);
168
dw_mci_init_debugfs(struct dw_mci_slot * slot)169 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
170 {
171 struct mmc_host *mmc = slot->mmc;
172 struct dw_mci *host = slot->host;
173 struct dentry *root;
174
175 root = mmc->debugfs_root;
176 if (!root)
177 return;
178
179 debugfs_create_file("regs", S_IRUSR, root, host, &dw_mci_regs_fops);
180 debugfs_create_file("req", S_IRUSR, root, slot, &dw_mci_req_fops);
181 debugfs_create_u32("state", S_IRUSR, root, &host->state);
182 debugfs_create_xul("pending_events", S_IRUSR, root,
183 &host->pending_events);
184 debugfs_create_xul("completed_events", S_IRUSR, root,
185 &host->completed_events);
186 #ifdef CONFIG_FAULT_INJECTION
187 fault_create_debugfs_attr("fail_data_crc", root, &host->fail_data_crc);
188 #endif
189 }
190 #endif /* defined(CONFIG_DEBUG_FS) */
191
dw_mci_ctrl_reset(struct dw_mci * host,u32 reset)192 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
193 {
194 u32 ctrl;
195
196 ctrl = mci_readl(host, CTRL);
197 ctrl |= reset;
198 mci_writel(host, CTRL, ctrl);
199
200 /* wait till resets clear */
201 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
202 !(ctrl & reset),
203 1, 500 * USEC_PER_MSEC)) {
204 dev_err(host->dev,
205 "Timeout resetting block (ctrl reset %#x)\n",
206 ctrl & reset);
207 return false;
208 }
209
210 return true;
211 }
212
dw_mci_wait_while_busy(struct dw_mci * host,u32 cmd_flags)213 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
214 {
215 u32 status;
216
217 /*
218 * Databook says that before issuing a new data transfer command
219 * we need to check to see if the card is busy. Data transfer commands
220 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
221 *
222 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
223 * expected.
224 */
225 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
226 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
227 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
228 status,
229 !(status & SDMMC_STATUS_BUSY),
230 10, 500 * USEC_PER_MSEC))
231 dev_err(host->dev, "Busy; trying anyway\n");
232 }
233 }
234
mci_send_cmd(struct dw_mci_slot * slot,u32 cmd,u32 arg)235 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
236 {
237 struct dw_mci *host = slot->host;
238 unsigned int cmd_status = 0;
239
240 mci_writel(host, CMDARG, arg);
241 wmb(); /* drain writebuffer */
242 dw_mci_wait_while_busy(host, cmd);
243 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
244
245 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
246 !(cmd_status & SDMMC_CMD_START),
247 1, 500 * USEC_PER_MSEC))
248 dev_err(&slot->mmc->class_dev,
249 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
250 cmd, arg, cmd_status);
251 }
252
dw_mci_prepare_command(struct mmc_host * mmc,struct mmc_command * cmd)253 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
254 {
255 struct dw_mci_slot *slot = mmc_priv(mmc);
256 struct dw_mci *host = slot->host;
257 u32 cmdr;
258
259 cmd->error = -EINPROGRESS;
260 cmdr = cmd->opcode;
261
262 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
263 cmd->opcode == MMC_GO_IDLE_STATE ||
264 cmd->opcode == MMC_GO_INACTIVE_STATE ||
265 (cmd->opcode == SD_IO_RW_DIRECT &&
266 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
267 cmdr |= SDMMC_CMD_STOP;
268 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
269 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
270
271 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
272 u32 clk_en_a;
273
274 /* Special bit makes CMD11 not die */
275 cmdr |= SDMMC_CMD_VOLT_SWITCH;
276
277 /* Change state to continue to handle CMD11 weirdness */
278 WARN_ON(slot->host->state != STATE_SENDING_CMD);
279 slot->host->state = STATE_SENDING_CMD11;
280
281 /*
282 * We need to disable low power mode (automatic clock stop)
283 * while doing voltage switch so we don't confuse the card,
284 * since stopping the clock is a specific part of the UHS
285 * voltage change dance.
286 *
287 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
288 * unconditionally turned back on in dw_mci_setup_bus() if it's
289 * ever called with a non-zero clock. That shouldn't happen
290 * until the voltage change is all done.
291 */
292 clk_en_a = mci_readl(host, CLKENA);
293 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
294 mci_writel(host, CLKENA, clk_en_a);
295 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
296 SDMMC_CMD_PRV_DAT_WAIT, 0);
297 }
298
299 if (cmd->flags & MMC_RSP_PRESENT) {
300 /* We expect a response, so set this bit */
301 cmdr |= SDMMC_CMD_RESP_EXP;
302 if (cmd->flags & MMC_RSP_136)
303 cmdr |= SDMMC_CMD_RESP_LONG;
304 }
305
306 if (cmd->flags & MMC_RSP_CRC)
307 cmdr |= SDMMC_CMD_RESP_CRC;
308
309 if (cmd->data) {
310 cmdr |= SDMMC_CMD_DAT_EXP;
311 if (cmd->data->flags & MMC_DATA_WRITE)
312 cmdr |= SDMMC_CMD_DAT_WR;
313 }
314
315 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
316 cmdr |= SDMMC_CMD_USE_HOLD_REG;
317
318 return cmdr;
319 }
320
dw_mci_prep_stop_abort(struct dw_mci * host,struct mmc_command * cmd)321 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
322 {
323 struct mmc_command *stop;
324 u32 cmdr;
325
326 if (!cmd->data)
327 return 0;
328
329 stop = &host->stop_abort;
330 cmdr = cmd->opcode;
331 memset(stop, 0, sizeof(struct mmc_command));
332
333 if (cmdr == MMC_READ_SINGLE_BLOCK ||
334 cmdr == MMC_READ_MULTIPLE_BLOCK ||
335 cmdr == MMC_WRITE_BLOCK ||
336 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
337 cmdr == MMC_SEND_TUNING_BLOCK ||
338 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
339 stop->opcode = MMC_STOP_TRANSMISSION;
340 stop->arg = 0;
341 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
342 } else if (cmdr == SD_IO_RW_EXTENDED) {
343 stop->opcode = SD_IO_RW_DIRECT;
344 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
345 ((cmd->arg >> 28) & 0x7);
346 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
347 } else {
348 return 0;
349 }
350
351 cmdr = stop->opcode | SDMMC_CMD_STOP |
352 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
353
354 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
355 cmdr |= SDMMC_CMD_USE_HOLD_REG;
356
357 return cmdr;
358 }
359
dw_mci_set_cto(struct dw_mci * host)360 static inline void dw_mci_set_cto(struct dw_mci *host)
361 {
362 unsigned int cto_clks;
363 unsigned int cto_div;
364 unsigned int cto_ms;
365 unsigned long irqflags;
366
367 cto_clks = mci_readl(host, TMOUT) & 0xff;
368 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
369 if (cto_div == 0)
370 cto_div = 1;
371
372 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
373 host->bus_hz);
374
375 /* add a bit spare time */
376 cto_ms += 10;
377
378 /*
379 * The durations we're working with are fairly short so we have to be
380 * extra careful about synchronization here. Specifically in hardware a
381 * command timeout is _at most_ 5.1 ms, so that means we expect an
382 * interrupt (either command done or timeout) to come rather quickly
383 * after the mci_writel. ...but just in case we have a long interrupt
384 * latency let's add a bit of paranoia.
385 *
386 * In general we'll assume that at least an interrupt will be asserted
387 * in hardware by the time the cto_timer runs. ...and if it hasn't
388 * been asserted in hardware by that time then we'll assume it'll never
389 * come.
390 */
391 spin_lock_irqsave(&host->irq_lock, irqflags);
392 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
393 mod_timer(&host->cto_timer,
394 jiffies + msecs_to_jiffies(cto_ms) + 1);
395 spin_unlock_irqrestore(&host->irq_lock, irqflags);
396 }
397
dw_mci_start_command(struct dw_mci * host,struct mmc_command * cmd,u32 cmd_flags)398 static void dw_mci_start_command(struct dw_mci *host,
399 struct mmc_command *cmd, u32 cmd_flags)
400 {
401 host->cmd = cmd;
402 dev_vdbg(host->dev,
403 "start command: ARGR=0x%08x CMDR=0x%08x\n",
404 cmd->arg, cmd_flags);
405
406 mci_writel(host, CMDARG, cmd->arg);
407 wmb(); /* drain writebuffer */
408 dw_mci_wait_while_busy(host, cmd_flags);
409
410 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
411
412 /* response expected command only */
413 if (cmd_flags & SDMMC_CMD_RESP_EXP)
414 dw_mci_set_cto(host);
415 }
416
send_stop_abort(struct dw_mci * host,struct mmc_data * data)417 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
418 {
419 struct mmc_command *stop = &host->stop_abort;
420
421 dw_mci_start_command(host, stop, host->stop_cmdr);
422 }
423
424 /* DMA interface functions */
dw_mci_stop_dma(struct dw_mci * host)425 static void dw_mci_stop_dma(struct dw_mci *host)
426 {
427 if (host->using_dma) {
428 host->dma_ops->stop(host);
429 host->dma_ops->cleanup(host);
430 }
431
432 /* Data transfer was stopped by the interrupt handler */
433 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
434 }
435
dw_mci_dma_cleanup(struct dw_mci * host)436 static void dw_mci_dma_cleanup(struct dw_mci *host)
437 {
438 struct mmc_data *data = host->data;
439
440 if (data && data->host_cookie == COOKIE_MAPPED) {
441 dma_unmap_sg(host->dev,
442 data->sg,
443 data->sg_len,
444 mmc_get_dma_dir(data));
445 data->host_cookie = COOKIE_UNMAPPED;
446 }
447 }
448
dw_mci_idmac_reset(struct dw_mci * host)449 static void dw_mci_idmac_reset(struct dw_mci *host)
450 {
451 u32 bmod = mci_readl(host, BMOD);
452 /* Software reset of DMA */
453 bmod |= SDMMC_IDMAC_SWRESET;
454 mci_writel(host, BMOD, bmod);
455 }
456
dw_mci_idmac_stop_dma(struct dw_mci * host)457 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
458 {
459 u32 temp;
460
461 /* Disable and reset the IDMAC interface */
462 temp = mci_readl(host, CTRL);
463 temp &= ~SDMMC_CTRL_USE_IDMAC;
464 temp |= SDMMC_CTRL_DMA_RESET;
465 mci_writel(host, CTRL, temp);
466
467 /* Stop the IDMAC running */
468 temp = mci_readl(host, BMOD);
469 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
470 temp |= SDMMC_IDMAC_SWRESET;
471 mci_writel(host, BMOD, temp);
472 }
473
dw_mci_dmac_complete_dma(void * arg)474 static void dw_mci_dmac_complete_dma(void *arg)
475 {
476 struct dw_mci *host = arg;
477 struct mmc_data *data = host->data;
478
479 dev_vdbg(host->dev, "DMA complete\n");
480
481 if ((host->use_dma == TRANS_MODE_EDMAC) &&
482 data && (data->flags & MMC_DATA_READ))
483 /* Invalidate cache after read */
484 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
485 data->sg,
486 data->sg_len,
487 DMA_FROM_DEVICE);
488
489 host->dma_ops->cleanup(host);
490
491 /*
492 * If the card was removed, data will be NULL. No point in trying to
493 * send the stop command or waiting for NBUSY in this case.
494 */
495 if (data) {
496 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
497 tasklet_schedule(&host->tasklet);
498 }
499 }
500
dw_mci_idmac_init(struct dw_mci * host)501 static int dw_mci_idmac_init(struct dw_mci *host)
502 {
503 int i;
504
505 if (host->dma_64bit_address == 1) {
506 struct idmac_desc_64addr *p;
507 /* Number of descriptors in the ring buffer */
508 host->ring_size =
509 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
510
511 /* Forward link the descriptor list */
512 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
513 i++, p++) {
514 p->des6 = (host->sg_dma +
515 (sizeof(struct idmac_desc_64addr) *
516 (i + 1))) & 0xffffffff;
517
518 p->des7 = (u64)(host->sg_dma +
519 (sizeof(struct idmac_desc_64addr) *
520 (i + 1))) >> 32;
521 /* Initialize reserved and buffer size fields to "0" */
522 p->des0 = 0;
523 p->des1 = 0;
524 p->des2 = 0;
525 p->des3 = 0;
526 }
527
528 /* Set the last descriptor as the end-of-ring descriptor */
529 p->des6 = host->sg_dma & 0xffffffff;
530 p->des7 = (u64)host->sg_dma >> 32;
531 p->des0 = IDMAC_DES0_ER;
532
533 } else {
534 struct idmac_desc *p;
535 /* Number of descriptors in the ring buffer */
536 host->ring_size =
537 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
538
539 /* Forward link the descriptor list */
540 for (i = 0, p = host->sg_cpu;
541 i < host->ring_size - 1;
542 i++, p++) {
543 p->des3 = cpu_to_le32(host->sg_dma +
544 (sizeof(struct idmac_desc) * (i + 1)));
545 p->des0 = 0;
546 p->des1 = 0;
547 }
548
549 /* Set the last descriptor as the end-of-ring descriptor */
550 p->des3 = cpu_to_le32(host->sg_dma);
551 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
552 }
553
554 dw_mci_idmac_reset(host);
555
556 if (host->dma_64bit_address == 1) {
557 /* Mask out interrupts - get Tx & Rx complete only */
558 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
559 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
560 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
561
562 /* Set the descriptor base address */
563 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
564 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
565
566 } else {
567 /* Mask out interrupts - get Tx & Rx complete only */
568 mci_writel(host, IDSTS, IDMAC_INT_CLR);
569 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
570 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
571
572 /* Set the descriptor base address */
573 mci_writel(host, DBADDR, host->sg_dma);
574 }
575
576 return 0;
577 }
578
dw_mci_prepare_desc64(struct dw_mci * host,struct mmc_data * data,unsigned int sg_len)579 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
580 struct mmc_data *data,
581 unsigned int sg_len)
582 {
583 unsigned int desc_len;
584 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
585 u32 val;
586 int i;
587
588 desc_first = desc_last = desc = host->sg_cpu;
589
590 for (i = 0; i < sg_len; i++) {
591 unsigned int length = sg_dma_len(&data->sg[i]);
592
593 u64 mem_addr = sg_dma_address(&data->sg[i]);
594
595 for ( ; length ; desc++) {
596 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
597 length : DW_MCI_DESC_DATA_LENGTH;
598
599 length -= desc_len;
600
601 /*
602 * Wait for the former clear OWN bit operation
603 * of IDMAC to make sure that this descriptor
604 * isn't still owned by IDMAC as IDMAC's write
605 * ops and CPU's read ops are asynchronous.
606 */
607 if (readl_poll_timeout_atomic(&desc->des0, val,
608 !(val & IDMAC_DES0_OWN),
609 10, 100 * USEC_PER_MSEC))
610 goto err_own_bit;
611
612 /*
613 * Set the OWN bit and disable interrupts
614 * for this descriptor
615 */
616 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
617 IDMAC_DES0_CH;
618
619 /* Buffer length */
620 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
621
622 /* Physical address to DMA to/from */
623 desc->des4 = mem_addr & 0xffffffff;
624 desc->des5 = mem_addr >> 32;
625
626 /* Update physical address for the next desc */
627 mem_addr += desc_len;
628
629 /* Save pointer to the last descriptor */
630 desc_last = desc;
631 }
632 }
633
634 /* Set first descriptor */
635 desc_first->des0 |= IDMAC_DES0_FD;
636
637 /* Set last descriptor */
638 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
639 desc_last->des0 |= IDMAC_DES0_LD;
640
641 return 0;
642 err_own_bit:
643 /* restore the descriptor chain as it's polluted */
644 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
645 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
646 dw_mci_idmac_init(host);
647 return -EINVAL;
648 }
649
650
dw_mci_prepare_desc32(struct dw_mci * host,struct mmc_data * data,unsigned int sg_len)651 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
652 struct mmc_data *data,
653 unsigned int sg_len)
654 {
655 unsigned int desc_len;
656 struct idmac_desc *desc_first, *desc_last, *desc;
657 u32 val;
658 int i;
659
660 desc_first = desc_last = desc = host->sg_cpu;
661
662 for (i = 0; i < sg_len; i++) {
663 unsigned int length = sg_dma_len(&data->sg[i]);
664
665 u32 mem_addr = sg_dma_address(&data->sg[i]);
666
667 for ( ; length ; desc++) {
668 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
669 length : DW_MCI_DESC_DATA_LENGTH;
670
671 length -= desc_len;
672
673 /*
674 * Wait for the former clear OWN bit operation
675 * of IDMAC to make sure that this descriptor
676 * isn't still owned by IDMAC as IDMAC's write
677 * ops and CPU's read ops are asynchronous.
678 */
679 if (readl_poll_timeout_atomic(&desc->des0, val,
680 IDMAC_OWN_CLR64(val),
681 10,
682 100 * USEC_PER_MSEC))
683 goto err_own_bit;
684
685 /*
686 * Set the OWN bit and disable interrupts
687 * for this descriptor
688 */
689 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
690 IDMAC_DES0_DIC |
691 IDMAC_DES0_CH);
692
693 /* Buffer length */
694 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
695
696 /* Physical address to DMA to/from */
697 desc->des2 = cpu_to_le32(mem_addr);
698
699 /* Update physical address for the next desc */
700 mem_addr += desc_len;
701
702 /* Save pointer to the last descriptor */
703 desc_last = desc;
704 }
705 }
706
707 /* Set first descriptor */
708 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
709
710 /* Set last descriptor */
711 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
712 IDMAC_DES0_DIC));
713 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
714
715 return 0;
716 err_own_bit:
717 /* restore the descriptor chain as it's polluted */
718 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
719 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
720 dw_mci_idmac_init(host);
721 return -EINVAL;
722 }
723
dw_mci_idmac_start_dma(struct dw_mci * host,unsigned int sg_len)724 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
725 {
726 u32 temp;
727 int ret;
728
729 if (host->dma_64bit_address == 1)
730 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
731 else
732 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
733
734 if (ret)
735 goto out;
736
737 /* drain writebuffer */
738 wmb();
739
740 /* Make sure to reset DMA in case we did PIO before this */
741 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
742 dw_mci_idmac_reset(host);
743
744 /* Select IDMAC interface */
745 temp = mci_readl(host, CTRL);
746 temp |= SDMMC_CTRL_USE_IDMAC;
747 mci_writel(host, CTRL, temp);
748
749 /* drain writebuffer */
750 wmb();
751
752 /* Enable the IDMAC */
753 temp = mci_readl(host, BMOD);
754 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
755 mci_writel(host, BMOD, temp);
756
757 /* Start it running */
758 mci_writel(host, PLDMND, 1);
759
760 out:
761 return ret;
762 }
763
764 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
765 .init = dw_mci_idmac_init,
766 .start = dw_mci_idmac_start_dma,
767 .stop = dw_mci_idmac_stop_dma,
768 .complete = dw_mci_dmac_complete_dma,
769 .cleanup = dw_mci_dma_cleanup,
770 };
771
dw_mci_edmac_stop_dma(struct dw_mci * host)772 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
773 {
774 dmaengine_terminate_async(host->dms->ch);
775 }
776
dw_mci_edmac_start_dma(struct dw_mci * host,unsigned int sg_len)777 static int dw_mci_edmac_start_dma(struct dw_mci *host,
778 unsigned int sg_len)
779 {
780 struct dma_slave_config cfg;
781 struct dma_async_tx_descriptor *desc = NULL;
782 struct scatterlist *sgl = host->data->sg;
783 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
784 u32 sg_elems = host->data->sg_len;
785 u32 fifoth_val;
786 u32 fifo_offset = host->fifo_reg - host->regs;
787 int ret = 0;
788
789 /* Set external dma config: burst size, burst width */
790 memset(&cfg, 0, sizeof(cfg));
791 cfg.dst_addr = host->phy_regs + fifo_offset;
792 cfg.src_addr = cfg.dst_addr;
793 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
794 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
795
796 /* Match burst msize with external dma config */
797 fifoth_val = mci_readl(host, FIFOTH);
798 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
799 cfg.src_maxburst = cfg.dst_maxburst;
800
801 if (host->data->flags & MMC_DATA_WRITE)
802 cfg.direction = DMA_MEM_TO_DEV;
803 else
804 cfg.direction = DMA_DEV_TO_MEM;
805
806 ret = dmaengine_slave_config(host->dms->ch, &cfg);
807 if (ret) {
808 dev_err(host->dev, "Failed to config edmac.\n");
809 return -EBUSY;
810 }
811
812 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
813 sg_len, cfg.direction,
814 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
815 if (!desc) {
816 dev_err(host->dev, "Can't prepare slave sg.\n");
817 return -EBUSY;
818 }
819
820 /* Set dw_mci_dmac_complete_dma as callback */
821 desc->callback = dw_mci_dmac_complete_dma;
822 desc->callback_param = (void *)host;
823 dmaengine_submit(desc);
824
825 /* Flush cache before write */
826 if (host->data->flags & MMC_DATA_WRITE)
827 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
828 sg_elems, DMA_TO_DEVICE);
829
830 dma_async_issue_pending(host->dms->ch);
831
832 return 0;
833 }
834
dw_mci_edmac_init(struct dw_mci * host)835 static int dw_mci_edmac_init(struct dw_mci *host)
836 {
837 /* Request external dma channel */
838 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
839 if (!host->dms)
840 return -ENOMEM;
841
842 host->dms->ch = dma_request_chan(host->dev, "rx-tx");
843 if (IS_ERR(host->dms->ch)) {
844 int ret = PTR_ERR(host->dms->ch);
845
846 dev_err(host->dev, "Failed to get external DMA channel.\n");
847 kfree(host->dms);
848 host->dms = NULL;
849 return ret;
850 }
851
852 return 0;
853 }
854
dw_mci_edmac_exit(struct dw_mci * host)855 static void dw_mci_edmac_exit(struct dw_mci *host)
856 {
857 if (host->dms) {
858 if (host->dms->ch) {
859 dma_release_channel(host->dms->ch);
860 host->dms->ch = NULL;
861 }
862 kfree(host->dms);
863 host->dms = NULL;
864 }
865 }
866
867 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
868 .init = dw_mci_edmac_init,
869 .exit = dw_mci_edmac_exit,
870 .start = dw_mci_edmac_start_dma,
871 .stop = dw_mci_edmac_stop_dma,
872 .complete = dw_mci_dmac_complete_dma,
873 .cleanup = dw_mci_dma_cleanup,
874 };
875
dw_mci_pre_dma_transfer(struct dw_mci * host,struct mmc_data * data,int cookie)876 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
877 struct mmc_data *data,
878 int cookie)
879 {
880 struct scatterlist *sg;
881 unsigned int i, sg_len;
882
883 if (data->host_cookie == COOKIE_PRE_MAPPED)
884 return data->sg_len;
885
886 /*
887 * We don't do DMA on "complex" transfers, i.e. with
888 * non-word-aligned buffers or lengths. Also, we don't bother
889 * with all the DMA setup overhead for short transfers.
890 */
891 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
892 return -EINVAL;
893
894 if (data->blksz & 3)
895 return -EINVAL;
896
897 for_each_sg(data->sg, sg, data->sg_len, i) {
898 if (sg->offset & 3 || sg->length & 3)
899 return -EINVAL;
900 }
901
902 sg_len = dma_map_sg(host->dev,
903 data->sg,
904 data->sg_len,
905 mmc_get_dma_dir(data));
906 if (sg_len == 0)
907 return -EINVAL;
908
909 data->host_cookie = cookie;
910
911 return sg_len;
912 }
913
dw_mci_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)914 static void dw_mci_pre_req(struct mmc_host *mmc,
915 struct mmc_request *mrq)
916 {
917 struct dw_mci_slot *slot = mmc_priv(mmc);
918 struct mmc_data *data = mrq->data;
919
920 if (!slot->host->use_dma || !data)
921 return;
922
923 /* This data might be unmapped at this time */
924 data->host_cookie = COOKIE_UNMAPPED;
925
926 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
927 COOKIE_PRE_MAPPED) < 0)
928 data->host_cookie = COOKIE_UNMAPPED;
929 }
930
dw_mci_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)931 static void dw_mci_post_req(struct mmc_host *mmc,
932 struct mmc_request *mrq,
933 int err)
934 {
935 struct dw_mci_slot *slot = mmc_priv(mmc);
936 struct mmc_data *data = mrq->data;
937
938 if (!slot->host->use_dma || !data)
939 return;
940
941 if (data->host_cookie != COOKIE_UNMAPPED)
942 dma_unmap_sg(slot->host->dev,
943 data->sg,
944 data->sg_len,
945 mmc_get_dma_dir(data));
946 data->host_cookie = COOKIE_UNMAPPED;
947 }
948
dw_mci_get_cd(struct mmc_host * mmc)949 static int dw_mci_get_cd(struct mmc_host *mmc)
950 {
951 int present;
952 struct dw_mci_slot *slot = mmc_priv(mmc);
953 struct dw_mci *host = slot->host;
954 int gpio_cd = mmc_gpio_get_cd(mmc);
955
956 /* Use platform get_cd function, else try onboard card detect */
957 if (((mmc->caps & MMC_CAP_NEEDS_POLL)
958 || !mmc_card_is_removable(mmc))) {
959 present = 1;
960
961 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
962 if (mmc->caps & MMC_CAP_NEEDS_POLL) {
963 dev_info(&mmc->class_dev,
964 "card is polling.\n");
965 } else {
966 dev_info(&mmc->class_dev,
967 "card is non-removable.\n");
968 }
969 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
970 }
971
972 return present;
973 } else if (gpio_cd >= 0)
974 present = gpio_cd;
975 else
976 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
977 == 0 ? 1 : 0;
978
979 spin_lock_bh(&host->lock);
980 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
981 dev_dbg(&mmc->class_dev, "card is present\n");
982 else if (!present &&
983 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
984 dev_dbg(&mmc->class_dev, "card is not present\n");
985 spin_unlock_bh(&host->lock);
986
987 return present;
988 }
989
dw_mci_adjust_fifoth(struct dw_mci * host,struct mmc_data * data)990 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
991 {
992 unsigned int blksz = data->blksz;
993 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
994 u32 fifo_width = 1 << host->data_shift;
995 u32 blksz_depth = blksz / fifo_width, fifoth_val;
996 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
997 int idx = ARRAY_SIZE(mszs) - 1;
998
999 /* pio should ship this scenario */
1000 if (!host->use_dma)
1001 return;
1002
1003 tx_wmark = (host->fifo_depth) / 2;
1004 tx_wmark_invers = host->fifo_depth - tx_wmark;
1005
1006 /*
1007 * MSIZE is '1',
1008 * if blksz is not a multiple of the FIFO width
1009 */
1010 if (blksz % fifo_width)
1011 goto done;
1012
1013 do {
1014 if (!((blksz_depth % mszs[idx]) ||
1015 (tx_wmark_invers % mszs[idx]))) {
1016 msize = idx;
1017 rx_wmark = mszs[idx] - 1;
1018 break;
1019 }
1020 } while (--idx > 0);
1021 /*
1022 * If idx is '0', it won't be tried
1023 * Thus, initial values are uesed
1024 */
1025 done:
1026 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1027 mci_writel(host, FIFOTH, fifoth_val);
1028 }
1029
dw_mci_ctrl_thld(struct dw_mci * host,struct mmc_data * data)1030 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1031 {
1032 unsigned int blksz = data->blksz;
1033 u32 blksz_depth, fifo_depth;
1034 u16 thld_size;
1035 u8 enable;
1036
1037 /*
1038 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1039 * in the FIFO region, so we really shouldn't access it).
1040 */
1041 if (host->verid < DW_MMC_240A ||
1042 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1043 return;
1044
1045 /*
1046 * Card write Threshold is introduced since 2.80a
1047 * It's used when HS400 mode is enabled.
1048 */
1049 if (data->flags & MMC_DATA_WRITE &&
1050 host->timing != MMC_TIMING_MMC_HS400)
1051 goto disable;
1052
1053 if (data->flags & MMC_DATA_WRITE)
1054 enable = SDMMC_CARD_WR_THR_EN;
1055 else
1056 enable = SDMMC_CARD_RD_THR_EN;
1057
1058 if (host->timing != MMC_TIMING_MMC_HS200 &&
1059 host->timing != MMC_TIMING_UHS_SDR104 &&
1060 host->timing != MMC_TIMING_MMC_HS400)
1061 goto disable;
1062
1063 blksz_depth = blksz / (1 << host->data_shift);
1064 fifo_depth = host->fifo_depth;
1065
1066 if (blksz_depth > fifo_depth)
1067 goto disable;
1068
1069 /*
1070 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1071 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1072 * Currently just choose blksz.
1073 */
1074 thld_size = blksz;
1075 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1076 return;
1077
1078 disable:
1079 mci_writel(host, CDTHRCTL, 0);
1080 }
1081
dw_mci_submit_data_dma(struct dw_mci * host,struct mmc_data * data)1082 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1083 {
1084 unsigned long irqflags;
1085 int sg_len;
1086 u32 temp;
1087
1088 host->using_dma = 0;
1089
1090 /* If we don't have a channel, we can't do DMA */
1091 if (!host->use_dma)
1092 return -ENODEV;
1093
1094 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1095 if (sg_len < 0) {
1096 host->dma_ops->stop(host);
1097 return sg_len;
1098 }
1099
1100 host->using_dma = 1;
1101
1102 if (host->use_dma == TRANS_MODE_IDMAC)
1103 dev_vdbg(host->dev,
1104 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1105 (unsigned long)host->sg_cpu,
1106 (unsigned long)host->sg_dma,
1107 sg_len);
1108
1109 /*
1110 * Decide the MSIZE and RX/TX Watermark.
1111 * If current block size is same with previous size,
1112 * no need to update fifoth.
1113 */
1114 if (host->prev_blksz != data->blksz)
1115 dw_mci_adjust_fifoth(host, data);
1116
1117 /* Enable the DMA interface */
1118 temp = mci_readl(host, CTRL);
1119 temp |= SDMMC_CTRL_DMA_ENABLE;
1120 mci_writel(host, CTRL, temp);
1121
1122 /* Disable RX/TX IRQs, let DMA handle it */
1123 spin_lock_irqsave(&host->irq_lock, irqflags);
1124 temp = mci_readl(host, INTMASK);
1125 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1126 mci_writel(host, INTMASK, temp);
1127 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1128
1129 if (host->dma_ops->start(host, sg_len)) {
1130 host->dma_ops->stop(host);
1131 /* We can't do DMA, try PIO for this one */
1132 dev_dbg(host->dev,
1133 "%s: fall back to PIO mode for current transfer\n",
1134 __func__);
1135 return -ENODEV;
1136 }
1137
1138 return 0;
1139 }
1140
dw_mci_submit_data(struct dw_mci * host,struct mmc_data * data)1141 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1142 {
1143 unsigned long irqflags;
1144 int flags = SG_MITER_ATOMIC;
1145 u32 temp;
1146
1147 data->error = -EINPROGRESS;
1148
1149 WARN_ON(host->data);
1150 host->sg = NULL;
1151 host->data = data;
1152
1153 if (data->flags & MMC_DATA_READ)
1154 host->dir_status = DW_MCI_RECV_STATUS;
1155 else
1156 host->dir_status = DW_MCI_SEND_STATUS;
1157
1158 dw_mci_ctrl_thld(host, data);
1159
1160 if (dw_mci_submit_data_dma(host, data)) {
1161 if (host->data->flags & MMC_DATA_READ)
1162 flags |= SG_MITER_TO_SG;
1163 else
1164 flags |= SG_MITER_FROM_SG;
1165
1166 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1167 host->sg = data->sg;
1168 host->part_buf_start = 0;
1169 host->part_buf_count = 0;
1170
1171 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1172
1173 spin_lock_irqsave(&host->irq_lock, irqflags);
1174 temp = mci_readl(host, INTMASK);
1175 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1176 mci_writel(host, INTMASK, temp);
1177 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1178
1179 temp = mci_readl(host, CTRL);
1180 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1181 mci_writel(host, CTRL, temp);
1182
1183 /*
1184 * Use the initial fifoth_val for PIO mode. If wm_algined
1185 * is set, we set watermark same as data size.
1186 * If next issued data may be transfered by DMA mode,
1187 * prev_blksz should be invalidated.
1188 */
1189 if (host->wm_aligned)
1190 dw_mci_adjust_fifoth(host, data);
1191 else
1192 mci_writel(host, FIFOTH, host->fifoth_val);
1193 host->prev_blksz = 0;
1194 } else {
1195 /*
1196 * Keep the current block size.
1197 * It will be used to decide whether to update
1198 * fifoth register next time.
1199 */
1200 host->prev_blksz = data->blksz;
1201 }
1202 }
1203
dw_mci_setup_bus(struct dw_mci_slot * slot,bool force_clkinit)1204 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1205 {
1206 struct dw_mci *host = slot->host;
1207 unsigned int clock = slot->clock;
1208 u32 div;
1209 u32 clk_en_a;
1210 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1211
1212 /* We must continue to set bit 28 in CMD until the change is complete */
1213 if (host->state == STATE_WAITING_CMD11_DONE)
1214 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1215
1216 slot->mmc->actual_clock = 0;
1217
1218 if (!clock) {
1219 mci_writel(host, CLKENA, 0);
1220 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1221 } else if (clock != host->current_speed || force_clkinit) {
1222 div = host->bus_hz / clock;
1223 if (host->bus_hz % clock && host->bus_hz > clock)
1224 /*
1225 * move the + 1 after the divide to prevent
1226 * over-clocking the card.
1227 */
1228 div += 1;
1229
1230 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1231
1232 if ((clock != slot->__clk_old &&
1233 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1234 force_clkinit) {
1235 /* Silent the verbose log if calling from PM context */
1236 if (!force_clkinit)
1237 dev_info(&slot->mmc->class_dev,
1238 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1239 slot->id, host->bus_hz, clock,
1240 div ? ((host->bus_hz / div) >> 1) :
1241 host->bus_hz, div);
1242
1243 /*
1244 * If card is polling, display the message only
1245 * one time at boot time.
1246 */
1247 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1248 slot->mmc->f_min == clock)
1249 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1250 }
1251
1252 /* disable clock */
1253 mci_writel(host, CLKENA, 0);
1254 mci_writel(host, CLKSRC, 0);
1255
1256 /* inform CIU */
1257 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1258
1259 /* set clock to desired speed */
1260 mci_writel(host, CLKDIV, div);
1261
1262 /* inform CIU */
1263 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1264
1265 /* enable clock; only low power if no SDIO */
1266 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1267 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1268 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1269 mci_writel(host, CLKENA, clk_en_a);
1270
1271 /* inform CIU */
1272 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1273
1274 /* keep the last clock value that was requested from core */
1275 slot->__clk_old = clock;
1276 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) :
1277 host->bus_hz;
1278 }
1279
1280 host->current_speed = clock;
1281
1282 /* Set the current slot bus width */
1283 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1284 }
1285
__dw_mci_start_request(struct dw_mci * host,struct dw_mci_slot * slot,struct mmc_command * cmd)1286 static void __dw_mci_start_request(struct dw_mci *host,
1287 struct dw_mci_slot *slot,
1288 struct mmc_command *cmd)
1289 {
1290 struct mmc_request *mrq;
1291 struct mmc_data *data;
1292 u32 cmdflags;
1293
1294 mrq = slot->mrq;
1295
1296 host->mrq = mrq;
1297
1298 host->pending_events = 0;
1299 host->completed_events = 0;
1300 host->cmd_status = 0;
1301 host->data_status = 0;
1302 host->dir_status = 0;
1303
1304 data = cmd->data;
1305 if (data) {
1306 mci_writel(host, TMOUT, 0xFFFFFFFF);
1307 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1308 mci_writel(host, BLKSIZ, data->blksz);
1309 }
1310
1311 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1312
1313 /* this is the first command, send the initialization clock */
1314 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1315 cmdflags |= SDMMC_CMD_INIT;
1316
1317 if (data) {
1318 dw_mci_submit_data(host, data);
1319 wmb(); /* drain writebuffer */
1320 }
1321
1322 dw_mci_start_command(host, cmd, cmdflags);
1323
1324 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1325 unsigned long irqflags;
1326
1327 /*
1328 * Databook says to fail after 2ms w/ no response, but evidence
1329 * shows that sometimes the cmd11 interrupt takes over 130ms.
1330 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1331 * is just about to roll over.
1332 *
1333 * We do this whole thing under spinlock and only if the
1334 * command hasn't already completed (indicating the the irq
1335 * already ran so we don't want the timeout).
1336 */
1337 spin_lock_irqsave(&host->irq_lock, irqflags);
1338 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1339 mod_timer(&host->cmd11_timer,
1340 jiffies + msecs_to_jiffies(500) + 1);
1341 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1342 }
1343
1344 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1345 }
1346
dw_mci_start_request(struct dw_mci * host,struct dw_mci_slot * slot)1347 static void dw_mci_start_request(struct dw_mci *host,
1348 struct dw_mci_slot *slot)
1349 {
1350 struct mmc_request *mrq = slot->mrq;
1351 struct mmc_command *cmd;
1352
1353 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1354 __dw_mci_start_request(host, slot, cmd);
1355 }
1356
1357 /* must be called with host->lock held */
dw_mci_queue_request(struct dw_mci * host,struct dw_mci_slot * slot,struct mmc_request * mrq)1358 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1359 struct mmc_request *mrq)
1360 {
1361 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1362 host->state);
1363
1364 slot->mrq = mrq;
1365
1366 if (host->state == STATE_WAITING_CMD11_DONE) {
1367 dev_warn(&slot->mmc->class_dev,
1368 "Voltage change didn't complete\n");
1369 /*
1370 * this case isn't expected to happen, so we can
1371 * either crash here or just try to continue on
1372 * in the closest possible state
1373 */
1374 host->state = STATE_IDLE;
1375 }
1376
1377 if (host->state == STATE_IDLE) {
1378 host->state = STATE_SENDING_CMD;
1379 dw_mci_start_request(host, slot);
1380 } else {
1381 list_add_tail(&slot->queue_node, &host->queue);
1382 }
1383 }
1384
dw_mci_request(struct mmc_host * mmc,struct mmc_request * mrq)1385 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1386 {
1387 struct dw_mci_slot *slot = mmc_priv(mmc);
1388 struct dw_mci *host = slot->host;
1389
1390 WARN_ON(slot->mrq);
1391
1392 /*
1393 * The check for card presence and queueing of the request must be
1394 * atomic, otherwise the card could be removed in between and the
1395 * request wouldn't fail until another card was inserted.
1396 */
1397
1398 if (!dw_mci_get_cd(mmc)) {
1399 mrq->cmd->error = -ENOMEDIUM;
1400 mmc_request_done(mmc, mrq);
1401 return;
1402 }
1403
1404 spin_lock_bh(&host->lock);
1405
1406 dw_mci_queue_request(host, slot, mrq);
1407
1408 spin_unlock_bh(&host->lock);
1409 }
1410
dw_mci_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1411 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1412 {
1413 struct dw_mci_slot *slot = mmc_priv(mmc);
1414 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1415 u32 regs;
1416 int ret;
1417
1418 switch (ios->bus_width) {
1419 case MMC_BUS_WIDTH_4:
1420 slot->ctype = SDMMC_CTYPE_4BIT;
1421 break;
1422 case MMC_BUS_WIDTH_8:
1423 slot->ctype = SDMMC_CTYPE_8BIT;
1424 break;
1425 default:
1426 /* set default 1 bit mode */
1427 slot->ctype = SDMMC_CTYPE_1BIT;
1428 }
1429
1430 regs = mci_readl(slot->host, UHS_REG);
1431
1432 /* DDR mode set */
1433 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1434 ios->timing == MMC_TIMING_UHS_DDR50 ||
1435 ios->timing == MMC_TIMING_MMC_HS400)
1436 regs |= ((0x1 << slot->id) << 16);
1437 else
1438 regs &= ~((0x1 << slot->id) << 16);
1439
1440 mci_writel(slot->host, UHS_REG, regs);
1441 slot->host->timing = ios->timing;
1442
1443 /*
1444 * Use mirror of ios->clock to prevent race with mmc
1445 * core ios update when finding the minimum.
1446 */
1447 slot->clock = ios->clock;
1448
1449 if (drv_data && drv_data->set_ios)
1450 drv_data->set_ios(slot->host, ios);
1451
1452 switch (ios->power_mode) {
1453 case MMC_POWER_UP:
1454 if (!IS_ERR(mmc->supply.vmmc)) {
1455 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1456 ios->vdd);
1457 if (ret) {
1458 dev_err(slot->host->dev,
1459 "failed to enable vmmc regulator\n");
1460 /*return, if failed turn on vmmc*/
1461 return;
1462 }
1463 }
1464 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1465 regs = mci_readl(slot->host, PWREN);
1466 regs |= (1 << slot->id);
1467 mci_writel(slot->host, PWREN, regs);
1468 break;
1469 case MMC_POWER_ON:
1470 if (!slot->host->vqmmc_enabled) {
1471 if (!IS_ERR(mmc->supply.vqmmc)) {
1472 ret = regulator_enable(mmc->supply.vqmmc);
1473 if (ret < 0)
1474 dev_err(slot->host->dev,
1475 "failed to enable vqmmc\n");
1476 else
1477 slot->host->vqmmc_enabled = true;
1478
1479 } else {
1480 /* Keep track so we don't reset again */
1481 slot->host->vqmmc_enabled = true;
1482 }
1483
1484 /* Reset our state machine after powering on */
1485 dw_mci_ctrl_reset(slot->host,
1486 SDMMC_CTRL_ALL_RESET_FLAGS);
1487 }
1488
1489 /* Adjust clock / bus width after power is up */
1490 dw_mci_setup_bus(slot, false);
1491
1492 break;
1493 case MMC_POWER_OFF:
1494 /* Turn clock off before power goes down */
1495 dw_mci_setup_bus(slot, false);
1496
1497 if (!IS_ERR(mmc->supply.vmmc))
1498 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1499
1500 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1501 regulator_disable(mmc->supply.vqmmc);
1502 slot->host->vqmmc_enabled = false;
1503
1504 regs = mci_readl(slot->host, PWREN);
1505 regs &= ~(1 << slot->id);
1506 mci_writel(slot->host, PWREN, regs);
1507 break;
1508 default:
1509 break;
1510 }
1511
1512 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1513 slot->host->state = STATE_IDLE;
1514 }
1515
dw_mci_card_busy(struct mmc_host * mmc)1516 static int dw_mci_card_busy(struct mmc_host *mmc)
1517 {
1518 struct dw_mci_slot *slot = mmc_priv(mmc);
1519 u32 status;
1520
1521 /*
1522 * Check the busy bit which is low when DAT[3:0]
1523 * (the data lines) are 0000
1524 */
1525 status = mci_readl(slot->host, STATUS);
1526
1527 return !!(status & SDMMC_STATUS_BUSY);
1528 }
1529
dw_mci_switch_voltage(struct mmc_host * mmc,struct mmc_ios * ios)1530 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1531 {
1532 struct dw_mci_slot *slot = mmc_priv(mmc);
1533 struct dw_mci *host = slot->host;
1534 const struct dw_mci_drv_data *drv_data = host->drv_data;
1535 u32 uhs;
1536 u32 v18 = SDMMC_UHS_18V << slot->id;
1537 int ret;
1538
1539 if (drv_data && drv_data->switch_voltage)
1540 return drv_data->switch_voltage(mmc, ios);
1541
1542 /*
1543 * Program the voltage. Note that some instances of dw_mmc may use
1544 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1545 * does no harm but you need to set the regulator directly. Try both.
1546 */
1547 uhs = mci_readl(host, UHS_REG);
1548 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1549 uhs &= ~v18;
1550 else
1551 uhs |= v18;
1552
1553 if (!IS_ERR(mmc->supply.vqmmc)) {
1554 ret = mmc_regulator_set_vqmmc(mmc, ios);
1555 if (ret < 0) {
1556 dev_dbg(&mmc->class_dev,
1557 "Regulator set error %d - %s V\n",
1558 ret, uhs & v18 ? "1.8" : "3.3");
1559 return ret;
1560 }
1561 }
1562 mci_writel(host, UHS_REG, uhs);
1563
1564 return 0;
1565 }
1566
dw_mci_get_ro(struct mmc_host * mmc)1567 static int dw_mci_get_ro(struct mmc_host *mmc)
1568 {
1569 int read_only;
1570 struct dw_mci_slot *slot = mmc_priv(mmc);
1571 int gpio_ro = mmc_gpio_get_ro(mmc);
1572
1573 /* Use platform get_ro function, else try on board write protect */
1574 if (gpio_ro >= 0)
1575 read_only = gpio_ro;
1576 else
1577 read_only =
1578 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1579
1580 dev_dbg(&mmc->class_dev, "card is %s\n",
1581 read_only ? "read-only" : "read-write");
1582
1583 return read_only;
1584 }
1585
dw_mci_hw_reset(struct mmc_host * mmc)1586 static void dw_mci_hw_reset(struct mmc_host *mmc)
1587 {
1588 struct dw_mci_slot *slot = mmc_priv(mmc);
1589 struct dw_mci *host = slot->host;
1590 int reset;
1591
1592 if (host->use_dma == TRANS_MODE_IDMAC)
1593 dw_mci_idmac_reset(host);
1594
1595 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1596 SDMMC_CTRL_FIFO_RESET))
1597 return;
1598
1599 /*
1600 * According to eMMC spec, card reset procedure:
1601 * tRstW >= 1us: RST_n pulse width
1602 * tRSCA >= 200us: RST_n to Command time
1603 * tRSTH >= 1us: RST_n high period
1604 */
1605 reset = mci_readl(host, RST_N);
1606 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1607 mci_writel(host, RST_N, reset);
1608 usleep_range(1, 2);
1609 reset |= SDMMC_RST_HWACTIVE << slot->id;
1610 mci_writel(host, RST_N, reset);
1611 usleep_range(200, 300);
1612 }
1613
dw_mci_init_card(struct mmc_host * mmc,struct mmc_card * card)1614 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1615 {
1616 struct dw_mci_slot *slot = mmc_priv(mmc);
1617 struct dw_mci *host = slot->host;
1618
1619 /*
1620 * Low power mode will stop the card clock when idle. According to the
1621 * description of the CLKENA register we should disable low power mode
1622 * for SDIO cards if we need SDIO interrupts to work.
1623 */
1624 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1625 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1626 u32 clk_en_a_old;
1627 u32 clk_en_a;
1628
1629 clk_en_a_old = mci_readl(host, CLKENA);
1630
1631 if (card->type == MMC_TYPE_SDIO ||
1632 card->type == MMC_TYPE_SD_COMBO) {
1633 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1634 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1635 } else {
1636 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1637 clk_en_a = clk_en_a_old | clken_low_pwr;
1638 }
1639
1640 if (clk_en_a != clk_en_a_old) {
1641 mci_writel(host, CLKENA, clk_en_a);
1642 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1643 SDMMC_CMD_PRV_DAT_WAIT, 0);
1644 }
1645 }
1646 }
1647
__dw_mci_enable_sdio_irq(struct dw_mci_slot * slot,int enb)1648 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1649 {
1650 struct dw_mci *host = slot->host;
1651 unsigned long irqflags;
1652 u32 int_mask;
1653
1654 spin_lock_irqsave(&host->irq_lock, irqflags);
1655
1656 /* Enable/disable Slot Specific SDIO interrupt */
1657 int_mask = mci_readl(host, INTMASK);
1658 if (enb)
1659 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1660 else
1661 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1662 mci_writel(host, INTMASK, int_mask);
1663
1664 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1665 }
1666
dw_mci_enable_sdio_irq(struct mmc_host * mmc,int enb)1667 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1668 {
1669 struct dw_mci_slot *slot = mmc_priv(mmc);
1670 struct dw_mci *host = slot->host;
1671
1672 __dw_mci_enable_sdio_irq(slot, enb);
1673
1674 /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1675 if (enb)
1676 pm_runtime_get_noresume(host->dev);
1677 else
1678 pm_runtime_put_noidle(host->dev);
1679 }
1680
dw_mci_ack_sdio_irq(struct mmc_host * mmc)1681 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1682 {
1683 struct dw_mci_slot *slot = mmc_priv(mmc);
1684
1685 __dw_mci_enable_sdio_irq(slot, 1);
1686 }
1687
dw_mci_execute_tuning(struct mmc_host * mmc,u32 opcode)1688 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1689 {
1690 struct dw_mci_slot *slot = mmc_priv(mmc);
1691 struct dw_mci *host = slot->host;
1692 const struct dw_mci_drv_data *drv_data = host->drv_data;
1693 int err = -EINVAL;
1694
1695 if (drv_data && drv_data->execute_tuning)
1696 err = drv_data->execute_tuning(slot, opcode);
1697 return err;
1698 }
1699
dw_mci_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)1700 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1701 struct mmc_ios *ios)
1702 {
1703 struct dw_mci_slot *slot = mmc_priv(mmc);
1704 struct dw_mci *host = slot->host;
1705 const struct dw_mci_drv_data *drv_data = host->drv_data;
1706
1707 if (drv_data && drv_data->prepare_hs400_tuning)
1708 return drv_data->prepare_hs400_tuning(host, ios);
1709
1710 return 0;
1711 }
1712
dw_mci_reset(struct dw_mci * host)1713 static bool dw_mci_reset(struct dw_mci *host)
1714 {
1715 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1716 bool ret = false;
1717 u32 status = 0;
1718
1719 /*
1720 * Resetting generates a block interrupt, hence setting
1721 * the scatter-gather pointer to NULL.
1722 */
1723 if (host->sg) {
1724 sg_miter_stop(&host->sg_miter);
1725 host->sg = NULL;
1726 }
1727
1728 if (host->use_dma)
1729 flags |= SDMMC_CTRL_DMA_RESET;
1730
1731 if (dw_mci_ctrl_reset(host, flags)) {
1732 /*
1733 * In all cases we clear the RAWINTS
1734 * register to clear any interrupts.
1735 */
1736 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1737
1738 if (!host->use_dma) {
1739 ret = true;
1740 goto ciu_out;
1741 }
1742
1743 /* Wait for dma_req to be cleared */
1744 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1745 status,
1746 !(status & SDMMC_STATUS_DMA_REQ),
1747 1, 500 * USEC_PER_MSEC)) {
1748 dev_err(host->dev,
1749 "%s: Timeout waiting for dma_req to be cleared\n",
1750 __func__);
1751 goto ciu_out;
1752 }
1753
1754 /* when using DMA next we reset the fifo again */
1755 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1756 goto ciu_out;
1757 } else {
1758 /* if the controller reset bit did clear, then set clock regs */
1759 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1760 dev_err(host->dev,
1761 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1762 __func__);
1763 goto ciu_out;
1764 }
1765 }
1766
1767 if (host->use_dma == TRANS_MODE_IDMAC)
1768 /* It is also required that we reinit idmac */
1769 dw_mci_idmac_init(host);
1770
1771 ret = true;
1772
1773 ciu_out:
1774 /* After a CTRL reset we need to have CIU set clock registers */
1775 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1776
1777 return ret;
1778 }
1779
1780 static const struct mmc_host_ops dw_mci_ops = {
1781 .request = dw_mci_request,
1782 .pre_req = dw_mci_pre_req,
1783 .post_req = dw_mci_post_req,
1784 .set_ios = dw_mci_set_ios,
1785 .get_ro = dw_mci_get_ro,
1786 .get_cd = dw_mci_get_cd,
1787 .hw_reset = dw_mci_hw_reset,
1788 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1789 .ack_sdio_irq = dw_mci_ack_sdio_irq,
1790 .execute_tuning = dw_mci_execute_tuning,
1791 .card_busy = dw_mci_card_busy,
1792 .start_signal_voltage_switch = dw_mci_switch_voltage,
1793 .init_card = dw_mci_init_card,
1794 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1795 };
1796
1797 #ifdef CONFIG_FAULT_INJECTION
dw_mci_fault_timer(struct hrtimer * t)1798 static enum hrtimer_restart dw_mci_fault_timer(struct hrtimer *t)
1799 {
1800 struct dw_mci *host = container_of(t, struct dw_mci, fault_timer);
1801 unsigned long flags;
1802
1803 spin_lock_irqsave(&host->irq_lock, flags);
1804
1805 /*
1806 * Only inject an error if we haven't already got an error or data over
1807 * interrupt.
1808 */
1809 if (!host->data_status) {
1810 host->data_status = SDMMC_INT_DCRC;
1811 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1812 tasklet_schedule(&host->tasklet);
1813 }
1814
1815 spin_unlock_irqrestore(&host->irq_lock, flags);
1816
1817 return HRTIMER_NORESTART;
1818 }
1819
dw_mci_start_fault_timer(struct dw_mci * host)1820 static void dw_mci_start_fault_timer(struct dw_mci *host)
1821 {
1822 struct mmc_data *data = host->data;
1823
1824 if (!data || data->blocks <= 1)
1825 return;
1826
1827 if (!should_fail(&host->fail_data_crc, 1))
1828 return;
1829
1830 /*
1831 * Try to inject the error at random points during the data transfer.
1832 */
1833 hrtimer_start(&host->fault_timer,
1834 ms_to_ktime(prandom_u32() % 25),
1835 HRTIMER_MODE_REL);
1836 }
1837
dw_mci_stop_fault_timer(struct dw_mci * host)1838 static void dw_mci_stop_fault_timer(struct dw_mci *host)
1839 {
1840 hrtimer_cancel(&host->fault_timer);
1841 }
1842
dw_mci_init_fault(struct dw_mci * host)1843 static void dw_mci_init_fault(struct dw_mci *host)
1844 {
1845 host->fail_data_crc = (struct fault_attr) FAULT_ATTR_INITIALIZER;
1846
1847 hrtimer_init(&host->fault_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1848 host->fault_timer.function = dw_mci_fault_timer;
1849 }
1850 #else
dw_mci_init_fault(struct dw_mci * host)1851 static void dw_mci_init_fault(struct dw_mci *host)
1852 {
1853 }
1854
dw_mci_start_fault_timer(struct dw_mci * host)1855 static void dw_mci_start_fault_timer(struct dw_mci *host)
1856 {
1857 }
1858
dw_mci_stop_fault_timer(struct dw_mci * host)1859 static void dw_mci_stop_fault_timer(struct dw_mci *host)
1860 {
1861 }
1862 #endif
1863
dw_mci_request_end(struct dw_mci * host,struct mmc_request * mrq)1864 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1865 __releases(&host->lock)
1866 __acquires(&host->lock)
1867 {
1868 struct dw_mci_slot *slot;
1869 struct mmc_host *prev_mmc = host->slot->mmc;
1870
1871 WARN_ON(host->cmd || host->data);
1872
1873 host->slot->mrq = NULL;
1874 host->mrq = NULL;
1875 if (!list_empty(&host->queue)) {
1876 slot = list_entry(host->queue.next,
1877 struct dw_mci_slot, queue_node);
1878 list_del(&slot->queue_node);
1879 dev_vdbg(host->dev, "list not empty: %s is next\n",
1880 mmc_hostname(slot->mmc));
1881 host->state = STATE_SENDING_CMD;
1882 dw_mci_start_request(host, slot);
1883 } else {
1884 dev_vdbg(host->dev, "list empty\n");
1885
1886 if (host->state == STATE_SENDING_CMD11)
1887 host->state = STATE_WAITING_CMD11_DONE;
1888 else
1889 host->state = STATE_IDLE;
1890 }
1891
1892 spin_unlock(&host->lock);
1893 mmc_request_done(prev_mmc, mrq);
1894 spin_lock(&host->lock);
1895 }
1896
dw_mci_command_complete(struct dw_mci * host,struct mmc_command * cmd)1897 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1898 {
1899 u32 status = host->cmd_status;
1900
1901 host->cmd_status = 0;
1902
1903 /* Read the response from the card (up to 16 bytes) */
1904 if (cmd->flags & MMC_RSP_PRESENT) {
1905 if (cmd->flags & MMC_RSP_136) {
1906 cmd->resp[3] = mci_readl(host, RESP0);
1907 cmd->resp[2] = mci_readl(host, RESP1);
1908 cmd->resp[1] = mci_readl(host, RESP2);
1909 cmd->resp[0] = mci_readl(host, RESP3);
1910 } else {
1911 cmd->resp[0] = mci_readl(host, RESP0);
1912 cmd->resp[1] = 0;
1913 cmd->resp[2] = 0;
1914 cmd->resp[3] = 0;
1915 }
1916 }
1917
1918 if (status & SDMMC_INT_RTO)
1919 cmd->error = -ETIMEDOUT;
1920 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1921 cmd->error = -EILSEQ;
1922 else if (status & SDMMC_INT_RESP_ERR)
1923 cmd->error = -EIO;
1924 else
1925 cmd->error = 0;
1926
1927 return cmd->error;
1928 }
1929
dw_mci_data_complete(struct dw_mci * host,struct mmc_data * data)1930 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1931 {
1932 u32 status = host->data_status;
1933
1934 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1935 if (status & SDMMC_INT_DRTO) {
1936 data->error = -ETIMEDOUT;
1937 } else if (status & SDMMC_INT_DCRC) {
1938 data->error = -EILSEQ;
1939 } else if (status & SDMMC_INT_EBE) {
1940 if (host->dir_status ==
1941 DW_MCI_SEND_STATUS) {
1942 /*
1943 * No data CRC status was returned.
1944 * The number of bytes transferred
1945 * will be exaggerated in PIO mode.
1946 */
1947 data->bytes_xfered = 0;
1948 data->error = -ETIMEDOUT;
1949 } else if (host->dir_status ==
1950 DW_MCI_RECV_STATUS) {
1951 data->error = -EILSEQ;
1952 }
1953 } else {
1954 /* SDMMC_INT_SBE is included */
1955 data->error = -EILSEQ;
1956 }
1957
1958 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1959
1960 /*
1961 * After an error, there may be data lingering
1962 * in the FIFO
1963 */
1964 dw_mci_reset(host);
1965 } else {
1966 data->bytes_xfered = data->blocks * data->blksz;
1967 data->error = 0;
1968 }
1969
1970 return data->error;
1971 }
1972
dw_mci_set_drto(struct dw_mci * host)1973 static void dw_mci_set_drto(struct dw_mci *host)
1974 {
1975 unsigned int drto_clks;
1976 unsigned int drto_div;
1977 unsigned int drto_ms;
1978 unsigned long irqflags;
1979
1980 drto_clks = mci_readl(host, TMOUT) >> 8;
1981 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
1982 if (drto_div == 0)
1983 drto_div = 1;
1984
1985 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
1986 host->bus_hz);
1987
1988 /* add a bit spare time */
1989 drto_ms += 10;
1990
1991 spin_lock_irqsave(&host->irq_lock, irqflags);
1992 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1993 mod_timer(&host->dto_timer,
1994 jiffies + msecs_to_jiffies(drto_ms));
1995 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1996 }
1997
dw_mci_clear_pending_cmd_complete(struct dw_mci * host)1998 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
1999 {
2000 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
2001 return false;
2002
2003 /*
2004 * Really be certain that the timer has stopped. This is a bit of
2005 * paranoia and could only really happen if we had really bad
2006 * interrupt latency and the interrupt routine and timeout were
2007 * running concurrently so that the del_timer() in the interrupt
2008 * handler couldn't run.
2009 */
2010 WARN_ON(del_timer_sync(&host->cto_timer));
2011 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2012
2013 return true;
2014 }
2015
dw_mci_clear_pending_data_complete(struct dw_mci * host)2016 static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
2017 {
2018 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
2019 return false;
2020
2021 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
2022 WARN_ON(del_timer_sync(&host->dto_timer));
2023 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2024
2025 return true;
2026 }
2027
dw_mci_tasklet_func(struct tasklet_struct * t)2028 static void dw_mci_tasklet_func(struct tasklet_struct *t)
2029 {
2030 struct dw_mci *host = from_tasklet(host, t, tasklet);
2031 struct mmc_data *data;
2032 struct mmc_command *cmd;
2033 struct mmc_request *mrq;
2034 enum dw_mci_state state;
2035 enum dw_mci_state prev_state;
2036 unsigned int err;
2037
2038 spin_lock(&host->lock);
2039
2040 state = host->state;
2041 data = host->data;
2042 mrq = host->mrq;
2043
2044 do {
2045 prev_state = state;
2046
2047 switch (state) {
2048 case STATE_IDLE:
2049 case STATE_WAITING_CMD11_DONE:
2050 break;
2051
2052 case STATE_SENDING_CMD11:
2053 case STATE_SENDING_CMD:
2054 if (!dw_mci_clear_pending_cmd_complete(host))
2055 break;
2056
2057 cmd = host->cmd;
2058 host->cmd = NULL;
2059 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2060 err = dw_mci_command_complete(host, cmd);
2061 if (cmd == mrq->sbc && !err) {
2062 __dw_mci_start_request(host, host->slot,
2063 mrq->cmd);
2064 goto unlock;
2065 }
2066
2067 if (cmd->data && err) {
2068 /*
2069 * During UHS tuning sequence, sending the stop
2070 * command after the response CRC error would
2071 * throw the system into a confused state
2072 * causing all future tuning phases to report
2073 * failure.
2074 *
2075 * In such case controller will move into a data
2076 * transfer state after a response error or
2077 * response CRC error. Let's let that finish
2078 * before trying to send a stop, so we'll go to
2079 * STATE_SENDING_DATA.
2080 *
2081 * Although letting the data transfer take place
2082 * will waste a bit of time (we already know
2083 * the command was bad), it can't cause any
2084 * errors since it's possible it would have
2085 * taken place anyway if this tasklet got
2086 * delayed. Allowing the transfer to take place
2087 * avoids races and keeps things simple.
2088 */
2089 if (err != -ETIMEDOUT &&
2090 host->dir_status == DW_MCI_RECV_STATUS) {
2091 state = STATE_SENDING_DATA;
2092 continue;
2093 }
2094
2095 send_stop_abort(host, data);
2096 dw_mci_stop_dma(host);
2097 state = STATE_SENDING_STOP;
2098 break;
2099 }
2100
2101 if (!cmd->data || err) {
2102 dw_mci_request_end(host, mrq);
2103 goto unlock;
2104 }
2105
2106 prev_state = state = STATE_SENDING_DATA;
2107 fallthrough;
2108
2109 case STATE_SENDING_DATA:
2110 /*
2111 * We could get a data error and never a transfer
2112 * complete so we'd better check for it here.
2113 *
2114 * Note that we don't really care if we also got a
2115 * transfer complete; stopping the DMA and sending an
2116 * abort won't hurt.
2117 */
2118 if (test_and_clear_bit(EVENT_DATA_ERROR,
2119 &host->pending_events)) {
2120 if (!(host->data_status & (SDMMC_INT_DRTO |
2121 SDMMC_INT_EBE)))
2122 send_stop_abort(host, data);
2123 dw_mci_stop_dma(host);
2124 state = STATE_DATA_ERROR;
2125 break;
2126 }
2127
2128 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2129 &host->pending_events)) {
2130 /*
2131 * If all data-related interrupts don't come
2132 * within the given time in reading data state.
2133 */
2134 if (host->dir_status == DW_MCI_RECV_STATUS)
2135 dw_mci_set_drto(host);
2136 break;
2137 }
2138
2139 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2140
2141 /*
2142 * Handle an EVENT_DATA_ERROR that might have shown up
2143 * before the transfer completed. This might not have
2144 * been caught by the check above because the interrupt
2145 * could have gone off between the previous check and
2146 * the check for transfer complete.
2147 *
2148 * Technically this ought not be needed assuming we
2149 * get a DATA_COMPLETE eventually (we'll notice the
2150 * error and end the request), but it shouldn't hurt.
2151 *
2152 * This has the advantage of sending the stop command.
2153 */
2154 if (test_and_clear_bit(EVENT_DATA_ERROR,
2155 &host->pending_events)) {
2156 if (!(host->data_status & (SDMMC_INT_DRTO |
2157 SDMMC_INT_EBE)))
2158 send_stop_abort(host, data);
2159 dw_mci_stop_dma(host);
2160 state = STATE_DATA_ERROR;
2161 break;
2162 }
2163 prev_state = state = STATE_DATA_BUSY;
2164
2165 fallthrough;
2166
2167 case STATE_DATA_BUSY:
2168 if (!dw_mci_clear_pending_data_complete(host)) {
2169 /*
2170 * If data error interrupt comes but data over
2171 * interrupt doesn't come within the given time.
2172 * in reading data state.
2173 */
2174 if (host->dir_status == DW_MCI_RECV_STATUS)
2175 dw_mci_set_drto(host);
2176 break;
2177 }
2178
2179 dw_mci_stop_fault_timer(host);
2180 host->data = NULL;
2181 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2182 err = dw_mci_data_complete(host, data);
2183
2184 if (!err) {
2185 if (!data->stop || mrq->sbc) {
2186 if (mrq->sbc && data->stop)
2187 data->stop->error = 0;
2188 dw_mci_request_end(host, mrq);
2189 goto unlock;
2190 }
2191
2192 /* stop command for open-ended transfer*/
2193 if (data->stop)
2194 send_stop_abort(host, data);
2195 } else {
2196 /*
2197 * If we don't have a command complete now we'll
2198 * never get one since we just reset everything;
2199 * better end the request.
2200 *
2201 * If we do have a command complete we'll fall
2202 * through to the SENDING_STOP command and
2203 * everything will be peachy keen.
2204 */
2205 if (!test_bit(EVENT_CMD_COMPLETE,
2206 &host->pending_events)) {
2207 host->cmd = NULL;
2208 dw_mci_request_end(host, mrq);
2209 goto unlock;
2210 }
2211 }
2212
2213 /*
2214 * If err has non-zero,
2215 * stop-abort command has been already issued.
2216 */
2217 prev_state = state = STATE_SENDING_STOP;
2218
2219 fallthrough;
2220
2221 case STATE_SENDING_STOP:
2222 if (!dw_mci_clear_pending_cmd_complete(host))
2223 break;
2224
2225 /* CMD error in data command */
2226 if (mrq->cmd->error && mrq->data)
2227 dw_mci_reset(host);
2228
2229 dw_mci_stop_fault_timer(host);
2230 host->cmd = NULL;
2231 host->data = NULL;
2232
2233 if (!mrq->sbc && mrq->stop)
2234 dw_mci_command_complete(host, mrq->stop);
2235 else
2236 host->cmd_status = 0;
2237
2238 dw_mci_request_end(host, mrq);
2239 goto unlock;
2240
2241 case STATE_DATA_ERROR:
2242 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2243 &host->pending_events))
2244 break;
2245
2246 state = STATE_DATA_BUSY;
2247 break;
2248 }
2249 } while (state != prev_state);
2250
2251 host->state = state;
2252 unlock:
2253 spin_unlock(&host->lock);
2254
2255 }
2256
2257 /* push final bytes to part_buf, only use during push */
dw_mci_set_part_bytes(struct dw_mci * host,void * buf,int cnt)2258 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2259 {
2260 memcpy((void *)&host->part_buf, buf, cnt);
2261 host->part_buf_count = cnt;
2262 }
2263
2264 /* append bytes to part_buf, only use during push */
dw_mci_push_part_bytes(struct dw_mci * host,void * buf,int cnt)2265 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2266 {
2267 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2268 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2269 host->part_buf_count += cnt;
2270 return cnt;
2271 }
2272
2273 /* pull first bytes from part_buf, only use during pull */
dw_mci_pull_part_bytes(struct dw_mci * host,void * buf,int cnt)2274 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2275 {
2276 cnt = min_t(int, cnt, host->part_buf_count);
2277 if (cnt) {
2278 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2279 cnt);
2280 host->part_buf_count -= cnt;
2281 host->part_buf_start += cnt;
2282 }
2283 return cnt;
2284 }
2285
2286 /* pull final bytes from the part_buf, assuming it's just been filled */
dw_mci_pull_final_bytes(struct dw_mci * host,void * buf,int cnt)2287 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2288 {
2289 memcpy(buf, &host->part_buf, cnt);
2290 host->part_buf_start = cnt;
2291 host->part_buf_count = (1 << host->data_shift) - cnt;
2292 }
2293
dw_mci_push_data16(struct dw_mci * host,void * buf,int cnt)2294 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2295 {
2296 struct mmc_data *data = host->data;
2297 int init_cnt = cnt;
2298
2299 /* try and push anything in the part_buf */
2300 if (unlikely(host->part_buf_count)) {
2301 int len = dw_mci_push_part_bytes(host, buf, cnt);
2302
2303 buf += len;
2304 cnt -= len;
2305 if (host->part_buf_count == 2) {
2306 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2307 host->part_buf_count = 0;
2308 }
2309 }
2310 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2311 if (unlikely((unsigned long)buf & 0x1)) {
2312 while (cnt >= 2) {
2313 u16 aligned_buf[64];
2314 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2315 int items = len >> 1;
2316 int i;
2317 /* memcpy from input buffer into aligned buffer */
2318 memcpy(aligned_buf, buf, len);
2319 buf += len;
2320 cnt -= len;
2321 /* push data from aligned buffer into fifo */
2322 for (i = 0; i < items; ++i)
2323 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2324 }
2325 } else
2326 #endif
2327 {
2328 u16 *pdata = buf;
2329
2330 for (; cnt >= 2; cnt -= 2)
2331 mci_fifo_writew(host->fifo_reg, *pdata++);
2332 buf = pdata;
2333 }
2334 /* put anything remaining in the part_buf */
2335 if (cnt) {
2336 dw_mci_set_part_bytes(host, buf, cnt);
2337 /* Push data if we have reached the expected data length */
2338 if ((data->bytes_xfered + init_cnt) ==
2339 (data->blksz * data->blocks))
2340 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2341 }
2342 }
2343
dw_mci_pull_data16(struct dw_mci * host,void * buf,int cnt)2344 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2345 {
2346 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2347 if (unlikely((unsigned long)buf & 0x1)) {
2348 while (cnt >= 2) {
2349 /* pull data from fifo into aligned buffer */
2350 u16 aligned_buf[64];
2351 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2352 int items = len >> 1;
2353 int i;
2354
2355 for (i = 0; i < items; ++i)
2356 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2357 /* memcpy from aligned buffer into output buffer */
2358 memcpy(buf, aligned_buf, len);
2359 buf += len;
2360 cnt -= len;
2361 }
2362 } else
2363 #endif
2364 {
2365 u16 *pdata = buf;
2366
2367 for (; cnt >= 2; cnt -= 2)
2368 *pdata++ = mci_fifo_readw(host->fifo_reg);
2369 buf = pdata;
2370 }
2371 if (cnt) {
2372 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2373 dw_mci_pull_final_bytes(host, buf, cnt);
2374 }
2375 }
2376
dw_mci_push_data32(struct dw_mci * host,void * buf,int cnt)2377 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2378 {
2379 struct mmc_data *data = host->data;
2380 int init_cnt = cnt;
2381
2382 /* try and push anything in the part_buf */
2383 if (unlikely(host->part_buf_count)) {
2384 int len = dw_mci_push_part_bytes(host, buf, cnt);
2385
2386 buf += len;
2387 cnt -= len;
2388 if (host->part_buf_count == 4) {
2389 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2390 host->part_buf_count = 0;
2391 }
2392 }
2393 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2394 if (unlikely((unsigned long)buf & 0x3)) {
2395 while (cnt >= 4) {
2396 u32 aligned_buf[32];
2397 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2398 int items = len >> 2;
2399 int i;
2400 /* memcpy from input buffer into aligned buffer */
2401 memcpy(aligned_buf, buf, len);
2402 buf += len;
2403 cnt -= len;
2404 /* push data from aligned buffer into fifo */
2405 for (i = 0; i < items; ++i)
2406 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2407 }
2408 } else
2409 #endif
2410 {
2411 u32 *pdata = buf;
2412
2413 for (; cnt >= 4; cnt -= 4)
2414 mci_fifo_writel(host->fifo_reg, *pdata++);
2415 buf = pdata;
2416 }
2417 /* put anything remaining in the part_buf */
2418 if (cnt) {
2419 dw_mci_set_part_bytes(host, buf, cnt);
2420 /* Push data if we have reached the expected data length */
2421 if ((data->bytes_xfered + init_cnt) ==
2422 (data->blksz * data->blocks))
2423 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2424 }
2425 }
2426
dw_mci_pull_data32(struct dw_mci * host,void * buf,int cnt)2427 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2428 {
2429 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2430 if (unlikely((unsigned long)buf & 0x3)) {
2431 while (cnt >= 4) {
2432 /* pull data from fifo into aligned buffer */
2433 u32 aligned_buf[32];
2434 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2435 int items = len >> 2;
2436 int i;
2437
2438 for (i = 0; i < items; ++i)
2439 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2440 /* memcpy from aligned buffer into output buffer */
2441 memcpy(buf, aligned_buf, len);
2442 buf += len;
2443 cnt -= len;
2444 }
2445 } else
2446 #endif
2447 {
2448 u32 *pdata = buf;
2449
2450 for (; cnt >= 4; cnt -= 4)
2451 *pdata++ = mci_fifo_readl(host->fifo_reg);
2452 buf = pdata;
2453 }
2454 if (cnt) {
2455 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2456 dw_mci_pull_final_bytes(host, buf, cnt);
2457 }
2458 }
2459
dw_mci_push_data64(struct dw_mci * host,void * buf,int cnt)2460 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2461 {
2462 struct mmc_data *data = host->data;
2463 int init_cnt = cnt;
2464
2465 /* try and push anything in the part_buf */
2466 if (unlikely(host->part_buf_count)) {
2467 int len = dw_mci_push_part_bytes(host, buf, cnt);
2468
2469 buf += len;
2470 cnt -= len;
2471
2472 if (host->part_buf_count == 8) {
2473 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2474 host->part_buf_count = 0;
2475 }
2476 }
2477 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2478 if (unlikely((unsigned long)buf & 0x7)) {
2479 while (cnt >= 8) {
2480 u64 aligned_buf[16];
2481 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2482 int items = len >> 3;
2483 int i;
2484 /* memcpy from input buffer into aligned buffer */
2485 memcpy(aligned_buf, buf, len);
2486 buf += len;
2487 cnt -= len;
2488 /* push data from aligned buffer into fifo */
2489 for (i = 0; i < items; ++i)
2490 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2491 }
2492 } else
2493 #endif
2494 {
2495 u64 *pdata = buf;
2496
2497 for (; cnt >= 8; cnt -= 8)
2498 mci_fifo_writeq(host->fifo_reg, *pdata++);
2499 buf = pdata;
2500 }
2501 /* put anything remaining in the part_buf */
2502 if (cnt) {
2503 dw_mci_set_part_bytes(host, buf, cnt);
2504 /* Push data if we have reached the expected data length */
2505 if ((data->bytes_xfered + init_cnt) ==
2506 (data->blksz * data->blocks))
2507 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2508 }
2509 }
2510
dw_mci_pull_data64(struct dw_mci * host,void * buf,int cnt)2511 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2512 {
2513 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2514 if (unlikely((unsigned long)buf & 0x7)) {
2515 while (cnt >= 8) {
2516 /* pull data from fifo into aligned buffer */
2517 u64 aligned_buf[16];
2518 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2519 int items = len >> 3;
2520 int i;
2521
2522 for (i = 0; i < items; ++i)
2523 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2524
2525 /* memcpy from aligned buffer into output buffer */
2526 memcpy(buf, aligned_buf, len);
2527 buf += len;
2528 cnt -= len;
2529 }
2530 } else
2531 #endif
2532 {
2533 u64 *pdata = buf;
2534
2535 for (; cnt >= 8; cnt -= 8)
2536 *pdata++ = mci_fifo_readq(host->fifo_reg);
2537 buf = pdata;
2538 }
2539 if (cnt) {
2540 host->part_buf = mci_fifo_readq(host->fifo_reg);
2541 dw_mci_pull_final_bytes(host, buf, cnt);
2542 }
2543 }
2544
dw_mci_pull_data(struct dw_mci * host,void * buf,int cnt)2545 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2546 {
2547 int len;
2548
2549 /* get remaining partial bytes */
2550 len = dw_mci_pull_part_bytes(host, buf, cnt);
2551 if (unlikely(len == cnt))
2552 return;
2553 buf += len;
2554 cnt -= len;
2555
2556 /* get the rest of the data */
2557 host->pull_data(host, buf, cnt);
2558 }
2559
dw_mci_read_data_pio(struct dw_mci * host,bool dto)2560 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2561 {
2562 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2563 void *buf;
2564 unsigned int offset;
2565 struct mmc_data *data = host->data;
2566 int shift = host->data_shift;
2567 u32 status;
2568 unsigned int len;
2569 unsigned int remain, fcnt;
2570
2571 do {
2572 if (!sg_miter_next(sg_miter))
2573 goto done;
2574
2575 host->sg = sg_miter->piter.sg;
2576 buf = sg_miter->addr;
2577 remain = sg_miter->length;
2578 offset = 0;
2579
2580 do {
2581 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2582 << shift) + host->part_buf_count;
2583 len = min(remain, fcnt);
2584 if (!len)
2585 break;
2586 dw_mci_pull_data(host, (void *)(buf + offset), len);
2587 data->bytes_xfered += len;
2588 offset += len;
2589 remain -= len;
2590 } while (remain);
2591
2592 sg_miter->consumed = offset;
2593 status = mci_readl(host, MINTSTS);
2594 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2595 /* if the RXDR is ready read again */
2596 } while ((status & SDMMC_INT_RXDR) ||
2597 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2598
2599 if (!remain) {
2600 if (!sg_miter_next(sg_miter))
2601 goto done;
2602 sg_miter->consumed = 0;
2603 }
2604 sg_miter_stop(sg_miter);
2605 return;
2606
2607 done:
2608 sg_miter_stop(sg_miter);
2609 host->sg = NULL;
2610 smp_wmb(); /* drain writebuffer */
2611 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2612 }
2613
dw_mci_write_data_pio(struct dw_mci * host)2614 static void dw_mci_write_data_pio(struct dw_mci *host)
2615 {
2616 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2617 void *buf;
2618 unsigned int offset;
2619 struct mmc_data *data = host->data;
2620 int shift = host->data_shift;
2621 u32 status;
2622 unsigned int len;
2623 unsigned int fifo_depth = host->fifo_depth;
2624 unsigned int remain, fcnt;
2625
2626 do {
2627 if (!sg_miter_next(sg_miter))
2628 goto done;
2629
2630 host->sg = sg_miter->piter.sg;
2631 buf = sg_miter->addr;
2632 remain = sg_miter->length;
2633 offset = 0;
2634
2635 do {
2636 fcnt = ((fifo_depth -
2637 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2638 << shift) - host->part_buf_count;
2639 len = min(remain, fcnt);
2640 if (!len)
2641 break;
2642 host->push_data(host, (void *)(buf + offset), len);
2643 data->bytes_xfered += len;
2644 offset += len;
2645 remain -= len;
2646 } while (remain);
2647
2648 sg_miter->consumed = offset;
2649 status = mci_readl(host, MINTSTS);
2650 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2651 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2652
2653 if (!remain) {
2654 if (!sg_miter_next(sg_miter))
2655 goto done;
2656 sg_miter->consumed = 0;
2657 }
2658 sg_miter_stop(sg_miter);
2659 return;
2660
2661 done:
2662 sg_miter_stop(sg_miter);
2663 host->sg = NULL;
2664 smp_wmb(); /* drain writebuffer */
2665 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2666 }
2667
dw_mci_cmd_interrupt(struct dw_mci * host,u32 status)2668 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2669 {
2670 del_timer(&host->cto_timer);
2671
2672 if (!host->cmd_status)
2673 host->cmd_status = status;
2674
2675 smp_wmb(); /* drain writebuffer */
2676
2677 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2678 tasklet_schedule(&host->tasklet);
2679
2680 dw_mci_start_fault_timer(host);
2681 }
2682
dw_mci_handle_cd(struct dw_mci * host)2683 static void dw_mci_handle_cd(struct dw_mci *host)
2684 {
2685 struct dw_mci_slot *slot = host->slot;
2686
2687 mmc_detect_change(slot->mmc,
2688 msecs_to_jiffies(host->pdata->detect_delay_ms));
2689 }
2690
dw_mci_interrupt(int irq,void * dev_id)2691 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2692 {
2693 struct dw_mci *host = dev_id;
2694 u32 pending;
2695 struct dw_mci_slot *slot = host->slot;
2696
2697 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2698
2699 if (pending) {
2700 /* Check volt switch first, since it can look like an error */
2701 if ((host->state == STATE_SENDING_CMD11) &&
2702 (pending & SDMMC_INT_VOLT_SWITCH)) {
2703 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2704 pending &= ~SDMMC_INT_VOLT_SWITCH;
2705
2706 /*
2707 * Hold the lock; we know cmd11_timer can't be kicked
2708 * off after the lock is released, so safe to delete.
2709 */
2710 spin_lock(&host->irq_lock);
2711 dw_mci_cmd_interrupt(host, pending);
2712 spin_unlock(&host->irq_lock);
2713
2714 del_timer(&host->cmd11_timer);
2715 }
2716
2717 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2718 spin_lock(&host->irq_lock);
2719
2720 del_timer(&host->cto_timer);
2721 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2722 host->cmd_status = pending;
2723 smp_wmb(); /* drain writebuffer */
2724 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2725
2726 spin_unlock(&host->irq_lock);
2727 }
2728
2729 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2730 spin_lock(&host->irq_lock);
2731
2732 /* if there is an error report DATA_ERROR */
2733 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2734 host->data_status = pending;
2735 smp_wmb(); /* drain writebuffer */
2736 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2737 tasklet_schedule(&host->tasklet);
2738
2739 spin_unlock(&host->irq_lock);
2740 }
2741
2742 if (pending & SDMMC_INT_DATA_OVER) {
2743 spin_lock(&host->irq_lock);
2744
2745 del_timer(&host->dto_timer);
2746
2747 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2748 if (!host->data_status)
2749 host->data_status = pending;
2750 smp_wmb(); /* drain writebuffer */
2751 if (host->dir_status == DW_MCI_RECV_STATUS) {
2752 if (host->sg != NULL)
2753 dw_mci_read_data_pio(host, true);
2754 }
2755 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2756 tasklet_schedule(&host->tasklet);
2757
2758 spin_unlock(&host->irq_lock);
2759 }
2760
2761 if (pending & SDMMC_INT_RXDR) {
2762 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2763 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2764 dw_mci_read_data_pio(host, false);
2765 }
2766
2767 if (pending & SDMMC_INT_TXDR) {
2768 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2769 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2770 dw_mci_write_data_pio(host);
2771 }
2772
2773 if (pending & SDMMC_INT_CMD_DONE) {
2774 spin_lock(&host->irq_lock);
2775
2776 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2777 dw_mci_cmd_interrupt(host, pending);
2778
2779 spin_unlock(&host->irq_lock);
2780 }
2781
2782 if (pending & SDMMC_INT_CD) {
2783 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2784 dw_mci_handle_cd(host);
2785 }
2786
2787 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2788 mci_writel(host, RINTSTS,
2789 SDMMC_INT_SDIO(slot->sdio_id));
2790 __dw_mci_enable_sdio_irq(slot, 0);
2791 sdio_signal_irq(slot->mmc);
2792 }
2793
2794 }
2795
2796 if (host->use_dma != TRANS_MODE_IDMAC)
2797 return IRQ_HANDLED;
2798
2799 /* Handle IDMA interrupts */
2800 if (host->dma_64bit_address == 1) {
2801 pending = mci_readl(host, IDSTS64);
2802 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2803 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2804 SDMMC_IDMAC_INT_RI);
2805 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2806 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2807 host->dma_ops->complete((void *)host);
2808 }
2809 } else {
2810 pending = mci_readl(host, IDSTS);
2811 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2812 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2813 SDMMC_IDMAC_INT_RI);
2814 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2815 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2816 host->dma_ops->complete((void *)host);
2817 }
2818 }
2819
2820 return IRQ_HANDLED;
2821 }
2822
dw_mci_init_slot_caps(struct dw_mci_slot * slot)2823 static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
2824 {
2825 struct dw_mci *host = slot->host;
2826 const struct dw_mci_drv_data *drv_data = host->drv_data;
2827 struct mmc_host *mmc = slot->mmc;
2828 int ctrl_id;
2829
2830 if (host->pdata->caps)
2831 mmc->caps = host->pdata->caps;
2832
2833 if (host->pdata->pm_caps)
2834 mmc->pm_caps = host->pdata->pm_caps;
2835
2836 if (host->dev->of_node) {
2837 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2838 if (ctrl_id < 0)
2839 ctrl_id = 0;
2840 } else {
2841 ctrl_id = to_platform_device(host->dev)->id;
2842 }
2843
2844 if (drv_data && drv_data->caps) {
2845 if (ctrl_id >= drv_data->num_caps) {
2846 dev_err(host->dev, "invalid controller id %d\n",
2847 ctrl_id);
2848 return -EINVAL;
2849 }
2850 mmc->caps |= drv_data->caps[ctrl_id];
2851 }
2852
2853 if (host->pdata->caps2)
2854 mmc->caps2 = host->pdata->caps2;
2855
2856 mmc->f_min = DW_MCI_FREQ_MIN;
2857 if (!mmc->f_max)
2858 mmc->f_max = DW_MCI_FREQ_MAX;
2859
2860 /* Process SDIO IRQs through the sdio_irq_work. */
2861 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2862 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2863
2864 return 0;
2865 }
2866
dw_mci_init_slot(struct dw_mci * host)2867 static int dw_mci_init_slot(struct dw_mci *host)
2868 {
2869 struct mmc_host *mmc;
2870 struct dw_mci_slot *slot;
2871 int ret;
2872
2873 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2874 if (!mmc)
2875 return -ENOMEM;
2876
2877 slot = mmc_priv(mmc);
2878 slot->id = 0;
2879 slot->sdio_id = host->sdio_id0 + slot->id;
2880 slot->mmc = mmc;
2881 slot->host = host;
2882 host->slot = slot;
2883
2884 mmc->ops = &dw_mci_ops;
2885
2886 /*if there are external regulators, get them*/
2887 ret = mmc_regulator_get_supply(mmc);
2888 if (ret)
2889 goto err_host_allocated;
2890
2891 if (!mmc->ocr_avail)
2892 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2893
2894 ret = mmc_of_parse(mmc);
2895 if (ret)
2896 goto err_host_allocated;
2897
2898 ret = dw_mci_init_slot_caps(slot);
2899 if (ret)
2900 goto err_host_allocated;
2901
2902 /* Useful defaults if platform data is unset. */
2903 if (host->use_dma == TRANS_MODE_IDMAC) {
2904 mmc->max_segs = host->ring_size;
2905 mmc->max_blk_size = 65535;
2906 mmc->max_seg_size = 0x1000;
2907 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2908 mmc->max_blk_count = mmc->max_req_size / 512;
2909 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2910 mmc->max_segs = 64;
2911 mmc->max_blk_size = 65535;
2912 mmc->max_blk_count = 65535;
2913 mmc->max_req_size =
2914 mmc->max_blk_size * mmc->max_blk_count;
2915 mmc->max_seg_size = mmc->max_req_size;
2916 } else {
2917 /* TRANS_MODE_PIO */
2918 mmc->max_segs = 64;
2919 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2920 mmc->max_blk_count = 512;
2921 mmc->max_req_size = mmc->max_blk_size *
2922 mmc->max_blk_count;
2923 mmc->max_seg_size = mmc->max_req_size;
2924 }
2925
2926 dw_mci_get_cd(mmc);
2927
2928 ret = mmc_add_host(mmc);
2929 if (ret)
2930 goto err_host_allocated;
2931
2932 #if defined(CONFIG_DEBUG_FS)
2933 dw_mci_init_debugfs(slot);
2934 #endif
2935
2936 return 0;
2937
2938 err_host_allocated:
2939 mmc_free_host(mmc);
2940 return ret;
2941 }
2942
dw_mci_cleanup_slot(struct dw_mci_slot * slot)2943 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
2944 {
2945 /* Debugfs stuff is cleaned up by mmc core */
2946 mmc_remove_host(slot->mmc);
2947 slot->host->slot = NULL;
2948 mmc_free_host(slot->mmc);
2949 }
2950
dw_mci_init_dma(struct dw_mci * host)2951 static void dw_mci_init_dma(struct dw_mci *host)
2952 {
2953 int addr_config;
2954 struct device *dev = host->dev;
2955
2956 /*
2957 * Check tansfer mode from HCON[17:16]
2958 * Clear the ambiguous description of dw_mmc databook:
2959 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2960 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2961 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2962 * 2b'11: Non DW DMA Interface -> pio only
2963 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2964 * simpler request/acknowledge handshake mechanism and both of them
2965 * are regarded as external dma master for dw_mmc.
2966 */
2967 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2968 if (host->use_dma == DMA_INTERFACE_IDMA) {
2969 host->use_dma = TRANS_MODE_IDMAC;
2970 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2971 host->use_dma == DMA_INTERFACE_GDMA) {
2972 host->use_dma = TRANS_MODE_EDMAC;
2973 } else {
2974 goto no_dma;
2975 }
2976
2977 /* Determine which DMA interface to use */
2978 if (host->use_dma == TRANS_MODE_IDMAC) {
2979 /*
2980 * Check ADDR_CONFIG bit in HCON to find
2981 * IDMAC address bus width
2982 */
2983 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2984
2985 if (addr_config == 1) {
2986 /* host supports IDMAC in 64-bit address mode */
2987 host->dma_64bit_address = 1;
2988 dev_info(host->dev,
2989 "IDMAC supports 64-bit address mode.\n");
2990 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2991 dma_set_coherent_mask(host->dev,
2992 DMA_BIT_MASK(64));
2993 } else {
2994 /* host supports IDMAC in 32-bit address mode */
2995 host->dma_64bit_address = 0;
2996 dev_info(host->dev,
2997 "IDMAC supports 32-bit address mode.\n");
2998 }
2999
3000 /* Alloc memory for sg translation */
3001 host->sg_cpu = dmam_alloc_coherent(host->dev,
3002 DESC_RING_BUF_SZ,
3003 &host->sg_dma, GFP_KERNEL);
3004 if (!host->sg_cpu) {
3005 dev_err(host->dev,
3006 "%s: could not alloc DMA memory\n",
3007 __func__);
3008 goto no_dma;
3009 }
3010
3011 host->dma_ops = &dw_mci_idmac_ops;
3012 dev_info(host->dev, "Using internal DMA controller.\n");
3013 } else {
3014 /* TRANS_MODE_EDMAC: check dma bindings again */
3015 if ((device_property_read_string_array(dev, "dma-names",
3016 NULL, 0) < 0) ||
3017 !device_property_present(dev, "dmas")) {
3018 goto no_dma;
3019 }
3020 host->dma_ops = &dw_mci_edmac_ops;
3021 dev_info(host->dev, "Using external DMA controller.\n");
3022 }
3023
3024 if (host->dma_ops->init && host->dma_ops->start &&
3025 host->dma_ops->stop && host->dma_ops->cleanup) {
3026 if (host->dma_ops->init(host)) {
3027 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
3028 __func__);
3029 goto no_dma;
3030 }
3031 } else {
3032 dev_err(host->dev, "DMA initialization not found.\n");
3033 goto no_dma;
3034 }
3035
3036 return;
3037
3038 no_dma:
3039 dev_info(host->dev, "Using PIO mode.\n");
3040 host->use_dma = TRANS_MODE_PIO;
3041 }
3042
dw_mci_cmd11_timer(struct timer_list * t)3043 static void dw_mci_cmd11_timer(struct timer_list *t)
3044 {
3045 struct dw_mci *host = from_timer(host, t, cmd11_timer);
3046
3047 if (host->state != STATE_SENDING_CMD11) {
3048 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
3049 return;
3050 }
3051
3052 host->cmd_status = SDMMC_INT_RTO;
3053 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3054 tasklet_schedule(&host->tasklet);
3055 }
3056
dw_mci_cto_timer(struct timer_list * t)3057 static void dw_mci_cto_timer(struct timer_list *t)
3058 {
3059 struct dw_mci *host = from_timer(host, t, cto_timer);
3060 unsigned long irqflags;
3061 u32 pending;
3062
3063 spin_lock_irqsave(&host->irq_lock, irqflags);
3064
3065 /*
3066 * If somehow we have very bad interrupt latency it's remotely possible
3067 * that the timer could fire while the interrupt is still pending or
3068 * while the interrupt is midway through running. Let's be paranoid
3069 * and detect those two cases. Note that this is paranoia is somewhat
3070 * justified because in this function we don't actually cancel the
3071 * pending command in the controller--we just assume it will never come.
3072 */
3073 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3074 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
3075 /* The interrupt should fire; no need to act but we can warn */
3076 dev_warn(host->dev, "Unexpected interrupt latency\n");
3077 goto exit;
3078 }
3079 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3080 /* Presumably interrupt handler couldn't delete the timer */
3081 dev_warn(host->dev, "CTO timeout when already completed\n");
3082 goto exit;
3083 }
3084
3085 /*
3086 * Continued paranoia to make sure we're in the state we expect.
3087 * This paranoia isn't really justified but it seems good to be safe.
3088 */
3089 switch (host->state) {
3090 case STATE_SENDING_CMD11:
3091 case STATE_SENDING_CMD:
3092 case STATE_SENDING_STOP:
3093 /*
3094 * If CMD_DONE interrupt does NOT come in sending command
3095 * state, we should notify the driver to terminate current
3096 * transfer and report a command timeout to the core.
3097 */
3098 host->cmd_status = SDMMC_INT_RTO;
3099 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3100 tasklet_schedule(&host->tasklet);
3101 break;
3102 default:
3103 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3104 host->state);
3105 break;
3106 }
3107
3108 exit:
3109 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3110 }
3111
dw_mci_dto_timer(struct timer_list * t)3112 static void dw_mci_dto_timer(struct timer_list *t)
3113 {
3114 struct dw_mci *host = from_timer(host, t, dto_timer);
3115 unsigned long irqflags;
3116 u32 pending;
3117
3118 spin_lock_irqsave(&host->irq_lock, irqflags);
3119
3120 /*
3121 * The DTO timer is much longer than the CTO timer, so it's even less
3122 * likely that we'll these cases, but it pays to be paranoid.
3123 */
3124 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3125 if (pending & SDMMC_INT_DATA_OVER) {
3126 /* The interrupt should fire; no need to act but we can warn */
3127 dev_warn(host->dev, "Unexpected data interrupt latency\n");
3128 goto exit;
3129 }
3130 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
3131 /* Presumably interrupt handler couldn't delete the timer */
3132 dev_warn(host->dev, "DTO timeout when already completed\n");
3133 goto exit;
3134 }
3135
3136 /*
3137 * Continued paranoia to make sure we're in the state we expect.
3138 * This paranoia isn't really justified but it seems good to be safe.
3139 */
3140 switch (host->state) {
3141 case STATE_SENDING_DATA:
3142 case STATE_DATA_BUSY:
3143 /*
3144 * If DTO interrupt does NOT come in sending data state,
3145 * we should notify the driver to terminate current transfer
3146 * and report a data timeout to the core.
3147 */
3148 host->data_status = SDMMC_INT_DRTO;
3149 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3150 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3151 tasklet_schedule(&host->tasklet);
3152 break;
3153 default:
3154 dev_warn(host->dev, "Unexpected data timeout, state %d\n",
3155 host->state);
3156 break;
3157 }
3158
3159 exit:
3160 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3161 }
3162
3163 #ifdef CONFIG_OF
dw_mci_parse_dt(struct dw_mci * host)3164 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3165 {
3166 struct dw_mci_board *pdata;
3167 struct device *dev = host->dev;
3168 const struct dw_mci_drv_data *drv_data = host->drv_data;
3169 int ret;
3170 u32 clock_frequency;
3171
3172 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3173 if (!pdata)
3174 return ERR_PTR(-ENOMEM);
3175
3176 /* find reset controller when exist */
3177 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
3178 if (IS_ERR(pdata->rstc))
3179 return ERR_CAST(pdata->rstc);
3180
3181 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
3182 dev_info(dev,
3183 "fifo-depth property not found, using value of FIFOTH register as default\n");
3184
3185 device_property_read_u32(dev, "card-detect-delay",
3186 &pdata->detect_delay_ms);
3187
3188 device_property_read_u32(dev, "data-addr", &host->data_addr_override);
3189
3190 if (device_property_present(dev, "fifo-watermark-aligned"))
3191 host->wm_aligned = true;
3192
3193 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3194 pdata->bus_hz = clock_frequency;
3195
3196 if (drv_data && drv_data->parse_dt) {
3197 ret = drv_data->parse_dt(host);
3198 if (ret)
3199 return ERR_PTR(ret);
3200 }
3201
3202 return pdata;
3203 }
3204
3205 #else /* CONFIG_OF */
dw_mci_parse_dt(struct dw_mci * host)3206 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3207 {
3208 return ERR_PTR(-EINVAL);
3209 }
3210 #endif /* CONFIG_OF */
3211
dw_mci_enable_cd(struct dw_mci * host)3212 static void dw_mci_enable_cd(struct dw_mci *host)
3213 {
3214 unsigned long irqflags;
3215 u32 temp;
3216
3217 /*
3218 * No need for CD if all slots have a non-error GPIO
3219 * as well as broken card detection is found.
3220 */
3221 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3222 return;
3223
3224 if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
3225 spin_lock_irqsave(&host->irq_lock, irqflags);
3226 temp = mci_readl(host, INTMASK);
3227 temp |= SDMMC_INT_CD;
3228 mci_writel(host, INTMASK, temp);
3229 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3230 }
3231 }
3232
dw_mci_probe(struct dw_mci * host)3233 int dw_mci_probe(struct dw_mci *host)
3234 {
3235 const struct dw_mci_drv_data *drv_data = host->drv_data;
3236 int width, i, ret = 0;
3237 u32 fifo_size;
3238
3239 if (!host->pdata) {
3240 host->pdata = dw_mci_parse_dt(host);
3241 if (IS_ERR(host->pdata))
3242 return dev_err_probe(host->dev, PTR_ERR(host->pdata),
3243 "platform data not available\n");
3244 }
3245
3246 host->biu_clk = devm_clk_get(host->dev, "biu");
3247 if (IS_ERR(host->biu_clk)) {
3248 dev_dbg(host->dev, "biu clock not available\n");
3249 } else {
3250 ret = clk_prepare_enable(host->biu_clk);
3251 if (ret) {
3252 dev_err(host->dev, "failed to enable biu clock\n");
3253 return ret;
3254 }
3255 }
3256
3257 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3258 if (IS_ERR(host->ciu_clk)) {
3259 dev_dbg(host->dev, "ciu clock not available\n");
3260 host->bus_hz = host->pdata->bus_hz;
3261 } else {
3262 ret = clk_prepare_enable(host->ciu_clk);
3263 if (ret) {
3264 dev_err(host->dev, "failed to enable ciu clock\n");
3265 goto err_clk_biu;
3266 }
3267
3268 if (host->pdata->bus_hz) {
3269 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3270 if (ret)
3271 dev_warn(host->dev,
3272 "Unable to set bus rate to %uHz\n",
3273 host->pdata->bus_hz);
3274 }
3275 host->bus_hz = clk_get_rate(host->ciu_clk);
3276 }
3277
3278 if (!host->bus_hz) {
3279 dev_err(host->dev,
3280 "Platform data must supply bus speed\n");
3281 ret = -ENODEV;
3282 goto err_clk_ciu;
3283 }
3284
3285 if (host->pdata->rstc) {
3286 reset_control_assert(host->pdata->rstc);
3287 usleep_range(10, 50);
3288 reset_control_deassert(host->pdata->rstc);
3289 }
3290
3291 if (drv_data && drv_data->init) {
3292 ret = drv_data->init(host);
3293 if (ret) {
3294 dev_err(host->dev,
3295 "implementation specific init failed\n");
3296 goto err_clk_ciu;
3297 }
3298 }
3299
3300 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0);
3301 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0);
3302 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0);
3303
3304 spin_lock_init(&host->lock);
3305 spin_lock_init(&host->irq_lock);
3306 INIT_LIST_HEAD(&host->queue);
3307
3308 dw_mci_init_fault(host);
3309
3310 /*
3311 * Get the host data width - this assumes that HCON has been set with
3312 * the correct values.
3313 */
3314 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3315 if (!i) {
3316 host->push_data = dw_mci_push_data16;
3317 host->pull_data = dw_mci_pull_data16;
3318 width = 16;
3319 host->data_shift = 1;
3320 } else if (i == 2) {
3321 host->push_data = dw_mci_push_data64;
3322 host->pull_data = dw_mci_pull_data64;
3323 width = 64;
3324 host->data_shift = 3;
3325 } else {
3326 /* Check for a reserved value, and warn if it is */
3327 WARN((i != 1),
3328 "HCON reports a reserved host data width!\n"
3329 "Defaulting to 32-bit access.\n");
3330 host->push_data = dw_mci_push_data32;
3331 host->pull_data = dw_mci_pull_data32;
3332 width = 32;
3333 host->data_shift = 2;
3334 }
3335
3336 /* Reset all blocks */
3337 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3338 ret = -ENODEV;
3339 goto err_clk_ciu;
3340 }
3341
3342 host->dma_ops = host->pdata->dma_ops;
3343 dw_mci_init_dma(host);
3344
3345 /* Clear the interrupts for the host controller */
3346 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3347 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3348
3349 /* Put in max timeout */
3350 mci_writel(host, TMOUT, 0xFFFFFFFF);
3351
3352 /*
3353 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3354 * Tx Mark = fifo_size / 2 DMA Size = 8
3355 */
3356 if (!host->pdata->fifo_depth) {
3357 /*
3358 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3359 * have been overwritten by the bootloader, just like we're
3360 * about to do, so if you know the value for your hardware, you
3361 * should put it in the platform data.
3362 */
3363 fifo_size = mci_readl(host, FIFOTH);
3364 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3365 } else {
3366 fifo_size = host->pdata->fifo_depth;
3367 }
3368 host->fifo_depth = fifo_size;
3369 host->fifoth_val =
3370 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3371 mci_writel(host, FIFOTH, host->fifoth_val);
3372
3373 /* disable clock to CIU */
3374 mci_writel(host, CLKENA, 0);
3375 mci_writel(host, CLKSRC, 0);
3376
3377 /*
3378 * In 2.40a spec, Data offset is changed.
3379 * Need to check the version-id and set data-offset for DATA register.
3380 */
3381 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3382 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3383
3384 if (host->data_addr_override)
3385 host->fifo_reg = host->regs + host->data_addr_override;
3386 else if (host->verid < DW_MMC_240A)
3387 host->fifo_reg = host->regs + DATA_OFFSET;
3388 else
3389 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3390
3391 tasklet_setup(&host->tasklet, dw_mci_tasklet_func);
3392 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3393 host->irq_flags, "dw-mci", host);
3394 if (ret)
3395 goto err_dmaunmap;
3396
3397 /*
3398 * Enable interrupts for command done, data over, data empty,
3399 * receive ready and error such as transmit, receive timeout, crc error
3400 */
3401 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3402 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3403 DW_MCI_ERROR_FLAGS);
3404 /* Enable mci interrupt */
3405 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3406
3407 dev_info(host->dev,
3408 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3409 host->irq, width, fifo_size);
3410
3411 /* We need at least one slot to succeed */
3412 ret = dw_mci_init_slot(host);
3413 if (ret) {
3414 dev_dbg(host->dev, "slot %d init failed\n", i);
3415 goto err_dmaunmap;
3416 }
3417
3418 /* Now that slots are all setup, we can enable card detect */
3419 dw_mci_enable_cd(host);
3420
3421 return 0;
3422
3423 err_dmaunmap:
3424 if (host->use_dma && host->dma_ops->exit)
3425 host->dma_ops->exit(host);
3426
3427 reset_control_assert(host->pdata->rstc);
3428
3429 err_clk_ciu:
3430 clk_disable_unprepare(host->ciu_clk);
3431
3432 err_clk_biu:
3433 clk_disable_unprepare(host->biu_clk);
3434
3435 return ret;
3436 }
3437 EXPORT_SYMBOL(dw_mci_probe);
3438
dw_mci_remove(struct dw_mci * host)3439 void dw_mci_remove(struct dw_mci *host)
3440 {
3441 dev_dbg(host->dev, "remove slot\n");
3442 if (host->slot)
3443 dw_mci_cleanup_slot(host->slot);
3444
3445 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3446 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3447
3448 /* disable clock to CIU */
3449 mci_writel(host, CLKENA, 0);
3450 mci_writel(host, CLKSRC, 0);
3451
3452 if (host->use_dma && host->dma_ops->exit)
3453 host->dma_ops->exit(host);
3454
3455 reset_control_assert(host->pdata->rstc);
3456
3457 clk_disable_unprepare(host->ciu_clk);
3458 clk_disable_unprepare(host->biu_clk);
3459 }
3460 EXPORT_SYMBOL(dw_mci_remove);
3461
3462
3463
3464 #ifdef CONFIG_PM
dw_mci_runtime_suspend(struct device * dev)3465 int dw_mci_runtime_suspend(struct device *dev)
3466 {
3467 struct dw_mci *host = dev_get_drvdata(dev);
3468
3469 if (host->use_dma && host->dma_ops->exit)
3470 host->dma_ops->exit(host);
3471
3472 clk_disable_unprepare(host->ciu_clk);
3473
3474 if (host->slot &&
3475 (mmc_can_gpio_cd(host->slot->mmc) ||
3476 !mmc_card_is_removable(host->slot->mmc)))
3477 clk_disable_unprepare(host->biu_clk);
3478
3479 return 0;
3480 }
3481 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3482
dw_mci_runtime_resume(struct device * dev)3483 int dw_mci_runtime_resume(struct device *dev)
3484 {
3485 int ret = 0;
3486 struct dw_mci *host = dev_get_drvdata(dev);
3487
3488 if (host->slot &&
3489 (mmc_can_gpio_cd(host->slot->mmc) ||
3490 !mmc_card_is_removable(host->slot->mmc))) {
3491 ret = clk_prepare_enable(host->biu_clk);
3492 if (ret)
3493 return ret;
3494 }
3495
3496 ret = clk_prepare_enable(host->ciu_clk);
3497 if (ret)
3498 goto err;
3499
3500 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3501 clk_disable_unprepare(host->ciu_clk);
3502 ret = -ENODEV;
3503 goto err;
3504 }
3505
3506 if (host->use_dma && host->dma_ops->init)
3507 host->dma_ops->init(host);
3508
3509 /*
3510 * Restore the initial value at FIFOTH register
3511 * And Invalidate the prev_blksz with zero
3512 */
3513 mci_writel(host, FIFOTH, host->fifoth_val);
3514 host->prev_blksz = 0;
3515
3516 /* Put in max timeout */
3517 mci_writel(host, TMOUT, 0xFFFFFFFF);
3518
3519 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3520 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3521 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3522 DW_MCI_ERROR_FLAGS);
3523 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3524
3525
3526 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3527 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
3528
3529 /* Force setup bus to guarantee available clock output */
3530 dw_mci_setup_bus(host->slot, true);
3531
3532 /* Re-enable SDIO interrupts. */
3533 if (sdio_irq_claimed(host->slot->mmc))
3534 __dw_mci_enable_sdio_irq(host->slot, 1);
3535
3536 /* Now that slots are all setup, we can enable card detect */
3537 dw_mci_enable_cd(host);
3538
3539 return 0;
3540
3541 err:
3542 if (host->slot &&
3543 (mmc_can_gpio_cd(host->slot->mmc) ||
3544 !mmc_card_is_removable(host->slot->mmc)))
3545 clk_disable_unprepare(host->biu_clk);
3546
3547 return ret;
3548 }
3549 EXPORT_SYMBOL(dw_mci_runtime_resume);
3550 #endif /* CONFIG_PM */
3551
dw_mci_init(void)3552 static int __init dw_mci_init(void)
3553 {
3554 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3555 return 0;
3556 }
3557
dw_mci_exit(void)3558 static void __exit dw_mci_exit(void)
3559 {
3560 }
3561
3562 module_init(dw_mci_init);
3563 module_exit(dw_mci_exit);
3564
3565 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3566 MODULE_AUTHOR("NXP Semiconductor VietNam");
3567 MODULE_AUTHOR("Imagination Technologies Ltd");
3568 MODULE_LICENSE("GPL v2");
3569