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1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 #include "mlx5_ifc_fpga.h"
36 
37 enum {
38 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62 	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65 
66 enum {
67 	MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
68 	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
69 	MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
70 	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
71 };
72 
73 enum {
74 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
75 	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
76 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
77 	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
78 };
79 
80 enum {
81 	MLX5_SHARED_RESOURCE_UID = 0xffff,
82 };
83 
84 enum {
85 	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
86 };
87 
88 enum {
89 	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
90 	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
91 	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
92 };
93 
94 enum {
95 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
96 	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
97 	MLX5_OBJ_TYPE_MKEY = 0xff01,
98 	MLX5_OBJ_TYPE_QP = 0xff02,
99 	MLX5_OBJ_TYPE_PSV = 0xff03,
100 	MLX5_OBJ_TYPE_RMP = 0xff04,
101 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
102 	MLX5_OBJ_TYPE_RQ = 0xff06,
103 	MLX5_OBJ_TYPE_SQ = 0xff07,
104 	MLX5_OBJ_TYPE_TIR = 0xff08,
105 	MLX5_OBJ_TYPE_TIS = 0xff09,
106 	MLX5_OBJ_TYPE_DCT = 0xff0a,
107 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
108 	MLX5_OBJ_TYPE_RQT = 0xff0e,
109 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
110 	MLX5_OBJ_TYPE_CQ = 0xff10,
111 };
112 
113 enum {
114 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
115 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
116 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
117 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
118 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
119 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
120 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
121 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
122 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
123 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
124 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
125 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
126 	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
127 	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
128 	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
129 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
130 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
131 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
132 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
133 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
134 	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
135 	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
136 	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
137 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
138 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
139 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
140 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
141 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
142 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
143 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
144 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
145 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
146 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
147 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
148 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
149 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
150 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
151 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
152 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
153 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
154 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
155 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
156 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
157 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
158 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
159 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
160 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
161 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
162 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
163 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
164 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
165 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
166 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
167 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
168 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
169 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
170 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
171 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
172 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
173 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
174 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
175 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
176 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
177 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
178 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
179 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
180 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
181 	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
182 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
183 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
184 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
185 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
186 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
187 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
188 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
189 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
190 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
191 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
192 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
193 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
194 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
195 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
196 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
197 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
198 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
199 	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
200 	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
201 	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
202 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
203 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
204 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
205 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
206 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
207 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
208 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
209 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
210 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
211 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
212 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
213 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
214 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
215 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
216 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
217 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
218 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
219 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
220 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
221 	MLX5_CMD_OP_NOP                           = 0x80d,
222 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
223 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
224 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
225 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
226 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
227 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
228 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
229 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
230 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
231 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
232 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
233 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
234 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
235 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
236 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
237 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
238 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
239 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
240 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
241 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
242 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
243 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
244 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
245 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
246 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
247 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
248 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
249 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
250 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
251 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
252 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
253 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
254 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
255 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
256 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
257 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
258 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
259 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
260 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
261 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
262 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
263 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
264 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
265 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
266 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
267 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
268 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
269 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
270 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
271 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
272 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
273 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
274 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
275 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
276 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
277 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
278 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
279 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
280 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
281 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
282 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
283 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
284 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
285 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
286 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
287 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
288 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
289 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
290 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
291 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
292 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
293 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
294 	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
295 	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
296 	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
297 	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
298 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
299 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
300 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
301 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
302 	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
303 	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
304 	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
305 	MLX5_CMD_OP_MAX
306 };
307 
308 /* Valid range for general commands that don't work over an object */
309 enum {
310 	MLX5_CMD_OP_GENERAL_START = 0xb00,
311 	MLX5_CMD_OP_GENERAL_END = 0xd00,
312 };
313 
314 struct mlx5_ifc_flow_table_fields_supported_bits {
315 	u8         outer_dmac[0x1];
316 	u8         outer_smac[0x1];
317 	u8         outer_ether_type[0x1];
318 	u8         outer_ip_version[0x1];
319 	u8         outer_first_prio[0x1];
320 	u8         outer_first_cfi[0x1];
321 	u8         outer_first_vid[0x1];
322 	u8         outer_ipv4_ttl[0x1];
323 	u8         outer_second_prio[0x1];
324 	u8         outer_second_cfi[0x1];
325 	u8         outer_second_vid[0x1];
326 	u8         reserved_at_b[0x1];
327 	u8         outer_sip[0x1];
328 	u8         outer_dip[0x1];
329 	u8         outer_frag[0x1];
330 	u8         outer_ip_protocol[0x1];
331 	u8         outer_ip_ecn[0x1];
332 	u8         outer_ip_dscp[0x1];
333 	u8         outer_udp_sport[0x1];
334 	u8         outer_udp_dport[0x1];
335 	u8         outer_tcp_sport[0x1];
336 	u8         outer_tcp_dport[0x1];
337 	u8         outer_tcp_flags[0x1];
338 	u8         outer_gre_protocol[0x1];
339 	u8         outer_gre_key[0x1];
340 	u8         outer_vxlan_vni[0x1];
341 	u8         outer_geneve_vni[0x1];
342 	u8         outer_geneve_oam[0x1];
343 	u8         outer_geneve_protocol_type[0x1];
344 	u8         outer_geneve_opt_len[0x1];
345 	u8         reserved_at_1e[0x1];
346 	u8         source_eswitch_port[0x1];
347 
348 	u8         inner_dmac[0x1];
349 	u8         inner_smac[0x1];
350 	u8         inner_ether_type[0x1];
351 	u8         inner_ip_version[0x1];
352 	u8         inner_first_prio[0x1];
353 	u8         inner_first_cfi[0x1];
354 	u8         inner_first_vid[0x1];
355 	u8         reserved_at_27[0x1];
356 	u8         inner_second_prio[0x1];
357 	u8         inner_second_cfi[0x1];
358 	u8         inner_second_vid[0x1];
359 	u8         reserved_at_2b[0x1];
360 	u8         inner_sip[0x1];
361 	u8         inner_dip[0x1];
362 	u8         inner_frag[0x1];
363 	u8         inner_ip_protocol[0x1];
364 	u8         inner_ip_ecn[0x1];
365 	u8         inner_ip_dscp[0x1];
366 	u8         inner_udp_sport[0x1];
367 	u8         inner_udp_dport[0x1];
368 	u8         inner_tcp_sport[0x1];
369 	u8         inner_tcp_dport[0x1];
370 	u8         inner_tcp_flags[0x1];
371 	u8         reserved_at_37[0x9];
372 
373 	u8         geneve_tlv_option_0_data[0x1];
374 	u8         reserved_at_41[0x4];
375 	u8         outer_first_mpls_over_udp[0x4];
376 	u8         outer_first_mpls_over_gre[0x4];
377 	u8         inner_first_mpls[0x4];
378 	u8         outer_first_mpls[0x4];
379 	u8         reserved_at_55[0x2];
380 	u8	   outer_esp_spi[0x1];
381 	u8         reserved_at_58[0x2];
382 	u8         bth_dst_qp[0x1];
383 	u8         reserved_at_5b[0x5];
384 
385 	u8         reserved_at_60[0x18];
386 	u8         metadata_reg_c_7[0x1];
387 	u8         metadata_reg_c_6[0x1];
388 	u8         metadata_reg_c_5[0x1];
389 	u8         metadata_reg_c_4[0x1];
390 	u8         metadata_reg_c_3[0x1];
391 	u8         metadata_reg_c_2[0x1];
392 	u8         metadata_reg_c_1[0x1];
393 	u8         metadata_reg_c_0[0x1];
394 };
395 
396 struct mlx5_ifc_flow_table_prop_layout_bits {
397 	u8         ft_support[0x1];
398 	u8         reserved_at_1[0x1];
399 	u8         flow_counter[0x1];
400 	u8	   flow_modify_en[0x1];
401 	u8         modify_root[0x1];
402 	u8         identified_miss_table_mode[0x1];
403 	u8         flow_table_modify[0x1];
404 	u8         reformat[0x1];
405 	u8         decap[0x1];
406 	u8         reserved_at_9[0x1];
407 	u8         pop_vlan[0x1];
408 	u8         push_vlan[0x1];
409 	u8         reserved_at_c[0x1];
410 	u8         pop_vlan_2[0x1];
411 	u8         push_vlan_2[0x1];
412 	u8	   reformat_and_vlan_action[0x1];
413 	u8	   reserved_at_10[0x1];
414 	u8         sw_owner[0x1];
415 	u8	   reformat_l3_tunnel_to_l2[0x1];
416 	u8	   reformat_l2_to_l3_tunnel[0x1];
417 	u8	   reformat_and_modify_action[0x1];
418 	u8	   ignore_flow_level[0x1];
419 	u8         reserved_at_16[0x1];
420 	u8	   table_miss_action_domain[0x1];
421 	u8         termination_table[0x1];
422 	u8         reformat_and_fwd_to_table[0x1];
423 	u8         reserved_at_1a[0x2];
424 	u8         ipsec_encrypt[0x1];
425 	u8         ipsec_decrypt[0x1];
426 	u8         sw_owner_v2[0x1];
427 	u8         reserved_at_1f[0x1];
428 
429 	u8         termination_table_raw_traffic[0x1];
430 	u8         reserved_at_21[0x1];
431 	u8         log_max_ft_size[0x6];
432 	u8         log_max_modify_header_context[0x8];
433 	u8         max_modify_header_actions[0x8];
434 	u8         max_ft_level[0x8];
435 
436 	u8         reserved_at_40[0x20];
437 
438 	u8         reserved_at_60[0x2];
439 	u8         reformat_insert[0x1];
440 	u8         reformat_remove[0x1];
441 	u8         reserver_at_64[0x14];
442 	u8         log_max_ft_num[0x8];
443 
444 	u8         reserved_at_80[0x10];
445 	u8         log_max_flow_counter[0x8];
446 	u8         log_max_destination[0x8];
447 
448 	u8         reserved_at_a0[0x18];
449 	u8         log_max_flow[0x8];
450 
451 	u8         reserved_at_c0[0x40];
452 
453 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
454 
455 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
456 };
457 
458 struct mlx5_ifc_odp_per_transport_service_cap_bits {
459 	u8         send[0x1];
460 	u8         receive[0x1];
461 	u8         write[0x1];
462 	u8         read[0x1];
463 	u8         atomic[0x1];
464 	u8         srq_receive[0x1];
465 	u8         reserved_at_6[0x1a];
466 };
467 
468 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
469 	u8         smac_47_16[0x20];
470 
471 	u8         smac_15_0[0x10];
472 	u8         ethertype[0x10];
473 
474 	u8         dmac_47_16[0x20];
475 
476 	u8         dmac_15_0[0x10];
477 	u8         first_prio[0x3];
478 	u8         first_cfi[0x1];
479 	u8         first_vid[0xc];
480 
481 	u8         ip_protocol[0x8];
482 	u8         ip_dscp[0x6];
483 	u8         ip_ecn[0x2];
484 	u8         cvlan_tag[0x1];
485 	u8         svlan_tag[0x1];
486 	u8         frag[0x1];
487 	u8         ip_version[0x4];
488 	u8         tcp_flags[0x9];
489 
490 	u8         tcp_sport[0x10];
491 	u8         tcp_dport[0x10];
492 
493 	u8         reserved_at_c0[0x18];
494 	u8         ttl_hoplimit[0x8];
495 
496 	u8         udp_sport[0x10];
497 	u8         udp_dport[0x10];
498 
499 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
500 
501 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
502 };
503 
504 struct mlx5_ifc_nvgre_key_bits {
505 	u8 hi[0x18];
506 	u8 lo[0x8];
507 };
508 
509 union mlx5_ifc_gre_key_bits {
510 	struct mlx5_ifc_nvgre_key_bits nvgre;
511 	u8 key[0x20];
512 };
513 
514 struct mlx5_ifc_fte_match_set_misc_bits {
515 	u8         gre_c_present[0x1];
516 	u8         reserved_at_1[0x1];
517 	u8         gre_k_present[0x1];
518 	u8         gre_s_present[0x1];
519 	u8         source_vhca_port[0x4];
520 	u8         source_sqn[0x18];
521 
522 	u8         source_eswitch_owner_vhca_id[0x10];
523 	u8         source_port[0x10];
524 
525 	u8         outer_second_prio[0x3];
526 	u8         outer_second_cfi[0x1];
527 	u8         outer_second_vid[0xc];
528 	u8         inner_second_prio[0x3];
529 	u8         inner_second_cfi[0x1];
530 	u8         inner_second_vid[0xc];
531 
532 	u8         outer_second_cvlan_tag[0x1];
533 	u8         inner_second_cvlan_tag[0x1];
534 	u8         outer_second_svlan_tag[0x1];
535 	u8         inner_second_svlan_tag[0x1];
536 	u8         reserved_at_64[0xc];
537 	u8         gre_protocol[0x10];
538 
539 	union mlx5_ifc_gre_key_bits gre_key;
540 
541 	u8         vxlan_vni[0x18];
542 	u8         reserved_at_b8[0x8];
543 
544 	u8         geneve_vni[0x18];
545 	u8         reserved_at_d8[0x7];
546 	u8         geneve_oam[0x1];
547 
548 	u8         reserved_at_e0[0xc];
549 	u8         outer_ipv6_flow_label[0x14];
550 
551 	u8         reserved_at_100[0xc];
552 	u8         inner_ipv6_flow_label[0x14];
553 
554 	u8         reserved_at_120[0xa];
555 	u8         geneve_opt_len[0x6];
556 	u8         geneve_protocol_type[0x10];
557 
558 	u8         reserved_at_140[0x8];
559 	u8         bth_dst_qp[0x18];
560 	u8	   reserved_at_160[0x20];
561 	u8	   outer_esp_spi[0x20];
562 	u8         reserved_at_1a0[0x60];
563 };
564 
565 struct mlx5_ifc_fte_match_mpls_bits {
566 	u8         mpls_label[0x14];
567 	u8         mpls_exp[0x3];
568 	u8         mpls_s_bos[0x1];
569 	u8         mpls_ttl[0x8];
570 };
571 
572 struct mlx5_ifc_fte_match_set_misc2_bits {
573 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
574 
575 	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
576 
577 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
578 
579 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
580 
581 	u8         metadata_reg_c_7[0x20];
582 
583 	u8         metadata_reg_c_6[0x20];
584 
585 	u8         metadata_reg_c_5[0x20];
586 
587 	u8         metadata_reg_c_4[0x20];
588 
589 	u8         metadata_reg_c_3[0x20];
590 
591 	u8         metadata_reg_c_2[0x20];
592 
593 	u8         metadata_reg_c_1[0x20];
594 
595 	u8         metadata_reg_c_0[0x20];
596 
597 	u8         metadata_reg_a[0x20];
598 
599 	u8         reserved_at_1a0[0x60];
600 };
601 
602 struct mlx5_ifc_fte_match_set_misc3_bits {
603 	u8         inner_tcp_seq_num[0x20];
604 
605 	u8         outer_tcp_seq_num[0x20];
606 
607 	u8         inner_tcp_ack_num[0x20];
608 
609 	u8         outer_tcp_ack_num[0x20];
610 
611 	u8	   reserved_at_80[0x8];
612 	u8         outer_vxlan_gpe_vni[0x18];
613 
614 	u8         outer_vxlan_gpe_next_protocol[0x8];
615 	u8         outer_vxlan_gpe_flags[0x8];
616 	u8	   reserved_at_b0[0x10];
617 
618 	u8	   icmp_header_data[0x20];
619 
620 	u8	   icmpv6_header_data[0x20];
621 
622 	u8	   icmp_type[0x8];
623 	u8	   icmp_code[0x8];
624 	u8	   icmpv6_type[0x8];
625 	u8	   icmpv6_code[0x8];
626 
627 	u8         geneve_tlv_option_0_data[0x20];
628 
629 	u8	   gtpu_teid[0x20];
630 
631 	u8	   gtpu_msg_type[0x8];
632 	u8	   gtpu_msg_flags[0x8];
633 	u8	   reserved_at_170[0x10];
634 
635 	u8	   gtpu_dw_2[0x20];
636 
637 	u8	   gtpu_first_ext_dw_0[0x20];
638 
639 	u8	   gtpu_dw_0[0x20];
640 
641 	u8	   reserved_at_1e0[0x20];
642 };
643 
644 struct mlx5_ifc_fte_match_set_misc4_bits {
645 	u8         prog_sample_field_value_0[0x20];
646 
647 	u8         prog_sample_field_id_0[0x20];
648 
649 	u8         prog_sample_field_value_1[0x20];
650 
651 	u8         prog_sample_field_id_1[0x20];
652 
653 	u8         prog_sample_field_value_2[0x20];
654 
655 	u8         prog_sample_field_id_2[0x20];
656 
657 	u8         prog_sample_field_value_3[0x20];
658 
659 	u8         prog_sample_field_id_3[0x20];
660 
661 	u8         reserved_at_100[0x100];
662 };
663 
664 struct mlx5_ifc_cmd_pas_bits {
665 	u8         pa_h[0x20];
666 
667 	u8         pa_l[0x14];
668 	u8         reserved_at_34[0xc];
669 };
670 
671 struct mlx5_ifc_uint64_bits {
672 	u8         hi[0x20];
673 
674 	u8         lo[0x20];
675 };
676 
677 enum {
678 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
679 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
680 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
681 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
682 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
683 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
684 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
685 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
686 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
687 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
688 };
689 
690 struct mlx5_ifc_ads_bits {
691 	u8         fl[0x1];
692 	u8         free_ar[0x1];
693 	u8         reserved_at_2[0xe];
694 	u8         pkey_index[0x10];
695 
696 	u8         reserved_at_20[0x8];
697 	u8         grh[0x1];
698 	u8         mlid[0x7];
699 	u8         rlid[0x10];
700 
701 	u8         ack_timeout[0x5];
702 	u8         reserved_at_45[0x3];
703 	u8         src_addr_index[0x8];
704 	u8         reserved_at_50[0x4];
705 	u8         stat_rate[0x4];
706 	u8         hop_limit[0x8];
707 
708 	u8         reserved_at_60[0x4];
709 	u8         tclass[0x8];
710 	u8         flow_label[0x14];
711 
712 	u8         rgid_rip[16][0x8];
713 
714 	u8         reserved_at_100[0x4];
715 	u8         f_dscp[0x1];
716 	u8         f_ecn[0x1];
717 	u8         reserved_at_106[0x1];
718 	u8         f_eth_prio[0x1];
719 	u8         ecn[0x2];
720 	u8         dscp[0x6];
721 	u8         udp_sport[0x10];
722 
723 	u8         dei_cfi[0x1];
724 	u8         eth_prio[0x3];
725 	u8         sl[0x4];
726 	u8         vhca_port_num[0x8];
727 	u8         rmac_47_32[0x10];
728 
729 	u8         rmac_31_0[0x20];
730 };
731 
732 struct mlx5_ifc_flow_table_nic_cap_bits {
733 	u8         nic_rx_multi_path_tirs[0x1];
734 	u8         nic_rx_multi_path_tirs_fts[0x1];
735 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
736 	u8	   reserved_at_3[0x4];
737 	u8	   sw_owner_reformat_supported[0x1];
738 	u8	   reserved_at_8[0x18];
739 
740 	u8	   encap_general_header[0x1];
741 	u8	   reserved_at_21[0xa];
742 	u8	   log_max_packet_reformat_context[0x5];
743 	u8	   reserved_at_30[0x6];
744 	u8	   max_encap_header_size[0xa];
745 	u8	   reserved_at_40[0x1c0];
746 
747 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
748 
749 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
750 
751 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
752 
753 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
754 
755 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
756 
757 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
758 
759 	u8         reserved_at_e00[0x1200];
760 
761 	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
762 
763 	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
764 
765 	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
766 
767 	u8         reserved_at_20c0[0x5f40];
768 };
769 
770 enum {
771 	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
772 	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
773 	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
774 	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
775 	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
776 	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
777 	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
778 	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
779 };
780 
781 struct mlx5_ifc_flow_table_eswitch_cap_bits {
782 	u8      fdb_to_vport_reg_c_id[0x8];
783 	u8      reserved_at_8[0xd];
784 	u8      fdb_modify_header_fwd_to_table[0x1];
785 	u8      reserved_at_16[0x1];
786 	u8      flow_source[0x1];
787 	u8      reserved_at_18[0x2];
788 	u8      multi_fdb_encap[0x1];
789 	u8      egress_acl_forward_to_vport[0x1];
790 	u8      fdb_multi_path_to_table[0x1];
791 	u8      reserved_at_1d[0x3];
792 
793 	u8      reserved_at_20[0x1e0];
794 
795 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
796 
797 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
798 
799 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
800 
801 	u8      reserved_at_800[0x1000];
802 
803 	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
804 
805 	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
806 
807 	u8      sw_steering_uplink_icm_address_rx[0x40];
808 
809 	u8      sw_steering_uplink_icm_address_tx[0x40];
810 
811 	u8      reserved_at_1900[0x6700];
812 };
813 
814 enum {
815 	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
816 	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
817 };
818 
819 struct mlx5_ifc_e_switch_cap_bits {
820 	u8         vport_svlan_strip[0x1];
821 	u8         vport_cvlan_strip[0x1];
822 	u8         vport_svlan_insert[0x1];
823 	u8         vport_cvlan_insert_if_not_exist[0x1];
824 	u8         vport_cvlan_insert_overwrite[0x1];
825 	u8         reserved_at_5[0x1];
826 	u8         vport_cvlan_insert_always[0x1];
827 	u8         esw_shared_ingress_acl[0x1];
828 	u8         esw_uplink_ingress_acl[0x1];
829 	u8         root_ft_on_other_esw[0x1];
830 	u8         reserved_at_a[0xf];
831 	u8         esw_functions_changed[0x1];
832 	u8         reserved_at_1a[0x1];
833 	u8         ecpf_vport_exists[0x1];
834 	u8         counter_eswitch_affinity[0x1];
835 	u8         merged_eswitch[0x1];
836 	u8         nic_vport_node_guid_modify[0x1];
837 	u8         nic_vport_port_guid_modify[0x1];
838 
839 	u8         vxlan_encap_decap[0x1];
840 	u8         nvgre_encap_decap[0x1];
841 	u8         reserved_at_22[0x1];
842 	u8         log_max_fdb_encap_uplink[0x5];
843 	u8         reserved_at_21[0x3];
844 	u8         log_max_packet_reformat_context[0x5];
845 	u8         reserved_2b[0x6];
846 	u8         max_encap_header_size[0xa];
847 
848 	u8         reserved_at_40[0xb];
849 	u8         log_max_esw_sf[0x5];
850 	u8         esw_sf_base_id[0x10];
851 
852 	u8         reserved_at_60[0x7a0];
853 
854 };
855 
856 struct mlx5_ifc_qos_cap_bits {
857 	u8         packet_pacing[0x1];
858 	u8         esw_scheduling[0x1];
859 	u8         esw_bw_share[0x1];
860 	u8         esw_rate_limit[0x1];
861 	u8         reserved_at_4[0x1];
862 	u8         packet_pacing_burst_bound[0x1];
863 	u8         packet_pacing_typical_size[0x1];
864 	u8         reserved_at_7[0x1];
865 	u8         nic_sq_scheduling[0x1];
866 	u8         nic_bw_share[0x1];
867 	u8         nic_rate_limit[0x1];
868 	u8         packet_pacing_uid[0x1];
869 	u8         log_esw_max_sched_depth[0x4];
870 	u8         reserved_at_10[0x10];
871 
872 	u8         reserved_at_20[0xb];
873 	u8         log_max_qos_nic_queue_group[0x5];
874 	u8         reserved_at_30[0x10];
875 
876 	u8         packet_pacing_max_rate[0x20];
877 
878 	u8         packet_pacing_min_rate[0x20];
879 
880 	u8         reserved_at_80[0x10];
881 	u8         packet_pacing_rate_table_size[0x10];
882 
883 	u8         esw_element_type[0x10];
884 	u8         esw_tsar_type[0x10];
885 
886 	u8         reserved_at_c0[0x10];
887 	u8         max_qos_para_vport[0x10];
888 
889 	u8         max_tsar_bw_share[0x20];
890 
891 	u8         reserved_at_100[0x700];
892 };
893 
894 struct mlx5_ifc_debug_cap_bits {
895 	u8         core_dump_general[0x1];
896 	u8         core_dump_qp[0x1];
897 	u8         reserved_at_2[0x7];
898 	u8         resource_dump[0x1];
899 	u8         reserved_at_a[0x16];
900 
901 	u8         reserved_at_20[0x2];
902 	u8         stall_detect[0x1];
903 	u8         reserved_at_23[0x1d];
904 
905 	u8         reserved_at_40[0x7c0];
906 };
907 
908 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
909 	u8         csum_cap[0x1];
910 	u8         vlan_cap[0x1];
911 	u8         lro_cap[0x1];
912 	u8         lro_psh_flag[0x1];
913 	u8         lro_time_stamp[0x1];
914 	u8         reserved_at_5[0x2];
915 	u8         wqe_vlan_insert[0x1];
916 	u8         self_lb_en_modifiable[0x1];
917 	u8         reserved_at_9[0x2];
918 	u8         max_lso_cap[0x5];
919 	u8         multi_pkt_send_wqe[0x2];
920 	u8	   wqe_inline_mode[0x2];
921 	u8         rss_ind_tbl_cap[0x4];
922 	u8         reg_umr_sq[0x1];
923 	u8         scatter_fcs[0x1];
924 	u8         enhanced_multi_pkt_send_wqe[0x1];
925 	u8         tunnel_lso_const_out_ip_id[0x1];
926 	u8         tunnel_lro_gre[0x1];
927 	u8         tunnel_lro_vxlan[0x1];
928 	u8         tunnel_stateless_gre[0x1];
929 	u8         tunnel_stateless_vxlan[0x1];
930 
931 	u8         swp[0x1];
932 	u8         swp_csum[0x1];
933 	u8         swp_lso[0x1];
934 	u8         cqe_checksum_full[0x1];
935 	u8         tunnel_stateless_geneve_tx[0x1];
936 	u8         tunnel_stateless_mpls_over_udp[0x1];
937 	u8         tunnel_stateless_mpls_over_gre[0x1];
938 	u8         tunnel_stateless_vxlan_gpe[0x1];
939 	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
940 	u8         tunnel_stateless_ip_over_ip[0x1];
941 	u8         insert_trailer[0x1];
942 	u8         reserved_at_2b[0x1];
943 	u8         tunnel_stateless_ip_over_ip_rx[0x1];
944 	u8         tunnel_stateless_ip_over_ip_tx[0x1];
945 	u8         reserved_at_2e[0x2];
946 	u8         max_vxlan_udp_ports[0x8];
947 	u8         reserved_at_38[0x6];
948 	u8         max_geneve_opt_len[0x1];
949 	u8         tunnel_stateless_geneve_rx[0x1];
950 
951 	u8         reserved_at_40[0x10];
952 	u8         lro_min_mss_size[0x10];
953 
954 	u8         reserved_at_60[0x120];
955 
956 	u8         lro_timer_supported_periods[4][0x20];
957 
958 	u8         reserved_at_200[0x600];
959 };
960 
961 enum {
962 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
963 	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
964 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
965 };
966 
967 struct mlx5_ifc_roce_cap_bits {
968 	u8         roce_apm[0x1];
969 	u8         reserved_at_1[0x3];
970 	u8         sw_r_roce_src_udp_port[0x1];
971 	u8         fl_rc_qp_when_roce_disabled[0x1];
972 	u8         fl_rc_qp_when_roce_enabled[0x1];
973 	u8         reserved_at_7[0x17];
974 	u8	   qp_ts_format[0x2];
975 
976 	u8         reserved_at_20[0x60];
977 
978 	u8         reserved_at_80[0xc];
979 	u8         l3_type[0x4];
980 	u8         reserved_at_90[0x8];
981 	u8         roce_version[0x8];
982 
983 	u8         reserved_at_a0[0x10];
984 	u8         r_roce_dest_udp_port[0x10];
985 
986 	u8         r_roce_max_src_udp_port[0x10];
987 	u8         r_roce_min_src_udp_port[0x10];
988 
989 	u8         reserved_at_e0[0x10];
990 	u8         roce_address_table_size[0x10];
991 
992 	u8         reserved_at_100[0x700];
993 };
994 
995 struct mlx5_ifc_sync_steering_in_bits {
996 	u8         opcode[0x10];
997 	u8         uid[0x10];
998 
999 	u8         reserved_at_20[0x10];
1000 	u8         op_mod[0x10];
1001 
1002 	u8         reserved_at_40[0xc0];
1003 };
1004 
1005 struct mlx5_ifc_sync_steering_out_bits {
1006 	u8         status[0x8];
1007 	u8         reserved_at_8[0x18];
1008 
1009 	u8         syndrome[0x20];
1010 
1011 	u8         reserved_at_40[0x40];
1012 };
1013 
1014 struct mlx5_ifc_device_mem_cap_bits {
1015 	u8         memic[0x1];
1016 	u8         reserved_at_1[0x1f];
1017 
1018 	u8         reserved_at_20[0xb];
1019 	u8         log_min_memic_alloc_size[0x5];
1020 	u8         reserved_at_30[0x8];
1021 	u8	   log_max_memic_addr_alignment[0x8];
1022 
1023 	u8         memic_bar_start_addr[0x40];
1024 
1025 	u8         memic_bar_size[0x20];
1026 
1027 	u8         max_memic_size[0x20];
1028 
1029 	u8         steering_sw_icm_start_address[0x40];
1030 
1031 	u8         reserved_at_100[0x8];
1032 	u8         log_header_modify_sw_icm_size[0x8];
1033 	u8         reserved_at_110[0x2];
1034 	u8         log_sw_icm_alloc_granularity[0x6];
1035 	u8         log_steering_sw_icm_size[0x8];
1036 
1037 	u8         reserved_at_120[0x20];
1038 
1039 	u8         header_modify_sw_icm_start_address[0x40];
1040 
1041 	u8         reserved_at_180[0x80];
1042 
1043 	u8         memic_operations[0x20];
1044 
1045 	u8         reserved_at_220[0x5e0];
1046 };
1047 
1048 struct mlx5_ifc_device_event_cap_bits {
1049 	u8         user_affiliated_events[4][0x40];
1050 
1051 	u8         user_unaffiliated_events[4][0x40];
1052 };
1053 
1054 struct mlx5_ifc_virtio_emulation_cap_bits {
1055 	u8         desc_tunnel_offload_type[0x1];
1056 	u8         eth_frame_offload_type[0x1];
1057 	u8         virtio_version_1_0[0x1];
1058 	u8         device_features_bits_mask[0xd];
1059 	u8         event_mode[0x8];
1060 	u8         virtio_queue_type[0x8];
1061 
1062 	u8         max_tunnel_desc[0x10];
1063 	u8         reserved_at_30[0x3];
1064 	u8         log_doorbell_stride[0x5];
1065 	u8         reserved_at_38[0x3];
1066 	u8         log_doorbell_bar_size[0x5];
1067 
1068 	u8         doorbell_bar_offset[0x40];
1069 
1070 	u8         max_emulated_devices[0x8];
1071 	u8         max_num_virtio_queues[0x18];
1072 
1073 	u8         reserved_at_a0[0x60];
1074 
1075 	u8         umem_1_buffer_param_a[0x20];
1076 
1077 	u8         umem_1_buffer_param_b[0x20];
1078 
1079 	u8         umem_2_buffer_param_a[0x20];
1080 
1081 	u8         umem_2_buffer_param_b[0x20];
1082 
1083 	u8         umem_3_buffer_param_a[0x20];
1084 
1085 	u8         umem_3_buffer_param_b[0x20];
1086 
1087 	u8         reserved_at_1c0[0x640];
1088 };
1089 
1090 enum {
1091 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1092 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1093 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1094 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1095 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1096 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1097 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1098 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1099 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1100 };
1101 
1102 enum {
1103 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1104 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1105 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1106 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1107 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1108 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1109 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1110 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1111 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1112 };
1113 
1114 struct mlx5_ifc_atomic_caps_bits {
1115 	u8         reserved_at_0[0x40];
1116 
1117 	u8         atomic_req_8B_endianness_mode[0x2];
1118 	u8         reserved_at_42[0x4];
1119 	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1120 
1121 	u8         reserved_at_47[0x19];
1122 
1123 	u8         reserved_at_60[0x20];
1124 
1125 	u8         reserved_at_80[0x10];
1126 	u8         atomic_operations[0x10];
1127 
1128 	u8         reserved_at_a0[0x10];
1129 	u8         atomic_size_qp[0x10];
1130 
1131 	u8         reserved_at_c0[0x10];
1132 	u8         atomic_size_dc[0x10];
1133 
1134 	u8         reserved_at_e0[0x720];
1135 };
1136 
1137 struct mlx5_ifc_odp_cap_bits {
1138 	u8         reserved_at_0[0x40];
1139 
1140 	u8         sig[0x1];
1141 	u8         reserved_at_41[0x1f];
1142 
1143 	u8         reserved_at_60[0x20];
1144 
1145 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1146 
1147 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1148 
1149 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1150 
1151 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1152 
1153 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1154 
1155 	u8         reserved_at_120[0x6E0];
1156 };
1157 
1158 struct mlx5_ifc_calc_op {
1159 	u8        reserved_at_0[0x10];
1160 	u8        reserved_at_10[0x9];
1161 	u8        op_swap_endianness[0x1];
1162 	u8        op_min[0x1];
1163 	u8        op_xor[0x1];
1164 	u8        op_or[0x1];
1165 	u8        op_and[0x1];
1166 	u8        op_max[0x1];
1167 	u8        op_add[0x1];
1168 };
1169 
1170 struct mlx5_ifc_vector_calc_cap_bits {
1171 	u8         calc_matrix[0x1];
1172 	u8         reserved_at_1[0x1f];
1173 	u8         reserved_at_20[0x8];
1174 	u8         max_vec_count[0x8];
1175 	u8         reserved_at_30[0xd];
1176 	u8         max_chunk_size[0x3];
1177 	struct mlx5_ifc_calc_op calc0;
1178 	struct mlx5_ifc_calc_op calc1;
1179 	struct mlx5_ifc_calc_op calc2;
1180 	struct mlx5_ifc_calc_op calc3;
1181 
1182 	u8         reserved_at_c0[0x720];
1183 };
1184 
1185 struct mlx5_ifc_tls_cap_bits {
1186 	u8         tls_1_2_aes_gcm_128[0x1];
1187 	u8         tls_1_3_aes_gcm_128[0x1];
1188 	u8         tls_1_2_aes_gcm_256[0x1];
1189 	u8         tls_1_3_aes_gcm_256[0x1];
1190 	u8         reserved_at_4[0x1c];
1191 
1192 	u8         reserved_at_20[0x7e0];
1193 };
1194 
1195 struct mlx5_ifc_ipsec_cap_bits {
1196 	u8         ipsec_full_offload[0x1];
1197 	u8         ipsec_crypto_offload[0x1];
1198 	u8         ipsec_esn[0x1];
1199 	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1200 	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1201 	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1202 	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1203 	u8         reserved_at_7[0x4];
1204 	u8         log_max_ipsec_offload[0x5];
1205 	u8         reserved_at_10[0x10];
1206 
1207 	u8         min_log_ipsec_full_replay_window[0x8];
1208 	u8         max_log_ipsec_full_replay_window[0x8];
1209 	u8         reserved_at_30[0x7d0];
1210 };
1211 
1212 enum {
1213 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1214 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1215 	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1216 	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1217 };
1218 
1219 enum {
1220 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1221 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1222 };
1223 
1224 enum {
1225 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1226 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1227 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1228 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1229 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1230 };
1231 
1232 enum {
1233 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1234 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1235 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1236 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1237 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1238 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1239 };
1240 
1241 enum {
1242 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1243 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1244 };
1245 
1246 enum {
1247 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1248 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1249 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1250 };
1251 
1252 enum {
1253 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1254 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1255 };
1256 
1257 enum {
1258 	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1259 	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1260 	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1261 };
1262 
1263 enum {
1264 	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1265 	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1266 	mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1267 	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1268 	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1269 	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1270 	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1271 	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1272 	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1273 	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1274 	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1275 	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1276 };
1277 
1278 enum {
1279 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1280 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1281 };
1282 
1283 #define MLX5_FC_BULK_SIZE_FACTOR 128
1284 
1285 enum mlx5_fc_bulk_alloc_bitmask {
1286 	MLX5_FC_BULK_128   = (1 << 0),
1287 	MLX5_FC_BULK_256   = (1 << 1),
1288 	MLX5_FC_BULK_512   = (1 << 2),
1289 	MLX5_FC_BULK_1024  = (1 << 3),
1290 	MLX5_FC_BULK_2048  = (1 << 4),
1291 	MLX5_FC_BULK_4096  = (1 << 5),
1292 	MLX5_FC_BULK_8192  = (1 << 6),
1293 	MLX5_FC_BULK_16384 = (1 << 7),
1294 };
1295 
1296 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1297 
1298 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1299 
1300 enum {
1301 	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1302 	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1303 };
1304 
1305 struct mlx5_ifc_cmd_hca_cap_bits {
1306 	u8         reserved_at_0[0x1f];
1307 	u8         vhca_resource_manager[0x1];
1308 
1309 	u8         hca_cap_2[0x1];
1310 	u8         reserved_at_21[0x2];
1311 	u8         event_on_vhca_state_teardown_request[0x1];
1312 	u8         event_on_vhca_state_in_use[0x1];
1313 	u8         event_on_vhca_state_active[0x1];
1314 	u8         event_on_vhca_state_allocated[0x1];
1315 	u8         event_on_vhca_state_invalid[0x1];
1316 	u8         reserved_at_28[0x8];
1317 	u8         vhca_id[0x10];
1318 
1319 	u8         reserved_at_40[0x40];
1320 
1321 	u8         log_max_srq_sz[0x8];
1322 	u8         log_max_qp_sz[0x8];
1323 	u8         event_cap[0x1];
1324 	u8         reserved_at_91[0x2];
1325 	u8         isolate_vl_tc_new[0x1];
1326 	u8         reserved_at_94[0x4];
1327 	u8         prio_tag_required[0x1];
1328 	u8         reserved_at_99[0x2];
1329 	u8         log_max_qp[0x5];
1330 
1331 	u8         reserved_at_a0[0x3];
1332 	u8	   ece_support[0x1];
1333 	u8	   reserved_at_a4[0x5];
1334 	u8         reg_c_preserve[0x1];
1335 	u8         reserved_at_aa[0x1];
1336 	u8         log_max_srq[0x5];
1337 	u8         reserved_at_b0[0x1];
1338 	u8         uplink_follow[0x1];
1339 	u8         ts_cqe_to_dest_cqn[0x1];
1340 	u8         reserved_at_b3[0xd];
1341 
1342 	u8         max_sgl_for_optimized_performance[0x8];
1343 	u8         log_max_cq_sz[0x8];
1344 	u8         relaxed_ordering_write_umr[0x1];
1345 	u8         relaxed_ordering_read_umr[0x1];
1346 	u8         reserved_at_d2[0x7];
1347 	u8         virtio_net_device_emualtion_manager[0x1];
1348 	u8         virtio_blk_device_emualtion_manager[0x1];
1349 	u8         log_max_cq[0x5];
1350 
1351 	u8         log_max_eq_sz[0x8];
1352 	u8         relaxed_ordering_write[0x1];
1353 	u8         relaxed_ordering_read[0x1];
1354 	u8         log_max_mkey[0x6];
1355 	u8         reserved_at_f0[0x8];
1356 	u8         dump_fill_mkey[0x1];
1357 	u8         reserved_at_f9[0x2];
1358 	u8         fast_teardown[0x1];
1359 	u8         log_max_eq[0x4];
1360 
1361 	u8         max_indirection[0x8];
1362 	u8         fixed_buffer_size[0x1];
1363 	u8         log_max_mrw_sz[0x7];
1364 	u8         force_teardown[0x1];
1365 	u8         reserved_at_111[0x1];
1366 	u8         log_max_bsf_list_size[0x6];
1367 	u8         umr_extended_translation_offset[0x1];
1368 	u8         null_mkey[0x1];
1369 	u8         log_max_klm_list_size[0x6];
1370 
1371 	u8         reserved_at_120[0xa];
1372 	u8         log_max_ra_req_dc[0x6];
1373 	u8         reserved_at_130[0xa];
1374 	u8         log_max_ra_res_dc[0x6];
1375 
1376 	u8         reserved_at_140[0x6];
1377 	u8         release_all_pages[0x1];
1378 	u8         reserved_at_147[0x2];
1379 	u8         roce_accl[0x1];
1380 	u8         log_max_ra_req_qp[0x6];
1381 	u8         reserved_at_150[0xa];
1382 	u8         log_max_ra_res_qp[0x6];
1383 
1384 	u8         end_pad[0x1];
1385 	u8         cc_query_allowed[0x1];
1386 	u8         cc_modify_allowed[0x1];
1387 	u8         start_pad[0x1];
1388 	u8         cache_line_128byte[0x1];
1389 	u8         reserved_at_165[0x4];
1390 	u8         rts2rts_qp_counters_set_id[0x1];
1391 	u8         reserved_at_16a[0x2];
1392 	u8         vnic_env_int_rq_oob[0x1];
1393 	u8         sbcam_reg[0x1];
1394 	u8         reserved_at_16e[0x1];
1395 	u8         qcam_reg[0x1];
1396 	u8         gid_table_size[0x10];
1397 
1398 	u8         out_of_seq_cnt[0x1];
1399 	u8         vport_counters[0x1];
1400 	u8         retransmission_q_counters[0x1];
1401 	u8         debug[0x1];
1402 	u8         modify_rq_counter_set_id[0x1];
1403 	u8         rq_delay_drop[0x1];
1404 	u8         max_qp_cnt[0xa];
1405 	u8         pkey_table_size[0x10];
1406 
1407 	u8         vport_group_manager[0x1];
1408 	u8         vhca_group_manager[0x1];
1409 	u8         ib_virt[0x1];
1410 	u8         eth_virt[0x1];
1411 	u8         vnic_env_queue_counters[0x1];
1412 	u8         ets[0x1];
1413 	u8         nic_flow_table[0x1];
1414 	u8         eswitch_manager[0x1];
1415 	u8         device_memory[0x1];
1416 	u8         mcam_reg[0x1];
1417 	u8         pcam_reg[0x1];
1418 	u8         local_ca_ack_delay[0x5];
1419 	u8         port_module_event[0x1];
1420 	u8         enhanced_error_q_counters[0x1];
1421 	u8         ports_check[0x1];
1422 	u8         reserved_at_1b3[0x1];
1423 	u8         disable_link_up[0x1];
1424 	u8         beacon_led[0x1];
1425 	u8         port_type[0x2];
1426 	u8         num_ports[0x8];
1427 
1428 	u8         reserved_at_1c0[0x1];
1429 	u8         pps[0x1];
1430 	u8         pps_modify[0x1];
1431 	u8         log_max_msg[0x5];
1432 	u8         reserved_at_1c8[0x4];
1433 	u8         max_tc[0x4];
1434 	u8         temp_warn_event[0x1];
1435 	u8         dcbx[0x1];
1436 	u8         general_notification_event[0x1];
1437 	u8         reserved_at_1d3[0x2];
1438 	u8         fpga[0x1];
1439 	u8         rol_s[0x1];
1440 	u8         rol_g[0x1];
1441 	u8         reserved_at_1d8[0x1];
1442 	u8         wol_s[0x1];
1443 	u8         wol_g[0x1];
1444 	u8         wol_a[0x1];
1445 	u8         wol_b[0x1];
1446 	u8         wol_m[0x1];
1447 	u8         wol_u[0x1];
1448 	u8         wol_p[0x1];
1449 
1450 	u8         stat_rate_support[0x10];
1451 	u8         reserved_at_1f0[0x1];
1452 	u8         pci_sync_for_fw_update_event[0x1];
1453 	u8         reserved_at_1f2[0x6];
1454 	u8         init2_lag_tx_port_affinity[0x1];
1455 	u8         reserved_at_1fa[0x3];
1456 	u8         cqe_version[0x4];
1457 
1458 	u8         compact_address_vector[0x1];
1459 	u8         striding_rq[0x1];
1460 	u8         reserved_at_202[0x1];
1461 	u8         ipoib_enhanced_offloads[0x1];
1462 	u8         ipoib_basic_offloads[0x1];
1463 	u8         reserved_at_205[0x1];
1464 	u8         repeated_block_disabled[0x1];
1465 	u8         umr_modify_entity_size_disabled[0x1];
1466 	u8         umr_modify_atomic_disabled[0x1];
1467 	u8         umr_indirect_mkey_disabled[0x1];
1468 	u8         umr_fence[0x2];
1469 	u8         dc_req_scat_data_cqe[0x1];
1470 	u8         reserved_at_20d[0x2];
1471 	u8         drain_sigerr[0x1];
1472 	u8         cmdif_checksum[0x2];
1473 	u8         sigerr_cqe[0x1];
1474 	u8         reserved_at_213[0x1];
1475 	u8         wq_signature[0x1];
1476 	u8         sctr_data_cqe[0x1];
1477 	u8         reserved_at_216[0x1];
1478 	u8         sho[0x1];
1479 	u8         tph[0x1];
1480 	u8         rf[0x1];
1481 	u8         dct[0x1];
1482 	u8         qos[0x1];
1483 	u8         eth_net_offloads[0x1];
1484 	u8         roce[0x1];
1485 	u8         atomic[0x1];
1486 	u8         reserved_at_21f[0x1];
1487 
1488 	u8         cq_oi[0x1];
1489 	u8         cq_resize[0x1];
1490 	u8         cq_moderation[0x1];
1491 	u8         reserved_at_223[0x3];
1492 	u8         cq_eq_remap[0x1];
1493 	u8         pg[0x1];
1494 	u8         block_lb_mc[0x1];
1495 	u8         reserved_at_229[0x1];
1496 	u8         scqe_break_moderation[0x1];
1497 	u8         cq_period_start_from_cqe[0x1];
1498 	u8         cd[0x1];
1499 	u8         reserved_at_22d[0x1];
1500 	u8         apm[0x1];
1501 	u8         vector_calc[0x1];
1502 	u8         umr_ptr_rlky[0x1];
1503 	u8	   imaicl[0x1];
1504 	u8	   qp_packet_based[0x1];
1505 	u8         reserved_at_233[0x3];
1506 	u8         qkv[0x1];
1507 	u8         pkv[0x1];
1508 	u8         set_deth_sqpn[0x1];
1509 	u8         reserved_at_239[0x3];
1510 	u8         xrc[0x1];
1511 	u8         ud[0x1];
1512 	u8         uc[0x1];
1513 	u8         rc[0x1];
1514 
1515 	u8         uar_4k[0x1];
1516 	u8         reserved_at_241[0x7];
1517 	u8         fl_rc_qp_when_roce_disabled[0x1];
1518 	u8         regexp_params[0x1];
1519 	u8         uar_sz[0x6];
1520 	u8         reserved_at_248[0x2];
1521 	u8         umem_uid_0[0x1];
1522 	u8         reserved_at_250[0x5];
1523 	u8         log_pg_sz[0x8];
1524 
1525 	u8         bf[0x1];
1526 	u8         driver_version[0x1];
1527 	u8         pad_tx_eth_packet[0x1];
1528 	u8         reserved_at_263[0x3];
1529 	u8         mkey_by_name[0x1];
1530 	u8         reserved_at_267[0x4];
1531 
1532 	u8         log_bf_reg_size[0x5];
1533 
1534 	u8         reserved_at_270[0x6];
1535 	u8         lag_dct[0x2];
1536 	u8         lag_tx_port_affinity[0x1];
1537 	u8         lag_native_fdb_selection[0x1];
1538 	u8         reserved_at_27a[0x1];
1539 	u8         lag_master[0x1];
1540 	u8         num_lag_ports[0x4];
1541 
1542 	u8         reserved_at_280[0x10];
1543 	u8         max_wqe_sz_sq[0x10];
1544 
1545 	u8         reserved_at_2a0[0x10];
1546 	u8         max_wqe_sz_rq[0x10];
1547 
1548 	u8         max_flow_counter_31_16[0x10];
1549 	u8         max_wqe_sz_sq_dc[0x10];
1550 
1551 	u8         reserved_at_2e0[0x7];
1552 	u8         max_qp_mcg[0x19];
1553 
1554 	u8         reserved_at_300[0x10];
1555 	u8         flow_counter_bulk_alloc[0x8];
1556 	u8         log_max_mcg[0x8];
1557 
1558 	u8         reserved_at_320[0x3];
1559 	u8         log_max_transport_domain[0x5];
1560 	u8         reserved_at_328[0x3];
1561 	u8         log_max_pd[0x5];
1562 	u8         reserved_at_330[0xb];
1563 	u8         log_max_xrcd[0x5];
1564 
1565 	u8         nic_receive_steering_discard[0x1];
1566 	u8         receive_discard_vport_down[0x1];
1567 	u8         transmit_discard_vport_down[0x1];
1568 	u8         reserved_at_343[0x5];
1569 	u8         log_max_flow_counter_bulk[0x8];
1570 	u8         max_flow_counter_15_0[0x10];
1571 
1572 
1573 	u8         reserved_at_360[0x3];
1574 	u8         log_max_rq[0x5];
1575 	u8         reserved_at_368[0x3];
1576 	u8         log_max_sq[0x5];
1577 	u8         reserved_at_370[0x3];
1578 	u8         log_max_tir[0x5];
1579 	u8         reserved_at_378[0x3];
1580 	u8         log_max_tis[0x5];
1581 
1582 	u8         basic_cyclic_rcv_wqe[0x1];
1583 	u8         reserved_at_381[0x2];
1584 	u8         log_max_rmp[0x5];
1585 	u8         reserved_at_388[0x3];
1586 	u8         log_max_rqt[0x5];
1587 	u8         reserved_at_390[0x3];
1588 	u8         log_max_rqt_size[0x5];
1589 	u8         reserved_at_398[0x3];
1590 	u8         log_max_tis_per_sq[0x5];
1591 
1592 	u8         ext_stride_num_range[0x1];
1593 	u8         reserved_at_3a1[0x2];
1594 	u8         log_max_stride_sz_rq[0x5];
1595 	u8         reserved_at_3a8[0x3];
1596 	u8         log_min_stride_sz_rq[0x5];
1597 	u8         reserved_at_3b0[0x3];
1598 	u8         log_max_stride_sz_sq[0x5];
1599 	u8         reserved_at_3b8[0x3];
1600 	u8         log_min_stride_sz_sq[0x5];
1601 
1602 	u8         hairpin[0x1];
1603 	u8         reserved_at_3c1[0x2];
1604 	u8         log_max_hairpin_queues[0x5];
1605 	u8         reserved_at_3c8[0x3];
1606 	u8         log_max_hairpin_wq_data_sz[0x5];
1607 	u8         reserved_at_3d0[0x3];
1608 	u8         log_max_hairpin_num_packets[0x5];
1609 	u8         reserved_at_3d8[0x3];
1610 	u8         log_max_wq_sz[0x5];
1611 
1612 	u8         nic_vport_change_event[0x1];
1613 	u8         disable_local_lb_uc[0x1];
1614 	u8         disable_local_lb_mc[0x1];
1615 	u8         log_min_hairpin_wq_data_sz[0x5];
1616 	u8         reserved_at_3e8[0x2];
1617 	u8         vhca_state[0x1];
1618 	u8         log_max_vlan_list[0x5];
1619 	u8         reserved_at_3f0[0x3];
1620 	u8         log_max_current_mc_list[0x5];
1621 	u8         reserved_at_3f8[0x3];
1622 	u8         log_max_current_uc_list[0x5];
1623 
1624 	u8         general_obj_types[0x40];
1625 
1626 	u8         sq_ts_format[0x2];
1627 	u8         rq_ts_format[0x2];
1628 	u8         steering_format_version[0x4];
1629 	u8         create_qp_start_hint[0x18];
1630 
1631 	u8         reserved_at_460[0x3];
1632 	u8         log_max_uctx[0x5];
1633 	u8         reserved_at_468[0x2];
1634 	u8         ipsec_offload[0x1];
1635 	u8         log_max_umem[0x5];
1636 	u8         max_num_eqs[0x10];
1637 
1638 	u8         reserved_at_480[0x1];
1639 	u8         tls_tx[0x1];
1640 	u8         tls_rx[0x1];
1641 	u8         log_max_l2_table[0x5];
1642 	u8         reserved_at_488[0x8];
1643 	u8         log_uar_page_sz[0x10];
1644 
1645 	u8         reserved_at_4a0[0x20];
1646 	u8         device_frequency_mhz[0x20];
1647 	u8         device_frequency_khz[0x20];
1648 
1649 	u8         reserved_at_500[0x20];
1650 	u8	   num_of_uars_per_page[0x20];
1651 
1652 	u8         flex_parser_protocols[0x20];
1653 
1654 	u8         max_geneve_tlv_options[0x8];
1655 	u8         reserved_at_568[0x3];
1656 	u8         max_geneve_tlv_option_data_len[0x5];
1657 	u8         reserved_at_570[0x10];
1658 
1659 	u8	   reserved_at_580[0xb];
1660 	u8	   log_max_dci_stream_channels[0x5];
1661 	u8	   reserved_at_590[0x3];
1662 	u8	   log_max_dci_errored_streams[0x5];
1663 	u8	   reserved_at_598[0x8];
1664 
1665 	u8         reserved_at_5a0[0x13];
1666 	u8         log_max_dek[0x5];
1667 	u8         reserved_at_5b8[0x4];
1668 	u8         mini_cqe_resp_stride_index[0x1];
1669 	u8         cqe_128_always[0x1];
1670 	u8         cqe_compression_128[0x1];
1671 	u8         cqe_compression[0x1];
1672 
1673 	u8         cqe_compression_timeout[0x10];
1674 	u8         cqe_compression_max_num[0x10];
1675 
1676 	u8         reserved_at_5e0[0x8];
1677 	u8         flex_parser_id_gtpu_dw_0[0x4];
1678 	u8         reserved_at_5ec[0x4];
1679 	u8         tag_matching[0x1];
1680 	u8         rndv_offload_rc[0x1];
1681 	u8         rndv_offload_dc[0x1];
1682 	u8         log_tag_matching_list_sz[0x5];
1683 	u8         reserved_at_5f8[0x3];
1684 	u8         log_max_xrq[0x5];
1685 
1686 	u8	   affiliate_nic_vport_criteria[0x8];
1687 	u8	   native_port_num[0x8];
1688 	u8	   num_vhca_ports[0x8];
1689 	u8         flex_parser_id_gtpu_teid[0x4];
1690 	u8         reserved_at_61c[0x2];
1691 	u8	   sw_owner_id[0x1];
1692 	u8         reserved_at_61f[0x1];
1693 
1694 	u8         max_num_of_monitor_counters[0x10];
1695 	u8         num_ppcnt_monitor_counters[0x10];
1696 
1697 	u8         max_num_sf[0x10];
1698 	u8         num_q_monitor_counters[0x10];
1699 
1700 	u8         reserved_at_660[0x20];
1701 
1702 	u8         sf[0x1];
1703 	u8         sf_set_partition[0x1];
1704 	u8         reserved_at_682[0x1];
1705 	u8         log_max_sf[0x5];
1706 	u8         apu[0x1];
1707 	u8         reserved_at_689[0x7];
1708 	u8         log_min_sf_size[0x8];
1709 	u8         max_num_sf_partitions[0x8];
1710 
1711 	u8         uctx_cap[0x20];
1712 
1713 	u8         reserved_at_6c0[0x4];
1714 	u8         flex_parser_id_geneve_tlv_option_0[0x4];
1715 	u8         flex_parser_id_icmp_dw1[0x4];
1716 	u8         flex_parser_id_icmp_dw0[0x4];
1717 	u8         flex_parser_id_icmpv6_dw1[0x4];
1718 	u8         flex_parser_id_icmpv6_dw0[0x4];
1719 	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1720 	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1721 
1722 	u8	   reserved_at_6e0[0x10];
1723 	u8	   sf_base_id[0x10];
1724 
1725 	u8         flex_parser_id_gtpu_dw_2[0x4];
1726 	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1727 	u8	   num_total_dynamic_vf_msix[0x18];
1728 	u8	   reserved_at_720[0x14];
1729 	u8	   dynamic_msix_table_size[0xc];
1730 	u8	   reserved_at_740[0xc];
1731 	u8	   min_dynamic_vf_msix_table_size[0x4];
1732 	u8	   reserved_at_750[0x4];
1733 	u8	   max_dynamic_vf_msix_table_size[0xc];
1734 
1735 	u8	   reserved_at_760[0x20];
1736 	u8	   vhca_tunnel_commands[0x40];
1737 	u8	   reserved_at_7c0[0x40];
1738 };
1739 
1740 struct mlx5_ifc_cmd_hca_cap_2_bits {
1741 	u8	   reserved_at_0[0xa0];
1742 
1743 	u8	   max_reformat_insert_size[0x8];
1744 	u8	   max_reformat_insert_offset[0x8];
1745 	u8	   max_reformat_remove_size[0x8];
1746 	u8	   max_reformat_remove_offset[0x8];
1747 
1748 	u8	   reserved_at_c0[0x740];
1749 };
1750 
1751 enum mlx5_flow_destination_type {
1752 	MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1753 	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1754 	MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1755 	MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1756 
1757 	MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1758 	MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1759 	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1760 };
1761 
1762 enum mlx5_flow_table_miss_action {
1763 	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1764 	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1765 	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1766 };
1767 
1768 struct mlx5_ifc_dest_format_struct_bits {
1769 	u8         destination_type[0x8];
1770 	u8         destination_id[0x18];
1771 
1772 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
1773 	u8         packet_reformat[0x1];
1774 	u8         reserved_at_22[0xe];
1775 	u8         destination_eswitch_owner_vhca_id[0x10];
1776 };
1777 
1778 struct mlx5_ifc_flow_counter_list_bits {
1779 	u8         flow_counter_id[0x20];
1780 
1781 	u8         reserved_at_20[0x20];
1782 };
1783 
1784 struct mlx5_ifc_extended_dest_format_bits {
1785 	struct mlx5_ifc_dest_format_struct_bits destination_entry;
1786 
1787 	u8         packet_reformat_id[0x20];
1788 
1789 	u8         reserved_at_60[0x20];
1790 };
1791 
1792 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1793 	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1794 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1795 };
1796 
1797 struct mlx5_ifc_fte_match_param_bits {
1798 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1799 
1800 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1801 
1802 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1803 
1804 	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1805 
1806 	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1807 
1808 	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1809 
1810 	u8         reserved_at_c00[0x400];
1811 };
1812 
1813 enum {
1814 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1815 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1816 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1817 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1818 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1819 };
1820 
1821 struct mlx5_ifc_rx_hash_field_select_bits {
1822 	u8         l3_prot_type[0x1];
1823 	u8         l4_prot_type[0x1];
1824 	u8         selected_fields[0x1e];
1825 };
1826 
1827 enum {
1828 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1829 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1830 };
1831 
1832 enum {
1833 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1834 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1835 };
1836 
1837 struct mlx5_ifc_wq_bits {
1838 	u8         wq_type[0x4];
1839 	u8         wq_signature[0x1];
1840 	u8         end_padding_mode[0x2];
1841 	u8         cd_slave[0x1];
1842 	u8         reserved_at_8[0x18];
1843 
1844 	u8         hds_skip_first_sge[0x1];
1845 	u8         log2_hds_buf_size[0x3];
1846 	u8         reserved_at_24[0x7];
1847 	u8         page_offset[0x5];
1848 	u8         lwm[0x10];
1849 
1850 	u8         reserved_at_40[0x8];
1851 	u8         pd[0x18];
1852 
1853 	u8         reserved_at_60[0x8];
1854 	u8         uar_page[0x18];
1855 
1856 	u8         dbr_addr[0x40];
1857 
1858 	u8         hw_counter[0x20];
1859 
1860 	u8         sw_counter[0x20];
1861 
1862 	u8         reserved_at_100[0xc];
1863 	u8         log_wq_stride[0x4];
1864 	u8         reserved_at_110[0x3];
1865 	u8         log_wq_pg_sz[0x5];
1866 	u8         reserved_at_118[0x3];
1867 	u8         log_wq_sz[0x5];
1868 
1869 	u8         dbr_umem_valid[0x1];
1870 	u8         wq_umem_valid[0x1];
1871 	u8         reserved_at_122[0x1];
1872 	u8         log_hairpin_num_packets[0x5];
1873 	u8         reserved_at_128[0x3];
1874 	u8         log_hairpin_data_sz[0x5];
1875 
1876 	u8         reserved_at_130[0x4];
1877 	u8         log_wqe_num_of_strides[0x4];
1878 	u8         two_byte_shift_en[0x1];
1879 	u8         reserved_at_139[0x4];
1880 	u8         log_wqe_stride_size[0x3];
1881 
1882 	u8         reserved_at_140[0x4c0];
1883 
1884 	struct mlx5_ifc_cmd_pas_bits pas[];
1885 };
1886 
1887 struct mlx5_ifc_rq_num_bits {
1888 	u8         reserved_at_0[0x8];
1889 	u8         rq_num[0x18];
1890 };
1891 
1892 struct mlx5_ifc_mac_address_layout_bits {
1893 	u8         reserved_at_0[0x10];
1894 	u8         mac_addr_47_32[0x10];
1895 
1896 	u8         mac_addr_31_0[0x20];
1897 };
1898 
1899 struct mlx5_ifc_vlan_layout_bits {
1900 	u8         reserved_at_0[0x14];
1901 	u8         vlan[0x0c];
1902 
1903 	u8         reserved_at_20[0x20];
1904 };
1905 
1906 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1907 	u8         reserved_at_0[0xa0];
1908 
1909 	u8         min_time_between_cnps[0x20];
1910 
1911 	u8         reserved_at_c0[0x12];
1912 	u8         cnp_dscp[0x6];
1913 	u8         reserved_at_d8[0x4];
1914 	u8         cnp_prio_mode[0x1];
1915 	u8         cnp_802p_prio[0x3];
1916 
1917 	u8         reserved_at_e0[0x720];
1918 };
1919 
1920 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1921 	u8         reserved_at_0[0x60];
1922 
1923 	u8         reserved_at_60[0x4];
1924 	u8         clamp_tgt_rate[0x1];
1925 	u8         reserved_at_65[0x3];
1926 	u8         clamp_tgt_rate_after_time_inc[0x1];
1927 	u8         reserved_at_69[0x17];
1928 
1929 	u8         reserved_at_80[0x20];
1930 
1931 	u8         rpg_time_reset[0x20];
1932 
1933 	u8         rpg_byte_reset[0x20];
1934 
1935 	u8         rpg_threshold[0x20];
1936 
1937 	u8         rpg_max_rate[0x20];
1938 
1939 	u8         rpg_ai_rate[0x20];
1940 
1941 	u8         rpg_hai_rate[0x20];
1942 
1943 	u8         rpg_gd[0x20];
1944 
1945 	u8         rpg_min_dec_fac[0x20];
1946 
1947 	u8         rpg_min_rate[0x20];
1948 
1949 	u8         reserved_at_1c0[0xe0];
1950 
1951 	u8         rate_to_set_on_first_cnp[0x20];
1952 
1953 	u8         dce_tcp_g[0x20];
1954 
1955 	u8         dce_tcp_rtt[0x20];
1956 
1957 	u8         rate_reduce_monitor_period[0x20];
1958 
1959 	u8         reserved_at_320[0x20];
1960 
1961 	u8         initial_alpha_value[0x20];
1962 
1963 	u8         reserved_at_360[0x4a0];
1964 };
1965 
1966 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1967 	u8         reserved_at_0[0x80];
1968 
1969 	u8         rppp_max_rps[0x20];
1970 
1971 	u8         rpg_time_reset[0x20];
1972 
1973 	u8         rpg_byte_reset[0x20];
1974 
1975 	u8         rpg_threshold[0x20];
1976 
1977 	u8         rpg_max_rate[0x20];
1978 
1979 	u8         rpg_ai_rate[0x20];
1980 
1981 	u8         rpg_hai_rate[0x20];
1982 
1983 	u8         rpg_gd[0x20];
1984 
1985 	u8         rpg_min_dec_fac[0x20];
1986 
1987 	u8         rpg_min_rate[0x20];
1988 
1989 	u8         reserved_at_1c0[0x640];
1990 };
1991 
1992 enum {
1993 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1994 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1995 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1996 };
1997 
1998 struct mlx5_ifc_resize_field_select_bits {
1999 	u8         resize_field_select[0x20];
2000 };
2001 
2002 struct mlx5_ifc_resource_dump_bits {
2003 	u8         more_dump[0x1];
2004 	u8         inline_dump[0x1];
2005 	u8         reserved_at_2[0xa];
2006 	u8         seq_num[0x4];
2007 	u8         segment_type[0x10];
2008 
2009 	u8         reserved_at_20[0x10];
2010 	u8         vhca_id[0x10];
2011 
2012 	u8         index1[0x20];
2013 
2014 	u8         index2[0x20];
2015 
2016 	u8         num_of_obj1[0x10];
2017 	u8         num_of_obj2[0x10];
2018 
2019 	u8         reserved_at_a0[0x20];
2020 
2021 	u8         device_opaque[0x40];
2022 
2023 	u8         mkey[0x20];
2024 
2025 	u8         size[0x20];
2026 
2027 	u8         address[0x40];
2028 
2029 	u8         inline_data[52][0x20];
2030 };
2031 
2032 struct mlx5_ifc_resource_dump_menu_record_bits {
2033 	u8         reserved_at_0[0x4];
2034 	u8         num_of_obj2_supports_active[0x1];
2035 	u8         num_of_obj2_supports_all[0x1];
2036 	u8         must_have_num_of_obj2[0x1];
2037 	u8         support_num_of_obj2[0x1];
2038 	u8         num_of_obj1_supports_active[0x1];
2039 	u8         num_of_obj1_supports_all[0x1];
2040 	u8         must_have_num_of_obj1[0x1];
2041 	u8         support_num_of_obj1[0x1];
2042 	u8         must_have_index2[0x1];
2043 	u8         support_index2[0x1];
2044 	u8         must_have_index1[0x1];
2045 	u8         support_index1[0x1];
2046 	u8         segment_type[0x10];
2047 
2048 	u8         segment_name[4][0x20];
2049 
2050 	u8         index1_name[4][0x20];
2051 
2052 	u8         index2_name[4][0x20];
2053 };
2054 
2055 struct mlx5_ifc_resource_dump_segment_header_bits {
2056 	u8         length_dw[0x10];
2057 	u8         segment_type[0x10];
2058 };
2059 
2060 struct mlx5_ifc_resource_dump_command_segment_bits {
2061 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2062 
2063 	u8         segment_called[0x10];
2064 	u8         vhca_id[0x10];
2065 
2066 	u8         index1[0x20];
2067 
2068 	u8         index2[0x20];
2069 
2070 	u8         num_of_obj1[0x10];
2071 	u8         num_of_obj2[0x10];
2072 };
2073 
2074 struct mlx5_ifc_resource_dump_error_segment_bits {
2075 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2076 
2077 	u8         reserved_at_20[0x10];
2078 	u8         syndrome_id[0x10];
2079 
2080 	u8         reserved_at_40[0x40];
2081 
2082 	u8         error[8][0x20];
2083 };
2084 
2085 struct mlx5_ifc_resource_dump_info_segment_bits {
2086 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2087 
2088 	u8         reserved_at_20[0x18];
2089 	u8         dump_version[0x8];
2090 
2091 	u8         hw_version[0x20];
2092 
2093 	u8         fw_version[0x20];
2094 };
2095 
2096 struct mlx5_ifc_resource_dump_menu_segment_bits {
2097 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2098 
2099 	u8         reserved_at_20[0x10];
2100 	u8         num_of_records[0x10];
2101 
2102 	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2103 };
2104 
2105 struct mlx5_ifc_resource_dump_resource_segment_bits {
2106 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2107 
2108 	u8         reserved_at_20[0x20];
2109 
2110 	u8         index1[0x20];
2111 
2112 	u8         index2[0x20];
2113 
2114 	u8         payload[][0x20];
2115 };
2116 
2117 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2118 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2119 };
2120 
2121 struct mlx5_ifc_menu_resource_dump_response_bits {
2122 	struct mlx5_ifc_resource_dump_info_segment_bits info;
2123 	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2124 	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2125 	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2126 };
2127 
2128 enum {
2129 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2130 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2131 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2132 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2133 };
2134 
2135 struct mlx5_ifc_modify_field_select_bits {
2136 	u8         modify_field_select[0x20];
2137 };
2138 
2139 struct mlx5_ifc_field_select_r_roce_np_bits {
2140 	u8         field_select_r_roce_np[0x20];
2141 };
2142 
2143 struct mlx5_ifc_field_select_r_roce_rp_bits {
2144 	u8         field_select_r_roce_rp[0x20];
2145 };
2146 
2147 enum {
2148 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2149 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2150 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2151 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2152 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2153 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2154 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2155 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2156 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2157 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2158 };
2159 
2160 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2161 	u8         field_select_8021qaurp[0x20];
2162 };
2163 
2164 struct mlx5_ifc_phys_layer_cntrs_bits {
2165 	u8         time_since_last_clear_high[0x20];
2166 
2167 	u8         time_since_last_clear_low[0x20];
2168 
2169 	u8         symbol_errors_high[0x20];
2170 
2171 	u8         symbol_errors_low[0x20];
2172 
2173 	u8         sync_headers_errors_high[0x20];
2174 
2175 	u8         sync_headers_errors_low[0x20];
2176 
2177 	u8         edpl_bip_errors_lane0_high[0x20];
2178 
2179 	u8         edpl_bip_errors_lane0_low[0x20];
2180 
2181 	u8         edpl_bip_errors_lane1_high[0x20];
2182 
2183 	u8         edpl_bip_errors_lane1_low[0x20];
2184 
2185 	u8         edpl_bip_errors_lane2_high[0x20];
2186 
2187 	u8         edpl_bip_errors_lane2_low[0x20];
2188 
2189 	u8         edpl_bip_errors_lane3_high[0x20];
2190 
2191 	u8         edpl_bip_errors_lane3_low[0x20];
2192 
2193 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2194 
2195 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2196 
2197 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2198 
2199 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2200 
2201 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2202 
2203 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2204 
2205 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2206 
2207 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2208 
2209 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2210 
2211 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2212 
2213 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2214 
2215 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2216 
2217 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2218 
2219 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2220 
2221 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2222 
2223 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2224 
2225 	u8         rs_fec_corrected_blocks_high[0x20];
2226 
2227 	u8         rs_fec_corrected_blocks_low[0x20];
2228 
2229 	u8         rs_fec_uncorrectable_blocks_high[0x20];
2230 
2231 	u8         rs_fec_uncorrectable_blocks_low[0x20];
2232 
2233 	u8         rs_fec_no_errors_blocks_high[0x20];
2234 
2235 	u8         rs_fec_no_errors_blocks_low[0x20];
2236 
2237 	u8         rs_fec_single_error_blocks_high[0x20];
2238 
2239 	u8         rs_fec_single_error_blocks_low[0x20];
2240 
2241 	u8         rs_fec_corrected_symbols_total_high[0x20];
2242 
2243 	u8         rs_fec_corrected_symbols_total_low[0x20];
2244 
2245 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2246 
2247 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2248 
2249 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2250 
2251 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2252 
2253 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2254 
2255 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2256 
2257 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2258 
2259 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2260 
2261 	u8         link_down_events[0x20];
2262 
2263 	u8         successful_recovery_events[0x20];
2264 
2265 	u8         reserved_at_640[0x180];
2266 };
2267 
2268 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2269 	u8         time_since_last_clear_high[0x20];
2270 
2271 	u8         time_since_last_clear_low[0x20];
2272 
2273 	u8         phy_received_bits_high[0x20];
2274 
2275 	u8         phy_received_bits_low[0x20];
2276 
2277 	u8         phy_symbol_errors_high[0x20];
2278 
2279 	u8         phy_symbol_errors_low[0x20];
2280 
2281 	u8         phy_corrected_bits_high[0x20];
2282 
2283 	u8         phy_corrected_bits_low[0x20];
2284 
2285 	u8         phy_corrected_bits_lane0_high[0x20];
2286 
2287 	u8         phy_corrected_bits_lane0_low[0x20];
2288 
2289 	u8         phy_corrected_bits_lane1_high[0x20];
2290 
2291 	u8         phy_corrected_bits_lane1_low[0x20];
2292 
2293 	u8         phy_corrected_bits_lane2_high[0x20];
2294 
2295 	u8         phy_corrected_bits_lane2_low[0x20];
2296 
2297 	u8         phy_corrected_bits_lane3_high[0x20];
2298 
2299 	u8         phy_corrected_bits_lane3_low[0x20];
2300 
2301 	u8         reserved_at_200[0x5c0];
2302 };
2303 
2304 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2305 	u8	   symbol_error_counter[0x10];
2306 
2307 	u8         link_error_recovery_counter[0x8];
2308 
2309 	u8         link_downed_counter[0x8];
2310 
2311 	u8         port_rcv_errors[0x10];
2312 
2313 	u8         port_rcv_remote_physical_errors[0x10];
2314 
2315 	u8         port_rcv_switch_relay_errors[0x10];
2316 
2317 	u8         port_xmit_discards[0x10];
2318 
2319 	u8         port_xmit_constraint_errors[0x8];
2320 
2321 	u8         port_rcv_constraint_errors[0x8];
2322 
2323 	u8         reserved_at_70[0x8];
2324 
2325 	u8         link_overrun_errors[0x8];
2326 
2327 	u8	   reserved_at_80[0x10];
2328 
2329 	u8         vl_15_dropped[0x10];
2330 
2331 	u8	   reserved_at_a0[0x80];
2332 
2333 	u8         port_xmit_wait[0x20];
2334 };
2335 
2336 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2337 	u8         transmit_queue_high[0x20];
2338 
2339 	u8         transmit_queue_low[0x20];
2340 
2341 	u8         no_buffer_discard_uc_high[0x20];
2342 
2343 	u8         no_buffer_discard_uc_low[0x20];
2344 
2345 	u8         reserved_at_80[0x740];
2346 };
2347 
2348 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2349 	u8         wred_discard_high[0x20];
2350 
2351 	u8         wred_discard_low[0x20];
2352 
2353 	u8         ecn_marked_tc_high[0x20];
2354 
2355 	u8         ecn_marked_tc_low[0x20];
2356 
2357 	u8         reserved_at_80[0x740];
2358 };
2359 
2360 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2361 	u8         rx_octets_high[0x20];
2362 
2363 	u8         rx_octets_low[0x20];
2364 
2365 	u8         reserved_at_40[0xc0];
2366 
2367 	u8         rx_frames_high[0x20];
2368 
2369 	u8         rx_frames_low[0x20];
2370 
2371 	u8         tx_octets_high[0x20];
2372 
2373 	u8         tx_octets_low[0x20];
2374 
2375 	u8         reserved_at_180[0xc0];
2376 
2377 	u8         tx_frames_high[0x20];
2378 
2379 	u8         tx_frames_low[0x20];
2380 
2381 	u8         rx_pause_high[0x20];
2382 
2383 	u8         rx_pause_low[0x20];
2384 
2385 	u8         rx_pause_duration_high[0x20];
2386 
2387 	u8         rx_pause_duration_low[0x20];
2388 
2389 	u8         tx_pause_high[0x20];
2390 
2391 	u8         tx_pause_low[0x20];
2392 
2393 	u8         tx_pause_duration_high[0x20];
2394 
2395 	u8         tx_pause_duration_low[0x20];
2396 
2397 	u8         rx_pause_transition_high[0x20];
2398 
2399 	u8         rx_pause_transition_low[0x20];
2400 
2401 	u8         rx_discards_high[0x20];
2402 
2403 	u8         rx_discards_low[0x20];
2404 
2405 	u8         device_stall_minor_watermark_cnt_high[0x20];
2406 
2407 	u8         device_stall_minor_watermark_cnt_low[0x20];
2408 
2409 	u8         device_stall_critical_watermark_cnt_high[0x20];
2410 
2411 	u8         device_stall_critical_watermark_cnt_low[0x20];
2412 
2413 	u8         reserved_at_480[0x340];
2414 };
2415 
2416 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2417 	u8         port_transmit_wait_high[0x20];
2418 
2419 	u8         port_transmit_wait_low[0x20];
2420 
2421 	u8         reserved_at_40[0x100];
2422 
2423 	u8         rx_buffer_almost_full_high[0x20];
2424 
2425 	u8         rx_buffer_almost_full_low[0x20];
2426 
2427 	u8         rx_buffer_full_high[0x20];
2428 
2429 	u8         rx_buffer_full_low[0x20];
2430 
2431 	u8         rx_icrc_encapsulated_high[0x20];
2432 
2433 	u8         rx_icrc_encapsulated_low[0x20];
2434 
2435 	u8         reserved_at_200[0x5c0];
2436 };
2437 
2438 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2439 	u8         dot3stats_alignment_errors_high[0x20];
2440 
2441 	u8         dot3stats_alignment_errors_low[0x20];
2442 
2443 	u8         dot3stats_fcs_errors_high[0x20];
2444 
2445 	u8         dot3stats_fcs_errors_low[0x20];
2446 
2447 	u8         dot3stats_single_collision_frames_high[0x20];
2448 
2449 	u8         dot3stats_single_collision_frames_low[0x20];
2450 
2451 	u8         dot3stats_multiple_collision_frames_high[0x20];
2452 
2453 	u8         dot3stats_multiple_collision_frames_low[0x20];
2454 
2455 	u8         dot3stats_sqe_test_errors_high[0x20];
2456 
2457 	u8         dot3stats_sqe_test_errors_low[0x20];
2458 
2459 	u8         dot3stats_deferred_transmissions_high[0x20];
2460 
2461 	u8         dot3stats_deferred_transmissions_low[0x20];
2462 
2463 	u8         dot3stats_late_collisions_high[0x20];
2464 
2465 	u8         dot3stats_late_collisions_low[0x20];
2466 
2467 	u8         dot3stats_excessive_collisions_high[0x20];
2468 
2469 	u8         dot3stats_excessive_collisions_low[0x20];
2470 
2471 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2472 
2473 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2474 
2475 	u8         dot3stats_carrier_sense_errors_high[0x20];
2476 
2477 	u8         dot3stats_carrier_sense_errors_low[0x20];
2478 
2479 	u8         dot3stats_frame_too_longs_high[0x20];
2480 
2481 	u8         dot3stats_frame_too_longs_low[0x20];
2482 
2483 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
2484 
2485 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
2486 
2487 	u8         dot3stats_symbol_errors_high[0x20];
2488 
2489 	u8         dot3stats_symbol_errors_low[0x20];
2490 
2491 	u8         dot3control_in_unknown_opcodes_high[0x20];
2492 
2493 	u8         dot3control_in_unknown_opcodes_low[0x20];
2494 
2495 	u8         dot3in_pause_frames_high[0x20];
2496 
2497 	u8         dot3in_pause_frames_low[0x20];
2498 
2499 	u8         dot3out_pause_frames_high[0x20];
2500 
2501 	u8         dot3out_pause_frames_low[0x20];
2502 
2503 	u8         reserved_at_400[0x3c0];
2504 };
2505 
2506 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2507 	u8         ether_stats_drop_events_high[0x20];
2508 
2509 	u8         ether_stats_drop_events_low[0x20];
2510 
2511 	u8         ether_stats_octets_high[0x20];
2512 
2513 	u8         ether_stats_octets_low[0x20];
2514 
2515 	u8         ether_stats_pkts_high[0x20];
2516 
2517 	u8         ether_stats_pkts_low[0x20];
2518 
2519 	u8         ether_stats_broadcast_pkts_high[0x20];
2520 
2521 	u8         ether_stats_broadcast_pkts_low[0x20];
2522 
2523 	u8         ether_stats_multicast_pkts_high[0x20];
2524 
2525 	u8         ether_stats_multicast_pkts_low[0x20];
2526 
2527 	u8         ether_stats_crc_align_errors_high[0x20];
2528 
2529 	u8         ether_stats_crc_align_errors_low[0x20];
2530 
2531 	u8         ether_stats_undersize_pkts_high[0x20];
2532 
2533 	u8         ether_stats_undersize_pkts_low[0x20];
2534 
2535 	u8         ether_stats_oversize_pkts_high[0x20];
2536 
2537 	u8         ether_stats_oversize_pkts_low[0x20];
2538 
2539 	u8         ether_stats_fragments_high[0x20];
2540 
2541 	u8         ether_stats_fragments_low[0x20];
2542 
2543 	u8         ether_stats_jabbers_high[0x20];
2544 
2545 	u8         ether_stats_jabbers_low[0x20];
2546 
2547 	u8         ether_stats_collisions_high[0x20];
2548 
2549 	u8         ether_stats_collisions_low[0x20];
2550 
2551 	u8         ether_stats_pkts64octets_high[0x20];
2552 
2553 	u8         ether_stats_pkts64octets_low[0x20];
2554 
2555 	u8         ether_stats_pkts65to127octets_high[0x20];
2556 
2557 	u8         ether_stats_pkts65to127octets_low[0x20];
2558 
2559 	u8         ether_stats_pkts128to255octets_high[0x20];
2560 
2561 	u8         ether_stats_pkts128to255octets_low[0x20];
2562 
2563 	u8         ether_stats_pkts256to511octets_high[0x20];
2564 
2565 	u8         ether_stats_pkts256to511octets_low[0x20];
2566 
2567 	u8         ether_stats_pkts512to1023octets_high[0x20];
2568 
2569 	u8         ether_stats_pkts512to1023octets_low[0x20];
2570 
2571 	u8         ether_stats_pkts1024to1518octets_high[0x20];
2572 
2573 	u8         ether_stats_pkts1024to1518octets_low[0x20];
2574 
2575 	u8         ether_stats_pkts1519to2047octets_high[0x20];
2576 
2577 	u8         ether_stats_pkts1519to2047octets_low[0x20];
2578 
2579 	u8         ether_stats_pkts2048to4095octets_high[0x20];
2580 
2581 	u8         ether_stats_pkts2048to4095octets_low[0x20];
2582 
2583 	u8         ether_stats_pkts4096to8191octets_high[0x20];
2584 
2585 	u8         ether_stats_pkts4096to8191octets_low[0x20];
2586 
2587 	u8         ether_stats_pkts8192to10239octets_high[0x20];
2588 
2589 	u8         ether_stats_pkts8192to10239octets_low[0x20];
2590 
2591 	u8         reserved_at_540[0x280];
2592 };
2593 
2594 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2595 	u8         if_in_octets_high[0x20];
2596 
2597 	u8         if_in_octets_low[0x20];
2598 
2599 	u8         if_in_ucast_pkts_high[0x20];
2600 
2601 	u8         if_in_ucast_pkts_low[0x20];
2602 
2603 	u8         if_in_discards_high[0x20];
2604 
2605 	u8         if_in_discards_low[0x20];
2606 
2607 	u8         if_in_errors_high[0x20];
2608 
2609 	u8         if_in_errors_low[0x20];
2610 
2611 	u8         if_in_unknown_protos_high[0x20];
2612 
2613 	u8         if_in_unknown_protos_low[0x20];
2614 
2615 	u8         if_out_octets_high[0x20];
2616 
2617 	u8         if_out_octets_low[0x20];
2618 
2619 	u8         if_out_ucast_pkts_high[0x20];
2620 
2621 	u8         if_out_ucast_pkts_low[0x20];
2622 
2623 	u8         if_out_discards_high[0x20];
2624 
2625 	u8         if_out_discards_low[0x20];
2626 
2627 	u8         if_out_errors_high[0x20];
2628 
2629 	u8         if_out_errors_low[0x20];
2630 
2631 	u8         if_in_multicast_pkts_high[0x20];
2632 
2633 	u8         if_in_multicast_pkts_low[0x20];
2634 
2635 	u8         if_in_broadcast_pkts_high[0x20];
2636 
2637 	u8         if_in_broadcast_pkts_low[0x20];
2638 
2639 	u8         if_out_multicast_pkts_high[0x20];
2640 
2641 	u8         if_out_multicast_pkts_low[0x20];
2642 
2643 	u8         if_out_broadcast_pkts_high[0x20];
2644 
2645 	u8         if_out_broadcast_pkts_low[0x20];
2646 
2647 	u8         reserved_at_340[0x480];
2648 };
2649 
2650 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2651 	u8         a_frames_transmitted_ok_high[0x20];
2652 
2653 	u8         a_frames_transmitted_ok_low[0x20];
2654 
2655 	u8         a_frames_received_ok_high[0x20];
2656 
2657 	u8         a_frames_received_ok_low[0x20];
2658 
2659 	u8         a_frame_check_sequence_errors_high[0x20];
2660 
2661 	u8         a_frame_check_sequence_errors_low[0x20];
2662 
2663 	u8         a_alignment_errors_high[0x20];
2664 
2665 	u8         a_alignment_errors_low[0x20];
2666 
2667 	u8         a_octets_transmitted_ok_high[0x20];
2668 
2669 	u8         a_octets_transmitted_ok_low[0x20];
2670 
2671 	u8         a_octets_received_ok_high[0x20];
2672 
2673 	u8         a_octets_received_ok_low[0x20];
2674 
2675 	u8         a_multicast_frames_xmitted_ok_high[0x20];
2676 
2677 	u8         a_multicast_frames_xmitted_ok_low[0x20];
2678 
2679 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
2680 
2681 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
2682 
2683 	u8         a_multicast_frames_received_ok_high[0x20];
2684 
2685 	u8         a_multicast_frames_received_ok_low[0x20];
2686 
2687 	u8         a_broadcast_frames_received_ok_high[0x20];
2688 
2689 	u8         a_broadcast_frames_received_ok_low[0x20];
2690 
2691 	u8         a_in_range_length_errors_high[0x20];
2692 
2693 	u8         a_in_range_length_errors_low[0x20];
2694 
2695 	u8         a_out_of_range_length_field_high[0x20];
2696 
2697 	u8         a_out_of_range_length_field_low[0x20];
2698 
2699 	u8         a_frame_too_long_errors_high[0x20];
2700 
2701 	u8         a_frame_too_long_errors_low[0x20];
2702 
2703 	u8         a_symbol_error_during_carrier_high[0x20];
2704 
2705 	u8         a_symbol_error_during_carrier_low[0x20];
2706 
2707 	u8         a_mac_control_frames_transmitted_high[0x20];
2708 
2709 	u8         a_mac_control_frames_transmitted_low[0x20];
2710 
2711 	u8         a_mac_control_frames_received_high[0x20];
2712 
2713 	u8         a_mac_control_frames_received_low[0x20];
2714 
2715 	u8         a_unsupported_opcodes_received_high[0x20];
2716 
2717 	u8         a_unsupported_opcodes_received_low[0x20];
2718 
2719 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
2720 
2721 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
2722 
2723 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2724 
2725 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2726 
2727 	u8         reserved_at_4c0[0x300];
2728 };
2729 
2730 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2731 	u8         life_time_counter_high[0x20];
2732 
2733 	u8         life_time_counter_low[0x20];
2734 
2735 	u8         rx_errors[0x20];
2736 
2737 	u8         tx_errors[0x20];
2738 
2739 	u8         l0_to_recovery_eieos[0x20];
2740 
2741 	u8         l0_to_recovery_ts[0x20];
2742 
2743 	u8         l0_to_recovery_framing[0x20];
2744 
2745 	u8         l0_to_recovery_retrain[0x20];
2746 
2747 	u8         crc_error_dllp[0x20];
2748 
2749 	u8         crc_error_tlp[0x20];
2750 
2751 	u8         tx_overflow_buffer_pkt_high[0x20];
2752 
2753 	u8         tx_overflow_buffer_pkt_low[0x20];
2754 
2755 	u8         outbound_stalled_reads[0x20];
2756 
2757 	u8         outbound_stalled_writes[0x20];
2758 
2759 	u8         outbound_stalled_reads_events[0x20];
2760 
2761 	u8         outbound_stalled_writes_events[0x20];
2762 
2763 	u8         reserved_at_200[0x5c0];
2764 };
2765 
2766 struct mlx5_ifc_cmd_inter_comp_event_bits {
2767 	u8         command_completion_vector[0x20];
2768 
2769 	u8         reserved_at_20[0xc0];
2770 };
2771 
2772 struct mlx5_ifc_stall_vl_event_bits {
2773 	u8         reserved_at_0[0x18];
2774 	u8         port_num[0x1];
2775 	u8         reserved_at_19[0x3];
2776 	u8         vl[0x4];
2777 
2778 	u8         reserved_at_20[0xa0];
2779 };
2780 
2781 struct mlx5_ifc_db_bf_congestion_event_bits {
2782 	u8         event_subtype[0x8];
2783 	u8         reserved_at_8[0x8];
2784 	u8         congestion_level[0x8];
2785 	u8         reserved_at_18[0x8];
2786 
2787 	u8         reserved_at_20[0xa0];
2788 };
2789 
2790 struct mlx5_ifc_gpio_event_bits {
2791 	u8         reserved_at_0[0x60];
2792 
2793 	u8         gpio_event_hi[0x20];
2794 
2795 	u8         gpio_event_lo[0x20];
2796 
2797 	u8         reserved_at_a0[0x40];
2798 };
2799 
2800 struct mlx5_ifc_port_state_change_event_bits {
2801 	u8         reserved_at_0[0x40];
2802 
2803 	u8         port_num[0x4];
2804 	u8         reserved_at_44[0x1c];
2805 
2806 	u8         reserved_at_60[0x80];
2807 };
2808 
2809 struct mlx5_ifc_dropped_packet_logged_bits {
2810 	u8         reserved_at_0[0xe0];
2811 };
2812 
2813 enum {
2814 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2815 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2816 };
2817 
2818 struct mlx5_ifc_cq_error_bits {
2819 	u8         reserved_at_0[0x8];
2820 	u8         cqn[0x18];
2821 
2822 	u8         reserved_at_20[0x20];
2823 
2824 	u8         reserved_at_40[0x18];
2825 	u8         syndrome[0x8];
2826 
2827 	u8         reserved_at_60[0x80];
2828 };
2829 
2830 struct mlx5_ifc_rdma_page_fault_event_bits {
2831 	u8         bytes_committed[0x20];
2832 
2833 	u8         r_key[0x20];
2834 
2835 	u8         reserved_at_40[0x10];
2836 	u8         packet_len[0x10];
2837 
2838 	u8         rdma_op_len[0x20];
2839 
2840 	u8         rdma_va[0x40];
2841 
2842 	u8         reserved_at_c0[0x5];
2843 	u8         rdma[0x1];
2844 	u8         write[0x1];
2845 	u8         requestor[0x1];
2846 	u8         qp_number[0x18];
2847 };
2848 
2849 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2850 	u8         bytes_committed[0x20];
2851 
2852 	u8         reserved_at_20[0x10];
2853 	u8         wqe_index[0x10];
2854 
2855 	u8         reserved_at_40[0x10];
2856 	u8         len[0x10];
2857 
2858 	u8         reserved_at_60[0x60];
2859 
2860 	u8         reserved_at_c0[0x5];
2861 	u8         rdma[0x1];
2862 	u8         write_read[0x1];
2863 	u8         requestor[0x1];
2864 	u8         qpn[0x18];
2865 };
2866 
2867 struct mlx5_ifc_qp_events_bits {
2868 	u8         reserved_at_0[0xa0];
2869 
2870 	u8         type[0x8];
2871 	u8         reserved_at_a8[0x18];
2872 
2873 	u8         reserved_at_c0[0x8];
2874 	u8         qpn_rqn_sqn[0x18];
2875 };
2876 
2877 struct mlx5_ifc_dct_events_bits {
2878 	u8         reserved_at_0[0xc0];
2879 
2880 	u8         reserved_at_c0[0x8];
2881 	u8         dct_number[0x18];
2882 };
2883 
2884 struct mlx5_ifc_comp_event_bits {
2885 	u8         reserved_at_0[0xc0];
2886 
2887 	u8         reserved_at_c0[0x8];
2888 	u8         cq_number[0x18];
2889 };
2890 
2891 enum {
2892 	MLX5_QPC_STATE_RST        = 0x0,
2893 	MLX5_QPC_STATE_INIT       = 0x1,
2894 	MLX5_QPC_STATE_RTR        = 0x2,
2895 	MLX5_QPC_STATE_RTS        = 0x3,
2896 	MLX5_QPC_STATE_SQER       = 0x4,
2897 	MLX5_QPC_STATE_ERR        = 0x6,
2898 	MLX5_QPC_STATE_SQD        = 0x7,
2899 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
2900 };
2901 
2902 enum {
2903 	MLX5_QPC_ST_RC            = 0x0,
2904 	MLX5_QPC_ST_UC            = 0x1,
2905 	MLX5_QPC_ST_UD            = 0x2,
2906 	MLX5_QPC_ST_XRC           = 0x3,
2907 	MLX5_QPC_ST_DCI           = 0x5,
2908 	MLX5_QPC_ST_QP0           = 0x7,
2909 	MLX5_QPC_ST_QP1           = 0x8,
2910 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2911 	MLX5_QPC_ST_REG_UMR       = 0xc,
2912 };
2913 
2914 enum {
2915 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
2916 	MLX5_QPC_PM_STATE_REARM     = 0x1,
2917 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2918 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2919 };
2920 
2921 enum {
2922 	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2923 };
2924 
2925 enum {
2926 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2927 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2928 };
2929 
2930 enum {
2931 	MLX5_QPC_MTU_256_BYTES        = 0x1,
2932 	MLX5_QPC_MTU_512_BYTES        = 0x2,
2933 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
2934 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
2935 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
2936 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2937 };
2938 
2939 enum {
2940 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2941 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2942 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2943 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2944 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2945 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2946 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2947 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2948 };
2949 
2950 enum {
2951 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2952 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2953 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2954 };
2955 
2956 enum {
2957 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
2958 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2959 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2960 };
2961 
2962 enum {
2963 	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2964 	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2965 	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2966 };
2967 
2968 struct mlx5_ifc_qpc_bits {
2969 	u8         state[0x4];
2970 	u8         lag_tx_port_affinity[0x4];
2971 	u8         st[0x8];
2972 	u8         reserved_at_10[0x2];
2973 	u8	   isolate_vl_tc[0x1];
2974 	u8         pm_state[0x2];
2975 	u8         reserved_at_15[0x1];
2976 	u8         req_e2e_credit_mode[0x2];
2977 	u8         offload_type[0x4];
2978 	u8         end_padding_mode[0x2];
2979 	u8         reserved_at_1e[0x2];
2980 
2981 	u8         wq_signature[0x1];
2982 	u8         block_lb_mc[0x1];
2983 	u8         atomic_like_write_en[0x1];
2984 	u8         latency_sensitive[0x1];
2985 	u8         reserved_at_24[0x1];
2986 	u8         drain_sigerr[0x1];
2987 	u8         reserved_at_26[0x2];
2988 	u8         pd[0x18];
2989 
2990 	u8         mtu[0x3];
2991 	u8         log_msg_max[0x5];
2992 	u8         reserved_at_48[0x1];
2993 	u8         log_rq_size[0x4];
2994 	u8         log_rq_stride[0x3];
2995 	u8         no_sq[0x1];
2996 	u8         log_sq_size[0x4];
2997 	u8         reserved_at_55[0x3];
2998 	u8	   ts_format[0x2];
2999 	u8         reserved_at_5a[0x1];
3000 	u8         rlky[0x1];
3001 	u8         ulp_stateless_offload_mode[0x4];
3002 
3003 	u8         counter_set_id[0x8];
3004 	u8         uar_page[0x18];
3005 
3006 	u8         reserved_at_80[0x8];
3007 	u8         user_index[0x18];
3008 
3009 	u8         reserved_at_a0[0x3];
3010 	u8         log_page_size[0x5];
3011 	u8         remote_qpn[0x18];
3012 
3013 	struct mlx5_ifc_ads_bits primary_address_path;
3014 
3015 	struct mlx5_ifc_ads_bits secondary_address_path;
3016 
3017 	u8         log_ack_req_freq[0x4];
3018 	u8         reserved_at_384[0x4];
3019 	u8         log_sra_max[0x3];
3020 	u8         reserved_at_38b[0x2];
3021 	u8         retry_count[0x3];
3022 	u8         rnr_retry[0x3];
3023 	u8         reserved_at_393[0x1];
3024 	u8         fre[0x1];
3025 	u8         cur_rnr_retry[0x3];
3026 	u8         cur_retry_count[0x3];
3027 	u8         reserved_at_39b[0x5];
3028 
3029 	u8         reserved_at_3a0[0x20];
3030 
3031 	u8         reserved_at_3c0[0x8];
3032 	u8         next_send_psn[0x18];
3033 
3034 	u8         reserved_at_3e0[0x3];
3035 	u8	   log_num_dci_stream_channels[0x5];
3036 	u8         cqn_snd[0x18];
3037 
3038 	u8         reserved_at_400[0x3];
3039 	u8	   log_num_dci_errored_streams[0x5];
3040 	u8         deth_sqpn[0x18];
3041 
3042 	u8         reserved_at_420[0x20];
3043 
3044 	u8         reserved_at_440[0x8];
3045 	u8         last_acked_psn[0x18];
3046 
3047 	u8         reserved_at_460[0x8];
3048 	u8         ssn[0x18];
3049 
3050 	u8         reserved_at_480[0x8];
3051 	u8         log_rra_max[0x3];
3052 	u8         reserved_at_48b[0x1];
3053 	u8         atomic_mode[0x4];
3054 	u8         rre[0x1];
3055 	u8         rwe[0x1];
3056 	u8         rae[0x1];
3057 	u8         reserved_at_493[0x1];
3058 	u8         page_offset[0x6];
3059 	u8         reserved_at_49a[0x3];
3060 	u8         cd_slave_receive[0x1];
3061 	u8         cd_slave_send[0x1];
3062 	u8         cd_master[0x1];
3063 
3064 	u8         reserved_at_4a0[0x3];
3065 	u8         min_rnr_nak[0x5];
3066 	u8         next_rcv_psn[0x18];
3067 
3068 	u8         reserved_at_4c0[0x8];
3069 	u8         xrcd[0x18];
3070 
3071 	u8         reserved_at_4e0[0x8];
3072 	u8         cqn_rcv[0x18];
3073 
3074 	u8         dbr_addr[0x40];
3075 
3076 	u8         q_key[0x20];
3077 
3078 	u8         reserved_at_560[0x5];
3079 	u8         rq_type[0x3];
3080 	u8         srqn_rmpn_xrqn[0x18];
3081 
3082 	u8         reserved_at_580[0x8];
3083 	u8         rmsn[0x18];
3084 
3085 	u8         hw_sq_wqebb_counter[0x10];
3086 	u8         sw_sq_wqebb_counter[0x10];
3087 
3088 	u8         hw_rq_counter[0x20];
3089 
3090 	u8         sw_rq_counter[0x20];
3091 
3092 	u8         reserved_at_600[0x20];
3093 
3094 	u8         reserved_at_620[0xf];
3095 	u8         cgs[0x1];
3096 	u8         cs_req[0x8];
3097 	u8         cs_res[0x8];
3098 
3099 	u8         dc_access_key[0x40];
3100 
3101 	u8         reserved_at_680[0x3];
3102 	u8         dbr_umem_valid[0x1];
3103 
3104 	u8         reserved_at_684[0xbc];
3105 };
3106 
3107 struct mlx5_ifc_roce_addr_layout_bits {
3108 	u8         source_l3_address[16][0x8];
3109 
3110 	u8         reserved_at_80[0x3];
3111 	u8         vlan_valid[0x1];
3112 	u8         vlan_id[0xc];
3113 	u8         source_mac_47_32[0x10];
3114 
3115 	u8         source_mac_31_0[0x20];
3116 
3117 	u8         reserved_at_c0[0x14];
3118 	u8         roce_l3_type[0x4];
3119 	u8         roce_version[0x8];
3120 
3121 	u8         reserved_at_e0[0x20];
3122 };
3123 
3124 union mlx5_ifc_hca_cap_union_bits {
3125 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3126 	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3127 	struct mlx5_ifc_odp_cap_bits odp_cap;
3128 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3129 	struct mlx5_ifc_roce_cap_bits roce_cap;
3130 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3131 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3132 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3133 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3134 	struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3135 	struct mlx5_ifc_qos_cap_bits qos_cap;
3136 	struct mlx5_ifc_debug_cap_bits debug_cap;
3137 	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3138 	struct mlx5_ifc_tls_cap_bits tls_cap;
3139 	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3140 	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3141 	u8         reserved_at_0[0x8000];
3142 };
3143 
3144 enum {
3145 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3146 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3147 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3148 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3149 	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3150 	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3151 	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3152 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3153 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3154 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3155 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3156 	MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3157 	MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3158 };
3159 
3160 enum {
3161 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3162 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3163 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3164 };
3165 
3166 struct mlx5_ifc_vlan_bits {
3167 	u8         ethtype[0x10];
3168 	u8         prio[0x3];
3169 	u8         cfi[0x1];
3170 	u8         vid[0xc];
3171 };
3172 
3173 struct mlx5_ifc_flow_context_bits {
3174 	struct mlx5_ifc_vlan_bits push_vlan;
3175 
3176 	u8         group_id[0x20];
3177 
3178 	u8         reserved_at_40[0x8];
3179 	u8         flow_tag[0x18];
3180 
3181 	u8         reserved_at_60[0x10];
3182 	u8         action[0x10];
3183 
3184 	u8         extended_destination[0x1];
3185 	u8         reserved_at_81[0x1];
3186 	u8         flow_source[0x2];
3187 	u8         reserved_at_84[0x4];
3188 	u8         destination_list_size[0x18];
3189 
3190 	u8         reserved_at_a0[0x8];
3191 	u8         flow_counter_list_size[0x18];
3192 
3193 	u8         packet_reformat_id[0x20];
3194 
3195 	u8         modify_header_id[0x20];
3196 
3197 	struct mlx5_ifc_vlan_bits push_vlan_2;
3198 
3199 	u8         ipsec_obj_id[0x20];
3200 	u8         reserved_at_140[0xc0];
3201 
3202 	struct mlx5_ifc_fte_match_param_bits match_value;
3203 
3204 	u8         reserved_at_1200[0x600];
3205 
3206 	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3207 };
3208 
3209 enum {
3210 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3211 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3212 };
3213 
3214 struct mlx5_ifc_xrc_srqc_bits {
3215 	u8         state[0x4];
3216 	u8         log_xrc_srq_size[0x4];
3217 	u8         reserved_at_8[0x18];
3218 
3219 	u8         wq_signature[0x1];
3220 	u8         cont_srq[0x1];
3221 	u8         reserved_at_22[0x1];
3222 	u8         rlky[0x1];
3223 	u8         basic_cyclic_rcv_wqe[0x1];
3224 	u8         log_rq_stride[0x3];
3225 	u8         xrcd[0x18];
3226 
3227 	u8         page_offset[0x6];
3228 	u8         reserved_at_46[0x1];
3229 	u8         dbr_umem_valid[0x1];
3230 	u8         cqn[0x18];
3231 
3232 	u8         reserved_at_60[0x20];
3233 
3234 	u8         user_index_equal_xrc_srqn[0x1];
3235 	u8         reserved_at_81[0x1];
3236 	u8         log_page_size[0x6];
3237 	u8         user_index[0x18];
3238 
3239 	u8         reserved_at_a0[0x20];
3240 
3241 	u8         reserved_at_c0[0x8];
3242 	u8         pd[0x18];
3243 
3244 	u8         lwm[0x10];
3245 	u8         wqe_cnt[0x10];
3246 
3247 	u8         reserved_at_100[0x40];
3248 
3249 	u8         db_record_addr_h[0x20];
3250 
3251 	u8         db_record_addr_l[0x1e];
3252 	u8         reserved_at_17e[0x2];
3253 
3254 	u8         reserved_at_180[0x80];
3255 };
3256 
3257 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3258 	u8         counter_error_queues[0x20];
3259 
3260 	u8         total_error_queues[0x20];
3261 
3262 	u8         send_queue_priority_update_flow[0x20];
3263 
3264 	u8         reserved_at_60[0x20];
3265 
3266 	u8         nic_receive_steering_discard[0x40];
3267 
3268 	u8         receive_discard_vport_down[0x40];
3269 
3270 	u8         transmit_discard_vport_down[0x40];
3271 
3272 	u8         reserved_at_140[0xa0];
3273 
3274 	u8         internal_rq_out_of_buffer[0x20];
3275 
3276 	u8         reserved_at_200[0xe00];
3277 };
3278 
3279 struct mlx5_ifc_traffic_counter_bits {
3280 	u8         packets[0x40];
3281 
3282 	u8         octets[0x40];
3283 };
3284 
3285 struct mlx5_ifc_tisc_bits {
3286 	u8         strict_lag_tx_port_affinity[0x1];
3287 	u8         tls_en[0x1];
3288 	u8         reserved_at_2[0x2];
3289 	u8         lag_tx_port_affinity[0x04];
3290 
3291 	u8         reserved_at_8[0x4];
3292 	u8         prio[0x4];
3293 	u8         reserved_at_10[0x10];
3294 
3295 	u8         reserved_at_20[0x100];
3296 
3297 	u8         reserved_at_120[0x8];
3298 	u8         transport_domain[0x18];
3299 
3300 	u8         reserved_at_140[0x8];
3301 	u8         underlay_qpn[0x18];
3302 
3303 	u8         reserved_at_160[0x8];
3304 	u8         pd[0x18];
3305 
3306 	u8         reserved_at_180[0x380];
3307 };
3308 
3309 enum {
3310 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3311 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3312 };
3313 
3314 enum {
3315 	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3316 	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3317 };
3318 
3319 enum {
3320 	MLX5_RX_HASH_FN_NONE           = 0x0,
3321 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3322 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3323 };
3324 
3325 enum {
3326 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3327 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3328 };
3329 
3330 struct mlx5_ifc_tirc_bits {
3331 	u8         reserved_at_0[0x20];
3332 
3333 	u8         disp_type[0x4];
3334 	u8         tls_en[0x1];
3335 	u8         reserved_at_25[0x1b];
3336 
3337 	u8         reserved_at_40[0x40];
3338 
3339 	u8         reserved_at_80[0x4];
3340 	u8         lro_timeout_period_usecs[0x10];
3341 	u8         packet_merge_mask[0x4];
3342 	u8         lro_max_ip_payload_size[0x8];
3343 
3344 	u8         reserved_at_a0[0x40];
3345 
3346 	u8         reserved_at_e0[0x8];
3347 	u8         inline_rqn[0x18];
3348 
3349 	u8         rx_hash_symmetric[0x1];
3350 	u8         reserved_at_101[0x1];
3351 	u8         tunneled_offload_en[0x1];
3352 	u8         reserved_at_103[0x5];
3353 	u8         indirect_table[0x18];
3354 
3355 	u8         rx_hash_fn[0x4];
3356 	u8         reserved_at_124[0x2];
3357 	u8         self_lb_block[0x2];
3358 	u8         transport_domain[0x18];
3359 
3360 	u8         rx_hash_toeplitz_key[10][0x20];
3361 
3362 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3363 
3364 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3365 
3366 	u8         reserved_at_2c0[0x4c0];
3367 };
3368 
3369 enum {
3370 	MLX5_SRQC_STATE_GOOD   = 0x0,
3371 	MLX5_SRQC_STATE_ERROR  = 0x1,
3372 };
3373 
3374 struct mlx5_ifc_srqc_bits {
3375 	u8         state[0x4];
3376 	u8         log_srq_size[0x4];
3377 	u8         reserved_at_8[0x18];
3378 
3379 	u8         wq_signature[0x1];
3380 	u8         cont_srq[0x1];
3381 	u8         reserved_at_22[0x1];
3382 	u8         rlky[0x1];
3383 	u8         reserved_at_24[0x1];
3384 	u8         log_rq_stride[0x3];
3385 	u8         xrcd[0x18];
3386 
3387 	u8         page_offset[0x6];
3388 	u8         reserved_at_46[0x2];
3389 	u8         cqn[0x18];
3390 
3391 	u8         reserved_at_60[0x20];
3392 
3393 	u8         reserved_at_80[0x2];
3394 	u8         log_page_size[0x6];
3395 	u8         reserved_at_88[0x18];
3396 
3397 	u8         reserved_at_a0[0x20];
3398 
3399 	u8         reserved_at_c0[0x8];
3400 	u8         pd[0x18];
3401 
3402 	u8         lwm[0x10];
3403 	u8         wqe_cnt[0x10];
3404 
3405 	u8         reserved_at_100[0x40];
3406 
3407 	u8         dbr_addr[0x40];
3408 
3409 	u8         reserved_at_180[0x80];
3410 };
3411 
3412 enum {
3413 	MLX5_SQC_STATE_RST  = 0x0,
3414 	MLX5_SQC_STATE_RDY  = 0x1,
3415 	MLX5_SQC_STATE_ERR  = 0x3,
3416 };
3417 
3418 struct mlx5_ifc_sqc_bits {
3419 	u8         rlky[0x1];
3420 	u8         cd_master[0x1];
3421 	u8         fre[0x1];
3422 	u8         flush_in_error_en[0x1];
3423 	u8         allow_multi_pkt_send_wqe[0x1];
3424 	u8	   min_wqe_inline_mode[0x3];
3425 	u8         state[0x4];
3426 	u8         reg_umr[0x1];
3427 	u8         allow_swp[0x1];
3428 	u8         hairpin[0x1];
3429 	u8         reserved_at_f[0xb];
3430 	u8	   ts_format[0x2];
3431 	u8	   reserved_at_1c[0x4];
3432 
3433 	u8         reserved_at_20[0x8];
3434 	u8         user_index[0x18];
3435 
3436 	u8         reserved_at_40[0x8];
3437 	u8         cqn[0x18];
3438 
3439 	u8         reserved_at_60[0x8];
3440 	u8         hairpin_peer_rq[0x18];
3441 
3442 	u8         reserved_at_80[0x10];
3443 	u8         hairpin_peer_vhca[0x10];
3444 
3445 	u8         reserved_at_a0[0x20];
3446 
3447 	u8         reserved_at_c0[0x8];
3448 	u8         ts_cqe_to_dest_cqn[0x18];
3449 
3450 	u8         reserved_at_e0[0x10];
3451 	u8         packet_pacing_rate_limit_index[0x10];
3452 	u8         tis_lst_sz[0x10];
3453 	u8         qos_queue_group_id[0x10];
3454 
3455 	u8         reserved_at_120[0x40];
3456 
3457 	u8         reserved_at_160[0x8];
3458 	u8         tis_num_0[0x18];
3459 
3460 	struct mlx5_ifc_wq_bits wq;
3461 };
3462 
3463 enum {
3464 	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3465 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3466 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3467 	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3468 	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3469 };
3470 
3471 enum {
3472 	ELEMENT_TYPE_CAP_MASK_TASR		= 1 << 0,
3473 	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
3474 	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
3475 	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
3476 };
3477 
3478 struct mlx5_ifc_scheduling_context_bits {
3479 	u8         element_type[0x8];
3480 	u8         reserved_at_8[0x18];
3481 
3482 	u8         element_attributes[0x20];
3483 
3484 	u8         parent_element_id[0x20];
3485 
3486 	u8         reserved_at_60[0x40];
3487 
3488 	u8         bw_share[0x20];
3489 
3490 	u8         max_average_bw[0x20];
3491 
3492 	u8         reserved_at_e0[0x120];
3493 };
3494 
3495 struct mlx5_ifc_rqtc_bits {
3496 	u8    reserved_at_0[0xa0];
3497 
3498 	u8    reserved_at_a0[0x5];
3499 	u8    list_q_type[0x3];
3500 	u8    reserved_at_a8[0x8];
3501 	u8    rqt_max_size[0x10];
3502 
3503 	u8    rq_vhca_id_format[0x1];
3504 	u8    reserved_at_c1[0xf];
3505 	u8    rqt_actual_size[0x10];
3506 
3507 	u8    reserved_at_e0[0x6a0];
3508 
3509 	struct mlx5_ifc_rq_num_bits rq_num[];
3510 };
3511 
3512 enum {
3513 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3514 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3515 };
3516 
3517 enum {
3518 	MLX5_RQC_STATE_RST  = 0x0,
3519 	MLX5_RQC_STATE_RDY  = 0x1,
3520 	MLX5_RQC_STATE_ERR  = 0x3,
3521 };
3522 
3523 struct mlx5_ifc_rqc_bits {
3524 	u8         rlky[0x1];
3525 	u8	   delay_drop_en[0x1];
3526 	u8         scatter_fcs[0x1];
3527 	u8         vsd[0x1];
3528 	u8         mem_rq_type[0x4];
3529 	u8         state[0x4];
3530 	u8         reserved_at_c[0x1];
3531 	u8         flush_in_error_en[0x1];
3532 	u8         hairpin[0x1];
3533 	u8         reserved_at_f[0xb];
3534 	u8	   ts_format[0x2];
3535 	u8	   reserved_at_1c[0x4];
3536 
3537 	u8         reserved_at_20[0x8];
3538 	u8         user_index[0x18];
3539 
3540 	u8         reserved_at_40[0x8];
3541 	u8         cqn[0x18];
3542 
3543 	u8         counter_set_id[0x8];
3544 	u8         reserved_at_68[0x18];
3545 
3546 	u8         reserved_at_80[0x8];
3547 	u8         rmpn[0x18];
3548 
3549 	u8         reserved_at_a0[0x8];
3550 	u8         hairpin_peer_sq[0x18];
3551 
3552 	u8         reserved_at_c0[0x10];
3553 	u8         hairpin_peer_vhca[0x10];
3554 
3555 	u8         reserved_at_e0[0xa0];
3556 
3557 	struct mlx5_ifc_wq_bits wq;
3558 };
3559 
3560 enum {
3561 	MLX5_RMPC_STATE_RDY  = 0x1,
3562 	MLX5_RMPC_STATE_ERR  = 0x3,
3563 };
3564 
3565 struct mlx5_ifc_rmpc_bits {
3566 	u8         reserved_at_0[0x8];
3567 	u8         state[0x4];
3568 	u8         reserved_at_c[0x14];
3569 
3570 	u8         basic_cyclic_rcv_wqe[0x1];
3571 	u8         reserved_at_21[0x1f];
3572 
3573 	u8         reserved_at_40[0x140];
3574 
3575 	struct mlx5_ifc_wq_bits wq;
3576 };
3577 
3578 struct mlx5_ifc_nic_vport_context_bits {
3579 	u8         reserved_at_0[0x5];
3580 	u8         min_wqe_inline_mode[0x3];
3581 	u8         reserved_at_8[0x15];
3582 	u8         disable_mc_local_lb[0x1];
3583 	u8         disable_uc_local_lb[0x1];
3584 	u8         roce_en[0x1];
3585 
3586 	u8         arm_change_event[0x1];
3587 	u8         reserved_at_21[0x1a];
3588 	u8         event_on_mtu[0x1];
3589 	u8         event_on_promisc_change[0x1];
3590 	u8         event_on_vlan_change[0x1];
3591 	u8         event_on_mc_address_change[0x1];
3592 	u8         event_on_uc_address_change[0x1];
3593 
3594 	u8         reserved_at_40[0xc];
3595 
3596 	u8	   affiliation_criteria[0x4];
3597 	u8	   affiliated_vhca_id[0x10];
3598 
3599 	u8	   reserved_at_60[0xd0];
3600 
3601 	u8         mtu[0x10];
3602 
3603 	u8         system_image_guid[0x40];
3604 	u8         port_guid[0x40];
3605 	u8         node_guid[0x40];
3606 
3607 	u8         reserved_at_200[0x140];
3608 	u8         qkey_violation_counter[0x10];
3609 	u8         reserved_at_350[0x430];
3610 
3611 	u8         promisc_uc[0x1];
3612 	u8         promisc_mc[0x1];
3613 	u8         promisc_all[0x1];
3614 	u8         reserved_at_783[0x2];
3615 	u8         allowed_list_type[0x3];
3616 	u8         reserved_at_788[0xc];
3617 	u8         allowed_list_size[0xc];
3618 
3619 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
3620 
3621 	u8         reserved_at_7e0[0x20];
3622 
3623 	u8         current_uc_mac_address[][0x40];
3624 };
3625 
3626 enum {
3627 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3628 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3629 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3630 	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3631 	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3632 	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3633 };
3634 
3635 struct mlx5_ifc_mkc_bits {
3636 	u8         reserved_at_0[0x1];
3637 	u8         free[0x1];
3638 	u8         reserved_at_2[0x1];
3639 	u8         access_mode_4_2[0x3];
3640 	u8         reserved_at_6[0x7];
3641 	u8         relaxed_ordering_write[0x1];
3642 	u8         reserved_at_e[0x1];
3643 	u8         small_fence_on_rdma_read_response[0x1];
3644 	u8         umr_en[0x1];
3645 	u8         a[0x1];
3646 	u8         rw[0x1];
3647 	u8         rr[0x1];
3648 	u8         lw[0x1];
3649 	u8         lr[0x1];
3650 	u8         access_mode_1_0[0x2];
3651 	u8         reserved_at_18[0x8];
3652 
3653 	u8         qpn[0x18];
3654 	u8         mkey_7_0[0x8];
3655 
3656 	u8         reserved_at_40[0x20];
3657 
3658 	u8         length64[0x1];
3659 	u8         bsf_en[0x1];
3660 	u8         sync_umr[0x1];
3661 	u8         reserved_at_63[0x2];
3662 	u8         expected_sigerr_count[0x1];
3663 	u8         reserved_at_66[0x1];
3664 	u8         en_rinval[0x1];
3665 	u8         pd[0x18];
3666 
3667 	u8         start_addr[0x40];
3668 
3669 	u8         len[0x40];
3670 
3671 	u8         bsf_octword_size[0x20];
3672 
3673 	u8         reserved_at_120[0x80];
3674 
3675 	u8         translations_octword_size[0x20];
3676 
3677 	u8         reserved_at_1c0[0x19];
3678 	u8         relaxed_ordering_read[0x1];
3679 	u8         reserved_at_1d9[0x1];
3680 	u8         log_page_size[0x5];
3681 
3682 	u8         reserved_at_1e0[0x20];
3683 };
3684 
3685 struct mlx5_ifc_pkey_bits {
3686 	u8         reserved_at_0[0x10];
3687 	u8         pkey[0x10];
3688 };
3689 
3690 struct mlx5_ifc_array128_auto_bits {
3691 	u8         array128_auto[16][0x8];
3692 };
3693 
3694 struct mlx5_ifc_hca_vport_context_bits {
3695 	u8         field_select[0x20];
3696 
3697 	u8         reserved_at_20[0xe0];
3698 
3699 	u8         sm_virt_aware[0x1];
3700 	u8         has_smi[0x1];
3701 	u8         has_raw[0x1];
3702 	u8         grh_required[0x1];
3703 	u8         reserved_at_104[0xc];
3704 	u8         port_physical_state[0x4];
3705 	u8         vport_state_policy[0x4];
3706 	u8         port_state[0x4];
3707 	u8         vport_state[0x4];
3708 
3709 	u8         reserved_at_120[0x20];
3710 
3711 	u8         system_image_guid[0x40];
3712 
3713 	u8         port_guid[0x40];
3714 
3715 	u8         node_guid[0x40];
3716 
3717 	u8         cap_mask1[0x20];
3718 
3719 	u8         cap_mask1_field_select[0x20];
3720 
3721 	u8         cap_mask2[0x20];
3722 
3723 	u8         cap_mask2_field_select[0x20];
3724 
3725 	u8         reserved_at_280[0x80];
3726 
3727 	u8         lid[0x10];
3728 	u8         reserved_at_310[0x4];
3729 	u8         init_type_reply[0x4];
3730 	u8         lmc[0x3];
3731 	u8         subnet_timeout[0x5];
3732 
3733 	u8         sm_lid[0x10];
3734 	u8         sm_sl[0x4];
3735 	u8         reserved_at_334[0xc];
3736 
3737 	u8         qkey_violation_counter[0x10];
3738 	u8         pkey_violation_counter[0x10];
3739 
3740 	u8         reserved_at_360[0xca0];
3741 };
3742 
3743 struct mlx5_ifc_esw_vport_context_bits {
3744 	u8         fdb_to_vport_reg_c[0x1];
3745 	u8         reserved_at_1[0x2];
3746 	u8         vport_svlan_strip[0x1];
3747 	u8         vport_cvlan_strip[0x1];
3748 	u8         vport_svlan_insert[0x1];
3749 	u8         vport_cvlan_insert[0x2];
3750 	u8         fdb_to_vport_reg_c_id[0x8];
3751 	u8         reserved_at_10[0x10];
3752 
3753 	u8         reserved_at_20[0x20];
3754 
3755 	u8         svlan_cfi[0x1];
3756 	u8         svlan_pcp[0x3];
3757 	u8         svlan_id[0xc];
3758 	u8         cvlan_cfi[0x1];
3759 	u8         cvlan_pcp[0x3];
3760 	u8         cvlan_id[0xc];
3761 
3762 	u8         reserved_at_60[0x720];
3763 
3764 	u8         sw_steering_vport_icm_address_rx[0x40];
3765 
3766 	u8         sw_steering_vport_icm_address_tx[0x40];
3767 };
3768 
3769 enum {
3770 	MLX5_EQC_STATUS_OK                = 0x0,
3771 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3772 };
3773 
3774 enum {
3775 	MLX5_EQC_ST_ARMED  = 0x9,
3776 	MLX5_EQC_ST_FIRED  = 0xa,
3777 };
3778 
3779 struct mlx5_ifc_eqc_bits {
3780 	u8         status[0x4];
3781 	u8         reserved_at_4[0x9];
3782 	u8         ec[0x1];
3783 	u8         oi[0x1];
3784 	u8         reserved_at_f[0x5];
3785 	u8         st[0x4];
3786 	u8         reserved_at_18[0x8];
3787 
3788 	u8         reserved_at_20[0x20];
3789 
3790 	u8         reserved_at_40[0x14];
3791 	u8         page_offset[0x6];
3792 	u8         reserved_at_5a[0x6];
3793 
3794 	u8         reserved_at_60[0x3];
3795 	u8         log_eq_size[0x5];
3796 	u8         uar_page[0x18];
3797 
3798 	u8         reserved_at_80[0x20];
3799 
3800 	u8         reserved_at_a0[0x14];
3801 	u8         intr[0xc];
3802 
3803 	u8         reserved_at_c0[0x3];
3804 	u8         log_page_size[0x5];
3805 	u8         reserved_at_c8[0x18];
3806 
3807 	u8         reserved_at_e0[0x60];
3808 
3809 	u8         reserved_at_140[0x8];
3810 	u8         consumer_counter[0x18];
3811 
3812 	u8         reserved_at_160[0x8];
3813 	u8         producer_counter[0x18];
3814 
3815 	u8         reserved_at_180[0x80];
3816 };
3817 
3818 enum {
3819 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
3820 	MLX5_DCTC_STATE_DRAINING  = 0x1,
3821 	MLX5_DCTC_STATE_DRAINED   = 0x2,
3822 };
3823 
3824 enum {
3825 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3826 	MLX5_DCTC_CS_RES_NA         = 0x1,
3827 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3828 };
3829 
3830 enum {
3831 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
3832 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
3833 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3834 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3835 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3836 };
3837 
3838 struct mlx5_ifc_dctc_bits {
3839 	u8         reserved_at_0[0x4];
3840 	u8         state[0x4];
3841 	u8         reserved_at_8[0x18];
3842 
3843 	u8         reserved_at_20[0x8];
3844 	u8         user_index[0x18];
3845 
3846 	u8         reserved_at_40[0x8];
3847 	u8         cqn[0x18];
3848 
3849 	u8         counter_set_id[0x8];
3850 	u8         atomic_mode[0x4];
3851 	u8         rre[0x1];
3852 	u8         rwe[0x1];
3853 	u8         rae[0x1];
3854 	u8         atomic_like_write_en[0x1];
3855 	u8         latency_sensitive[0x1];
3856 	u8         rlky[0x1];
3857 	u8         free_ar[0x1];
3858 	u8         reserved_at_73[0xd];
3859 
3860 	u8         reserved_at_80[0x8];
3861 	u8         cs_res[0x8];
3862 	u8         reserved_at_90[0x3];
3863 	u8         min_rnr_nak[0x5];
3864 	u8         reserved_at_98[0x8];
3865 
3866 	u8         reserved_at_a0[0x8];
3867 	u8         srqn_xrqn[0x18];
3868 
3869 	u8         reserved_at_c0[0x8];
3870 	u8         pd[0x18];
3871 
3872 	u8         tclass[0x8];
3873 	u8         reserved_at_e8[0x4];
3874 	u8         flow_label[0x14];
3875 
3876 	u8         dc_access_key[0x40];
3877 
3878 	u8         reserved_at_140[0x5];
3879 	u8         mtu[0x3];
3880 	u8         port[0x8];
3881 	u8         pkey_index[0x10];
3882 
3883 	u8         reserved_at_160[0x8];
3884 	u8         my_addr_index[0x8];
3885 	u8         reserved_at_170[0x8];
3886 	u8         hop_limit[0x8];
3887 
3888 	u8         dc_access_key_violation_count[0x20];
3889 
3890 	u8         reserved_at_1a0[0x14];
3891 	u8         dei_cfi[0x1];
3892 	u8         eth_prio[0x3];
3893 	u8         ecn[0x2];
3894 	u8         dscp[0x6];
3895 
3896 	u8         reserved_at_1c0[0x20];
3897 	u8         ece[0x20];
3898 };
3899 
3900 enum {
3901 	MLX5_CQC_STATUS_OK             = 0x0,
3902 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3903 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3904 };
3905 
3906 enum {
3907 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3908 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3909 };
3910 
3911 enum {
3912 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3913 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3914 	MLX5_CQC_ST_FIRED                                 = 0xa,
3915 };
3916 
3917 enum {
3918 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3919 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3920 	MLX5_CQ_PERIOD_NUM_MODES
3921 };
3922 
3923 struct mlx5_ifc_cqc_bits {
3924 	u8         status[0x4];
3925 	u8         reserved_at_4[0x2];
3926 	u8         dbr_umem_valid[0x1];
3927 	u8         apu_cq[0x1];
3928 	u8         cqe_sz[0x3];
3929 	u8         cc[0x1];
3930 	u8         reserved_at_c[0x1];
3931 	u8         scqe_break_moderation_en[0x1];
3932 	u8         oi[0x1];
3933 	u8         cq_period_mode[0x2];
3934 	u8         cqe_comp_en[0x1];
3935 	u8         mini_cqe_res_format[0x2];
3936 	u8         st[0x4];
3937 	u8         reserved_at_18[0x8];
3938 
3939 	u8         reserved_at_20[0x20];
3940 
3941 	u8         reserved_at_40[0x14];
3942 	u8         page_offset[0x6];
3943 	u8         reserved_at_5a[0x6];
3944 
3945 	u8         reserved_at_60[0x3];
3946 	u8         log_cq_size[0x5];
3947 	u8         uar_page[0x18];
3948 
3949 	u8         reserved_at_80[0x4];
3950 	u8         cq_period[0xc];
3951 	u8         cq_max_count[0x10];
3952 
3953 	u8         c_eqn_or_apu_element[0x20];
3954 
3955 	u8         reserved_at_c0[0x3];
3956 	u8         log_page_size[0x5];
3957 	u8         reserved_at_c8[0x18];
3958 
3959 	u8         reserved_at_e0[0x20];
3960 
3961 	u8         reserved_at_100[0x8];
3962 	u8         last_notified_index[0x18];
3963 
3964 	u8         reserved_at_120[0x8];
3965 	u8         last_solicit_index[0x18];
3966 
3967 	u8         reserved_at_140[0x8];
3968 	u8         consumer_counter[0x18];
3969 
3970 	u8         reserved_at_160[0x8];
3971 	u8         producer_counter[0x18];
3972 
3973 	u8         reserved_at_180[0x40];
3974 
3975 	u8         dbr_addr[0x40];
3976 };
3977 
3978 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3979 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3980 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3981 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3982 	u8         reserved_at_0[0x800];
3983 };
3984 
3985 struct mlx5_ifc_query_adapter_param_block_bits {
3986 	u8         reserved_at_0[0xc0];
3987 
3988 	u8         reserved_at_c0[0x8];
3989 	u8         ieee_vendor_id[0x18];
3990 
3991 	u8         reserved_at_e0[0x10];
3992 	u8         vsd_vendor_id[0x10];
3993 
3994 	u8         vsd[208][0x8];
3995 
3996 	u8         vsd_contd_psid[16][0x8];
3997 };
3998 
3999 enum {
4000 	MLX5_XRQC_STATE_GOOD   = 0x0,
4001 	MLX5_XRQC_STATE_ERROR  = 0x1,
4002 };
4003 
4004 enum {
4005 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4006 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4007 };
4008 
4009 enum {
4010 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4011 };
4012 
4013 struct mlx5_ifc_tag_matching_topology_context_bits {
4014 	u8         log_matching_list_sz[0x4];
4015 	u8         reserved_at_4[0xc];
4016 	u8         append_next_index[0x10];
4017 
4018 	u8         sw_phase_cnt[0x10];
4019 	u8         hw_phase_cnt[0x10];
4020 
4021 	u8         reserved_at_40[0x40];
4022 };
4023 
4024 struct mlx5_ifc_xrqc_bits {
4025 	u8         state[0x4];
4026 	u8         rlkey[0x1];
4027 	u8         reserved_at_5[0xf];
4028 	u8         topology[0x4];
4029 	u8         reserved_at_18[0x4];
4030 	u8         offload[0x4];
4031 
4032 	u8         reserved_at_20[0x8];
4033 	u8         user_index[0x18];
4034 
4035 	u8         reserved_at_40[0x8];
4036 	u8         cqn[0x18];
4037 
4038 	u8         reserved_at_60[0xa0];
4039 
4040 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4041 
4042 	u8         reserved_at_180[0x280];
4043 
4044 	struct mlx5_ifc_wq_bits wq;
4045 };
4046 
4047 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4048 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4049 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4050 	u8         reserved_at_0[0x20];
4051 };
4052 
4053 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4054 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4055 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4056 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4057 	u8         reserved_at_0[0x20];
4058 };
4059 
4060 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4061 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4062 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4063 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4064 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4065 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4066 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4067 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4068 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4069 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4070 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4071 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4072 	u8         reserved_at_0[0x7c0];
4073 };
4074 
4075 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4076 	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4077 	u8         reserved_at_0[0x7c0];
4078 };
4079 
4080 union mlx5_ifc_event_auto_bits {
4081 	struct mlx5_ifc_comp_event_bits comp_event;
4082 	struct mlx5_ifc_dct_events_bits dct_events;
4083 	struct mlx5_ifc_qp_events_bits qp_events;
4084 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4085 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4086 	struct mlx5_ifc_cq_error_bits cq_error;
4087 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4088 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4089 	struct mlx5_ifc_gpio_event_bits gpio_event;
4090 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4091 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4092 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4093 	u8         reserved_at_0[0xe0];
4094 };
4095 
4096 struct mlx5_ifc_health_buffer_bits {
4097 	u8         reserved_at_0[0x100];
4098 
4099 	u8         assert_existptr[0x20];
4100 
4101 	u8         assert_callra[0x20];
4102 
4103 	u8         reserved_at_140[0x40];
4104 
4105 	u8         fw_version[0x20];
4106 
4107 	u8         hw_id[0x20];
4108 
4109 	u8         reserved_at_1c0[0x20];
4110 
4111 	u8         irisc_index[0x8];
4112 	u8         synd[0x8];
4113 	u8         ext_synd[0x10];
4114 };
4115 
4116 struct mlx5_ifc_register_loopback_control_bits {
4117 	u8         no_lb[0x1];
4118 	u8         reserved_at_1[0x7];
4119 	u8         port[0x8];
4120 	u8         reserved_at_10[0x10];
4121 
4122 	u8         reserved_at_20[0x60];
4123 };
4124 
4125 struct mlx5_ifc_vport_tc_element_bits {
4126 	u8         traffic_class[0x4];
4127 	u8         reserved_at_4[0xc];
4128 	u8         vport_number[0x10];
4129 };
4130 
4131 struct mlx5_ifc_vport_element_bits {
4132 	u8         reserved_at_0[0x10];
4133 	u8         vport_number[0x10];
4134 };
4135 
4136 enum {
4137 	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4138 	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4139 	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4140 };
4141 
4142 struct mlx5_ifc_tsar_element_bits {
4143 	u8         reserved_at_0[0x8];
4144 	u8         tsar_type[0x8];
4145 	u8         reserved_at_10[0x10];
4146 };
4147 
4148 enum {
4149 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4150 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4151 };
4152 
4153 struct mlx5_ifc_teardown_hca_out_bits {
4154 	u8         status[0x8];
4155 	u8         reserved_at_8[0x18];
4156 
4157 	u8         syndrome[0x20];
4158 
4159 	u8         reserved_at_40[0x3f];
4160 
4161 	u8         state[0x1];
4162 };
4163 
4164 enum {
4165 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4166 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4167 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4168 };
4169 
4170 struct mlx5_ifc_teardown_hca_in_bits {
4171 	u8         opcode[0x10];
4172 	u8         reserved_at_10[0x10];
4173 
4174 	u8         reserved_at_20[0x10];
4175 	u8         op_mod[0x10];
4176 
4177 	u8         reserved_at_40[0x10];
4178 	u8         profile[0x10];
4179 
4180 	u8         reserved_at_60[0x20];
4181 };
4182 
4183 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4184 	u8         status[0x8];
4185 	u8         reserved_at_8[0x18];
4186 
4187 	u8         syndrome[0x20];
4188 
4189 	u8         reserved_at_40[0x40];
4190 };
4191 
4192 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4193 	u8         opcode[0x10];
4194 	u8         uid[0x10];
4195 
4196 	u8         reserved_at_20[0x10];
4197 	u8         op_mod[0x10];
4198 
4199 	u8         reserved_at_40[0x8];
4200 	u8         qpn[0x18];
4201 
4202 	u8         reserved_at_60[0x20];
4203 
4204 	u8         opt_param_mask[0x20];
4205 
4206 	u8         reserved_at_a0[0x20];
4207 
4208 	struct mlx5_ifc_qpc_bits qpc;
4209 
4210 	u8         reserved_at_800[0x80];
4211 };
4212 
4213 struct mlx5_ifc_sqd2rts_qp_out_bits {
4214 	u8         status[0x8];
4215 	u8         reserved_at_8[0x18];
4216 
4217 	u8         syndrome[0x20];
4218 
4219 	u8         reserved_at_40[0x40];
4220 };
4221 
4222 struct mlx5_ifc_sqd2rts_qp_in_bits {
4223 	u8         opcode[0x10];
4224 	u8         uid[0x10];
4225 
4226 	u8         reserved_at_20[0x10];
4227 	u8         op_mod[0x10];
4228 
4229 	u8         reserved_at_40[0x8];
4230 	u8         qpn[0x18];
4231 
4232 	u8         reserved_at_60[0x20];
4233 
4234 	u8         opt_param_mask[0x20];
4235 
4236 	u8         reserved_at_a0[0x20];
4237 
4238 	struct mlx5_ifc_qpc_bits qpc;
4239 
4240 	u8         reserved_at_800[0x80];
4241 };
4242 
4243 struct mlx5_ifc_set_roce_address_out_bits {
4244 	u8         status[0x8];
4245 	u8         reserved_at_8[0x18];
4246 
4247 	u8         syndrome[0x20];
4248 
4249 	u8         reserved_at_40[0x40];
4250 };
4251 
4252 struct mlx5_ifc_set_roce_address_in_bits {
4253 	u8         opcode[0x10];
4254 	u8         reserved_at_10[0x10];
4255 
4256 	u8         reserved_at_20[0x10];
4257 	u8         op_mod[0x10];
4258 
4259 	u8         roce_address_index[0x10];
4260 	u8         reserved_at_50[0xc];
4261 	u8	   vhca_port_num[0x4];
4262 
4263 	u8         reserved_at_60[0x20];
4264 
4265 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4266 };
4267 
4268 struct mlx5_ifc_set_mad_demux_out_bits {
4269 	u8         status[0x8];
4270 	u8         reserved_at_8[0x18];
4271 
4272 	u8         syndrome[0x20];
4273 
4274 	u8         reserved_at_40[0x40];
4275 };
4276 
4277 enum {
4278 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4279 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4280 };
4281 
4282 struct mlx5_ifc_set_mad_demux_in_bits {
4283 	u8         opcode[0x10];
4284 	u8         reserved_at_10[0x10];
4285 
4286 	u8         reserved_at_20[0x10];
4287 	u8         op_mod[0x10];
4288 
4289 	u8         reserved_at_40[0x20];
4290 
4291 	u8         reserved_at_60[0x6];
4292 	u8         demux_mode[0x2];
4293 	u8         reserved_at_68[0x18];
4294 };
4295 
4296 struct mlx5_ifc_set_l2_table_entry_out_bits {
4297 	u8         status[0x8];
4298 	u8         reserved_at_8[0x18];
4299 
4300 	u8         syndrome[0x20];
4301 
4302 	u8         reserved_at_40[0x40];
4303 };
4304 
4305 struct mlx5_ifc_set_l2_table_entry_in_bits {
4306 	u8         opcode[0x10];
4307 	u8         reserved_at_10[0x10];
4308 
4309 	u8         reserved_at_20[0x10];
4310 	u8         op_mod[0x10];
4311 
4312 	u8         reserved_at_40[0x60];
4313 
4314 	u8         reserved_at_a0[0x8];
4315 	u8         table_index[0x18];
4316 
4317 	u8         reserved_at_c0[0x20];
4318 
4319 	u8         reserved_at_e0[0x13];
4320 	u8         vlan_valid[0x1];
4321 	u8         vlan[0xc];
4322 
4323 	struct mlx5_ifc_mac_address_layout_bits mac_address;
4324 
4325 	u8         reserved_at_140[0xc0];
4326 };
4327 
4328 struct mlx5_ifc_set_issi_out_bits {
4329 	u8         status[0x8];
4330 	u8         reserved_at_8[0x18];
4331 
4332 	u8         syndrome[0x20];
4333 
4334 	u8         reserved_at_40[0x40];
4335 };
4336 
4337 struct mlx5_ifc_set_issi_in_bits {
4338 	u8         opcode[0x10];
4339 	u8         reserved_at_10[0x10];
4340 
4341 	u8         reserved_at_20[0x10];
4342 	u8         op_mod[0x10];
4343 
4344 	u8         reserved_at_40[0x10];
4345 	u8         current_issi[0x10];
4346 
4347 	u8         reserved_at_60[0x20];
4348 };
4349 
4350 struct mlx5_ifc_set_hca_cap_out_bits {
4351 	u8         status[0x8];
4352 	u8         reserved_at_8[0x18];
4353 
4354 	u8         syndrome[0x20];
4355 
4356 	u8         reserved_at_40[0x40];
4357 };
4358 
4359 struct mlx5_ifc_set_hca_cap_in_bits {
4360 	u8         opcode[0x10];
4361 	u8         reserved_at_10[0x10];
4362 
4363 	u8         reserved_at_20[0x10];
4364 	u8         op_mod[0x10];
4365 
4366 	u8         other_function[0x1];
4367 	u8         reserved_at_41[0xf];
4368 	u8         function_id[0x10];
4369 
4370 	u8         reserved_at_60[0x20];
4371 
4372 	union mlx5_ifc_hca_cap_union_bits capability;
4373 };
4374 
4375 enum {
4376 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4377 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4378 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4379 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4380 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4381 };
4382 
4383 struct mlx5_ifc_set_fte_out_bits {
4384 	u8         status[0x8];
4385 	u8         reserved_at_8[0x18];
4386 
4387 	u8         syndrome[0x20];
4388 
4389 	u8         reserved_at_40[0x40];
4390 };
4391 
4392 struct mlx5_ifc_set_fte_in_bits {
4393 	u8         opcode[0x10];
4394 	u8         reserved_at_10[0x10];
4395 
4396 	u8         reserved_at_20[0x10];
4397 	u8         op_mod[0x10];
4398 
4399 	u8         other_vport[0x1];
4400 	u8         reserved_at_41[0xf];
4401 	u8         vport_number[0x10];
4402 
4403 	u8         reserved_at_60[0x20];
4404 
4405 	u8         table_type[0x8];
4406 	u8         reserved_at_88[0x18];
4407 
4408 	u8         reserved_at_a0[0x8];
4409 	u8         table_id[0x18];
4410 
4411 	u8         ignore_flow_level[0x1];
4412 	u8         reserved_at_c1[0x17];
4413 	u8         modify_enable_mask[0x8];
4414 
4415 	u8         reserved_at_e0[0x20];
4416 
4417 	u8         flow_index[0x20];
4418 
4419 	u8         reserved_at_120[0xe0];
4420 
4421 	struct mlx5_ifc_flow_context_bits flow_context;
4422 };
4423 
4424 struct mlx5_ifc_rts2rts_qp_out_bits {
4425 	u8         status[0x8];
4426 	u8         reserved_at_8[0x18];
4427 
4428 	u8         syndrome[0x20];
4429 
4430 	u8         reserved_at_40[0x20];
4431 	u8         ece[0x20];
4432 };
4433 
4434 struct mlx5_ifc_rts2rts_qp_in_bits {
4435 	u8         opcode[0x10];
4436 	u8         uid[0x10];
4437 
4438 	u8         reserved_at_20[0x10];
4439 	u8         op_mod[0x10];
4440 
4441 	u8         reserved_at_40[0x8];
4442 	u8         qpn[0x18];
4443 
4444 	u8         reserved_at_60[0x20];
4445 
4446 	u8         opt_param_mask[0x20];
4447 
4448 	u8         ece[0x20];
4449 
4450 	struct mlx5_ifc_qpc_bits qpc;
4451 
4452 	u8         reserved_at_800[0x80];
4453 };
4454 
4455 struct mlx5_ifc_rtr2rts_qp_out_bits {
4456 	u8         status[0x8];
4457 	u8         reserved_at_8[0x18];
4458 
4459 	u8         syndrome[0x20];
4460 
4461 	u8         reserved_at_40[0x20];
4462 	u8         ece[0x20];
4463 };
4464 
4465 struct mlx5_ifc_rtr2rts_qp_in_bits {
4466 	u8         opcode[0x10];
4467 	u8         uid[0x10];
4468 
4469 	u8         reserved_at_20[0x10];
4470 	u8         op_mod[0x10];
4471 
4472 	u8         reserved_at_40[0x8];
4473 	u8         qpn[0x18];
4474 
4475 	u8         reserved_at_60[0x20];
4476 
4477 	u8         opt_param_mask[0x20];
4478 
4479 	u8         ece[0x20];
4480 
4481 	struct mlx5_ifc_qpc_bits qpc;
4482 
4483 	u8         reserved_at_800[0x80];
4484 };
4485 
4486 struct mlx5_ifc_rst2init_qp_out_bits {
4487 	u8         status[0x8];
4488 	u8         reserved_at_8[0x18];
4489 
4490 	u8         syndrome[0x20];
4491 
4492 	u8         reserved_at_40[0x20];
4493 	u8         ece[0x20];
4494 };
4495 
4496 struct mlx5_ifc_rst2init_qp_in_bits {
4497 	u8         opcode[0x10];
4498 	u8         uid[0x10];
4499 
4500 	u8         reserved_at_20[0x10];
4501 	u8         op_mod[0x10];
4502 
4503 	u8         reserved_at_40[0x8];
4504 	u8         qpn[0x18];
4505 
4506 	u8         reserved_at_60[0x20];
4507 
4508 	u8         opt_param_mask[0x20];
4509 
4510 	u8         ece[0x20];
4511 
4512 	struct mlx5_ifc_qpc_bits qpc;
4513 
4514 	u8         reserved_at_800[0x80];
4515 };
4516 
4517 struct mlx5_ifc_query_xrq_out_bits {
4518 	u8         status[0x8];
4519 	u8         reserved_at_8[0x18];
4520 
4521 	u8         syndrome[0x20];
4522 
4523 	u8         reserved_at_40[0x40];
4524 
4525 	struct mlx5_ifc_xrqc_bits xrq_context;
4526 };
4527 
4528 struct mlx5_ifc_query_xrq_in_bits {
4529 	u8         opcode[0x10];
4530 	u8         reserved_at_10[0x10];
4531 
4532 	u8         reserved_at_20[0x10];
4533 	u8         op_mod[0x10];
4534 
4535 	u8         reserved_at_40[0x8];
4536 	u8         xrqn[0x18];
4537 
4538 	u8         reserved_at_60[0x20];
4539 };
4540 
4541 struct mlx5_ifc_query_xrc_srq_out_bits {
4542 	u8         status[0x8];
4543 	u8         reserved_at_8[0x18];
4544 
4545 	u8         syndrome[0x20];
4546 
4547 	u8         reserved_at_40[0x40];
4548 
4549 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4550 
4551 	u8         reserved_at_280[0x600];
4552 
4553 	u8         pas[][0x40];
4554 };
4555 
4556 struct mlx5_ifc_query_xrc_srq_in_bits {
4557 	u8         opcode[0x10];
4558 	u8         reserved_at_10[0x10];
4559 
4560 	u8         reserved_at_20[0x10];
4561 	u8         op_mod[0x10];
4562 
4563 	u8         reserved_at_40[0x8];
4564 	u8         xrc_srqn[0x18];
4565 
4566 	u8         reserved_at_60[0x20];
4567 };
4568 
4569 enum {
4570 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4571 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4572 };
4573 
4574 struct mlx5_ifc_query_vport_state_out_bits {
4575 	u8         status[0x8];
4576 	u8         reserved_at_8[0x18];
4577 
4578 	u8         syndrome[0x20];
4579 
4580 	u8         reserved_at_40[0x20];
4581 
4582 	u8         reserved_at_60[0x18];
4583 	u8         admin_state[0x4];
4584 	u8         state[0x4];
4585 };
4586 
4587 enum {
4588 	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4589 	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4590 	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
4591 };
4592 
4593 struct mlx5_ifc_arm_monitor_counter_in_bits {
4594 	u8         opcode[0x10];
4595 	u8         uid[0x10];
4596 
4597 	u8         reserved_at_20[0x10];
4598 	u8         op_mod[0x10];
4599 
4600 	u8         reserved_at_40[0x20];
4601 
4602 	u8         reserved_at_60[0x20];
4603 };
4604 
4605 struct mlx5_ifc_arm_monitor_counter_out_bits {
4606 	u8         status[0x8];
4607 	u8         reserved_at_8[0x18];
4608 
4609 	u8         syndrome[0x20];
4610 
4611 	u8         reserved_at_40[0x40];
4612 };
4613 
4614 enum {
4615 	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4616 	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4617 };
4618 
4619 enum mlx5_monitor_counter_ppcnt {
4620 	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4621 	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4622 	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4623 	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4624 	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4625 	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4626 };
4627 
4628 enum {
4629 	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4630 };
4631 
4632 struct mlx5_ifc_monitor_counter_output_bits {
4633 	u8         reserved_at_0[0x4];
4634 	u8         type[0x4];
4635 	u8         reserved_at_8[0x8];
4636 	u8         counter[0x10];
4637 
4638 	u8         counter_group_id[0x20];
4639 };
4640 
4641 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4642 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4643 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4644 					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4645 
4646 struct mlx5_ifc_set_monitor_counter_in_bits {
4647 	u8         opcode[0x10];
4648 	u8         uid[0x10];
4649 
4650 	u8         reserved_at_20[0x10];
4651 	u8         op_mod[0x10];
4652 
4653 	u8         reserved_at_40[0x10];
4654 	u8         num_of_counters[0x10];
4655 
4656 	u8         reserved_at_60[0x20];
4657 
4658 	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4659 };
4660 
4661 struct mlx5_ifc_set_monitor_counter_out_bits {
4662 	u8         status[0x8];
4663 	u8         reserved_at_8[0x18];
4664 
4665 	u8         syndrome[0x20];
4666 
4667 	u8         reserved_at_40[0x40];
4668 };
4669 
4670 struct mlx5_ifc_query_vport_state_in_bits {
4671 	u8         opcode[0x10];
4672 	u8         reserved_at_10[0x10];
4673 
4674 	u8         reserved_at_20[0x10];
4675 	u8         op_mod[0x10];
4676 
4677 	u8         other_vport[0x1];
4678 	u8         reserved_at_41[0xf];
4679 	u8         vport_number[0x10];
4680 
4681 	u8         reserved_at_60[0x20];
4682 };
4683 
4684 struct mlx5_ifc_query_vnic_env_out_bits {
4685 	u8         status[0x8];
4686 	u8         reserved_at_8[0x18];
4687 
4688 	u8         syndrome[0x20];
4689 
4690 	u8         reserved_at_40[0x40];
4691 
4692 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4693 };
4694 
4695 enum {
4696 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4697 };
4698 
4699 struct mlx5_ifc_query_vnic_env_in_bits {
4700 	u8         opcode[0x10];
4701 	u8         reserved_at_10[0x10];
4702 
4703 	u8         reserved_at_20[0x10];
4704 	u8         op_mod[0x10];
4705 
4706 	u8         other_vport[0x1];
4707 	u8         reserved_at_41[0xf];
4708 	u8         vport_number[0x10];
4709 
4710 	u8         reserved_at_60[0x20];
4711 };
4712 
4713 struct mlx5_ifc_query_vport_counter_out_bits {
4714 	u8         status[0x8];
4715 	u8         reserved_at_8[0x18];
4716 
4717 	u8         syndrome[0x20];
4718 
4719 	u8         reserved_at_40[0x40];
4720 
4721 	struct mlx5_ifc_traffic_counter_bits received_errors;
4722 
4723 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
4724 
4725 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4726 
4727 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4728 
4729 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4730 
4731 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4732 
4733 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4734 
4735 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4736 
4737 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4738 
4739 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4740 
4741 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4742 
4743 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4744 
4745 	u8         reserved_at_680[0xa00];
4746 };
4747 
4748 enum {
4749 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4750 };
4751 
4752 struct mlx5_ifc_query_vport_counter_in_bits {
4753 	u8         opcode[0x10];
4754 	u8         reserved_at_10[0x10];
4755 
4756 	u8         reserved_at_20[0x10];
4757 	u8         op_mod[0x10];
4758 
4759 	u8         other_vport[0x1];
4760 	u8         reserved_at_41[0xb];
4761 	u8	   port_num[0x4];
4762 	u8         vport_number[0x10];
4763 
4764 	u8         reserved_at_60[0x60];
4765 
4766 	u8         clear[0x1];
4767 	u8         reserved_at_c1[0x1f];
4768 
4769 	u8         reserved_at_e0[0x20];
4770 };
4771 
4772 struct mlx5_ifc_query_tis_out_bits {
4773 	u8         status[0x8];
4774 	u8         reserved_at_8[0x18];
4775 
4776 	u8         syndrome[0x20];
4777 
4778 	u8         reserved_at_40[0x40];
4779 
4780 	struct mlx5_ifc_tisc_bits tis_context;
4781 };
4782 
4783 struct mlx5_ifc_query_tis_in_bits {
4784 	u8         opcode[0x10];
4785 	u8         reserved_at_10[0x10];
4786 
4787 	u8         reserved_at_20[0x10];
4788 	u8         op_mod[0x10];
4789 
4790 	u8         reserved_at_40[0x8];
4791 	u8         tisn[0x18];
4792 
4793 	u8         reserved_at_60[0x20];
4794 };
4795 
4796 struct mlx5_ifc_query_tir_out_bits {
4797 	u8         status[0x8];
4798 	u8         reserved_at_8[0x18];
4799 
4800 	u8         syndrome[0x20];
4801 
4802 	u8         reserved_at_40[0xc0];
4803 
4804 	struct mlx5_ifc_tirc_bits tir_context;
4805 };
4806 
4807 struct mlx5_ifc_query_tir_in_bits {
4808 	u8         opcode[0x10];
4809 	u8         reserved_at_10[0x10];
4810 
4811 	u8         reserved_at_20[0x10];
4812 	u8         op_mod[0x10];
4813 
4814 	u8         reserved_at_40[0x8];
4815 	u8         tirn[0x18];
4816 
4817 	u8         reserved_at_60[0x20];
4818 };
4819 
4820 struct mlx5_ifc_query_srq_out_bits {
4821 	u8         status[0x8];
4822 	u8         reserved_at_8[0x18];
4823 
4824 	u8         syndrome[0x20];
4825 
4826 	u8         reserved_at_40[0x40];
4827 
4828 	struct mlx5_ifc_srqc_bits srq_context_entry;
4829 
4830 	u8         reserved_at_280[0x600];
4831 
4832 	u8         pas[][0x40];
4833 };
4834 
4835 struct mlx5_ifc_query_srq_in_bits {
4836 	u8         opcode[0x10];
4837 	u8         reserved_at_10[0x10];
4838 
4839 	u8         reserved_at_20[0x10];
4840 	u8         op_mod[0x10];
4841 
4842 	u8         reserved_at_40[0x8];
4843 	u8         srqn[0x18];
4844 
4845 	u8         reserved_at_60[0x20];
4846 };
4847 
4848 struct mlx5_ifc_query_sq_out_bits {
4849 	u8         status[0x8];
4850 	u8         reserved_at_8[0x18];
4851 
4852 	u8         syndrome[0x20];
4853 
4854 	u8         reserved_at_40[0xc0];
4855 
4856 	struct mlx5_ifc_sqc_bits sq_context;
4857 };
4858 
4859 struct mlx5_ifc_query_sq_in_bits {
4860 	u8         opcode[0x10];
4861 	u8         reserved_at_10[0x10];
4862 
4863 	u8         reserved_at_20[0x10];
4864 	u8         op_mod[0x10];
4865 
4866 	u8         reserved_at_40[0x8];
4867 	u8         sqn[0x18];
4868 
4869 	u8         reserved_at_60[0x20];
4870 };
4871 
4872 struct mlx5_ifc_query_special_contexts_out_bits {
4873 	u8         status[0x8];
4874 	u8         reserved_at_8[0x18];
4875 
4876 	u8         syndrome[0x20];
4877 
4878 	u8         dump_fill_mkey[0x20];
4879 
4880 	u8         resd_lkey[0x20];
4881 
4882 	u8         null_mkey[0x20];
4883 
4884 	u8         reserved_at_a0[0x60];
4885 };
4886 
4887 struct mlx5_ifc_query_special_contexts_in_bits {
4888 	u8         opcode[0x10];
4889 	u8         reserved_at_10[0x10];
4890 
4891 	u8         reserved_at_20[0x10];
4892 	u8         op_mod[0x10];
4893 
4894 	u8         reserved_at_40[0x40];
4895 };
4896 
4897 struct mlx5_ifc_query_scheduling_element_out_bits {
4898 	u8         opcode[0x10];
4899 	u8         reserved_at_10[0x10];
4900 
4901 	u8         reserved_at_20[0x10];
4902 	u8         op_mod[0x10];
4903 
4904 	u8         reserved_at_40[0xc0];
4905 
4906 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
4907 
4908 	u8         reserved_at_300[0x100];
4909 };
4910 
4911 enum {
4912 	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4913 	SCHEDULING_HIERARCHY_NIC = 0x3,
4914 };
4915 
4916 struct mlx5_ifc_query_scheduling_element_in_bits {
4917 	u8         opcode[0x10];
4918 	u8         reserved_at_10[0x10];
4919 
4920 	u8         reserved_at_20[0x10];
4921 	u8         op_mod[0x10];
4922 
4923 	u8         scheduling_hierarchy[0x8];
4924 	u8         reserved_at_48[0x18];
4925 
4926 	u8         scheduling_element_id[0x20];
4927 
4928 	u8         reserved_at_80[0x180];
4929 };
4930 
4931 struct mlx5_ifc_query_rqt_out_bits {
4932 	u8         status[0x8];
4933 	u8         reserved_at_8[0x18];
4934 
4935 	u8         syndrome[0x20];
4936 
4937 	u8         reserved_at_40[0xc0];
4938 
4939 	struct mlx5_ifc_rqtc_bits rqt_context;
4940 };
4941 
4942 struct mlx5_ifc_query_rqt_in_bits {
4943 	u8         opcode[0x10];
4944 	u8         reserved_at_10[0x10];
4945 
4946 	u8         reserved_at_20[0x10];
4947 	u8         op_mod[0x10];
4948 
4949 	u8         reserved_at_40[0x8];
4950 	u8         rqtn[0x18];
4951 
4952 	u8         reserved_at_60[0x20];
4953 };
4954 
4955 struct mlx5_ifc_query_rq_out_bits {
4956 	u8         status[0x8];
4957 	u8         reserved_at_8[0x18];
4958 
4959 	u8         syndrome[0x20];
4960 
4961 	u8         reserved_at_40[0xc0];
4962 
4963 	struct mlx5_ifc_rqc_bits rq_context;
4964 };
4965 
4966 struct mlx5_ifc_query_rq_in_bits {
4967 	u8         opcode[0x10];
4968 	u8         reserved_at_10[0x10];
4969 
4970 	u8         reserved_at_20[0x10];
4971 	u8         op_mod[0x10];
4972 
4973 	u8         reserved_at_40[0x8];
4974 	u8         rqn[0x18];
4975 
4976 	u8         reserved_at_60[0x20];
4977 };
4978 
4979 struct mlx5_ifc_query_roce_address_out_bits {
4980 	u8         status[0x8];
4981 	u8         reserved_at_8[0x18];
4982 
4983 	u8         syndrome[0x20];
4984 
4985 	u8         reserved_at_40[0x40];
4986 
4987 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4988 };
4989 
4990 struct mlx5_ifc_query_roce_address_in_bits {
4991 	u8         opcode[0x10];
4992 	u8         reserved_at_10[0x10];
4993 
4994 	u8         reserved_at_20[0x10];
4995 	u8         op_mod[0x10];
4996 
4997 	u8         roce_address_index[0x10];
4998 	u8         reserved_at_50[0xc];
4999 	u8	   vhca_port_num[0x4];
5000 
5001 	u8         reserved_at_60[0x20];
5002 };
5003 
5004 struct mlx5_ifc_query_rmp_out_bits {
5005 	u8         status[0x8];
5006 	u8         reserved_at_8[0x18];
5007 
5008 	u8         syndrome[0x20];
5009 
5010 	u8         reserved_at_40[0xc0];
5011 
5012 	struct mlx5_ifc_rmpc_bits rmp_context;
5013 };
5014 
5015 struct mlx5_ifc_query_rmp_in_bits {
5016 	u8         opcode[0x10];
5017 	u8         reserved_at_10[0x10];
5018 
5019 	u8         reserved_at_20[0x10];
5020 	u8         op_mod[0x10];
5021 
5022 	u8         reserved_at_40[0x8];
5023 	u8         rmpn[0x18];
5024 
5025 	u8         reserved_at_60[0x20];
5026 };
5027 
5028 struct mlx5_ifc_query_qp_out_bits {
5029 	u8         status[0x8];
5030 	u8         reserved_at_8[0x18];
5031 
5032 	u8         syndrome[0x20];
5033 
5034 	u8         reserved_at_40[0x40];
5035 
5036 	u8         opt_param_mask[0x20];
5037 
5038 	u8         ece[0x20];
5039 
5040 	struct mlx5_ifc_qpc_bits qpc;
5041 
5042 	u8         reserved_at_800[0x80];
5043 
5044 	u8         pas[][0x40];
5045 };
5046 
5047 struct mlx5_ifc_query_qp_in_bits {
5048 	u8         opcode[0x10];
5049 	u8         reserved_at_10[0x10];
5050 
5051 	u8         reserved_at_20[0x10];
5052 	u8         op_mod[0x10];
5053 
5054 	u8         reserved_at_40[0x8];
5055 	u8         qpn[0x18];
5056 
5057 	u8         reserved_at_60[0x20];
5058 };
5059 
5060 struct mlx5_ifc_query_q_counter_out_bits {
5061 	u8         status[0x8];
5062 	u8         reserved_at_8[0x18];
5063 
5064 	u8         syndrome[0x20];
5065 
5066 	u8         reserved_at_40[0x40];
5067 
5068 	u8         rx_write_requests[0x20];
5069 
5070 	u8         reserved_at_a0[0x20];
5071 
5072 	u8         rx_read_requests[0x20];
5073 
5074 	u8         reserved_at_e0[0x20];
5075 
5076 	u8         rx_atomic_requests[0x20];
5077 
5078 	u8         reserved_at_120[0x20];
5079 
5080 	u8         rx_dct_connect[0x20];
5081 
5082 	u8         reserved_at_160[0x20];
5083 
5084 	u8         out_of_buffer[0x20];
5085 
5086 	u8         reserved_at_1a0[0x20];
5087 
5088 	u8         out_of_sequence[0x20];
5089 
5090 	u8         reserved_at_1e0[0x20];
5091 
5092 	u8         duplicate_request[0x20];
5093 
5094 	u8         reserved_at_220[0x20];
5095 
5096 	u8         rnr_nak_retry_err[0x20];
5097 
5098 	u8         reserved_at_260[0x20];
5099 
5100 	u8         packet_seq_err[0x20];
5101 
5102 	u8         reserved_at_2a0[0x20];
5103 
5104 	u8         implied_nak_seq_err[0x20];
5105 
5106 	u8         reserved_at_2e0[0x20];
5107 
5108 	u8         local_ack_timeout_err[0x20];
5109 
5110 	u8         reserved_at_320[0xa0];
5111 
5112 	u8         resp_local_length_error[0x20];
5113 
5114 	u8         req_local_length_error[0x20];
5115 
5116 	u8         resp_local_qp_error[0x20];
5117 
5118 	u8         local_operation_error[0x20];
5119 
5120 	u8         resp_local_protection[0x20];
5121 
5122 	u8         req_local_protection[0x20];
5123 
5124 	u8         resp_cqe_error[0x20];
5125 
5126 	u8         req_cqe_error[0x20];
5127 
5128 	u8         req_mw_binding[0x20];
5129 
5130 	u8         req_bad_response[0x20];
5131 
5132 	u8         req_remote_invalid_request[0x20];
5133 
5134 	u8         resp_remote_invalid_request[0x20];
5135 
5136 	u8         req_remote_access_errors[0x20];
5137 
5138 	u8	   resp_remote_access_errors[0x20];
5139 
5140 	u8         req_remote_operation_errors[0x20];
5141 
5142 	u8         req_transport_retries_exceeded[0x20];
5143 
5144 	u8         cq_overflow[0x20];
5145 
5146 	u8         resp_cqe_flush_error[0x20];
5147 
5148 	u8         req_cqe_flush_error[0x20];
5149 
5150 	u8         reserved_at_620[0x20];
5151 
5152 	u8         roce_adp_retrans[0x20];
5153 
5154 	u8         roce_adp_retrans_to[0x20];
5155 
5156 	u8         roce_slow_restart[0x20];
5157 
5158 	u8         roce_slow_restart_cnps[0x20];
5159 
5160 	u8         roce_slow_restart_trans[0x20];
5161 
5162 	u8         reserved_at_6e0[0x120];
5163 };
5164 
5165 struct mlx5_ifc_query_q_counter_in_bits {
5166 	u8         opcode[0x10];
5167 	u8         reserved_at_10[0x10];
5168 
5169 	u8         reserved_at_20[0x10];
5170 	u8         op_mod[0x10];
5171 
5172 	u8         reserved_at_40[0x80];
5173 
5174 	u8         clear[0x1];
5175 	u8         reserved_at_c1[0x1f];
5176 
5177 	u8         reserved_at_e0[0x18];
5178 	u8         counter_set_id[0x8];
5179 };
5180 
5181 struct mlx5_ifc_query_pages_out_bits {
5182 	u8         status[0x8];
5183 	u8         reserved_at_8[0x18];
5184 
5185 	u8         syndrome[0x20];
5186 
5187 	u8         embedded_cpu_function[0x1];
5188 	u8         reserved_at_41[0xf];
5189 	u8         function_id[0x10];
5190 
5191 	u8         num_pages[0x20];
5192 };
5193 
5194 enum {
5195 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5196 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5197 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5198 };
5199 
5200 struct mlx5_ifc_query_pages_in_bits {
5201 	u8         opcode[0x10];
5202 	u8         reserved_at_10[0x10];
5203 
5204 	u8         reserved_at_20[0x10];
5205 	u8         op_mod[0x10];
5206 
5207 	u8         embedded_cpu_function[0x1];
5208 	u8         reserved_at_41[0xf];
5209 	u8         function_id[0x10];
5210 
5211 	u8         reserved_at_60[0x20];
5212 };
5213 
5214 struct mlx5_ifc_query_nic_vport_context_out_bits {
5215 	u8         status[0x8];
5216 	u8         reserved_at_8[0x18];
5217 
5218 	u8         syndrome[0x20];
5219 
5220 	u8         reserved_at_40[0x40];
5221 
5222 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5223 };
5224 
5225 struct mlx5_ifc_query_nic_vport_context_in_bits {
5226 	u8         opcode[0x10];
5227 	u8         reserved_at_10[0x10];
5228 
5229 	u8         reserved_at_20[0x10];
5230 	u8         op_mod[0x10];
5231 
5232 	u8         other_vport[0x1];
5233 	u8         reserved_at_41[0xf];
5234 	u8         vport_number[0x10];
5235 
5236 	u8         reserved_at_60[0x5];
5237 	u8         allowed_list_type[0x3];
5238 	u8         reserved_at_68[0x18];
5239 };
5240 
5241 struct mlx5_ifc_query_mkey_out_bits {
5242 	u8         status[0x8];
5243 	u8         reserved_at_8[0x18];
5244 
5245 	u8         syndrome[0x20];
5246 
5247 	u8         reserved_at_40[0x40];
5248 
5249 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5250 
5251 	u8         reserved_at_280[0x600];
5252 
5253 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5254 
5255 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5256 };
5257 
5258 struct mlx5_ifc_query_mkey_in_bits {
5259 	u8         opcode[0x10];
5260 	u8         reserved_at_10[0x10];
5261 
5262 	u8         reserved_at_20[0x10];
5263 	u8         op_mod[0x10];
5264 
5265 	u8         reserved_at_40[0x8];
5266 	u8         mkey_index[0x18];
5267 
5268 	u8         pg_access[0x1];
5269 	u8         reserved_at_61[0x1f];
5270 };
5271 
5272 struct mlx5_ifc_query_mad_demux_out_bits {
5273 	u8         status[0x8];
5274 	u8         reserved_at_8[0x18];
5275 
5276 	u8         syndrome[0x20];
5277 
5278 	u8         reserved_at_40[0x40];
5279 
5280 	u8         mad_dumux_parameters_block[0x20];
5281 };
5282 
5283 struct mlx5_ifc_query_mad_demux_in_bits {
5284 	u8         opcode[0x10];
5285 	u8         reserved_at_10[0x10];
5286 
5287 	u8         reserved_at_20[0x10];
5288 	u8         op_mod[0x10];
5289 
5290 	u8         reserved_at_40[0x40];
5291 };
5292 
5293 struct mlx5_ifc_query_l2_table_entry_out_bits {
5294 	u8         status[0x8];
5295 	u8         reserved_at_8[0x18];
5296 
5297 	u8         syndrome[0x20];
5298 
5299 	u8         reserved_at_40[0xa0];
5300 
5301 	u8         reserved_at_e0[0x13];
5302 	u8         vlan_valid[0x1];
5303 	u8         vlan[0xc];
5304 
5305 	struct mlx5_ifc_mac_address_layout_bits mac_address;
5306 
5307 	u8         reserved_at_140[0xc0];
5308 };
5309 
5310 struct mlx5_ifc_query_l2_table_entry_in_bits {
5311 	u8         opcode[0x10];
5312 	u8         reserved_at_10[0x10];
5313 
5314 	u8         reserved_at_20[0x10];
5315 	u8         op_mod[0x10];
5316 
5317 	u8         reserved_at_40[0x60];
5318 
5319 	u8         reserved_at_a0[0x8];
5320 	u8         table_index[0x18];
5321 
5322 	u8         reserved_at_c0[0x140];
5323 };
5324 
5325 struct mlx5_ifc_query_issi_out_bits {
5326 	u8         status[0x8];
5327 	u8         reserved_at_8[0x18];
5328 
5329 	u8         syndrome[0x20];
5330 
5331 	u8         reserved_at_40[0x10];
5332 	u8         current_issi[0x10];
5333 
5334 	u8         reserved_at_60[0xa0];
5335 
5336 	u8         reserved_at_100[76][0x8];
5337 	u8         supported_issi_dw0[0x20];
5338 };
5339 
5340 struct mlx5_ifc_query_issi_in_bits {
5341 	u8         opcode[0x10];
5342 	u8         reserved_at_10[0x10];
5343 
5344 	u8         reserved_at_20[0x10];
5345 	u8         op_mod[0x10];
5346 
5347 	u8         reserved_at_40[0x40];
5348 };
5349 
5350 struct mlx5_ifc_set_driver_version_out_bits {
5351 	u8         status[0x8];
5352 	u8         reserved_0[0x18];
5353 
5354 	u8         syndrome[0x20];
5355 	u8         reserved_1[0x40];
5356 };
5357 
5358 struct mlx5_ifc_set_driver_version_in_bits {
5359 	u8         opcode[0x10];
5360 	u8         reserved_0[0x10];
5361 
5362 	u8         reserved_1[0x10];
5363 	u8         op_mod[0x10];
5364 
5365 	u8         reserved_2[0x40];
5366 	u8         driver_version[64][0x8];
5367 };
5368 
5369 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5370 	u8         status[0x8];
5371 	u8         reserved_at_8[0x18];
5372 
5373 	u8         syndrome[0x20];
5374 
5375 	u8         reserved_at_40[0x40];
5376 
5377 	struct mlx5_ifc_pkey_bits pkey[];
5378 };
5379 
5380 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5381 	u8         opcode[0x10];
5382 	u8         reserved_at_10[0x10];
5383 
5384 	u8         reserved_at_20[0x10];
5385 	u8         op_mod[0x10];
5386 
5387 	u8         other_vport[0x1];
5388 	u8         reserved_at_41[0xb];
5389 	u8         port_num[0x4];
5390 	u8         vport_number[0x10];
5391 
5392 	u8         reserved_at_60[0x10];
5393 	u8         pkey_index[0x10];
5394 };
5395 
5396 enum {
5397 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
5398 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
5399 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
5400 };
5401 
5402 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5403 	u8         status[0x8];
5404 	u8         reserved_at_8[0x18];
5405 
5406 	u8         syndrome[0x20];
5407 
5408 	u8         reserved_at_40[0x20];
5409 
5410 	u8         gids_num[0x10];
5411 	u8         reserved_at_70[0x10];
5412 
5413 	struct mlx5_ifc_array128_auto_bits gid[];
5414 };
5415 
5416 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5417 	u8         opcode[0x10];
5418 	u8         reserved_at_10[0x10];
5419 
5420 	u8         reserved_at_20[0x10];
5421 	u8         op_mod[0x10];
5422 
5423 	u8         other_vport[0x1];
5424 	u8         reserved_at_41[0xb];
5425 	u8         port_num[0x4];
5426 	u8         vport_number[0x10];
5427 
5428 	u8         reserved_at_60[0x10];
5429 	u8         gid_index[0x10];
5430 };
5431 
5432 struct mlx5_ifc_query_hca_vport_context_out_bits {
5433 	u8         status[0x8];
5434 	u8         reserved_at_8[0x18];
5435 
5436 	u8         syndrome[0x20];
5437 
5438 	u8         reserved_at_40[0x40];
5439 
5440 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5441 };
5442 
5443 struct mlx5_ifc_query_hca_vport_context_in_bits {
5444 	u8         opcode[0x10];
5445 	u8         reserved_at_10[0x10];
5446 
5447 	u8         reserved_at_20[0x10];
5448 	u8         op_mod[0x10];
5449 
5450 	u8         other_vport[0x1];
5451 	u8         reserved_at_41[0xb];
5452 	u8         port_num[0x4];
5453 	u8         vport_number[0x10];
5454 
5455 	u8         reserved_at_60[0x20];
5456 };
5457 
5458 struct mlx5_ifc_query_hca_cap_out_bits {
5459 	u8         status[0x8];
5460 	u8         reserved_at_8[0x18];
5461 
5462 	u8         syndrome[0x20];
5463 
5464 	u8         reserved_at_40[0x40];
5465 
5466 	union mlx5_ifc_hca_cap_union_bits capability;
5467 };
5468 
5469 struct mlx5_ifc_query_hca_cap_in_bits {
5470 	u8         opcode[0x10];
5471 	u8         reserved_at_10[0x10];
5472 
5473 	u8         reserved_at_20[0x10];
5474 	u8         op_mod[0x10];
5475 
5476 	u8         other_function[0x1];
5477 	u8         reserved_at_41[0xf];
5478 	u8         function_id[0x10];
5479 
5480 	u8         reserved_at_60[0x20];
5481 };
5482 
5483 struct mlx5_ifc_other_hca_cap_bits {
5484 	u8         roce[0x1];
5485 	u8         reserved_at_1[0x27f];
5486 };
5487 
5488 struct mlx5_ifc_query_other_hca_cap_out_bits {
5489 	u8         status[0x8];
5490 	u8         reserved_at_8[0x18];
5491 
5492 	u8         syndrome[0x20];
5493 
5494 	u8         reserved_at_40[0x40];
5495 
5496 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
5497 };
5498 
5499 struct mlx5_ifc_query_other_hca_cap_in_bits {
5500 	u8         opcode[0x10];
5501 	u8         reserved_at_10[0x10];
5502 
5503 	u8         reserved_at_20[0x10];
5504 	u8         op_mod[0x10];
5505 
5506 	u8         reserved_at_40[0x10];
5507 	u8         function_id[0x10];
5508 
5509 	u8         reserved_at_60[0x20];
5510 };
5511 
5512 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5513 	u8         status[0x8];
5514 	u8         reserved_at_8[0x18];
5515 
5516 	u8         syndrome[0x20];
5517 
5518 	u8         reserved_at_40[0x40];
5519 };
5520 
5521 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5522 	u8         opcode[0x10];
5523 	u8         reserved_at_10[0x10];
5524 
5525 	u8         reserved_at_20[0x10];
5526 	u8         op_mod[0x10];
5527 
5528 	u8         reserved_at_40[0x10];
5529 	u8         function_id[0x10];
5530 	u8         field_select[0x20];
5531 
5532 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
5533 };
5534 
5535 struct mlx5_ifc_flow_table_context_bits {
5536 	u8         reformat_en[0x1];
5537 	u8         decap_en[0x1];
5538 	u8         sw_owner[0x1];
5539 	u8         termination_table[0x1];
5540 	u8         table_miss_action[0x4];
5541 	u8         level[0x8];
5542 	u8         reserved_at_10[0x8];
5543 	u8         log_size[0x8];
5544 
5545 	u8         reserved_at_20[0x8];
5546 	u8         table_miss_id[0x18];
5547 
5548 	u8         reserved_at_40[0x8];
5549 	u8         lag_master_next_table_id[0x18];
5550 
5551 	u8         reserved_at_60[0x60];
5552 
5553 	u8         sw_owner_icm_root_1[0x40];
5554 
5555 	u8         sw_owner_icm_root_0[0x40];
5556 
5557 };
5558 
5559 struct mlx5_ifc_query_flow_table_out_bits {
5560 	u8         status[0x8];
5561 	u8         reserved_at_8[0x18];
5562 
5563 	u8         syndrome[0x20];
5564 
5565 	u8         reserved_at_40[0x80];
5566 
5567 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
5568 };
5569 
5570 struct mlx5_ifc_query_flow_table_in_bits {
5571 	u8         opcode[0x10];
5572 	u8         reserved_at_10[0x10];
5573 
5574 	u8         reserved_at_20[0x10];
5575 	u8         op_mod[0x10];
5576 
5577 	u8         reserved_at_40[0x40];
5578 
5579 	u8         table_type[0x8];
5580 	u8         reserved_at_88[0x18];
5581 
5582 	u8         reserved_at_a0[0x8];
5583 	u8         table_id[0x18];
5584 
5585 	u8         reserved_at_c0[0x140];
5586 };
5587 
5588 struct mlx5_ifc_query_fte_out_bits {
5589 	u8         status[0x8];
5590 	u8         reserved_at_8[0x18];
5591 
5592 	u8         syndrome[0x20];
5593 
5594 	u8         reserved_at_40[0x1c0];
5595 
5596 	struct mlx5_ifc_flow_context_bits flow_context;
5597 };
5598 
5599 struct mlx5_ifc_query_fte_in_bits {
5600 	u8         opcode[0x10];
5601 	u8         reserved_at_10[0x10];
5602 
5603 	u8         reserved_at_20[0x10];
5604 	u8         op_mod[0x10];
5605 
5606 	u8         reserved_at_40[0x40];
5607 
5608 	u8         table_type[0x8];
5609 	u8         reserved_at_88[0x18];
5610 
5611 	u8         reserved_at_a0[0x8];
5612 	u8         table_id[0x18];
5613 
5614 	u8         reserved_at_c0[0x40];
5615 
5616 	u8         flow_index[0x20];
5617 
5618 	u8         reserved_at_120[0xe0];
5619 };
5620 
5621 enum {
5622 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5623 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5624 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5625 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5626 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5627 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
5628 };
5629 
5630 struct mlx5_ifc_query_flow_group_out_bits {
5631 	u8         status[0x8];
5632 	u8         reserved_at_8[0x18];
5633 
5634 	u8         syndrome[0x20];
5635 
5636 	u8         reserved_at_40[0xa0];
5637 
5638 	u8         start_flow_index[0x20];
5639 
5640 	u8         reserved_at_100[0x20];
5641 
5642 	u8         end_flow_index[0x20];
5643 
5644 	u8         reserved_at_140[0xa0];
5645 
5646 	u8         reserved_at_1e0[0x18];
5647 	u8         match_criteria_enable[0x8];
5648 
5649 	struct mlx5_ifc_fte_match_param_bits match_criteria;
5650 
5651 	u8         reserved_at_1200[0xe00];
5652 };
5653 
5654 struct mlx5_ifc_query_flow_group_in_bits {
5655 	u8         opcode[0x10];
5656 	u8         reserved_at_10[0x10];
5657 
5658 	u8         reserved_at_20[0x10];
5659 	u8         op_mod[0x10];
5660 
5661 	u8         reserved_at_40[0x40];
5662 
5663 	u8         table_type[0x8];
5664 	u8         reserved_at_88[0x18];
5665 
5666 	u8         reserved_at_a0[0x8];
5667 	u8         table_id[0x18];
5668 
5669 	u8         group_id[0x20];
5670 
5671 	u8         reserved_at_e0[0x120];
5672 };
5673 
5674 struct mlx5_ifc_query_flow_counter_out_bits {
5675 	u8         status[0x8];
5676 	u8         reserved_at_8[0x18];
5677 
5678 	u8         syndrome[0x20];
5679 
5680 	u8         reserved_at_40[0x40];
5681 
5682 	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
5683 };
5684 
5685 struct mlx5_ifc_query_flow_counter_in_bits {
5686 	u8         opcode[0x10];
5687 	u8         reserved_at_10[0x10];
5688 
5689 	u8         reserved_at_20[0x10];
5690 	u8         op_mod[0x10];
5691 
5692 	u8         reserved_at_40[0x80];
5693 
5694 	u8         clear[0x1];
5695 	u8         reserved_at_c1[0xf];
5696 	u8         num_of_counters[0x10];
5697 
5698 	u8         flow_counter_id[0x20];
5699 };
5700 
5701 struct mlx5_ifc_query_esw_vport_context_out_bits {
5702 	u8         status[0x8];
5703 	u8         reserved_at_8[0x18];
5704 
5705 	u8         syndrome[0x20];
5706 
5707 	u8         reserved_at_40[0x40];
5708 
5709 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5710 };
5711 
5712 struct mlx5_ifc_query_esw_vport_context_in_bits {
5713 	u8         opcode[0x10];
5714 	u8         reserved_at_10[0x10];
5715 
5716 	u8         reserved_at_20[0x10];
5717 	u8         op_mod[0x10];
5718 
5719 	u8         other_vport[0x1];
5720 	u8         reserved_at_41[0xf];
5721 	u8         vport_number[0x10];
5722 
5723 	u8         reserved_at_60[0x20];
5724 };
5725 
5726 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5727 	u8         status[0x8];
5728 	u8         reserved_at_8[0x18];
5729 
5730 	u8         syndrome[0x20];
5731 
5732 	u8         reserved_at_40[0x40];
5733 };
5734 
5735 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5736 	u8         reserved_at_0[0x1b];
5737 	u8         fdb_to_vport_reg_c_id[0x1];
5738 	u8         vport_cvlan_insert[0x1];
5739 	u8         vport_svlan_insert[0x1];
5740 	u8         vport_cvlan_strip[0x1];
5741 	u8         vport_svlan_strip[0x1];
5742 };
5743 
5744 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5745 	u8         opcode[0x10];
5746 	u8         reserved_at_10[0x10];
5747 
5748 	u8         reserved_at_20[0x10];
5749 	u8         op_mod[0x10];
5750 
5751 	u8         other_vport[0x1];
5752 	u8         reserved_at_41[0xf];
5753 	u8         vport_number[0x10];
5754 
5755 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5756 
5757 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5758 };
5759 
5760 struct mlx5_ifc_query_eq_out_bits {
5761 	u8         status[0x8];
5762 	u8         reserved_at_8[0x18];
5763 
5764 	u8         syndrome[0x20];
5765 
5766 	u8         reserved_at_40[0x40];
5767 
5768 	struct mlx5_ifc_eqc_bits eq_context_entry;
5769 
5770 	u8         reserved_at_280[0x40];
5771 
5772 	u8         event_bitmask[0x40];
5773 
5774 	u8         reserved_at_300[0x580];
5775 
5776 	u8         pas[][0x40];
5777 };
5778 
5779 struct mlx5_ifc_query_eq_in_bits {
5780 	u8         opcode[0x10];
5781 	u8         reserved_at_10[0x10];
5782 
5783 	u8         reserved_at_20[0x10];
5784 	u8         op_mod[0x10];
5785 
5786 	u8         reserved_at_40[0x18];
5787 	u8         eq_number[0x8];
5788 
5789 	u8         reserved_at_60[0x20];
5790 };
5791 
5792 struct mlx5_ifc_packet_reformat_context_in_bits {
5793 	u8         reformat_type[0x8];
5794 	u8         reserved_at_8[0x4];
5795 	u8         reformat_param_0[0x4];
5796 	u8         reserved_at_10[0x6];
5797 	u8         reformat_data_size[0xa];
5798 
5799 	u8         reformat_param_1[0x8];
5800 	u8         reserved_at_28[0x8];
5801 	u8         reformat_data[2][0x8];
5802 
5803 	u8         more_reformat_data[][0x8];
5804 };
5805 
5806 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5807 	u8         status[0x8];
5808 	u8         reserved_at_8[0x18];
5809 
5810 	u8         syndrome[0x20];
5811 
5812 	u8         reserved_at_40[0xa0];
5813 
5814 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
5815 };
5816 
5817 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5818 	u8         opcode[0x10];
5819 	u8         reserved_at_10[0x10];
5820 
5821 	u8         reserved_at_20[0x10];
5822 	u8         op_mod[0x10];
5823 
5824 	u8         packet_reformat_id[0x20];
5825 
5826 	u8         reserved_at_60[0xa0];
5827 };
5828 
5829 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5830 	u8         status[0x8];
5831 	u8         reserved_at_8[0x18];
5832 
5833 	u8         syndrome[0x20];
5834 
5835 	u8         packet_reformat_id[0x20];
5836 
5837 	u8         reserved_at_60[0x20];
5838 };
5839 
5840 enum {
5841 	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
5842 	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
5843 	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
5844 };
5845 
5846 enum mlx5_reformat_ctx_type {
5847 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5848 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5849 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5850 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5851 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5852 	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
5853 	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
5854 };
5855 
5856 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5857 	u8         opcode[0x10];
5858 	u8         reserved_at_10[0x10];
5859 
5860 	u8         reserved_at_20[0x10];
5861 	u8         op_mod[0x10];
5862 
5863 	u8         reserved_at_40[0xa0];
5864 
5865 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5866 };
5867 
5868 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5869 	u8         status[0x8];
5870 	u8         reserved_at_8[0x18];
5871 
5872 	u8         syndrome[0x20];
5873 
5874 	u8         reserved_at_40[0x40];
5875 };
5876 
5877 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5878 	u8         opcode[0x10];
5879 	u8         reserved_at_10[0x10];
5880 
5881 	u8         reserved_20[0x10];
5882 	u8         op_mod[0x10];
5883 
5884 	u8         packet_reformat_id[0x20];
5885 
5886 	u8         reserved_60[0x20];
5887 };
5888 
5889 struct mlx5_ifc_set_action_in_bits {
5890 	u8         action_type[0x4];
5891 	u8         field[0xc];
5892 	u8         reserved_at_10[0x3];
5893 	u8         offset[0x5];
5894 	u8         reserved_at_18[0x3];
5895 	u8         length[0x5];
5896 
5897 	u8         data[0x20];
5898 };
5899 
5900 struct mlx5_ifc_add_action_in_bits {
5901 	u8         action_type[0x4];
5902 	u8         field[0xc];
5903 	u8         reserved_at_10[0x10];
5904 
5905 	u8         data[0x20];
5906 };
5907 
5908 struct mlx5_ifc_copy_action_in_bits {
5909 	u8         action_type[0x4];
5910 	u8         src_field[0xc];
5911 	u8         reserved_at_10[0x3];
5912 	u8         src_offset[0x5];
5913 	u8         reserved_at_18[0x3];
5914 	u8         length[0x5];
5915 
5916 	u8         reserved_at_20[0x4];
5917 	u8         dst_field[0xc];
5918 	u8         reserved_at_30[0x3];
5919 	u8         dst_offset[0x5];
5920 	u8         reserved_at_38[0x8];
5921 };
5922 
5923 union mlx5_ifc_set_add_copy_action_in_auto_bits {
5924 	struct mlx5_ifc_set_action_in_bits  set_action_in;
5925 	struct mlx5_ifc_add_action_in_bits  add_action_in;
5926 	struct mlx5_ifc_copy_action_in_bits copy_action_in;
5927 	u8         reserved_at_0[0x40];
5928 };
5929 
5930 enum {
5931 	MLX5_ACTION_TYPE_SET   = 0x1,
5932 	MLX5_ACTION_TYPE_ADD   = 0x2,
5933 	MLX5_ACTION_TYPE_COPY  = 0x3,
5934 };
5935 
5936 enum {
5937 	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5938 	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5939 	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5940 	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5941 	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5942 	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5943 	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5944 	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5945 	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5946 	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5947 	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5948 	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5949 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5950 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5951 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5952 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5953 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5954 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5955 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5956 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5957 	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5958 	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5959 	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5960 	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5961 	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
5962 	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
5963 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5964 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
5965 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
5966 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
5967 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
5968 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
5969 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
5970 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
5971 	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
5972 	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
5973 	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
5974 	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
5975 	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
5976 };
5977 
5978 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5979 	u8         status[0x8];
5980 	u8         reserved_at_8[0x18];
5981 
5982 	u8         syndrome[0x20];
5983 
5984 	u8         modify_header_id[0x20];
5985 
5986 	u8         reserved_at_60[0x20];
5987 };
5988 
5989 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5990 	u8         opcode[0x10];
5991 	u8         reserved_at_10[0x10];
5992 
5993 	u8         reserved_at_20[0x10];
5994 	u8         op_mod[0x10];
5995 
5996 	u8         reserved_at_40[0x20];
5997 
5998 	u8         table_type[0x8];
5999 	u8         reserved_at_68[0x10];
6000 	u8         num_of_actions[0x8];
6001 
6002 	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6003 };
6004 
6005 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6006 	u8         status[0x8];
6007 	u8         reserved_at_8[0x18];
6008 
6009 	u8         syndrome[0x20];
6010 
6011 	u8         reserved_at_40[0x40];
6012 };
6013 
6014 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6015 	u8         opcode[0x10];
6016 	u8         reserved_at_10[0x10];
6017 
6018 	u8         reserved_at_20[0x10];
6019 	u8         op_mod[0x10];
6020 
6021 	u8         modify_header_id[0x20];
6022 
6023 	u8         reserved_at_60[0x20];
6024 };
6025 
6026 struct mlx5_ifc_query_modify_header_context_in_bits {
6027 	u8         opcode[0x10];
6028 	u8         uid[0x10];
6029 
6030 	u8         reserved_at_20[0x10];
6031 	u8         op_mod[0x10];
6032 
6033 	u8         modify_header_id[0x20];
6034 
6035 	u8         reserved_at_60[0xa0];
6036 };
6037 
6038 struct mlx5_ifc_query_dct_out_bits {
6039 	u8         status[0x8];
6040 	u8         reserved_at_8[0x18];
6041 
6042 	u8         syndrome[0x20];
6043 
6044 	u8         reserved_at_40[0x40];
6045 
6046 	struct mlx5_ifc_dctc_bits dct_context_entry;
6047 
6048 	u8         reserved_at_280[0x180];
6049 };
6050 
6051 struct mlx5_ifc_query_dct_in_bits {
6052 	u8         opcode[0x10];
6053 	u8         reserved_at_10[0x10];
6054 
6055 	u8         reserved_at_20[0x10];
6056 	u8         op_mod[0x10];
6057 
6058 	u8         reserved_at_40[0x8];
6059 	u8         dctn[0x18];
6060 
6061 	u8         reserved_at_60[0x20];
6062 };
6063 
6064 struct mlx5_ifc_query_cq_out_bits {
6065 	u8         status[0x8];
6066 	u8         reserved_at_8[0x18];
6067 
6068 	u8         syndrome[0x20];
6069 
6070 	u8         reserved_at_40[0x40];
6071 
6072 	struct mlx5_ifc_cqc_bits cq_context;
6073 
6074 	u8         reserved_at_280[0x600];
6075 
6076 	u8         pas[][0x40];
6077 };
6078 
6079 struct mlx5_ifc_query_cq_in_bits {
6080 	u8         opcode[0x10];
6081 	u8         reserved_at_10[0x10];
6082 
6083 	u8         reserved_at_20[0x10];
6084 	u8         op_mod[0x10];
6085 
6086 	u8         reserved_at_40[0x8];
6087 	u8         cqn[0x18];
6088 
6089 	u8         reserved_at_60[0x20];
6090 };
6091 
6092 struct mlx5_ifc_query_cong_status_out_bits {
6093 	u8         status[0x8];
6094 	u8         reserved_at_8[0x18];
6095 
6096 	u8         syndrome[0x20];
6097 
6098 	u8         reserved_at_40[0x20];
6099 
6100 	u8         enable[0x1];
6101 	u8         tag_enable[0x1];
6102 	u8         reserved_at_62[0x1e];
6103 };
6104 
6105 struct mlx5_ifc_query_cong_status_in_bits {
6106 	u8         opcode[0x10];
6107 	u8         reserved_at_10[0x10];
6108 
6109 	u8         reserved_at_20[0x10];
6110 	u8         op_mod[0x10];
6111 
6112 	u8         reserved_at_40[0x18];
6113 	u8         priority[0x4];
6114 	u8         cong_protocol[0x4];
6115 
6116 	u8         reserved_at_60[0x20];
6117 };
6118 
6119 struct mlx5_ifc_query_cong_statistics_out_bits {
6120 	u8         status[0x8];
6121 	u8         reserved_at_8[0x18];
6122 
6123 	u8         syndrome[0x20];
6124 
6125 	u8         reserved_at_40[0x40];
6126 
6127 	u8         rp_cur_flows[0x20];
6128 
6129 	u8         sum_flows[0x20];
6130 
6131 	u8         rp_cnp_ignored_high[0x20];
6132 
6133 	u8         rp_cnp_ignored_low[0x20];
6134 
6135 	u8         rp_cnp_handled_high[0x20];
6136 
6137 	u8         rp_cnp_handled_low[0x20];
6138 
6139 	u8         reserved_at_140[0x100];
6140 
6141 	u8         time_stamp_high[0x20];
6142 
6143 	u8         time_stamp_low[0x20];
6144 
6145 	u8         accumulators_period[0x20];
6146 
6147 	u8         np_ecn_marked_roce_packets_high[0x20];
6148 
6149 	u8         np_ecn_marked_roce_packets_low[0x20];
6150 
6151 	u8         np_cnp_sent_high[0x20];
6152 
6153 	u8         np_cnp_sent_low[0x20];
6154 
6155 	u8         reserved_at_320[0x560];
6156 };
6157 
6158 struct mlx5_ifc_query_cong_statistics_in_bits {
6159 	u8         opcode[0x10];
6160 	u8         reserved_at_10[0x10];
6161 
6162 	u8         reserved_at_20[0x10];
6163 	u8         op_mod[0x10];
6164 
6165 	u8         clear[0x1];
6166 	u8         reserved_at_41[0x1f];
6167 
6168 	u8         reserved_at_60[0x20];
6169 };
6170 
6171 struct mlx5_ifc_query_cong_params_out_bits {
6172 	u8         status[0x8];
6173 	u8         reserved_at_8[0x18];
6174 
6175 	u8         syndrome[0x20];
6176 
6177 	u8         reserved_at_40[0x40];
6178 
6179 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6180 };
6181 
6182 struct mlx5_ifc_query_cong_params_in_bits {
6183 	u8         opcode[0x10];
6184 	u8         reserved_at_10[0x10];
6185 
6186 	u8         reserved_at_20[0x10];
6187 	u8         op_mod[0x10];
6188 
6189 	u8         reserved_at_40[0x1c];
6190 	u8         cong_protocol[0x4];
6191 
6192 	u8         reserved_at_60[0x20];
6193 };
6194 
6195 struct mlx5_ifc_query_adapter_out_bits {
6196 	u8         status[0x8];
6197 	u8         reserved_at_8[0x18];
6198 
6199 	u8         syndrome[0x20];
6200 
6201 	u8         reserved_at_40[0x40];
6202 
6203 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6204 };
6205 
6206 struct mlx5_ifc_query_adapter_in_bits {
6207 	u8         opcode[0x10];
6208 	u8         reserved_at_10[0x10];
6209 
6210 	u8         reserved_at_20[0x10];
6211 	u8         op_mod[0x10];
6212 
6213 	u8         reserved_at_40[0x40];
6214 };
6215 
6216 struct mlx5_ifc_qp_2rst_out_bits {
6217 	u8         status[0x8];
6218 	u8         reserved_at_8[0x18];
6219 
6220 	u8         syndrome[0x20];
6221 
6222 	u8         reserved_at_40[0x40];
6223 };
6224 
6225 struct mlx5_ifc_qp_2rst_in_bits {
6226 	u8         opcode[0x10];
6227 	u8         uid[0x10];
6228 
6229 	u8         reserved_at_20[0x10];
6230 	u8         op_mod[0x10];
6231 
6232 	u8         reserved_at_40[0x8];
6233 	u8         qpn[0x18];
6234 
6235 	u8         reserved_at_60[0x20];
6236 };
6237 
6238 struct mlx5_ifc_qp_2err_out_bits {
6239 	u8         status[0x8];
6240 	u8         reserved_at_8[0x18];
6241 
6242 	u8         syndrome[0x20];
6243 
6244 	u8         reserved_at_40[0x40];
6245 };
6246 
6247 struct mlx5_ifc_qp_2err_in_bits {
6248 	u8         opcode[0x10];
6249 	u8         uid[0x10];
6250 
6251 	u8         reserved_at_20[0x10];
6252 	u8         op_mod[0x10];
6253 
6254 	u8         reserved_at_40[0x8];
6255 	u8         qpn[0x18];
6256 
6257 	u8         reserved_at_60[0x20];
6258 };
6259 
6260 struct mlx5_ifc_page_fault_resume_out_bits {
6261 	u8         status[0x8];
6262 	u8         reserved_at_8[0x18];
6263 
6264 	u8         syndrome[0x20];
6265 
6266 	u8         reserved_at_40[0x40];
6267 };
6268 
6269 struct mlx5_ifc_page_fault_resume_in_bits {
6270 	u8         opcode[0x10];
6271 	u8         reserved_at_10[0x10];
6272 
6273 	u8         reserved_at_20[0x10];
6274 	u8         op_mod[0x10];
6275 
6276 	u8         error[0x1];
6277 	u8         reserved_at_41[0x4];
6278 	u8         page_fault_type[0x3];
6279 	u8         wq_number[0x18];
6280 
6281 	u8         reserved_at_60[0x8];
6282 	u8         token[0x18];
6283 };
6284 
6285 struct mlx5_ifc_nop_out_bits {
6286 	u8         status[0x8];
6287 	u8         reserved_at_8[0x18];
6288 
6289 	u8         syndrome[0x20];
6290 
6291 	u8         reserved_at_40[0x40];
6292 };
6293 
6294 struct mlx5_ifc_nop_in_bits {
6295 	u8         opcode[0x10];
6296 	u8         reserved_at_10[0x10];
6297 
6298 	u8         reserved_at_20[0x10];
6299 	u8         op_mod[0x10];
6300 
6301 	u8         reserved_at_40[0x40];
6302 };
6303 
6304 struct mlx5_ifc_modify_vport_state_out_bits {
6305 	u8         status[0x8];
6306 	u8         reserved_at_8[0x18];
6307 
6308 	u8         syndrome[0x20];
6309 
6310 	u8         reserved_at_40[0x40];
6311 };
6312 
6313 struct mlx5_ifc_modify_vport_state_in_bits {
6314 	u8         opcode[0x10];
6315 	u8         reserved_at_10[0x10];
6316 
6317 	u8         reserved_at_20[0x10];
6318 	u8         op_mod[0x10];
6319 
6320 	u8         other_vport[0x1];
6321 	u8         reserved_at_41[0xf];
6322 	u8         vport_number[0x10];
6323 
6324 	u8         reserved_at_60[0x18];
6325 	u8         admin_state[0x4];
6326 	u8         reserved_at_7c[0x4];
6327 };
6328 
6329 struct mlx5_ifc_modify_tis_out_bits {
6330 	u8         status[0x8];
6331 	u8         reserved_at_8[0x18];
6332 
6333 	u8         syndrome[0x20];
6334 
6335 	u8         reserved_at_40[0x40];
6336 };
6337 
6338 struct mlx5_ifc_modify_tis_bitmask_bits {
6339 	u8         reserved_at_0[0x20];
6340 
6341 	u8         reserved_at_20[0x1d];
6342 	u8         lag_tx_port_affinity[0x1];
6343 	u8         strict_lag_tx_port_affinity[0x1];
6344 	u8         prio[0x1];
6345 };
6346 
6347 struct mlx5_ifc_modify_tis_in_bits {
6348 	u8         opcode[0x10];
6349 	u8         uid[0x10];
6350 
6351 	u8         reserved_at_20[0x10];
6352 	u8         op_mod[0x10];
6353 
6354 	u8         reserved_at_40[0x8];
6355 	u8         tisn[0x18];
6356 
6357 	u8         reserved_at_60[0x20];
6358 
6359 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6360 
6361 	u8         reserved_at_c0[0x40];
6362 
6363 	struct mlx5_ifc_tisc_bits ctx;
6364 };
6365 
6366 struct mlx5_ifc_modify_tir_bitmask_bits {
6367 	u8	   reserved_at_0[0x20];
6368 
6369 	u8         reserved_at_20[0x1b];
6370 	u8         self_lb_en[0x1];
6371 	u8         reserved_at_3c[0x1];
6372 	u8         hash[0x1];
6373 	u8         reserved_at_3e[0x1];
6374 	u8         packet_merge[0x1];
6375 };
6376 
6377 struct mlx5_ifc_modify_tir_out_bits {
6378 	u8         status[0x8];
6379 	u8         reserved_at_8[0x18];
6380 
6381 	u8         syndrome[0x20];
6382 
6383 	u8         reserved_at_40[0x40];
6384 };
6385 
6386 struct mlx5_ifc_modify_tir_in_bits {
6387 	u8         opcode[0x10];
6388 	u8         uid[0x10];
6389 
6390 	u8         reserved_at_20[0x10];
6391 	u8         op_mod[0x10];
6392 
6393 	u8         reserved_at_40[0x8];
6394 	u8         tirn[0x18];
6395 
6396 	u8         reserved_at_60[0x20];
6397 
6398 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6399 
6400 	u8         reserved_at_c0[0x40];
6401 
6402 	struct mlx5_ifc_tirc_bits ctx;
6403 };
6404 
6405 struct mlx5_ifc_modify_sq_out_bits {
6406 	u8         status[0x8];
6407 	u8         reserved_at_8[0x18];
6408 
6409 	u8         syndrome[0x20];
6410 
6411 	u8         reserved_at_40[0x40];
6412 };
6413 
6414 struct mlx5_ifc_modify_sq_in_bits {
6415 	u8         opcode[0x10];
6416 	u8         uid[0x10];
6417 
6418 	u8         reserved_at_20[0x10];
6419 	u8         op_mod[0x10];
6420 
6421 	u8         sq_state[0x4];
6422 	u8         reserved_at_44[0x4];
6423 	u8         sqn[0x18];
6424 
6425 	u8         reserved_at_60[0x20];
6426 
6427 	u8         modify_bitmask[0x40];
6428 
6429 	u8         reserved_at_c0[0x40];
6430 
6431 	struct mlx5_ifc_sqc_bits ctx;
6432 };
6433 
6434 struct mlx5_ifc_modify_scheduling_element_out_bits {
6435 	u8         status[0x8];
6436 	u8         reserved_at_8[0x18];
6437 
6438 	u8         syndrome[0x20];
6439 
6440 	u8         reserved_at_40[0x1c0];
6441 };
6442 
6443 enum {
6444 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6445 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6446 };
6447 
6448 struct mlx5_ifc_modify_scheduling_element_in_bits {
6449 	u8         opcode[0x10];
6450 	u8         reserved_at_10[0x10];
6451 
6452 	u8         reserved_at_20[0x10];
6453 	u8         op_mod[0x10];
6454 
6455 	u8         scheduling_hierarchy[0x8];
6456 	u8         reserved_at_48[0x18];
6457 
6458 	u8         scheduling_element_id[0x20];
6459 
6460 	u8         reserved_at_80[0x20];
6461 
6462 	u8         modify_bitmask[0x20];
6463 
6464 	u8         reserved_at_c0[0x40];
6465 
6466 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
6467 
6468 	u8         reserved_at_300[0x100];
6469 };
6470 
6471 struct mlx5_ifc_modify_rqt_out_bits {
6472 	u8         status[0x8];
6473 	u8         reserved_at_8[0x18];
6474 
6475 	u8         syndrome[0x20];
6476 
6477 	u8         reserved_at_40[0x40];
6478 };
6479 
6480 struct mlx5_ifc_rqt_bitmask_bits {
6481 	u8	   reserved_at_0[0x20];
6482 
6483 	u8         reserved_at_20[0x1f];
6484 	u8         rqn_list[0x1];
6485 };
6486 
6487 struct mlx5_ifc_modify_rqt_in_bits {
6488 	u8         opcode[0x10];
6489 	u8         uid[0x10];
6490 
6491 	u8         reserved_at_20[0x10];
6492 	u8         op_mod[0x10];
6493 
6494 	u8         reserved_at_40[0x8];
6495 	u8         rqtn[0x18];
6496 
6497 	u8         reserved_at_60[0x20];
6498 
6499 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
6500 
6501 	u8         reserved_at_c0[0x40];
6502 
6503 	struct mlx5_ifc_rqtc_bits ctx;
6504 };
6505 
6506 struct mlx5_ifc_modify_rq_out_bits {
6507 	u8         status[0x8];
6508 	u8         reserved_at_8[0x18];
6509 
6510 	u8         syndrome[0x20];
6511 
6512 	u8         reserved_at_40[0x40];
6513 };
6514 
6515 enum {
6516 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6517 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6518 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6519 };
6520 
6521 struct mlx5_ifc_modify_rq_in_bits {
6522 	u8         opcode[0x10];
6523 	u8         uid[0x10];
6524 
6525 	u8         reserved_at_20[0x10];
6526 	u8         op_mod[0x10];
6527 
6528 	u8         rq_state[0x4];
6529 	u8         reserved_at_44[0x4];
6530 	u8         rqn[0x18];
6531 
6532 	u8         reserved_at_60[0x20];
6533 
6534 	u8         modify_bitmask[0x40];
6535 
6536 	u8         reserved_at_c0[0x40];
6537 
6538 	struct mlx5_ifc_rqc_bits ctx;
6539 };
6540 
6541 struct mlx5_ifc_modify_rmp_out_bits {
6542 	u8         status[0x8];
6543 	u8         reserved_at_8[0x18];
6544 
6545 	u8         syndrome[0x20];
6546 
6547 	u8         reserved_at_40[0x40];
6548 };
6549 
6550 struct mlx5_ifc_rmp_bitmask_bits {
6551 	u8	   reserved_at_0[0x20];
6552 
6553 	u8         reserved_at_20[0x1f];
6554 	u8         lwm[0x1];
6555 };
6556 
6557 struct mlx5_ifc_modify_rmp_in_bits {
6558 	u8         opcode[0x10];
6559 	u8         uid[0x10];
6560 
6561 	u8         reserved_at_20[0x10];
6562 	u8         op_mod[0x10];
6563 
6564 	u8         rmp_state[0x4];
6565 	u8         reserved_at_44[0x4];
6566 	u8         rmpn[0x18];
6567 
6568 	u8         reserved_at_60[0x20];
6569 
6570 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
6571 
6572 	u8         reserved_at_c0[0x40];
6573 
6574 	struct mlx5_ifc_rmpc_bits ctx;
6575 };
6576 
6577 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6578 	u8         status[0x8];
6579 	u8         reserved_at_8[0x18];
6580 
6581 	u8         syndrome[0x20];
6582 
6583 	u8         reserved_at_40[0x40];
6584 };
6585 
6586 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6587 	u8         reserved_at_0[0x12];
6588 	u8	   affiliation[0x1];
6589 	u8	   reserved_at_13[0x1];
6590 	u8         disable_uc_local_lb[0x1];
6591 	u8         disable_mc_local_lb[0x1];
6592 	u8         node_guid[0x1];
6593 	u8         port_guid[0x1];
6594 	u8         min_inline[0x1];
6595 	u8         mtu[0x1];
6596 	u8         change_event[0x1];
6597 	u8         promisc[0x1];
6598 	u8         permanent_address[0x1];
6599 	u8         addresses_list[0x1];
6600 	u8         roce_en[0x1];
6601 	u8         reserved_at_1f[0x1];
6602 };
6603 
6604 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6605 	u8         opcode[0x10];
6606 	u8         reserved_at_10[0x10];
6607 
6608 	u8         reserved_at_20[0x10];
6609 	u8         op_mod[0x10];
6610 
6611 	u8         other_vport[0x1];
6612 	u8         reserved_at_41[0xf];
6613 	u8         vport_number[0x10];
6614 
6615 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6616 
6617 	u8         reserved_at_80[0x780];
6618 
6619 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6620 };
6621 
6622 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6623 	u8         status[0x8];
6624 	u8         reserved_at_8[0x18];
6625 
6626 	u8         syndrome[0x20];
6627 
6628 	u8         reserved_at_40[0x40];
6629 };
6630 
6631 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6632 	u8         opcode[0x10];
6633 	u8         reserved_at_10[0x10];
6634 
6635 	u8         reserved_at_20[0x10];
6636 	u8         op_mod[0x10];
6637 
6638 	u8         other_vport[0x1];
6639 	u8         reserved_at_41[0xb];
6640 	u8         port_num[0x4];
6641 	u8         vport_number[0x10];
6642 
6643 	u8         reserved_at_60[0x20];
6644 
6645 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6646 };
6647 
6648 struct mlx5_ifc_modify_cq_out_bits {
6649 	u8         status[0x8];
6650 	u8         reserved_at_8[0x18];
6651 
6652 	u8         syndrome[0x20];
6653 
6654 	u8         reserved_at_40[0x40];
6655 };
6656 
6657 enum {
6658 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6659 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6660 };
6661 
6662 struct mlx5_ifc_modify_cq_in_bits {
6663 	u8         opcode[0x10];
6664 	u8         uid[0x10];
6665 
6666 	u8         reserved_at_20[0x10];
6667 	u8         op_mod[0x10];
6668 
6669 	u8         reserved_at_40[0x8];
6670 	u8         cqn[0x18];
6671 
6672 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6673 
6674 	struct mlx5_ifc_cqc_bits cq_context;
6675 
6676 	u8         reserved_at_280[0x60];
6677 
6678 	u8         cq_umem_valid[0x1];
6679 	u8         reserved_at_2e1[0x1f];
6680 
6681 	u8         reserved_at_300[0x580];
6682 
6683 	u8         pas[][0x40];
6684 };
6685 
6686 struct mlx5_ifc_modify_cong_status_out_bits {
6687 	u8         status[0x8];
6688 	u8         reserved_at_8[0x18];
6689 
6690 	u8         syndrome[0x20];
6691 
6692 	u8         reserved_at_40[0x40];
6693 };
6694 
6695 struct mlx5_ifc_modify_cong_status_in_bits {
6696 	u8         opcode[0x10];
6697 	u8         reserved_at_10[0x10];
6698 
6699 	u8         reserved_at_20[0x10];
6700 	u8         op_mod[0x10];
6701 
6702 	u8         reserved_at_40[0x18];
6703 	u8         priority[0x4];
6704 	u8         cong_protocol[0x4];
6705 
6706 	u8         enable[0x1];
6707 	u8         tag_enable[0x1];
6708 	u8         reserved_at_62[0x1e];
6709 };
6710 
6711 struct mlx5_ifc_modify_cong_params_out_bits {
6712 	u8         status[0x8];
6713 	u8         reserved_at_8[0x18];
6714 
6715 	u8         syndrome[0x20];
6716 
6717 	u8         reserved_at_40[0x40];
6718 };
6719 
6720 struct mlx5_ifc_modify_cong_params_in_bits {
6721 	u8         opcode[0x10];
6722 	u8         reserved_at_10[0x10];
6723 
6724 	u8         reserved_at_20[0x10];
6725 	u8         op_mod[0x10];
6726 
6727 	u8         reserved_at_40[0x1c];
6728 	u8         cong_protocol[0x4];
6729 
6730 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6731 
6732 	u8         reserved_at_80[0x80];
6733 
6734 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6735 };
6736 
6737 struct mlx5_ifc_manage_pages_out_bits {
6738 	u8         status[0x8];
6739 	u8         reserved_at_8[0x18];
6740 
6741 	u8         syndrome[0x20];
6742 
6743 	u8         output_num_entries[0x20];
6744 
6745 	u8         reserved_at_60[0x20];
6746 
6747 	u8         pas[][0x40];
6748 };
6749 
6750 enum {
6751 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6752 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6753 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6754 };
6755 
6756 struct mlx5_ifc_manage_pages_in_bits {
6757 	u8         opcode[0x10];
6758 	u8         reserved_at_10[0x10];
6759 
6760 	u8         reserved_at_20[0x10];
6761 	u8         op_mod[0x10];
6762 
6763 	u8         embedded_cpu_function[0x1];
6764 	u8         reserved_at_41[0xf];
6765 	u8         function_id[0x10];
6766 
6767 	u8         input_num_entries[0x20];
6768 
6769 	u8         pas[][0x40];
6770 };
6771 
6772 struct mlx5_ifc_mad_ifc_out_bits {
6773 	u8         status[0x8];
6774 	u8         reserved_at_8[0x18];
6775 
6776 	u8         syndrome[0x20];
6777 
6778 	u8         reserved_at_40[0x40];
6779 
6780 	u8         response_mad_packet[256][0x8];
6781 };
6782 
6783 struct mlx5_ifc_mad_ifc_in_bits {
6784 	u8         opcode[0x10];
6785 	u8         reserved_at_10[0x10];
6786 
6787 	u8         reserved_at_20[0x10];
6788 	u8         op_mod[0x10];
6789 
6790 	u8         remote_lid[0x10];
6791 	u8         reserved_at_50[0x8];
6792 	u8         port[0x8];
6793 
6794 	u8         reserved_at_60[0x20];
6795 
6796 	u8         mad[256][0x8];
6797 };
6798 
6799 struct mlx5_ifc_init_hca_out_bits {
6800 	u8         status[0x8];
6801 	u8         reserved_at_8[0x18];
6802 
6803 	u8         syndrome[0x20];
6804 
6805 	u8         reserved_at_40[0x40];
6806 };
6807 
6808 struct mlx5_ifc_init_hca_in_bits {
6809 	u8         opcode[0x10];
6810 	u8         reserved_at_10[0x10];
6811 
6812 	u8         reserved_at_20[0x10];
6813 	u8         op_mod[0x10];
6814 
6815 	u8         reserved_at_40[0x40];
6816 	u8	   sw_owner_id[4][0x20];
6817 };
6818 
6819 struct mlx5_ifc_init2rtr_qp_out_bits {
6820 	u8         status[0x8];
6821 	u8         reserved_at_8[0x18];
6822 
6823 	u8         syndrome[0x20];
6824 
6825 	u8         reserved_at_40[0x20];
6826 	u8         ece[0x20];
6827 };
6828 
6829 struct mlx5_ifc_init2rtr_qp_in_bits {
6830 	u8         opcode[0x10];
6831 	u8         uid[0x10];
6832 
6833 	u8         reserved_at_20[0x10];
6834 	u8         op_mod[0x10];
6835 
6836 	u8         reserved_at_40[0x8];
6837 	u8         qpn[0x18];
6838 
6839 	u8         reserved_at_60[0x20];
6840 
6841 	u8         opt_param_mask[0x20];
6842 
6843 	u8         ece[0x20];
6844 
6845 	struct mlx5_ifc_qpc_bits qpc;
6846 
6847 	u8         reserved_at_800[0x80];
6848 };
6849 
6850 struct mlx5_ifc_init2init_qp_out_bits {
6851 	u8         status[0x8];
6852 	u8         reserved_at_8[0x18];
6853 
6854 	u8         syndrome[0x20];
6855 
6856 	u8         reserved_at_40[0x20];
6857 	u8         ece[0x20];
6858 };
6859 
6860 struct mlx5_ifc_init2init_qp_in_bits {
6861 	u8         opcode[0x10];
6862 	u8         uid[0x10];
6863 
6864 	u8         reserved_at_20[0x10];
6865 	u8         op_mod[0x10];
6866 
6867 	u8         reserved_at_40[0x8];
6868 	u8         qpn[0x18];
6869 
6870 	u8         reserved_at_60[0x20];
6871 
6872 	u8         opt_param_mask[0x20];
6873 
6874 	u8         ece[0x20];
6875 
6876 	struct mlx5_ifc_qpc_bits qpc;
6877 
6878 	u8         reserved_at_800[0x80];
6879 };
6880 
6881 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6882 	u8         status[0x8];
6883 	u8         reserved_at_8[0x18];
6884 
6885 	u8         syndrome[0x20];
6886 
6887 	u8         reserved_at_40[0x40];
6888 
6889 	u8         packet_headers_log[128][0x8];
6890 
6891 	u8         packet_syndrome[64][0x8];
6892 };
6893 
6894 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6895 	u8         opcode[0x10];
6896 	u8         reserved_at_10[0x10];
6897 
6898 	u8         reserved_at_20[0x10];
6899 	u8         op_mod[0x10];
6900 
6901 	u8         reserved_at_40[0x40];
6902 };
6903 
6904 struct mlx5_ifc_gen_eqe_in_bits {
6905 	u8         opcode[0x10];
6906 	u8         reserved_at_10[0x10];
6907 
6908 	u8         reserved_at_20[0x10];
6909 	u8         op_mod[0x10];
6910 
6911 	u8         reserved_at_40[0x18];
6912 	u8         eq_number[0x8];
6913 
6914 	u8         reserved_at_60[0x20];
6915 
6916 	u8         eqe[64][0x8];
6917 };
6918 
6919 struct mlx5_ifc_gen_eq_out_bits {
6920 	u8         status[0x8];
6921 	u8         reserved_at_8[0x18];
6922 
6923 	u8         syndrome[0x20];
6924 
6925 	u8         reserved_at_40[0x40];
6926 };
6927 
6928 struct mlx5_ifc_enable_hca_out_bits {
6929 	u8         status[0x8];
6930 	u8         reserved_at_8[0x18];
6931 
6932 	u8         syndrome[0x20];
6933 
6934 	u8         reserved_at_40[0x20];
6935 };
6936 
6937 struct mlx5_ifc_enable_hca_in_bits {
6938 	u8         opcode[0x10];
6939 	u8         reserved_at_10[0x10];
6940 
6941 	u8         reserved_at_20[0x10];
6942 	u8         op_mod[0x10];
6943 
6944 	u8         embedded_cpu_function[0x1];
6945 	u8         reserved_at_41[0xf];
6946 	u8         function_id[0x10];
6947 
6948 	u8         reserved_at_60[0x20];
6949 };
6950 
6951 struct mlx5_ifc_drain_dct_out_bits {
6952 	u8         status[0x8];
6953 	u8         reserved_at_8[0x18];
6954 
6955 	u8         syndrome[0x20];
6956 
6957 	u8         reserved_at_40[0x40];
6958 };
6959 
6960 struct mlx5_ifc_drain_dct_in_bits {
6961 	u8         opcode[0x10];
6962 	u8         uid[0x10];
6963 
6964 	u8         reserved_at_20[0x10];
6965 	u8         op_mod[0x10];
6966 
6967 	u8         reserved_at_40[0x8];
6968 	u8         dctn[0x18];
6969 
6970 	u8         reserved_at_60[0x20];
6971 };
6972 
6973 struct mlx5_ifc_disable_hca_out_bits {
6974 	u8         status[0x8];
6975 	u8         reserved_at_8[0x18];
6976 
6977 	u8         syndrome[0x20];
6978 
6979 	u8         reserved_at_40[0x20];
6980 };
6981 
6982 struct mlx5_ifc_disable_hca_in_bits {
6983 	u8         opcode[0x10];
6984 	u8         reserved_at_10[0x10];
6985 
6986 	u8         reserved_at_20[0x10];
6987 	u8         op_mod[0x10];
6988 
6989 	u8         embedded_cpu_function[0x1];
6990 	u8         reserved_at_41[0xf];
6991 	u8         function_id[0x10];
6992 
6993 	u8         reserved_at_60[0x20];
6994 };
6995 
6996 struct mlx5_ifc_detach_from_mcg_out_bits {
6997 	u8         status[0x8];
6998 	u8         reserved_at_8[0x18];
6999 
7000 	u8         syndrome[0x20];
7001 
7002 	u8         reserved_at_40[0x40];
7003 };
7004 
7005 struct mlx5_ifc_detach_from_mcg_in_bits {
7006 	u8         opcode[0x10];
7007 	u8         uid[0x10];
7008 
7009 	u8         reserved_at_20[0x10];
7010 	u8         op_mod[0x10];
7011 
7012 	u8         reserved_at_40[0x8];
7013 	u8         qpn[0x18];
7014 
7015 	u8         reserved_at_60[0x20];
7016 
7017 	u8         multicast_gid[16][0x8];
7018 };
7019 
7020 struct mlx5_ifc_destroy_xrq_out_bits {
7021 	u8         status[0x8];
7022 	u8         reserved_at_8[0x18];
7023 
7024 	u8         syndrome[0x20];
7025 
7026 	u8         reserved_at_40[0x40];
7027 };
7028 
7029 struct mlx5_ifc_destroy_xrq_in_bits {
7030 	u8         opcode[0x10];
7031 	u8         uid[0x10];
7032 
7033 	u8         reserved_at_20[0x10];
7034 	u8         op_mod[0x10];
7035 
7036 	u8         reserved_at_40[0x8];
7037 	u8         xrqn[0x18];
7038 
7039 	u8         reserved_at_60[0x20];
7040 };
7041 
7042 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7043 	u8         status[0x8];
7044 	u8         reserved_at_8[0x18];
7045 
7046 	u8         syndrome[0x20];
7047 
7048 	u8         reserved_at_40[0x40];
7049 };
7050 
7051 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7052 	u8         opcode[0x10];
7053 	u8         uid[0x10];
7054 
7055 	u8         reserved_at_20[0x10];
7056 	u8         op_mod[0x10];
7057 
7058 	u8         reserved_at_40[0x8];
7059 	u8         xrc_srqn[0x18];
7060 
7061 	u8         reserved_at_60[0x20];
7062 };
7063 
7064 struct mlx5_ifc_destroy_tis_out_bits {
7065 	u8         status[0x8];
7066 	u8         reserved_at_8[0x18];
7067 
7068 	u8         syndrome[0x20];
7069 
7070 	u8         reserved_at_40[0x40];
7071 };
7072 
7073 struct mlx5_ifc_destroy_tis_in_bits {
7074 	u8         opcode[0x10];
7075 	u8         uid[0x10];
7076 
7077 	u8         reserved_at_20[0x10];
7078 	u8         op_mod[0x10];
7079 
7080 	u8         reserved_at_40[0x8];
7081 	u8         tisn[0x18];
7082 
7083 	u8         reserved_at_60[0x20];
7084 };
7085 
7086 struct mlx5_ifc_destroy_tir_out_bits {
7087 	u8         status[0x8];
7088 	u8         reserved_at_8[0x18];
7089 
7090 	u8         syndrome[0x20];
7091 
7092 	u8         reserved_at_40[0x40];
7093 };
7094 
7095 struct mlx5_ifc_destroy_tir_in_bits {
7096 	u8         opcode[0x10];
7097 	u8         uid[0x10];
7098 
7099 	u8         reserved_at_20[0x10];
7100 	u8         op_mod[0x10];
7101 
7102 	u8         reserved_at_40[0x8];
7103 	u8         tirn[0x18];
7104 
7105 	u8         reserved_at_60[0x20];
7106 };
7107 
7108 struct mlx5_ifc_destroy_srq_out_bits {
7109 	u8         status[0x8];
7110 	u8         reserved_at_8[0x18];
7111 
7112 	u8         syndrome[0x20];
7113 
7114 	u8         reserved_at_40[0x40];
7115 };
7116 
7117 struct mlx5_ifc_destroy_srq_in_bits {
7118 	u8         opcode[0x10];
7119 	u8         uid[0x10];
7120 
7121 	u8         reserved_at_20[0x10];
7122 	u8         op_mod[0x10];
7123 
7124 	u8         reserved_at_40[0x8];
7125 	u8         srqn[0x18];
7126 
7127 	u8         reserved_at_60[0x20];
7128 };
7129 
7130 struct mlx5_ifc_destroy_sq_out_bits {
7131 	u8         status[0x8];
7132 	u8         reserved_at_8[0x18];
7133 
7134 	u8         syndrome[0x20];
7135 
7136 	u8         reserved_at_40[0x40];
7137 };
7138 
7139 struct mlx5_ifc_destroy_sq_in_bits {
7140 	u8         opcode[0x10];
7141 	u8         uid[0x10];
7142 
7143 	u8         reserved_at_20[0x10];
7144 	u8         op_mod[0x10];
7145 
7146 	u8         reserved_at_40[0x8];
7147 	u8         sqn[0x18];
7148 
7149 	u8         reserved_at_60[0x20];
7150 };
7151 
7152 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7153 	u8         status[0x8];
7154 	u8         reserved_at_8[0x18];
7155 
7156 	u8         syndrome[0x20];
7157 
7158 	u8         reserved_at_40[0x1c0];
7159 };
7160 
7161 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7162 	u8         opcode[0x10];
7163 	u8         reserved_at_10[0x10];
7164 
7165 	u8         reserved_at_20[0x10];
7166 	u8         op_mod[0x10];
7167 
7168 	u8         scheduling_hierarchy[0x8];
7169 	u8         reserved_at_48[0x18];
7170 
7171 	u8         scheduling_element_id[0x20];
7172 
7173 	u8         reserved_at_80[0x180];
7174 };
7175 
7176 struct mlx5_ifc_destroy_rqt_out_bits {
7177 	u8         status[0x8];
7178 	u8         reserved_at_8[0x18];
7179 
7180 	u8         syndrome[0x20];
7181 
7182 	u8         reserved_at_40[0x40];
7183 };
7184 
7185 struct mlx5_ifc_destroy_rqt_in_bits {
7186 	u8         opcode[0x10];
7187 	u8         uid[0x10];
7188 
7189 	u8         reserved_at_20[0x10];
7190 	u8         op_mod[0x10];
7191 
7192 	u8         reserved_at_40[0x8];
7193 	u8         rqtn[0x18];
7194 
7195 	u8         reserved_at_60[0x20];
7196 };
7197 
7198 struct mlx5_ifc_destroy_rq_out_bits {
7199 	u8         status[0x8];
7200 	u8         reserved_at_8[0x18];
7201 
7202 	u8         syndrome[0x20];
7203 
7204 	u8         reserved_at_40[0x40];
7205 };
7206 
7207 struct mlx5_ifc_destroy_rq_in_bits {
7208 	u8         opcode[0x10];
7209 	u8         uid[0x10];
7210 
7211 	u8         reserved_at_20[0x10];
7212 	u8         op_mod[0x10];
7213 
7214 	u8         reserved_at_40[0x8];
7215 	u8         rqn[0x18];
7216 
7217 	u8         reserved_at_60[0x20];
7218 };
7219 
7220 struct mlx5_ifc_set_delay_drop_params_in_bits {
7221 	u8         opcode[0x10];
7222 	u8         reserved_at_10[0x10];
7223 
7224 	u8         reserved_at_20[0x10];
7225 	u8         op_mod[0x10];
7226 
7227 	u8         reserved_at_40[0x20];
7228 
7229 	u8         reserved_at_60[0x10];
7230 	u8         delay_drop_timeout[0x10];
7231 };
7232 
7233 struct mlx5_ifc_set_delay_drop_params_out_bits {
7234 	u8         status[0x8];
7235 	u8         reserved_at_8[0x18];
7236 
7237 	u8         syndrome[0x20];
7238 
7239 	u8         reserved_at_40[0x40];
7240 };
7241 
7242 struct mlx5_ifc_destroy_rmp_out_bits {
7243 	u8         status[0x8];
7244 	u8         reserved_at_8[0x18];
7245 
7246 	u8         syndrome[0x20];
7247 
7248 	u8         reserved_at_40[0x40];
7249 };
7250 
7251 struct mlx5_ifc_destroy_rmp_in_bits {
7252 	u8         opcode[0x10];
7253 	u8         uid[0x10];
7254 
7255 	u8         reserved_at_20[0x10];
7256 	u8         op_mod[0x10];
7257 
7258 	u8         reserved_at_40[0x8];
7259 	u8         rmpn[0x18];
7260 
7261 	u8         reserved_at_60[0x20];
7262 };
7263 
7264 struct mlx5_ifc_destroy_qp_out_bits {
7265 	u8         status[0x8];
7266 	u8         reserved_at_8[0x18];
7267 
7268 	u8         syndrome[0x20];
7269 
7270 	u8         reserved_at_40[0x40];
7271 };
7272 
7273 struct mlx5_ifc_destroy_qp_in_bits {
7274 	u8         opcode[0x10];
7275 	u8         uid[0x10];
7276 
7277 	u8         reserved_at_20[0x10];
7278 	u8         op_mod[0x10];
7279 
7280 	u8         reserved_at_40[0x8];
7281 	u8         qpn[0x18];
7282 
7283 	u8         reserved_at_60[0x20];
7284 };
7285 
7286 struct mlx5_ifc_destroy_psv_out_bits {
7287 	u8         status[0x8];
7288 	u8         reserved_at_8[0x18];
7289 
7290 	u8         syndrome[0x20];
7291 
7292 	u8         reserved_at_40[0x40];
7293 };
7294 
7295 struct mlx5_ifc_destroy_psv_in_bits {
7296 	u8         opcode[0x10];
7297 	u8         reserved_at_10[0x10];
7298 
7299 	u8         reserved_at_20[0x10];
7300 	u8         op_mod[0x10];
7301 
7302 	u8         reserved_at_40[0x8];
7303 	u8         psvn[0x18];
7304 
7305 	u8         reserved_at_60[0x20];
7306 };
7307 
7308 struct mlx5_ifc_destroy_mkey_out_bits {
7309 	u8         status[0x8];
7310 	u8         reserved_at_8[0x18];
7311 
7312 	u8         syndrome[0x20];
7313 
7314 	u8         reserved_at_40[0x40];
7315 };
7316 
7317 struct mlx5_ifc_destroy_mkey_in_bits {
7318 	u8         opcode[0x10];
7319 	u8         uid[0x10];
7320 
7321 	u8         reserved_at_20[0x10];
7322 	u8         op_mod[0x10];
7323 
7324 	u8         reserved_at_40[0x8];
7325 	u8         mkey_index[0x18];
7326 
7327 	u8         reserved_at_60[0x20];
7328 };
7329 
7330 struct mlx5_ifc_destroy_flow_table_out_bits {
7331 	u8         status[0x8];
7332 	u8         reserved_at_8[0x18];
7333 
7334 	u8         syndrome[0x20];
7335 
7336 	u8         reserved_at_40[0x40];
7337 };
7338 
7339 struct mlx5_ifc_destroy_flow_table_in_bits {
7340 	u8         opcode[0x10];
7341 	u8         reserved_at_10[0x10];
7342 
7343 	u8         reserved_at_20[0x10];
7344 	u8         op_mod[0x10];
7345 
7346 	u8         other_vport[0x1];
7347 	u8         reserved_at_41[0xf];
7348 	u8         vport_number[0x10];
7349 
7350 	u8         reserved_at_60[0x20];
7351 
7352 	u8         table_type[0x8];
7353 	u8         reserved_at_88[0x18];
7354 
7355 	u8         reserved_at_a0[0x8];
7356 	u8         table_id[0x18];
7357 
7358 	u8         reserved_at_c0[0x140];
7359 };
7360 
7361 struct mlx5_ifc_destroy_flow_group_out_bits {
7362 	u8         status[0x8];
7363 	u8         reserved_at_8[0x18];
7364 
7365 	u8         syndrome[0x20];
7366 
7367 	u8         reserved_at_40[0x40];
7368 };
7369 
7370 struct mlx5_ifc_destroy_flow_group_in_bits {
7371 	u8         opcode[0x10];
7372 	u8         reserved_at_10[0x10];
7373 
7374 	u8         reserved_at_20[0x10];
7375 	u8         op_mod[0x10];
7376 
7377 	u8         other_vport[0x1];
7378 	u8         reserved_at_41[0xf];
7379 	u8         vport_number[0x10];
7380 
7381 	u8         reserved_at_60[0x20];
7382 
7383 	u8         table_type[0x8];
7384 	u8         reserved_at_88[0x18];
7385 
7386 	u8         reserved_at_a0[0x8];
7387 	u8         table_id[0x18];
7388 
7389 	u8         group_id[0x20];
7390 
7391 	u8         reserved_at_e0[0x120];
7392 };
7393 
7394 struct mlx5_ifc_destroy_eq_out_bits {
7395 	u8         status[0x8];
7396 	u8         reserved_at_8[0x18];
7397 
7398 	u8         syndrome[0x20];
7399 
7400 	u8         reserved_at_40[0x40];
7401 };
7402 
7403 struct mlx5_ifc_destroy_eq_in_bits {
7404 	u8         opcode[0x10];
7405 	u8         reserved_at_10[0x10];
7406 
7407 	u8         reserved_at_20[0x10];
7408 	u8         op_mod[0x10];
7409 
7410 	u8         reserved_at_40[0x18];
7411 	u8         eq_number[0x8];
7412 
7413 	u8         reserved_at_60[0x20];
7414 };
7415 
7416 struct mlx5_ifc_destroy_dct_out_bits {
7417 	u8         status[0x8];
7418 	u8         reserved_at_8[0x18];
7419 
7420 	u8         syndrome[0x20];
7421 
7422 	u8         reserved_at_40[0x40];
7423 };
7424 
7425 struct mlx5_ifc_destroy_dct_in_bits {
7426 	u8         opcode[0x10];
7427 	u8         uid[0x10];
7428 
7429 	u8         reserved_at_20[0x10];
7430 	u8         op_mod[0x10];
7431 
7432 	u8         reserved_at_40[0x8];
7433 	u8         dctn[0x18];
7434 
7435 	u8         reserved_at_60[0x20];
7436 };
7437 
7438 struct mlx5_ifc_destroy_cq_out_bits {
7439 	u8         status[0x8];
7440 	u8         reserved_at_8[0x18];
7441 
7442 	u8         syndrome[0x20];
7443 
7444 	u8         reserved_at_40[0x40];
7445 };
7446 
7447 struct mlx5_ifc_destroy_cq_in_bits {
7448 	u8         opcode[0x10];
7449 	u8         uid[0x10];
7450 
7451 	u8         reserved_at_20[0x10];
7452 	u8         op_mod[0x10];
7453 
7454 	u8         reserved_at_40[0x8];
7455 	u8         cqn[0x18];
7456 
7457 	u8         reserved_at_60[0x20];
7458 };
7459 
7460 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7461 	u8         status[0x8];
7462 	u8         reserved_at_8[0x18];
7463 
7464 	u8         syndrome[0x20];
7465 
7466 	u8         reserved_at_40[0x40];
7467 };
7468 
7469 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7470 	u8         opcode[0x10];
7471 	u8         reserved_at_10[0x10];
7472 
7473 	u8         reserved_at_20[0x10];
7474 	u8         op_mod[0x10];
7475 
7476 	u8         reserved_at_40[0x20];
7477 
7478 	u8         reserved_at_60[0x10];
7479 	u8         vxlan_udp_port[0x10];
7480 };
7481 
7482 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7483 	u8         status[0x8];
7484 	u8         reserved_at_8[0x18];
7485 
7486 	u8         syndrome[0x20];
7487 
7488 	u8         reserved_at_40[0x40];
7489 };
7490 
7491 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7492 	u8         opcode[0x10];
7493 	u8         reserved_at_10[0x10];
7494 
7495 	u8         reserved_at_20[0x10];
7496 	u8         op_mod[0x10];
7497 
7498 	u8         reserved_at_40[0x60];
7499 
7500 	u8         reserved_at_a0[0x8];
7501 	u8         table_index[0x18];
7502 
7503 	u8         reserved_at_c0[0x140];
7504 };
7505 
7506 struct mlx5_ifc_delete_fte_out_bits {
7507 	u8         status[0x8];
7508 	u8         reserved_at_8[0x18];
7509 
7510 	u8         syndrome[0x20];
7511 
7512 	u8         reserved_at_40[0x40];
7513 };
7514 
7515 struct mlx5_ifc_delete_fte_in_bits {
7516 	u8         opcode[0x10];
7517 	u8         reserved_at_10[0x10];
7518 
7519 	u8         reserved_at_20[0x10];
7520 	u8         op_mod[0x10];
7521 
7522 	u8         other_vport[0x1];
7523 	u8         reserved_at_41[0xf];
7524 	u8         vport_number[0x10];
7525 
7526 	u8         reserved_at_60[0x20];
7527 
7528 	u8         table_type[0x8];
7529 	u8         reserved_at_88[0x18];
7530 
7531 	u8         reserved_at_a0[0x8];
7532 	u8         table_id[0x18];
7533 
7534 	u8         reserved_at_c0[0x40];
7535 
7536 	u8         flow_index[0x20];
7537 
7538 	u8         reserved_at_120[0xe0];
7539 };
7540 
7541 struct mlx5_ifc_dealloc_xrcd_out_bits {
7542 	u8         status[0x8];
7543 	u8         reserved_at_8[0x18];
7544 
7545 	u8         syndrome[0x20];
7546 
7547 	u8         reserved_at_40[0x40];
7548 };
7549 
7550 struct mlx5_ifc_dealloc_xrcd_in_bits {
7551 	u8         opcode[0x10];
7552 	u8         uid[0x10];
7553 
7554 	u8         reserved_at_20[0x10];
7555 	u8         op_mod[0x10];
7556 
7557 	u8         reserved_at_40[0x8];
7558 	u8         xrcd[0x18];
7559 
7560 	u8         reserved_at_60[0x20];
7561 };
7562 
7563 struct mlx5_ifc_dealloc_uar_out_bits {
7564 	u8         status[0x8];
7565 	u8         reserved_at_8[0x18];
7566 
7567 	u8         syndrome[0x20];
7568 
7569 	u8         reserved_at_40[0x40];
7570 };
7571 
7572 struct mlx5_ifc_dealloc_uar_in_bits {
7573 	u8         opcode[0x10];
7574 	u8         reserved_at_10[0x10];
7575 
7576 	u8         reserved_at_20[0x10];
7577 	u8         op_mod[0x10];
7578 
7579 	u8         reserved_at_40[0x8];
7580 	u8         uar[0x18];
7581 
7582 	u8         reserved_at_60[0x20];
7583 };
7584 
7585 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7586 	u8         status[0x8];
7587 	u8         reserved_at_8[0x18];
7588 
7589 	u8         syndrome[0x20];
7590 
7591 	u8         reserved_at_40[0x40];
7592 };
7593 
7594 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7595 	u8         opcode[0x10];
7596 	u8         uid[0x10];
7597 
7598 	u8         reserved_at_20[0x10];
7599 	u8         op_mod[0x10];
7600 
7601 	u8         reserved_at_40[0x8];
7602 	u8         transport_domain[0x18];
7603 
7604 	u8         reserved_at_60[0x20];
7605 };
7606 
7607 struct mlx5_ifc_dealloc_q_counter_out_bits {
7608 	u8         status[0x8];
7609 	u8         reserved_at_8[0x18];
7610 
7611 	u8         syndrome[0x20];
7612 
7613 	u8         reserved_at_40[0x40];
7614 };
7615 
7616 struct mlx5_ifc_dealloc_q_counter_in_bits {
7617 	u8         opcode[0x10];
7618 	u8         reserved_at_10[0x10];
7619 
7620 	u8         reserved_at_20[0x10];
7621 	u8         op_mod[0x10];
7622 
7623 	u8         reserved_at_40[0x18];
7624 	u8         counter_set_id[0x8];
7625 
7626 	u8         reserved_at_60[0x20];
7627 };
7628 
7629 struct mlx5_ifc_dealloc_pd_out_bits {
7630 	u8         status[0x8];
7631 	u8         reserved_at_8[0x18];
7632 
7633 	u8         syndrome[0x20];
7634 
7635 	u8         reserved_at_40[0x40];
7636 };
7637 
7638 struct mlx5_ifc_dealloc_pd_in_bits {
7639 	u8         opcode[0x10];
7640 	u8         uid[0x10];
7641 
7642 	u8         reserved_at_20[0x10];
7643 	u8         op_mod[0x10];
7644 
7645 	u8         reserved_at_40[0x8];
7646 	u8         pd[0x18];
7647 
7648 	u8         reserved_at_60[0x20];
7649 };
7650 
7651 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7652 	u8         status[0x8];
7653 	u8         reserved_at_8[0x18];
7654 
7655 	u8         syndrome[0x20];
7656 
7657 	u8         reserved_at_40[0x40];
7658 };
7659 
7660 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7661 	u8         opcode[0x10];
7662 	u8         reserved_at_10[0x10];
7663 
7664 	u8         reserved_at_20[0x10];
7665 	u8         op_mod[0x10];
7666 
7667 	u8         flow_counter_id[0x20];
7668 
7669 	u8         reserved_at_60[0x20];
7670 };
7671 
7672 struct mlx5_ifc_create_xrq_out_bits {
7673 	u8         status[0x8];
7674 	u8         reserved_at_8[0x18];
7675 
7676 	u8         syndrome[0x20];
7677 
7678 	u8         reserved_at_40[0x8];
7679 	u8         xrqn[0x18];
7680 
7681 	u8         reserved_at_60[0x20];
7682 };
7683 
7684 struct mlx5_ifc_create_xrq_in_bits {
7685 	u8         opcode[0x10];
7686 	u8         uid[0x10];
7687 
7688 	u8         reserved_at_20[0x10];
7689 	u8         op_mod[0x10];
7690 
7691 	u8         reserved_at_40[0x40];
7692 
7693 	struct mlx5_ifc_xrqc_bits xrq_context;
7694 };
7695 
7696 struct mlx5_ifc_create_xrc_srq_out_bits {
7697 	u8         status[0x8];
7698 	u8         reserved_at_8[0x18];
7699 
7700 	u8         syndrome[0x20];
7701 
7702 	u8         reserved_at_40[0x8];
7703 	u8         xrc_srqn[0x18];
7704 
7705 	u8         reserved_at_60[0x20];
7706 };
7707 
7708 struct mlx5_ifc_create_xrc_srq_in_bits {
7709 	u8         opcode[0x10];
7710 	u8         uid[0x10];
7711 
7712 	u8         reserved_at_20[0x10];
7713 	u8         op_mod[0x10];
7714 
7715 	u8         reserved_at_40[0x40];
7716 
7717 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7718 
7719 	u8         reserved_at_280[0x60];
7720 
7721 	u8         xrc_srq_umem_valid[0x1];
7722 	u8         reserved_at_2e1[0x1f];
7723 
7724 	u8         reserved_at_300[0x580];
7725 
7726 	u8         pas[][0x40];
7727 };
7728 
7729 struct mlx5_ifc_create_tis_out_bits {
7730 	u8         status[0x8];
7731 	u8         reserved_at_8[0x18];
7732 
7733 	u8         syndrome[0x20];
7734 
7735 	u8         reserved_at_40[0x8];
7736 	u8         tisn[0x18];
7737 
7738 	u8         reserved_at_60[0x20];
7739 };
7740 
7741 struct mlx5_ifc_create_tis_in_bits {
7742 	u8         opcode[0x10];
7743 	u8         uid[0x10];
7744 
7745 	u8         reserved_at_20[0x10];
7746 	u8         op_mod[0x10];
7747 
7748 	u8         reserved_at_40[0xc0];
7749 
7750 	struct mlx5_ifc_tisc_bits ctx;
7751 };
7752 
7753 struct mlx5_ifc_create_tir_out_bits {
7754 	u8         status[0x8];
7755 	u8         icm_address_63_40[0x18];
7756 
7757 	u8         syndrome[0x20];
7758 
7759 	u8         icm_address_39_32[0x8];
7760 	u8         tirn[0x18];
7761 
7762 	u8         icm_address_31_0[0x20];
7763 };
7764 
7765 struct mlx5_ifc_create_tir_in_bits {
7766 	u8         opcode[0x10];
7767 	u8         uid[0x10];
7768 
7769 	u8         reserved_at_20[0x10];
7770 	u8         op_mod[0x10];
7771 
7772 	u8         reserved_at_40[0xc0];
7773 
7774 	struct mlx5_ifc_tirc_bits ctx;
7775 };
7776 
7777 struct mlx5_ifc_create_srq_out_bits {
7778 	u8         status[0x8];
7779 	u8         reserved_at_8[0x18];
7780 
7781 	u8         syndrome[0x20];
7782 
7783 	u8         reserved_at_40[0x8];
7784 	u8         srqn[0x18];
7785 
7786 	u8         reserved_at_60[0x20];
7787 };
7788 
7789 struct mlx5_ifc_create_srq_in_bits {
7790 	u8         opcode[0x10];
7791 	u8         uid[0x10];
7792 
7793 	u8         reserved_at_20[0x10];
7794 	u8         op_mod[0x10];
7795 
7796 	u8         reserved_at_40[0x40];
7797 
7798 	struct mlx5_ifc_srqc_bits srq_context_entry;
7799 
7800 	u8         reserved_at_280[0x600];
7801 
7802 	u8         pas[][0x40];
7803 };
7804 
7805 struct mlx5_ifc_create_sq_out_bits {
7806 	u8         status[0x8];
7807 	u8         reserved_at_8[0x18];
7808 
7809 	u8         syndrome[0x20];
7810 
7811 	u8         reserved_at_40[0x8];
7812 	u8         sqn[0x18];
7813 
7814 	u8         reserved_at_60[0x20];
7815 };
7816 
7817 struct mlx5_ifc_create_sq_in_bits {
7818 	u8         opcode[0x10];
7819 	u8         uid[0x10];
7820 
7821 	u8         reserved_at_20[0x10];
7822 	u8         op_mod[0x10];
7823 
7824 	u8         reserved_at_40[0xc0];
7825 
7826 	struct mlx5_ifc_sqc_bits ctx;
7827 };
7828 
7829 struct mlx5_ifc_create_scheduling_element_out_bits {
7830 	u8         status[0x8];
7831 	u8         reserved_at_8[0x18];
7832 
7833 	u8         syndrome[0x20];
7834 
7835 	u8         reserved_at_40[0x40];
7836 
7837 	u8         scheduling_element_id[0x20];
7838 
7839 	u8         reserved_at_a0[0x160];
7840 };
7841 
7842 struct mlx5_ifc_create_scheduling_element_in_bits {
7843 	u8         opcode[0x10];
7844 	u8         reserved_at_10[0x10];
7845 
7846 	u8         reserved_at_20[0x10];
7847 	u8         op_mod[0x10];
7848 
7849 	u8         scheduling_hierarchy[0x8];
7850 	u8         reserved_at_48[0x18];
7851 
7852 	u8         reserved_at_60[0xa0];
7853 
7854 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7855 
7856 	u8         reserved_at_300[0x100];
7857 };
7858 
7859 struct mlx5_ifc_create_rqt_out_bits {
7860 	u8         status[0x8];
7861 	u8         reserved_at_8[0x18];
7862 
7863 	u8         syndrome[0x20];
7864 
7865 	u8         reserved_at_40[0x8];
7866 	u8         rqtn[0x18];
7867 
7868 	u8         reserved_at_60[0x20];
7869 };
7870 
7871 struct mlx5_ifc_create_rqt_in_bits {
7872 	u8         opcode[0x10];
7873 	u8         uid[0x10];
7874 
7875 	u8         reserved_at_20[0x10];
7876 	u8         op_mod[0x10];
7877 
7878 	u8         reserved_at_40[0xc0];
7879 
7880 	struct mlx5_ifc_rqtc_bits rqt_context;
7881 };
7882 
7883 struct mlx5_ifc_create_rq_out_bits {
7884 	u8         status[0x8];
7885 	u8         reserved_at_8[0x18];
7886 
7887 	u8         syndrome[0x20];
7888 
7889 	u8         reserved_at_40[0x8];
7890 	u8         rqn[0x18];
7891 
7892 	u8         reserved_at_60[0x20];
7893 };
7894 
7895 struct mlx5_ifc_create_rq_in_bits {
7896 	u8         opcode[0x10];
7897 	u8         uid[0x10];
7898 
7899 	u8         reserved_at_20[0x10];
7900 	u8         op_mod[0x10];
7901 
7902 	u8         reserved_at_40[0xc0];
7903 
7904 	struct mlx5_ifc_rqc_bits ctx;
7905 };
7906 
7907 struct mlx5_ifc_create_rmp_out_bits {
7908 	u8         status[0x8];
7909 	u8         reserved_at_8[0x18];
7910 
7911 	u8         syndrome[0x20];
7912 
7913 	u8         reserved_at_40[0x8];
7914 	u8         rmpn[0x18];
7915 
7916 	u8         reserved_at_60[0x20];
7917 };
7918 
7919 struct mlx5_ifc_create_rmp_in_bits {
7920 	u8         opcode[0x10];
7921 	u8         uid[0x10];
7922 
7923 	u8         reserved_at_20[0x10];
7924 	u8         op_mod[0x10];
7925 
7926 	u8         reserved_at_40[0xc0];
7927 
7928 	struct mlx5_ifc_rmpc_bits ctx;
7929 };
7930 
7931 struct mlx5_ifc_create_qp_out_bits {
7932 	u8         status[0x8];
7933 	u8         reserved_at_8[0x18];
7934 
7935 	u8         syndrome[0x20];
7936 
7937 	u8         reserved_at_40[0x8];
7938 	u8         qpn[0x18];
7939 
7940 	u8         ece[0x20];
7941 };
7942 
7943 struct mlx5_ifc_create_qp_in_bits {
7944 	u8         opcode[0x10];
7945 	u8         uid[0x10];
7946 
7947 	u8         reserved_at_20[0x10];
7948 	u8         op_mod[0x10];
7949 
7950 	u8         reserved_at_40[0x8];
7951 	u8         input_qpn[0x18];
7952 
7953 	u8         reserved_at_60[0x20];
7954 	u8         opt_param_mask[0x20];
7955 
7956 	u8         ece[0x20];
7957 
7958 	struct mlx5_ifc_qpc_bits qpc;
7959 
7960 	u8         reserved_at_800[0x60];
7961 
7962 	u8         wq_umem_valid[0x1];
7963 	u8         reserved_at_861[0x1f];
7964 
7965 	u8         pas[][0x40];
7966 };
7967 
7968 struct mlx5_ifc_create_psv_out_bits {
7969 	u8         status[0x8];
7970 	u8         reserved_at_8[0x18];
7971 
7972 	u8         syndrome[0x20];
7973 
7974 	u8         reserved_at_40[0x40];
7975 
7976 	u8         reserved_at_80[0x8];
7977 	u8         psv0_index[0x18];
7978 
7979 	u8         reserved_at_a0[0x8];
7980 	u8         psv1_index[0x18];
7981 
7982 	u8         reserved_at_c0[0x8];
7983 	u8         psv2_index[0x18];
7984 
7985 	u8         reserved_at_e0[0x8];
7986 	u8         psv3_index[0x18];
7987 };
7988 
7989 struct mlx5_ifc_create_psv_in_bits {
7990 	u8         opcode[0x10];
7991 	u8         reserved_at_10[0x10];
7992 
7993 	u8         reserved_at_20[0x10];
7994 	u8         op_mod[0x10];
7995 
7996 	u8         num_psv[0x4];
7997 	u8         reserved_at_44[0x4];
7998 	u8         pd[0x18];
7999 
8000 	u8         reserved_at_60[0x20];
8001 };
8002 
8003 struct mlx5_ifc_create_mkey_out_bits {
8004 	u8         status[0x8];
8005 	u8         reserved_at_8[0x18];
8006 
8007 	u8         syndrome[0x20];
8008 
8009 	u8         reserved_at_40[0x8];
8010 	u8         mkey_index[0x18];
8011 
8012 	u8         reserved_at_60[0x20];
8013 };
8014 
8015 struct mlx5_ifc_create_mkey_in_bits {
8016 	u8         opcode[0x10];
8017 	u8         uid[0x10];
8018 
8019 	u8         reserved_at_20[0x10];
8020 	u8         op_mod[0x10];
8021 
8022 	u8         reserved_at_40[0x20];
8023 
8024 	u8         pg_access[0x1];
8025 	u8         mkey_umem_valid[0x1];
8026 	u8         reserved_at_62[0x1e];
8027 
8028 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8029 
8030 	u8         reserved_at_280[0x80];
8031 
8032 	u8         translations_octword_actual_size[0x20];
8033 
8034 	u8         reserved_at_320[0x560];
8035 
8036 	u8         klm_pas_mtt[][0x20];
8037 };
8038 
8039 enum {
8040 	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
8041 	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
8042 	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
8043 	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
8044 	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
8045 	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
8046 	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
8047 };
8048 
8049 struct mlx5_ifc_create_flow_table_out_bits {
8050 	u8         status[0x8];
8051 	u8         icm_address_63_40[0x18];
8052 
8053 	u8         syndrome[0x20];
8054 
8055 	u8         icm_address_39_32[0x8];
8056 	u8         table_id[0x18];
8057 
8058 	u8         icm_address_31_0[0x20];
8059 };
8060 
8061 struct mlx5_ifc_create_flow_table_in_bits {
8062 	u8         opcode[0x10];
8063 	u8         reserved_at_10[0x10];
8064 
8065 	u8         reserved_at_20[0x10];
8066 	u8         op_mod[0x10];
8067 
8068 	u8         other_vport[0x1];
8069 	u8         reserved_at_41[0xf];
8070 	u8         vport_number[0x10];
8071 
8072 	u8         reserved_at_60[0x20];
8073 
8074 	u8         table_type[0x8];
8075 	u8         reserved_at_88[0x18];
8076 
8077 	u8         reserved_at_a0[0x20];
8078 
8079 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
8080 };
8081 
8082 struct mlx5_ifc_create_flow_group_out_bits {
8083 	u8         status[0x8];
8084 	u8         reserved_at_8[0x18];
8085 
8086 	u8         syndrome[0x20];
8087 
8088 	u8         reserved_at_40[0x8];
8089 	u8         group_id[0x18];
8090 
8091 	u8         reserved_at_60[0x20];
8092 };
8093 
8094 enum {
8095 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8096 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8097 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8098 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8099 };
8100 
8101 struct mlx5_ifc_create_flow_group_in_bits {
8102 	u8         opcode[0x10];
8103 	u8         reserved_at_10[0x10];
8104 
8105 	u8         reserved_at_20[0x10];
8106 	u8         op_mod[0x10];
8107 
8108 	u8         other_vport[0x1];
8109 	u8         reserved_at_41[0xf];
8110 	u8         vport_number[0x10];
8111 
8112 	u8         reserved_at_60[0x20];
8113 
8114 	u8         table_type[0x8];
8115 	u8         reserved_at_88[0x18];
8116 
8117 	u8         reserved_at_a0[0x8];
8118 	u8         table_id[0x18];
8119 
8120 	u8         source_eswitch_owner_vhca_id_valid[0x1];
8121 
8122 	u8         reserved_at_c1[0x1f];
8123 
8124 	u8         start_flow_index[0x20];
8125 
8126 	u8         reserved_at_100[0x20];
8127 
8128 	u8         end_flow_index[0x20];
8129 
8130 	u8         reserved_at_140[0xa0];
8131 
8132 	u8         reserved_at_1e0[0x18];
8133 	u8         match_criteria_enable[0x8];
8134 
8135 	struct mlx5_ifc_fte_match_param_bits match_criteria;
8136 
8137 	u8         reserved_at_1200[0xe00];
8138 };
8139 
8140 struct mlx5_ifc_create_eq_out_bits {
8141 	u8         status[0x8];
8142 	u8         reserved_at_8[0x18];
8143 
8144 	u8         syndrome[0x20];
8145 
8146 	u8         reserved_at_40[0x18];
8147 	u8         eq_number[0x8];
8148 
8149 	u8         reserved_at_60[0x20];
8150 };
8151 
8152 struct mlx5_ifc_create_eq_in_bits {
8153 	u8         opcode[0x10];
8154 	u8         uid[0x10];
8155 
8156 	u8         reserved_at_20[0x10];
8157 	u8         op_mod[0x10];
8158 
8159 	u8         reserved_at_40[0x40];
8160 
8161 	struct mlx5_ifc_eqc_bits eq_context_entry;
8162 
8163 	u8         reserved_at_280[0x40];
8164 
8165 	u8         event_bitmask[4][0x40];
8166 
8167 	u8         reserved_at_3c0[0x4c0];
8168 
8169 	u8         pas[][0x40];
8170 };
8171 
8172 struct mlx5_ifc_create_dct_out_bits {
8173 	u8         status[0x8];
8174 	u8         reserved_at_8[0x18];
8175 
8176 	u8         syndrome[0x20];
8177 
8178 	u8         reserved_at_40[0x8];
8179 	u8         dctn[0x18];
8180 
8181 	u8         ece[0x20];
8182 };
8183 
8184 struct mlx5_ifc_create_dct_in_bits {
8185 	u8         opcode[0x10];
8186 	u8         uid[0x10];
8187 
8188 	u8         reserved_at_20[0x10];
8189 	u8         op_mod[0x10];
8190 
8191 	u8         reserved_at_40[0x40];
8192 
8193 	struct mlx5_ifc_dctc_bits dct_context_entry;
8194 
8195 	u8         reserved_at_280[0x180];
8196 };
8197 
8198 struct mlx5_ifc_create_cq_out_bits {
8199 	u8         status[0x8];
8200 	u8         reserved_at_8[0x18];
8201 
8202 	u8         syndrome[0x20];
8203 
8204 	u8         reserved_at_40[0x8];
8205 	u8         cqn[0x18];
8206 
8207 	u8         reserved_at_60[0x20];
8208 };
8209 
8210 struct mlx5_ifc_create_cq_in_bits {
8211 	u8         opcode[0x10];
8212 	u8         uid[0x10];
8213 
8214 	u8         reserved_at_20[0x10];
8215 	u8         op_mod[0x10];
8216 
8217 	u8         reserved_at_40[0x40];
8218 
8219 	struct mlx5_ifc_cqc_bits cq_context;
8220 
8221 	u8         reserved_at_280[0x60];
8222 
8223 	u8         cq_umem_valid[0x1];
8224 	u8         reserved_at_2e1[0x59f];
8225 
8226 	u8         pas[][0x40];
8227 };
8228 
8229 struct mlx5_ifc_config_int_moderation_out_bits {
8230 	u8         status[0x8];
8231 	u8         reserved_at_8[0x18];
8232 
8233 	u8         syndrome[0x20];
8234 
8235 	u8         reserved_at_40[0x4];
8236 	u8         min_delay[0xc];
8237 	u8         int_vector[0x10];
8238 
8239 	u8         reserved_at_60[0x20];
8240 };
8241 
8242 enum {
8243 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8244 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8245 };
8246 
8247 struct mlx5_ifc_config_int_moderation_in_bits {
8248 	u8         opcode[0x10];
8249 	u8         reserved_at_10[0x10];
8250 
8251 	u8         reserved_at_20[0x10];
8252 	u8         op_mod[0x10];
8253 
8254 	u8         reserved_at_40[0x4];
8255 	u8         min_delay[0xc];
8256 	u8         int_vector[0x10];
8257 
8258 	u8         reserved_at_60[0x20];
8259 };
8260 
8261 struct mlx5_ifc_attach_to_mcg_out_bits {
8262 	u8         status[0x8];
8263 	u8         reserved_at_8[0x18];
8264 
8265 	u8         syndrome[0x20];
8266 
8267 	u8         reserved_at_40[0x40];
8268 };
8269 
8270 struct mlx5_ifc_attach_to_mcg_in_bits {
8271 	u8         opcode[0x10];
8272 	u8         uid[0x10];
8273 
8274 	u8         reserved_at_20[0x10];
8275 	u8         op_mod[0x10];
8276 
8277 	u8         reserved_at_40[0x8];
8278 	u8         qpn[0x18];
8279 
8280 	u8         reserved_at_60[0x20];
8281 
8282 	u8         multicast_gid[16][0x8];
8283 };
8284 
8285 struct mlx5_ifc_arm_xrq_out_bits {
8286 	u8         status[0x8];
8287 	u8         reserved_at_8[0x18];
8288 
8289 	u8         syndrome[0x20];
8290 
8291 	u8         reserved_at_40[0x40];
8292 };
8293 
8294 struct mlx5_ifc_arm_xrq_in_bits {
8295 	u8         opcode[0x10];
8296 	u8         reserved_at_10[0x10];
8297 
8298 	u8         reserved_at_20[0x10];
8299 	u8         op_mod[0x10];
8300 
8301 	u8         reserved_at_40[0x8];
8302 	u8         xrqn[0x18];
8303 
8304 	u8         reserved_at_60[0x10];
8305 	u8         lwm[0x10];
8306 };
8307 
8308 struct mlx5_ifc_arm_xrc_srq_out_bits {
8309 	u8         status[0x8];
8310 	u8         reserved_at_8[0x18];
8311 
8312 	u8         syndrome[0x20];
8313 
8314 	u8         reserved_at_40[0x40];
8315 };
8316 
8317 enum {
8318 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8319 };
8320 
8321 struct mlx5_ifc_arm_xrc_srq_in_bits {
8322 	u8         opcode[0x10];
8323 	u8         uid[0x10];
8324 
8325 	u8         reserved_at_20[0x10];
8326 	u8         op_mod[0x10];
8327 
8328 	u8         reserved_at_40[0x8];
8329 	u8         xrc_srqn[0x18];
8330 
8331 	u8         reserved_at_60[0x10];
8332 	u8         lwm[0x10];
8333 };
8334 
8335 struct mlx5_ifc_arm_rq_out_bits {
8336 	u8         status[0x8];
8337 	u8         reserved_at_8[0x18];
8338 
8339 	u8         syndrome[0x20];
8340 
8341 	u8         reserved_at_40[0x40];
8342 };
8343 
8344 enum {
8345 	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8346 	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8347 };
8348 
8349 struct mlx5_ifc_arm_rq_in_bits {
8350 	u8         opcode[0x10];
8351 	u8         uid[0x10];
8352 
8353 	u8         reserved_at_20[0x10];
8354 	u8         op_mod[0x10];
8355 
8356 	u8         reserved_at_40[0x8];
8357 	u8         srq_number[0x18];
8358 
8359 	u8         reserved_at_60[0x10];
8360 	u8         lwm[0x10];
8361 };
8362 
8363 struct mlx5_ifc_arm_dct_out_bits {
8364 	u8         status[0x8];
8365 	u8         reserved_at_8[0x18];
8366 
8367 	u8         syndrome[0x20];
8368 
8369 	u8         reserved_at_40[0x40];
8370 };
8371 
8372 struct mlx5_ifc_arm_dct_in_bits {
8373 	u8         opcode[0x10];
8374 	u8         reserved_at_10[0x10];
8375 
8376 	u8         reserved_at_20[0x10];
8377 	u8         op_mod[0x10];
8378 
8379 	u8         reserved_at_40[0x8];
8380 	u8         dct_number[0x18];
8381 
8382 	u8         reserved_at_60[0x20];
8383 };
8384 
8385 struct mlx5_ifc_alloc_xrcd_out_bits {
8386 	u8         status[0x8];
8387 	u8         reserved_at_8[0x18];
8388 
8389 	u8         syndrome[0x20];
8390 
8391 	u8         reserved_at_40[0x8];
8392 	u8         xrcd[0x18];
8393 
8394 	u8         reserved_at_60[0x20];
8395 };
8396 
8397 struct mlx5_ifc_alloc_xrcd_in_bits {
8398 	u8         opcode[0x10];
8399 	u8         uid[0x10];
8400 
8401 	u8         reserved_at_20[0x10];
8402 	u8         op_mod[0x10];
8403 
8404 	u8         reserved_at_40[0x40];
8405 };
8406 
8407 struct mlx5_ifc_alloc_uar_out_bits {
8408 	u8         status[0x8];
8409 	u8         reserved_at_8[0x18];
8410 
8411 	u8         syndrome[0x20];
8412 
8413 	u8         reserved_at_40[0x8];
8414 	u8         uar[0x18];
8415 
8416 	u8         reserved_at_60[0x20];
8417 };
8418 
8419 struct mlx5_ifc_alloc_uar_in_bits {
8420 	u8         opcode[0x10];
8421 	u8         reserved_at_10[0x10];
8422 
8423 	u8         reserved_at_20[0x10];
8424 	u8         op_mod[0x10];
8425 
8426 	u8         reserved_at_40[0x40];
8427 };
8428 
8429 struct mlx5_ifc_alloc_transport_domain_out_bits {
8430 	u8         status[0x8];
8431 	u8         reserved_at_8[0x18];
8432 
8433 	u8         syndrome[0x20];
8434 
8435 	u8         reserved_at_40[0x8];
8436 	u8         transport_domain[0x18];
8437 
8438 	u8         reserved_at_60[0x20];
8439 };
8440 
8441 struct mlx5_ifc_alloc_transport_domain_in_bits {
8442 	u8         opcode[0x10];
8443 	u8         uid[0x10];
8444 
8445 	u8         reserved_at_20[0x10];
8446 	u8         op_mod[0x10];
8447 
8448 	u8         reserved_at_40[0x40];
8449 };
8450 
8451 struct mlx5_ifc_alloc_q_counter_out_bits {
8452 	u8         status[0x8];
8453 	u8         reserved_at_8[0x18];
8454 
8455 	u8         syndrome[0x20];
8456 
8457 	u8         reserved_at_40[0x18];
8458 	u8         counter_set_id[0x8];
8459 
8460 	u8         reserved_at_60[0x20];
8461 };
8462 
8463 struct mlx5_ifc_alloc_q_counter_in_bits {
8464 	u8         opcode[0x10];
8465 	u8         uid[0x10];
8466 
8467 	u8         reserved_at_20[0x10];
8468 	u8         op_mod[0x10];
8469 
8470 	u8         reserved_at_40[0x40];
8471 };
8472 
8473 struct mlx5_ifc_alloc_pd_out_bits {
8474 	u8         status[0x8];
8475 	u8         reserved_at_8[0x18];
8476 
8477 	u8         syndrome[0x20];
8478 
8479 	u8         reserved_at_40[0x8];
8480 	u8         pd[0x18];
8481 
8482 	u8         reserved_at_60[0x20];
8483 };
8484 
8485 struct mlx5_ifc_alloc_pd_in_bits {
8486 	u8         opcode[0x10];
8487 	u8         uid[0x10];
8488 
8489 	u8         reserved_at_20[0x10];
8490 	u8         op_mod[0x10];
8491 
8492 	u8         reserved_at_40[0x40];
8493 };
8494 
8495 struct mlx5_ifc_alloc_flow_counter_out_bits {
8496 	u8         status[0x8];
8497 	u8         reserved_at_8[0x18];
8498 
8499 	u8         syndrome[0x20];
8500 
8501 	u8         flow_counter_id[0x20];
8502 
8503 	u8         reserved_at_60[0x20];
8504 };
8505 
8506 struct mlx5_ifc_alloc_flow_counter_in_bits {
8507 	u8         opcode[0x10];
8508 	u8         reserved_at_10[0x10];
8509 
8510 	u8         reserved_at_20[0x10];
8511 	u8         op_mod[0x10];
8512 
8513 	u8         reserved_at_40[0x33];
8514 	u8         flow_counter_bulk_log_size[0x5];
8515 	u8         flow_counter_bulk[0x8];
8516 };
8517 
8518 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8519 	u8         status[0x8];
8520 	u8         reserved_at_8[0x18];
8521 
8522 	u8         syndrome[0x20];
8523 
8524 	u8         reserved_at_40[0x40];
8525 };
8526 
8527 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8528 	u8         opcode[0x10];
8529 	u8         reserved_at_10[0x10];
8530 
8531 	u8         reserved_at_20[0x10];
8532 	u8         op_mod[0x10];
8533 
8534 	u8         reserved_at_40[0x20];
8535 
8536 	u8         reserved_at_60[0x10];
8537 	u8         vxlan_udp_port[0x10];
8538 };
8539 
8540 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8541 	u8         status[0x8];
8542 	u8         reserved_at_8[0x18];
8543 
8544 	u8         syndrome[0x20];
8545 
8546 	u8         reserved_at_40[0x40];
8547 };
8548 
8549 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8550 	u8         rate_limit[0x20];
8551 
8552 	u8	   burst_upper_bound[0x20];
8553 
8554 	u8         reserved_at_40[0x10];
8555 	u8	   typical_packet_size[0x10];
8556 
8557 	u8         reserved_at_60[0x120];
8558 };
8559 
8560 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8561 	u8         opcode[0x10];
8562 	u8         uid[0x10];
8563 
8564 	u8         reserved_at_20[0x10];
8565 	u8         op_mod[0x10];
8566 
8567 	u8         reserved_at_40[0x10];
8568 	u8         rate_limit_index[0x10];
8569 
8570 	u8         reserved_at_60[0x20];
8571 
8572 	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8573 };
8574 
8575 struct mlx5_ifc_access_register_out_bits {
8576 	u8         status[0x8];
8577 	u8         reserved_at_8[0x18];
8578 
8579 	u8         syndrome[0x20];
8580 
8581 	u8         reserved_at_40[0x40];
8582 
8583 	u8         register_data[][0x20];
8584 };
8585 
8586 enum {
8587 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8588 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8589 };
8590 
8591 struct mlx5_ifc_access_register_in_bits {
8592 	u8         opcode[0x10];
8593 	u8         reserved_at_10[0x10];
8594 
8595 	u8         reserved_at_20[0x10];
8596 	u8         op_mod[0x10];
8597 
8598 	u8         reserved_at_40[0x10];
8599 	u8         register_id[0x10];
8600 
8601 	u8         argument[0x20];
8602 
8603 	u8         register_data[][0x20];
8604 };
8605 
8606 struct mlx5_ifc_sltp_reg_bits {
8607 	u8         status[0x4];
8608 	u8         version[0x4];
8609 	u8         local_port[0x8];
8610 	u8         pnat[0x2];
8611 	u8         reserved_at_12[0x2];
8612 	u8         lane[0x4];
8613 	u8         reserved_at_18[0x8];
8614 
8615 	u8         reserved_at_20[0x20];
8616 
8617 	u8         reserved_at_40[0x7];
8618 	u8         polarity[0x1];
8619 	u8         ob_tap0[0x8];
8620 	u8         ob_tap1[0x8];
8621 	u8         ob_tap2[0x8];
8622 
8623 	u8         reserved_at_60[0xc];
8624 	u8         ob_preemp_mode[0x4];
8625 	u8         ob_reg[0x8];
8626 	u8         ob_bias[0x8];
8627 
8628 	u8         reserved_at_80[0x20];
8629 };
8630 
8631 struct mlx5_ifc_slrg_reg_bits {
8632 	u8         status[0x4];
8633 	u8         version[0x4];
8634 	u8         local_port[0x8];
8635 	u8         pnat[0x2];
8636 	u8         reserved_at_12[0x2];
8637 	u8         lane[0x4];
8638 	u8         reserved_at_18[0x8];
8639 
8640 	u8         time_to_link_up[0x10];
8641 	u8         reserved_at_30[0xc];
8642 	u8         grade_lane_speed[0x4];
8643 
8644 	u8         grade_version[0x8];
8645 	u8         grade[0x18];
8646 
8647 	u8         reserved_at_60[0x4];
8648 	u8         height_grade_type[0x4];
8649 	u8         height_grade[0x18];
8650 
8651 	u8         height_dz[0x10];
8652 	u8         height_dv[0x10];
8653 
8654 	u8         reserved_at_a0[0x10];
8655 	u8         height_sigma[0x10];
8656 
8657 	u8         reserved_at_c0[0x20];
8658 
8659 	u8         reserved_at_e0[0x4];
8660 	u8         phase_grade_type[0x4];
8661 	u8         phase_grade[0x18];
8662 
8663 	u8         reserved_at_100[0x8];
8664 	u8         phase_eo_pos[0x8];
8665 	u8         reserved_at_110[0x8];
8666 	u8         phase_eo_neg[0x8];
8667 
8668 	u8         ffe_set_tested[0x10];
8669 	u8         test_errors_per_lane[0x10];
8670 };
8671 
8672 struct mlx5_ifc_pvlc_reg_bits {
8673 	u8         reserved_at_0[0x8];
8674 	u8         local_port[0x8];
8675 	u8         reserved_at_10[0x10];
8676 
8677 	u8         reserved_at_20[0x1c];
8678 	u8         vl_hw_cap[0x4];
8679 
8680 	u8         reserved_at_40[0x1c];
8681 	u8         vl_admin[0x4];
8682 
8683 	u8         reserved_at_60[0x1c];
8684 	u8         vl_operational[0x4];
8685 };
8686 
8687 struct mlx5_ifc_pude_reg_bits {
8688 	u8         swid[0x8];
8689 	u8         local_port[0x8];
8690 	u8         reserved_at_10[0x4];
8691 	u8         admin_status[0x4];
8692 	u8         reserved_at_18[0x4];
8693 	u8         oper_status[0x4];
8694 
8695 	u8         reserved_at_20[0x60];
8696 };
8697 
8698 struct mlx5_ifc_ptys_reg_bits {
8699 	u8         reserved_at_0[0x1];
8700 	u8         an_disable_admin[0x1];
8701 	u8         an_disable_cap[0x1];
8702 	u8         reserved_at_3[0x5];
8703 	u8         local_port[0x8];
8704 	u8         reserved_at_10[0xd];
8705 	u8         proto_mask[0x3];
8706 
8707 	u8         an_status[0x4];
8708 	u8         reserved_at_24[0xc];
8709 	u8         data_rate_oper[0x10];
8710 
8711 	u8         ext_eth_proto_capability[0x20];
8712 
8713 	u8         eth_proto_capability[0x20];
8714 
8715 	u8         ib_link_width_capability[0x10];
8716 	u8         ib_proto_capability[0x10];
8717 
8718 	u8         ext_eth_proto_admin[0x20];
8719 
8720 	u8         eth_proto_admin[0x20];
8721 
8722 	u8         ib_link_width_admin[0x10];
8723 	u8         ib_proto_admin[0x10];
8724 
8725 	u8         ext_eth_proto_oper[0x20];
8726 
8727 	u8         eth_proto_oper[0x20];
8728 
8729 	u8         ib_link_width_oper[0x10];
8730 	u8         ib_proto_oper[0x10];
8731 
8732 	u8         reserved_at_160[0x1c];
8733 	u8         connector_type[0x4];
8734 
8735 	u8         eth_proto_lp_advertise[0x20];
8736 
8737 	u8         reserved_at_1a0[0x60];
8738 };
8739 
8740 struct mlx5_ifc_mlcr_reg_bits {
8741 	u8         reserved_at_0[0x8];
8742 	u8         local_port[0x8];
8743 	u8         reserved_at_10[0x20];
8744 
8745 	u8         beacon_duration[0x10];
8746 	u8         reserved_at_40[0x10];
8747 
8748 	u8         beacon_remain[0x10];
8749 };
8750 
8751 struct mlx5_ifc_ptas_reg_bits {
8752 	u8         reserved_at_0[0x20];
8753 
8754 	u8         algorithm_options[0x10];
8755 	u8         reserved_at_30[0x4];
8756 	u8         repetitions_mode[0x4];
8757 	u8         num_of_repetitions[0x8];
8758 
8759 	u8         grade_version[0x8];
8760 	u8         height_grade_type[0x4];
8761 	u8         phase_grade_type[0x4];
8762 	u8         height_grade_weight[0x8];
8763 	u8         phase_grade_weight[0x8];
8764 
8765 	u8         gisim_measure_bits[0x10];
8766 	u8         adaptive_tap_measure_bits[0x10];
8767 
8768 	u8         ber_bath_high_error_threshold[0x10];
8769 	u8         ber_bath_mid_error_threshold[0x10];
8770 
8771 	u8         ber_bath_low_error_threshold[0x10];
8772 	u8         one_ratio_high_threshold[0x10];
8773 
8774 	u8         one_ratio_high_mid_threshold[0x10];
8775 	u8         one_ratio_low_mid_threshold[0x10];
8776 
8777 	u8         one_ratio_low_threshold[0x10];
8778 	u8         ndeo_error_threshold[0x10];
8779 
8780 	u8         mixer_offset_step_size[0x10];
8781 	u8         reserved_at_110[0x8];
8782 	u8         mix90_phase_for_voltage_bath[0x8];
8783 
8784 	u8         mixer_offset_start[0x10];
8785 	u8         mixer_offset_end[0x10];
8786 
8787 	u8         reserved_at_140[0x15];
8788 	u8         ber_test_time[0xb];
8789 };
8790 
8791 struct mlx5_ifc_pspa_reg_bits {
8792 	u8         swid[0x8];
8793 	u8         local_port[0x8];
8794 	u8         sub_port[0x8];
8795 	u8         reserved_at_18[0x8];
8796 
8797 	u8         reserved_at_20[0x20];
8798 };
8799 
8800 struct mlx5_ifc_pqdr_reg_bits {
8801 	u8         reserved_at_0[0x8];
8802 	u8         local_port[0x8];
8803 	u8         reserved_at_10[0x5];
8804 	u8         prio[0x3];
8805 	u8         reserved_at_18[0x6];
8806 	u8         mode[0x2];
8807 
8808 	u8         reserved_at_20[0x20];
8809 
8810 	u8         reserved_at_40[0x10];
8811 	u8         min_threshold[0x10];
8812 
8813 	u8         reserved_at_60[0x10];
8814 	u8         max_threshold[0x10];
8815 
8816 	u8         reserved_at_80[0x10];
8817 	u8         mark_probability_denominator[0x10];
8818 
8819 	u8         reserved_at_a0[0x60];
8820 };
8821 
8822 struct mlx5_ifc_ppsc_reg_bits {
8823 	u8         reserved_at_0[0x8];
8824 	u8         local_port[0x8];
8825 	u8         reserved_at_10[0x10];
8826 
8827 	u8         reserved_at_20[0x60];
8828 
8829 	u8         reserved_at_80[0x1c];
8830 	u8         wrps_admin[0x4];
8831 
8832 	u8         reserved_at_a0[0x1c];
8833 	u8         wrps_status[0x4];
8834 
8835 	u8         reserved_at_c0[0x8];
8836 	u8         up_threshold[0x8];
8837 	u8         reserved_at_d0[0x8];
8838 	u8         down_threshold[0x8];
8839 
8840 	u8         reserved_at_e0[0x20];
8841 
8842 	u8         reserved_at_100[0x1c];
8843 	u8         srps_admin[0x4];
8844 
8845 	u8         reserved_at_120[0x1c];
8846 	u8         srps_status[0x4];
8847 
8848 	u8         reserved_at_140[0x40];
8849 };
8850 
8851 struct mlx5_ifc_pplr_reg_bits {
8852 	u8         reserved_at_0[0x8];
8853 	u8         local_port[0x8];
8854 	u8         reserved_at_10[0x10];
8855 
8856 	u8         reserved_at_20[0x8];
8857 	u8         lb_cap[0x8];
8858 	u8         reserved_at_30[0x8];
8859 	u8         lb_en[0x8];
8860 };
8861 
8862 struct mlx5_ifc_pplm_reg_bits {
8863 	u8         reserved_at_0[0x8];
8864 	u8	   local_port[0x8];
8865 	u8	   reserved_at_10[0x10];
8866 
8867 	u8	   reserved_at_20[0x20];
8868 
8869 	u8	   port_profile_mode[0x8];
8870 	u8	   static_port_profile[0x8];
8871 	u8	   active_port_profile[0x8];
8872 	u8	   reserved_at_58[0x8];
8873 
8874 	u8	   retransmission_active[0x8];
8875 	u8	   fec_mode_active[0x18];
8876 
8877 	u8	   rs_fec_correction_bypass_cap[0x4];
8878 	u8	   reserved_at_84[0x8];
8879 	u8	   fec_override_cap_56g[0x4];
8880 	u8	   fec_override_cap_100g[0x4];
8881 	u8	   fec_override_cap_50g[0x4];
8882 	u8	   fec_override_cap_25g[0x4];
8883 	u8	   fec_override_cap_10g_40g[0x4];
8884 
8885 	u8	   rs_fec_correction_bypass_admin[0x4];
8886 	u8	   reserved_at_a4[0x8];
8887 	u8	   fec_override_admin_56g[0x4];
8888 	u8	   fec_override_admin_100g[0x4];
8889 	u8	   fec_override_admin_50g[0x4];
8890 	u8	   fec_override_admin_25g[0x4];
8891 	u8	   fec_override_admin_10g_40g[0x4];
8892 
8893 	u8         fec_override_cap_400g_8x[0x10];
8894 	u8         fec_override_cap_200g_4x[0x10];
8895 
8896 	u8         fec_override_cap_100g_2x[0x10];
8897 	u8         fec_override_cap_50g_1x[0x10];
8898 
8899 	u8         fec_override_admin_400g_8x[0x10];
8900 	u8         fec_override_admin_200g_4x[0x10];
8901 
8902 	u8         fec_override_admin_100g_2x[0x10];
8903 	u8         fec_override_admin_50g_1x[0x10];
8904 
8905 	u8         reserved_at_140[0x140];
8906 };
8907 
8908 struct mlx5_ifc_ppcnt_reg_bits {
8909 	u8         swid[0x8];
8910 	u8         local_port[0x8];
8911 	u8         pnat[0x2];
8912 	u8         reserved_at_12[0x8];
8913 	u8         grp[0x6];
8914 
8915 	u8         clr[0x1];
8916 	u8         reserved_at_21[0x1c];
8917 	u8         prio_tc[0x3];
8918 
8919 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8920 };
8921 
8922 struct mlx5_ifc_mpein_reg_bits {
8923 	u8         reserved_at_0[0x2];
8924 	u8         depth[0x6];
8925 	u8         pcie_index[0x8];
8926 	u8         node[0x8];
8927 	u8         reserved_at_18[0x8];
8928 
8929 	u8         capability_mask[0x20];
8930 
8931 	u8         reserved_at_40[0x8];
8932 	u8         link_width_enabled[0x8];
8933 	u8         link_speed_enabled[0x10];
8934 
8935 	u8         lane0_physical_position[0x8];
8936 	u8         link_width_active[0x8];
8937 	u8         link_speed_active[0x10];
8938 
8939 	u8         num_of_pfs[0x10];
8940 	u8         num_of_vfs[0x10];
8941 
8942 	u8         bdf0[0x10];
8943 	u8         reserved_at_b0[0x10];
8944 
8945 	u8         max_read_request_size[0x4];
8946 	u8         max_payload_size[0x4];
8947 	u8         reserved_at_c8[0x5];
8948 	u8         pwr_status[0x3];
8949 	u8         port_type[0x4];
8950 	u8         reserved_at_d4[0xb];
8951 	u8         lane_reversal[0x1];
8952 
8953 	u8         reserved_at_e0[0x14];
8954 	u8         pci_power[0xc];
8955 
8956 	u8         reserved_at_100[0x20];
8957 
8958 	u8         device_status[0x10];
8959 	u8         port_state[0x8];
8960 	u8         reserved_at_138[0x8];
8961 
8962 	u8         reserved_at_140[0x10];
8963 	u8         receiver_detect_result[0x10];
8964 
8965 	u8         reserved_at_160[0x20];
8966 };
8967 
8968 struct mlx5_ifc_mpcnt_reg_bits {
8969 	u8         reserved_at_0[0x8];
8970 	u8         pcie_index[0x8];
8971 	u8         reserved_at_10[0xa];
8972 	u8         grp[0x6];
8973 
8974 	u8         clr[0x1];
8975 	u8         reserved_at_21[0x1f];
8976 
8977 	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8978 };
8979 
8980 struct mlx5_ifc_ppad_reg_bits {
8981 	u8         reserved_at_0[0x3];
8982 	u8         single_mac[0x1];
8983 	u8         reserved_at_4[0x4];
8984 	u8         local_port[0x8];
8985 	u8         mac_47_32[0x10];
8986 
8987 	u8         mac_31_0[0x20];
8988 
8989 	u8         reserved_at_40[0x40];
8990 };
8991 
8992 struct mlx5_ifc_pmtu_reg_bits {
8993 	u8         reserved_at_0[0x8];
8994 	u8         local_port[0x8];
8995 	u8         reserved_at_10[0x10];
8996 
8997 	u8         max_mtu[0x10];
8998 	u8         reserved_at_30[0x10];
8999 
9000 	u8         admin_mtu[0x10];
9001 	u8         reserved_at_50[0x10];
9002 
9003 	u8         oper_mtu[0x10];
9004 	u8         reserved_at_70[0x10];
9005 };
9006 
9007 struct mlx5_ifc_pmpr_reg_bits {
9008 	u8         reserved_at_0[0x8];
9009 	u8         module[0x8];
9010 	u8         reserved_at_10[0x10];
9011 
9012 	u8         reserved_at_20[0x18];
9013 	u8         attenuation_5g[0x8];
9014 
9015 	u8         reserved_at_40[0x18];
9016 	u8         attenuation_7g[0x8];
9017 
9018 	u8         reserved_at_60[0x18];
9019 	u8         attenuation_12g[0x8];
9020 };
9021 
9022 struct mlx5_ifc_pmpe_reg_bits {
9023 	u8         reserved_at_0[0x8];
9024 	u8         module[0x8];
9025 	u8         reserved_at_10[0xc];
9026 	u8         module_status[0x4];
9027 
9028 	u8         reserved_at_20[0x60];
9029 };
9030 
9031 struct mlx5_ifc_pmpc_reg_bits {
9032 	u8         module_state_updated[32][0x8];
9033 };
9034 
9035 struct mlx5_ifc_pmlpn_reg_bits {
9036 	u8         reserved_at_0[0x4];
9037 	u8         mlpn_status[0x4];
9038 	u8         local_port[0x8];
9039 	u8         reserved_at_10[0x10];
9040 
9041 	u8         e[0x1];
9042 	u8         reserved_at_21[0x1f];
9043 };
9044 
9045 struct mlx5_ifc_pmlp_reg_bits {
9046 	u8         rxtx[0x1];
9047 	u8         reserved_at_1[0x7];
9048 	u8         local_port[0x8];
9049 	u8         reserved_at_10[0x8];
9050 	u8         width[0x8];
9051 
9052 	u8         lane0_module_mapping[0x20];
9053 
9054 	u8         lane1_module_mapping[0x20];
9055 
9056 	u8         lane2_module_mapping[0x20];
9057 
9058 	u8         lane3_module_mapping[0x20];
9059 
9060 	u8         reserved_at_a0[0x160];
9061 };
9062 
9063 struct mlx5_ifc_pmaos_reg_bits {
9064 	u8         reserved_at_0[0x8];
9065 	u8         module[0x8];
9066 	u8         reserved_at_10[0x4];
9067 	u8         admin_status[0x4];
9068 	u8         reserved_at_18[0x4];
9069 	u8         oper_status[0x4];
9070 
9071 	u8         ase[0x1];
9072 	u8         ee[0x1];
9073 	u8         reserved_at_22[0x1c];
9074 	u8         e[0x2];
9075 
9076 	u8         reserved_at_40[0x40];
9077 };
9078 
9079 struct mlx5_ifc_plpc_reg_bits {
9080 	u8         reserved_at_0[0x4];
9081 	u8         profile_id[0xc];
9082 	u8         reserved_at_10[0x4];
9083 	u8         proto_mask[0x4];
9084 	u8         reserved_at_18[0x8];
9085 
9086 	u8         reserved_at_20[0x10];
9087 	u8         lane_speed[0x10];
9088 
9089 	u8         reserved_at_40[0x17];
9090 	u8         lpbf[0x1];
9091 	u8         fec_mode_policy[0x8];
9092 
9093 	u8         retransmission_capability[0x8];
9094 	u8         fec_mode_capability[0x18];
9095 
9096 	u8         retransmission_support_admin[0x8];
9097 	u8         fec_mode_support_admin[0x18];
9098 
9099 	u8         retransmission_request_admin[0x8];
9100 	u8         fec_mode_request_admin[0x18];
9101 
9102 	u8         reserved_at_c0[0x80];
9103 };
9104 
9105 struct mlx5_ifc_plib_reg_bits {
9106 	u8         reserved_at_0[0x8];
9107 	u8         local_port[0x8];
9108 	u8         reserved_at_10[0x8];
9109 	u8         ib_port[0x8];
9110 
9111 	u8         reserved_at_20[0x60];
9112 };
9113 
9114 struct mlx5_ifc_plbf_reg_bits {
9115 	u8         reserved_at_0[0x8];
9116 	u8         local_port[0x8];
9117 	u8         reserved_at_10[0xd];
9118 	u8         lbf_mode[0x3];
9119 
9120 	u8         reserved_at_20[0x20];
9121 };
9122 
9123 struct mlx5_ifc_pipg_reg_bits {
9124 	u8         reserved_at_0[0x8];
9125 	u8         local_port[0x8];
9126 	u8         reserved_at_10[0x10];
9127 
9128 	u8         dic[0x1];
9129 	u8         reserved_at_21[0x19];
9130 	u8         ipg[0x4];
9131 	u8         reserved_at_3e[0x2];
9132 };
9133 
9134 struct mlx5_ifc_pifr_reg_bits {
9135 	u8         reserved_at_0[0x8];
9136 	u8         local_port[0x8];
9137 	u8         reserved_at_10[0x10];
9138 
9139 	u8         reserved_at_20[0xe0];
9140 
9141 	u8         port_filter[8][0x20];
9142 
9143 	u8         port_filter_update_en[8][0x20];
9144 };
9145 
9146 struct mlx5_ifc_pfcc_reg_bits {
9147 	u8         reserved_at_0[0x8];
9148 	u8         local_port[0x8];
9149 	u8         reserved_at_10[0xb];
9150 	u8         ppan_mask_n[0x1];
9151 	u8         minor_stall_mask[0x1];
9152 	u8         critical_stall_mask[0x1];
9153 	u8         reserved_at_1e[0x2];
9154 
9155 	u8         ppan[0x4];
9156 	u8         reserved_at_24[0x4];
9157 	u8         prio_mask_tx[0x8];
9158 	u8         reserved_at_30[0x8];
9159 	u8         prio_mask_rx[0x8];
9160 
9161 	u8         pptx[0x1];
9162 	u8         aptx[0x1];
9163 	u8         pptx_mask_n[0x1];
9164 	u8         reserved_at_43[0x5];
9165 	u8         pfctx[0x8];
9166 	u8         reserved_at_50[0x10];
9167 
9168 	u8         pprx[0x1];
9169 	u8         aprx[0x1];
9170 	u8         pprx_mask_n[0x1];
9171 	u8         reserved_at_63[0x5];
9172 	u8         pfcrx[0x8];
9173 	u8         reserved_at_70[0x10];
9174 
9175 	u8         device_stall_minor_watermark[0x10];
9176 	u8         device_stall_critical_watermark[0x10];
9177 
9178 	u8         reserved_at_a0[0x60];
9179 };
9180 
9181 struct mlx5_ifc_pelc_reg_bits {
9182 	u8         op[0x4];
9183 	u8         reserved_at_4[0x4];
9184 	u8         local_port[0x8];
9185 	u8         reserved_at_10[0x10];
9186 
9187 	u8         op_admin[0x8];
9188 	u8         op_capability[0x8];
9189 	u8         op_request[0x8];
9190 	u8         op_active[0x8];
9191 
9192 	u8         admin[0x40];
9193 
9194 	u8         capability[0x40];
9195 
9196 	u8         request[0x40];
9197 
9198 	u8         active[0x40];
9199 
9200 	u8         reserved_at_140[0x80];
9201 };
9202 
9203 struct mlx5_ifc_peir_reg_bits {
9204 	u8         reserved_at_0[0x8];
9205 	u8         local_port[0x8];
9206 	u8         reserved_at_10[0x10];
9207 
9208 	u8         reserved_at_20[0xc];
9209 	u8         error_count[0x4];
9210 	u8         reserved_at_30[0x10];
9211 
9212 	u8         reserved_at_40[0xc];
9213 	u8         lane[0x4];
9214 	u8         reserved_at_50[0x8];
9215 	u8         error_type[0x8];
9216 };
9217 
9218 struct mlx5_ifc_mpegc_reg_bits {
9219 	u8         reserved_at_0[0x30];
9220 	u8         field_select[0x10];
9221 
9222 	u8         tx_overflow_sense[0x1];
9223 	u8         mark_cqe[0x1];
9224 	u8         mark_cnp[0x1];
9225 	u8         reserved_at_43[0x1b];
9226 	u8         tx_lossy_overflow_oper[0x2];
9227 
9228 	u8         reserved_at_60[0x100];
9229 };
9230 
9231 enum {
9232 	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
9233 	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
9234 	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
9235 };
9236 
9237 struct mlx5_ifc_mtutc_reg_bits {
9238 	u8         reserved_at_0[0x1c];
9239 	u8         operation[0x4];
9240 
9241 	u8         freq_adjustment[0x20];
9242 
9243 	u8         reserved_at_40[0x40];
9244 
9245 	u8         utc_sec[0x20];
9246 
9247 	u8         reserved_at_a0[0x2];
9248 	u8         utc_nsec[0x1e];
9249 
9250 	u8         time_adjustment[0x20];
9251 };
9252 
9253 struct mlx5_ifc_pcam_enhanced_features_bits {
9254 	u8         reserved_at_0[0x68];
9255 	u8         fec_50G_per_lane_in_pplm[0x1];
9256 	u8         reserved_at_69[0x4];
9257 	u8         rx_icrc_encapsulated_counter[0x1];
9258 	u8	   reserved_at_6e[0x4];
9259 	u8         ptys_extended_ethernet[0x1];
9260 	u8	   reserved_at_73[0x3];
9261 	u8         pfcc_mask[0x1];
9262 	u8         reserved_at_77[0x3];
9263 	u8         per_lane_error_counters[0x1];
9264 	u8         rx_buffer_fullness_counters[0x1];
9265 	u8         ptys_connector_type[0x1];
9266 	u8         reserved_at_7d[0x1];
9267 	u8         ppcnt_discard_group[0x1];
9268 	u8         ppcnt_statistical_group[0x1];
9269 };
9270 
9271 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9272 	u8         port_access_reg_cap_mask_127_to_96[0x20];
9273 	u8         port_access_reg_cap_mask_95_to_64[0x20];
9274 
9275 	u8         port_access_reg_cap_mask_63_to_36[0x1c];
9276 	u8         pplm[0x1];
9277 	u8         port_access_reg_cap_mask_34_to_32[0x3];
9278 
9279 	u8         port_access_reg_cap_mask_31_to_13[0x13];
9280 	u8         pbmc[0x1];
9281 	u8         pptb[0x1];
9282 	u8         port_access_reg_cap_mask_10_to_09[0x2];
9283 	u8         ppcnt[0x1];
9284 	u8         port_access_reg_cap_mask_07_to_00[0x8];
9285 };
9286 
9287 struct mlx5_ifc_pcam_reg_bits {
9288 	u8         reserved_at_0[0x8];
9289 	u8         feature_group[0x8];
9290 	u8         reserved_at_10[0x8];
9291 	u8         access_reg_group[0x8];
9292 
9293 	u8         reserved_at_20[0x20];
9294 
9295 	union {
9296 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9297 		u8         reserved_at_0[0x80];
9298 	} port_access_reg_cap_mask;
9299 
9300 	u8         reserved_at_c0[0x80];
9301 
9302 	union {
9303 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9304 		u8         reserved_at_0[0x80];
9305 	} feature_cap_mask;
9306 
9307 	u8         reserved_at_1c0[0xc0];
9308 };
9309 
9310 struct mlx5_ifc_mcam_enhanced_features_bits {
9311 	u8         reserved_at_0[0x6b];
9312 	u8         ptpcyc2realtime_modify[0x1];
9313 	u8         reserved_at_6c[0x2];
9314 	u8         pci_status_and_power[0x1];
9315 	u8         reserved_at_6f[0x5];
9316 	u8         mark_tx_action_cnp[0x1];
9317 	u8         mark_tx_action_cqe[0x1];
9318 	u8         dynamic_tx_overflow[0x1];
9319 	u8         reserved_at_77[0x4];
9320 	u8         pcie_outbound_stalled[0x1];
9321 	u8         tx_overflow_buffer_pkt[0x1];
9322 	u8         mtpps_enh_out_per_adj[0x1];
9323 	u8         mtpps_fs[0x1];
9324 	u8         pcie_performance_group[0x1];
9325 };
9326 
9327 struct mlx5_ifc_mcam_access_reg_bits {
9328 	u8         reserved_at_0[0x1c];
9329 	u8         mcda[0x1];
9330 	u8         mcc[0x1];
9331 	u8         mcqi[0x1];
9332 	u8         mcqs[0x1];
9333 
9334 	u8         regs_95_to_87[0x9];
9335 	u8         mpegc[0x1];
9336 	u8         mtutc[0x1];
9337 	u8         regs_84_to_68[0x11];
9338 	u8         tracer_registers[0x4];
9339 
9340 	u8         regs_63_to_32[0x20];
9341 	u8         regs_31_to_0[0x20];
9342 };
9343 
9344 struct mlx5_ifc_mcam_access_reg_bits1 {
9345 	u8         regs_127_to_96[0x20];
9346 
9347 	u8         regs_95_to_64[0x20];
9348 
9349 	u8         regs_63_to_32[0x20];
9350 
9351 	u8         regs_31_to_0[0x20];
9352 };
9353 
9354 struct mlx5_ifc_mcam_access_reg_bits2 {
9355 	u8         regs_127_to_99[0x1d];
9356 	u8         mirc[0x1];
9357 	u8         regs_97_to_96[0x2];
9358 
9359 	u8         regs_95_to_64[0x20];
9360 
9361 	u8         regs_63_to_32[0x20];
9362 
9363 	u8         regs_31_to_0[0x20];
9364 };
9365 
9366 struct mlx5_ifc_mcam_reg_bits {
9367 	u8         reserved_at_0[0x8];
9368 	u8         feature_group[0x8];
9369 	u8         reserved_at_10[0x8];
9370 	u8         access_reg_group[0x8];
9371 
9372 	u8         reserved_at_20[0x20];
9373 
9374 	union {
9375 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
9376 		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9377 		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9378 		u8         reserved_at_0[0x80];
9379 	} mng_access_reg_cap_mask;
9380 
9381 	u8         reserved_at_c0[0x80];
9382 
9383 	union {
9384 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9385 		u8         reserved_at_0[0x80];
9386 	} mng_feature_cap_mask;
9387 
9388 	u8         reserved_at_1c0[0x80];
9389 };
9390 
9391 struct mlx5_ifc_qcam_access_reg_cap_mask {
9392 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9393 	u8         qpdpm[0x1];
9394 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9395 	u8         qdpm[0x1];
9396 	u8         qpts[0x1];
9397 	u8         qcap[0x1];
9398 	u8         qcam_access_reg_cap_mask_0[0x1];
9399 };
9400 
9401 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9402 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9403 	u8         qpts_trust_both[0x1];
9404 };
9405 
9406 struct mlx5_ifc_qcam_reg_bits {
9407 	u8         reserved_at_0[0x8];
9408 	u8         feature_group[0x8];
9409 	u8         reserved_at_10[0x8];
9410 	u8         access_reg_group[0x8];
9411 	u8         reserved_at_20[0x20];
9412 
9413 	union {
9414 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9415 		u8  reserved_at_0[0x80];
9416 	} qos_access_reg_cap_mask;
9417 
9418 	u8         reserved_at_c0[0x80];
9419 
9420 	union {
9421 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9422 		u8  reserved_at_0[0x80];
9423 	} qos_feature_cap_mask;
9424 
9425 	u8         reserved_at_1c0[0x80];
9426 };
9427 
9428 struct mlx5_ifc_core_dump_reg_bits {
9429 	u8         reserved_at_0[0x18];
9430 	u8         core_dump_type[0x8];
9431 
9432 	u8         reserved_at_20[0x30];
9433 	u8         vhca_id[0x10];
9434 
9435 	u8         reserved_at_60[0x8];
9436 	u8         qpn[0x18];
9437 	u8         reserved_at_80[0x180];
9438 };
9439 
9440 struct mlx5_ifc_pcap_reg_bits {
9441 	u8         reserved_at_0[0x8];
9442 	u8         local_port[0x8];
9443 	u8         reserved_at_10[0x10];
9444 
9445 	u8         port_capability_mask[4][0x20];
9446 };
9447 
9448 struct mlx5_ifc_paos_reg_bits {
9449 	u8         swid[0x8];
9450 	u8         local_port[0x8];
9451 	u8         reserved_at_10[0x4];
9452 	u8         admin_status[0x4];
9453 	u8         reserved_at_18[0x4];
9454 	u8         oper_status[0x4];
9455 
9456 	u8         ase[0x1];
9457 	u8         ee[0x1];
9458 	u8         reserved_at_22[0x1c];
9459 	u8         e[0x2];
9460 
9461 	u8         reserved_at_40[0x40];
9462 };
9463 
9464 struct mlx5_ifc_pamp_reg_bits {
9465 	u8         reserved_at_0[0x8];
9466 	u8         opamp_group[0x8];
9467 	u8         reserved_at_10[0xc];
9468 	u8         opamp_group_type[0x4];
9469 
9470 	u8         start_index[0x10];
9471 	u8         reserved_at_30[0x4];
9472 	u8         num_of_indices[0xc];
9473 
9474 	u8         index_data[18][0x10];
9475 };
9476 
9477 struct mlx5_ifc_pcmr_reg_bits {
9478 	u8         reserved_at_0[0x8];
9479 	u8         local_port[0x8];
9480 	u8         reserved_at_10[0x10];
9481 
9482 	u8         entropy_force_cap[0x1];
9483 	u8         entropy_calc_cap[0x1];
9484 	u8         entropy_gre_calc_cap[0x1];
9485 	u8         reserved_at_23[0xf];
9486 	u8         rx_ts_over_crc_cap[0x1];
9487 	u8         reserved_at_33[0xb];
9488 	u8         fcs_cap[0x1];
9489 	u8         reserved_at_3f[0x1];
9490 
9491 	u8         entropy_force[0x1];
9492 	u8         entropy_calc[0x1];
9493 	u8         entropy_gre_calc[0x1];
9494 	u8         reserved_at_43[0xf];
9495 	u8         rx_ts_over_crc[0x1];
9496 	u8         reserved_at_53[0xb];
9497 	u8         fcs_chk[0x1];
9498 	u8         reserved_at_5f[0x1];
9499 };
9500 
9501 struct mlx5_ifc_lane_2_module_mapping_bits {
9502 	u8         reserved_at_0[0x6];
9503 	u8         rx_lane[0x2];
9504 	u8         reserved_at_8[0x6];
9505 	u8         tx_lane[0x2];
9506 	u8         reserved_at_10[0x8];
9507 	u8         module[0x8];
9508 };
9509 
9510 struct mlx5_ifc_bufferx_reg_bits {
9511 	u8         reserved_at_0[0x6];
9512 	u8         lossy[0x1];
9513 	u8         epsb[0x1];
9514 	u8         reserved_at_8[0x8];
9515 	u8         size[0x10];
9516 
9517 	u8         xoff_threshold[0x10];
9518 	u8         xon_threshold[0x10];
9519 };
9520 
9521 struct mlx5_ifc_set_node_in_bits {
9522 	u8         node_description[64][0x8];
9523 };
9524 
9525 struct mlx5_ifc_register_power_settings_bits {
9526 	u8         reserved_at_0[0x18];
9527 	u8         power_settings_level[0x8];
9528 
9529 	u8         reserved_at_20[0x60];
9530 };
9531 
9532 struct mlx5_ifc_register_host_endianness_bits {
9533 	u8         he[0x1];
9534 	u8         reserved_at_1[0x1f];
9535 
9536 	u8         reserved_at_20[0x60];
9537 };
9538 
9539 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9540 	u8         reserved_at_0[0x20];
9541 
9542 	u8         mkey[0x20];
9543 
9544 	u8         addressh_63_32[0x20];
9545 
9546 	u8         addressl_31_0[0x20];
9547 };
9548 
9549 struct mlx5_ifc_ud_adrs_vector_bits {
9550 	u8         dc_key[0x40];
9551 
9552 	u8         ext[0x1];
9553 	u8         reserved_at_41[0x7];
9554 	u8         destination_qp_dct[0x18];
9555 
9556 	u8         static_rate[0x4];
9557 	u8         sl_eth_prio[0x4];
9558 	u8         fl[0x1];
9559 	u8         mlid[0x7];
9560 	u8         rlid_udp_sport[0x10];
9561 
9562 	u8         reserved_at_80[0x20];
9563 
9564 	u8         rmac_47_16[0x20];
9565 
9566 	u8         rmac_15_0[0x10];
9567 	u8         tclass[0x8];
9568 	u8         hop_limit[0x8];
9569 
9570 	u8         reserved_at_e0[0x1];
9571 	u8         grh[0x1];
9572 	u8         reserved_at_e2[0x2];
9573 	u8         src_addr_index[0x8];
9574 	u8         flow_label[0x14];
9575 
9576 	u8         rgid_rip[16][0x8];
9577 };
9578 
9579 struct mlx5_ifc_pages_req_event_bits {
9580 	u8         reserved_at_0[0x10];
9581 	u8         function_id[0x10];
9582 
9583 	u8         num_pages[0x20];
9584 
9585 	u8         reserved_at_40[0xa0];
9586 };
9587 
9588 struct mlx5_ifc_eqe_bits {
9589 	u8         reserved_at_0[0x8];
9590 	u8         event_type[0x8];
9591 	u8         reserved_at_10[0x8];
9592 	u8         event_sub_type[0x8];
9593 
9594 	u8         reserved_at_20[0xe0];
9595 
9596 	union mlx5_ifc_event_auto_bits event_data;
9597 
9598 	u8         reserved_at_1e0[0x10];
9599 	u8         signature[0x8];
9600 	u8         reserved_at_1f8[0x7];
9601 	u8         owner[0x1];
9602 };
9603 
9604 enum {
9605 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9606 };
9607 
9608 struct mlx5_ifc_cmd_queue_entry_bits {
9609 	u8         type[0x8];
9610 	u8         reserved_at_8[0x18];
9611 
9612 	u8         input_length[0x20];
9613 
9614 	u8         input_mailbox_pointer_63_32[0x20];
9615 
9616 	u8         input_mailbox_pointer_31_9[0x17];
9617 	u8         reserved_at_77[0x9];
9618 
9619 	u8         command_input_inline_data[16][0x8];
9620 
9621 	u8         command_output_inline_data[16][0x8];
9622 
9623 	u8         output_mailbox_pointer_63_32[0x20];
9624 
9625 	u8         output_mailbox_pointer_31_9[0x17];
9626 	u8         reserved_at_1b7[0x9];
9627 
9628 	u8         output_length[0x20];
9629 
9630 	u8         token[0x8];
9631 	u8         signature[0x8];
9632 	u8         reserved_at_1f0[0x8];
9633 	u8         status[0x7];
9634 	u8         ownership[0x1];
9635 };
9636 
9637 struct mlx5_ifc_cmd_out_bits {
9638 	u8         status[0x8];
9639 	u8         reserved_at_8[0x18];
9640 
9641 	u8         syndrome[0x20];
9642 
9643 	u8         command_output[0x20];
9644 };
9645 
9646 struct mlx5_ifc_cmd_in_bits {
9647 	u8         opcode[0x10];
9648 	u8         reserved_at_10[0x10];
9649 
9650 	u8         reserved_at_20[0x10];
9651 	u8         op_mod[0x10];
9652 
9653 	u8         command[][0x20];
9654 };
9655 
9656 struct mlx5_ifc_cmd_if_box_bits {
9657 	u8         mailbox_data[512][0x8];
9658 
9659 	u8         reserved_at_1000[0x180];
9660 
9661 	u8         next_pointer_63_32[0x20];
9662 
9663 	u8         next_pointer_31_10[0x16];
9664 	u8         reserved_at_11b6[0xa];
9665 
9666 	u8         block_number[0x20];
9667 
9668 	u8         reserved_at_11e0[0x8];
9669 	u8         token[0x8];
9670 	u8         ctrl_signature[0x8];
9671 	u8         signature[0x8];
9672 };
9673 
9674 struct mlx5_ifc_mtt_bits {
9675 	u8         ptag_63_32[0x20];
9676 
9677 	u8         ptag_31_8[0x18];
9678 	u8         reserved_at_38[0x6];
9679 	u8         wr_en[0x1];
9680 	u8         rd_en[0x1];
9681 };
9682 
9683 struct mlx5_ifc_query_wol_rol_out_bits {
9684 	u8         status[0x8];
9685 	u8         reserved_at_8[0x18];
9686 
9687 	u8         syndrome[0x20];
9688 
9689 	u8         reserved_at_40[0x10];
9690 	u8         rol_mode[0x8];
9691 	u8         wol_mode[0x8];
9692 
9693 	u8         reserved_at_60[0x20];
9694 };
9695 
9696 struct mlx5_ifc_query_wol_rol_in_bits {
9697 	u8         opcode[0x10];
9698 	u8         reserved_at_10[0x10];
9699 
9700 	u8         reserved_at_20[0x10];
9701 	u8         op_mod[0x10];
9702 
9703 	u8         reserved_at_40[0x40];
9704 };
9705 
9706 struct mlx5_ifc_set_wol_rol_out_bits {
9707 	u8         status[0x8];
9708 	u8         reserved_at_8[0x18];
9709 
9710 	u8         syndrome[0x20];
9711 
9712 	u8         reserved_at_40[0x40];
9713 };
9714 
9715 struct mlx5_ifc_set_wol_rol_in_bits {
9716 	u8         opcode[0x10];
9717 	u8         reserved_at_10[0x10];
9718 
9719 	u8         reserved_at_20[0x10];
9720 	u8         op_mod[0x10];
9721 
9722 	u8         rol_mode_valid[0x1];
9723 	u8         wol_mode_valid[0x1];
9724 	u8         reserved_at_42[0xe];
9725 	u8         rol_mode[0x8];
9726 	u8         wol_mode[0x8];
9727 
9728 	u8         reserved_at_60[0x20];
9729 };
9730 
9731 enum {
9732 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9733 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9734 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9735 };
9736 
9737 enum {
9738 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9739 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9740 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9741 };
9742 
9743 enum {
9744 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
9745 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
9746 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
9747 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
9748 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
9749 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
9750 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
9751 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
9752 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
9753 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
9754 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
9755 };
9756 
9757 struct mlx5_ifc_initial_seg_bits {
9758 	u8         fw_rev_minor[0x10];
9759 	u8         fw_rev_major[0x10];
9760 
9761 	u8         cmd_interface_rev[0x10];
9762 	u8         fw_rev_subminor[0x10];
9763 
9764 	u8         reserved_at_40[0x40];
9765 
9766 	u8         cmdq_phy_addr_63_32[0x20];
9767 
9768 	u8         cmdq_phy_addr_31_12[0x14];
9769 	u8         reserved_at_b4[0x2];
9770 	u8         nic_interface[0x2];
9771 	u8         log_cmdq_size[0x4];
9772 	u8         log_cmdq_stride[0x4];
9773 
9774 	u8         command_doorbell_vector[0x20];
9775 
9776 	u8         reserved_at_e0[0xf00];
9777 
9778 	u8         initializing[0x1];
9779 	u8         reserved_at_fe1[0x4];
9780 	u8         nic_interface_supported[0x3];
9781 	u8         embedded_cpu[0x1];
9782 	u8         reserved_at_fe9[0x17];
9783 
9784 	struct mlx5_ifc_health_buffer_bits health_buffer;
9785 
9786 	u8         no_dram_nic_offset[0x20];
9787 
9788 	u8         reserved_at_1220[0x6e40];
9789 
9790 	u8         reserved_at_8060[0x1f];
9791 	u8         clear_int[0x1];
9792 
9793 	u8         health_syndrome[0x8];
9794 	u8         health_counter[0x18];
9795 
9796 	u8         reserved_at_80a0[0x17fc0];
9797 };
9798 
9799 struct mlx5_ifc_mtpps_reg_bits {
9800 	u8         reserved_at_0[0xc];
9801 	u8         cap_number_of_pps_pins[0x4];
9802 	u8         reserved_at_10[0x4];
9803 	u8         cap_max_num_of_pps_in_pins[0x4];
9804 	u8         reserved_at_18[0x4];
9805 	u8         cap_max_num_of_pps_out_pins[0x4];
9806 
9807 	u8         reserved_at_20[0x24];
9808 	u8         cap_pin_3_mode[0x4];
9809 	u8         reserved_at_48[0x4];
9810 	u8         cap_pin_2_mode[0x4];
9811 	u8         reserved_at_50[0x4];
9812 	u8         cap_pin_1_mode[0x4];
9813 	u8         reserved_at_58[0x4];
9814 	u8         cap_pin_0_mode[0x4];
9815 
9816 	u8         reserved_at_60[0x4];
9817 	u8         cap_pin_7_mode[0x4];
9818 	u8         reserved_at_68[0x4];
9819 	u8         cap_pin_6_mode[0x4];
9820 	u8         reserved_at_70[0x4];
9821 	u8         cap_pin_5_mode[0x4];
9822 	u8         reserved_at_78[0x4];
9823 	u8         cap_pin_4_mode[0x4];
9824 
9825 	u8         field_select[0x20];
9826 	u8         reserved_at_a0[0x60];
9827 
9828 	u8         enable[0x1];
9829 	u8         reserved_at_101[0xb];
9830 	u8         pattern[0x4];
9831 	u8         reserved_at_110[0x4];
9832 	u8         pin_mode[0x4];
9833 	u8         pin[0x8];
9834 
9835 	u8         reserved_at_120[0x20];
9836 
9837 	u8         time_stamp[0x40];
9838 
9839 	u8         out_pulse_duration[0x10];
9840 	u8         out_periodic_adjustment[0x10];
9841 	u8         enhanced_out_periodic_adjustment[0x20];
9842 
9843 	u8         reserved_at_1c0[0x20];
9844 };
9845 
9846 struct mlx5_ifc_mtppse_reg_bits {
9847 	u8         reserved_at_0[0x18];
9848 	u8         pin[0x8];
9849 	u8         event_arm[0x1];
9850 	u8         reserved_at_21[0x1b];
9851 	u8         event_generation_mode[0x4];
9852 	u8         reserved_at_40[0x40];
9853 };
9854 
9855 struct mlx5_ifc_mcqs_reg_bits {
9856 	u8         last_index_flag[0x1];
9857 	u8         reserved_at_1[0x7];
9858 	u8         fw_device[0x8];
9859 	u8         component_index[0x10];
9860 
9861 	u8         reserved_at_20[0x10];
9862 	u8         identifier[0x10];
9863 
9864 	u8         reserved_at_40[0x17];
9865 	u8         component_status[0x5];
9866 	u8         component_update_state[0x4];
9867 
9868 	u8         last_update_state_changer_type[0x4];
9869 	u8         last_update_state_changer_host_id[0x4];
9870 	u8         reserved_at_68[0x18];
9871 };
9872 
9873 struct mlx5_ifc_mcqi_cap_bits {
9874 	u8         supported_info_bitmask[0x20];
9875 
9876 	u8         component_size[0x20];
9877 
9878 	u8         max_component_size[0x20];
9879 
9880 	u8         log_mcda_word_size[0x4];
9881 	u8         reserved_at_64[0xc];
9882 	u8         mcda_max_write_size[0x10];
9883 
9884 	u8         rd_en[0x1];
9885 	u8         reserved_at_81[0x1];
9886 	u8         match_chip_id[0x1];
9887 	u8         match_psid[0x1];
9888 	u8         check_user_timestamp[0x1];
9889 	u8         match_base_guid_mac[0x1];
9890 	u8         reserved_at_86[0x1a];
9891 };
9892 
9893 struct mlx5_ifc_mcqi_version_bits {
9894 	u8         reserved_at_0[0x2];
9895 	u8         build_time_valid[0x1];
9896 	u8         user_defined_time_valid[0x1];
9897 	u8         reserved_at_4[0x14];
9898 	u8         version_string_length[0x8];
9899 
9900 	u8         version[0x20];
9901 
9902 	u8         build_time[0x40];
9903 
9904 	u8         user_defined_time[0x40];
9905 
9906 	u8         build_tool_version[0x20];
9907 
9908 	u8         reserved_at_e0[0x20];
9909 
9910 	u8         version_string[92][0x8];
9911 };
9912 
9913 struct mlx5_ifc_mcqi_activation_method_bits {
9914 	u8         pending_server_ac_power_cycle[0x1];
9915 	u8         pending_server_dc_power_cycle[0x1];
9916 	u8         pending_server_reboot[0x1];
9917 	u8         pending_fw_reset[0x1];
9918 	u8         auto_activate[0x1];
9919 	u8         all_hosts_sync[0x1];
9920 	u8         device_hw_reset[0x1];
9921 	u8         reserved_at_7[0x19];
9922 };
9923 
9924 union mlx5_ifc_mcqi_reg_data_bits {
9925 	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9926 	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9927 	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9928 };
9929 
9930 struct mlx5_ifc_mcqi_reg_bits {
9931 	u8         read_pending_component[0x1];
9932 	u8         reserved_at_1[0xf];
9933 	u8         component_index[0x10];
9934 
9935 	u8         reserved_at_20[0x20];
9936 
9937 	u8         reserved_at_40[0x1b];
9938 	u8         info_type[0x5];
9939 
9940 	u8         info_size[0x20];
9941 
9942 	u8         offset[0x20];
9943 
9944 	u8         reserved_at_a0[0x10];
9945 	u8         data_size[0x10];
9946 
9947 	union mlx5_ifc_mcqi_reg_data_bits data[];
9948 };
9949 
9950 struct mlx5_ifc_mcc_reg_bits {
9951 	u8         reserved_at_0[0x4];
9952 	u8         time_elapsed_since_last_cmd[0xc];
9953 	u8         reserved_at_10[0x8];
9954 	u8         instruction[0x8];
9955 
9956 	u8         reserved_at_20[0x10];
9957 	u8         component_index[0x10];
9958 
9959 	u8         reserved_at_40[0x8];
9960 	u8         update_handle[0x18];
9961 
9962 	u8         handle_owner_type[0x4];
9963 	u8         handle_owner_host_id[0x4];
9964 	u8         reserved_at_68[0x1];
9965 	u8         control_progress[0x7];
9966 	u8         error_code[0x8];
9967 	u8         reserved_at_78[0x4];
9968 	u8         control_state[0x4];
9969 
9970 	u8         component_size[0x20];
9971 
9972 	u8         reserved_at_a0[0x60];
9973 };
9974 
9975 struct mlx5_ifc_mcda_reg_bits {
9976 	u8         reserved_at_0[0x8];
9977 	u8         update_handle[0x18];
9978 
9979 	u8         offset[0x20];
9980 
9981 	u8         reserved_at_40[0x10];
9982 	u8         size[0x10];
9983 
9984 	u8         reserved_at_60[0x20];
9985 
9986 	u8         data[][0x20];
9987 };
9988 
9989 enum {
9990 	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
9991 	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
9992 };
9993 
9994 enum {
9995 	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
9996 	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
9997 	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
9998 };
9999 
10000 struct mlx5_ifc_mfrl_reg_bits {
10001 	u8         reserved_at_0[0x20];
10002 
10003 	u8         reserved_at_20[0x2];
10004 	u8         pci_sync_for_fw_update_start[0x1];
10005 	u8         pci_sync_for_fw_update_resp[0x2];
10006 	u8         rst_type_sel[0x3];
10007 	u8         reserved_at_28[0x8];
10008 	u8         reset_type[0x8];
10009 	u8         reset_level[0x8];
10010 };
10011 
10012 struct mlx5_ifc_mirc_reg_bits {
10013 	u8         reserved_at_0[0x18];
10014 	u8         status_code[0x8];
10015 
10016 	u8         reserved_at_20[0x20];
10017 };
10018 
10019 struct mlx5_ifc_pddr_monitor_opcode_bits {
10020 	u8         reserved_at_0[0x10];
10021 	u8         monitor_opcode[0x10];
10022 };
10023 
10024 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10025 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10026 	u8         reserved_at_0[0x20];
10027 };
10028 
10029 enum {
10030 	/* Monitor opcodes */
10031 	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10032 };
10033 
10034 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10035 	u8         reserved_at_0[0x10];
10036 	u8         group_opcode[0x10];
10037 
10038 	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10039 
10040 	u8         reserved_at_40[0x20];
10041 
10042 	u8         status_message[59][0x20];
10043 };
10044 
10045 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10046 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10047 	u8         reserved_at_0[0x7c0];
10048 };
10049 
10050 enum {
10051 	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10052 };
10053 
10054 struct mlx5_ifc_pddr_reg_bits {
10055 	u8         reserved_at_0[0x8];
10056 	u8         local_port[0x8];
10057 	u8         pnat[0x2];
10058 	u8         reserved_at_12[0xe];
10059 
10060 	u8         reserved_at_20[0x18];
10061 	u8         page_select[0x8];
10062 
10063 	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10064 };
10065 
10066 union mlx5_ifc_ports_control_registers_document_bits {
10067 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10068 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10069 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10070 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10071 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10072 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10073 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10074 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10075 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10076 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10077 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
10078 	struct mlx5_ifc_paos_reg_bits paos_reg;
10079 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
10080 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10081 	struct mlx5_ifc_pddr_reg_bits pddr_reg;
10082 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10083 	struct mlx5_ifc_peir_reg_bits peir_reg;
10084 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
10085 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10086 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10087 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10088 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
10089 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
10090 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
10091 	struct mlx5_ifc_plib_reg_bits plib_reg;
10092 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
10093 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10094 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10095 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10096 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10097 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10098 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10099 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10100 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
10101 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10102 	struct mlx5_ifc_mpein_reg_bits mpein_reg;
10103 	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10104 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
10105 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
10106 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10107 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10108 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
10109 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
10110 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
10111 	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
10112 	struct mlx5_ifc_pude_reg_bits pude_reg;
10113 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10114 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
10115 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
10116 	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10117 	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
10118 	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
10119 	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10120 	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
10121 	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10122 	struct mlx5_ifc_mcc_reg_bits mcc_reg;
10123 	struct mlx5_ifc_mcda_reg_bits mcda_reg;
10124 	struct mlx5_ifc_mirc_reg_bits mirc_reg;
10125 	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
10126 	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
10127 	u8         reserved_at_0[0x60e0];
10128 };
10129 
10130 union mlx5_ifc_debug_enhancements_document_bits {
10131 	struct mlx5_ifc_health_buffer_bits health_buffer;
10132 	u8         reserved_at_0[0x200];
10133 };
10134 
10135 union mlx5_ifc_uplink_pci_interface_document_bits {
10136 	struct mlx5_ifc_initial_seg_bits initial_seg;
10137 	u8         reserved_at_0[0x20060];
10138 };
10139 
10140 struct mlx5_ifc_set_flow_table_root_out_bits {
10141 	u8         status[0x8];
10142 	u8         reserved_at_8[0x18];
10143 
10144 	u8         syndrome[0x20];
10145 
10146 	u8         reserved_at_40[0x40];
10147 };
10148 
10149 struct mlx5_ifc_set_flow_table_root_in_bits {
10150 	u8         opcode[0x10];
10151 	u8         reserved_at_10[0x10];
10152 
10153 	u8         reserved_at_20[0x10];
10154 	u8         op_mod[0x10];
10155 
10156 	u8         other_vport[0x1];
10157 	u8         reserved_at_41[0xf];
10158 	u8         vport_number[0x10];
10159 
10160 	u8         reserved_at_60[0x20];
10161 
10162 	u8         table_type[0x8];
10163 	u8         reserved_at_88[0x7];
10164 	u8         table_of_other_vport[0x1];
10165 	u8         table_vport_number[0x10];
10166 
10167 	u8         reserved_at_a0[0x8];
10168 	u8         table_id[0x18];
10169 
10170 	u8         reserved_at_c0[0x8];
10171 	u8         underlay_qpn[0x18];
10172 	u8         table_eswitch_owner_vhca_id_valid[0x1];
10173 	u8         reserved_at_e1[0xf];
10174 	u8         table_eswitch_owner_vhca_id[0x10];
10175 	u8         reserved_at_100[0x100];
10176 };
10177 
10178 enum {
10179 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
10180 	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
10181 };
10182 
10183 struct mlx5_ifc_modify_flow_table_out_bits {
10184 	u8         status[0x8];
10185 	u8         reserved_at_8[0x18];
10186 
10187 	u8         syndrome[0x20];
10188 
10189 	u8         reserved_at_40[0x40];
10190 };
10191 
10192 struct mlx5_ifc_modify_flow_table_in_bits {
10193 	u8         opcode[0x10];
10194 	u8         reserved_at_10[0x10];
10195 
10196 	u8         reserved_at_20[0x10];
10197 	u8         op_mod[0x10];
10198 
10199 	u8         other_vport[0x1];
10200 	u8         reserved_at_41[0xf];
10201 	u8         vport_number[0x10];
10202 
10203 	u8         reserved_at_60[0x10];
10204 	u8         modify_field_select[0x10];
10205 
10206 	u8         table_type[0x8];
10207 	u8         reserved_at_88[0x18];
10208 
10209 	u8         reserved_at_a0[0x8];
10210 	u8         table_id[0x18];
10211 
10212 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
10213 };
10214 
10215 struct mlx5_ifc_ets_tcn_config_reg_bits {
10216 	u8         g[0x1];
10217 	u8         b[0x1];
10218 	u8         r[0x1];
10219 	u8         reserved_at_3[0x9];
10220 	u8         group[0x4];
10221 	u8         reserved_at_10[0x9];
10222 	u8         bw_allocation[0x7];
10223 
10224 	u8         reserved_at_20[0xc];
10225 	u8         max_bw_units[0x4];
10226 	u8         reserved_at_30[0x8];
10227 	u8         max_bw_value[0x8];
10228 };
10229 
10230 struct mlx5_ifc_ets_global_config_reg_bits {
10231 	u8         reserved_at_0[0x2];
10232 	u8         r[0x1];
10233 	u8         reserved_at_3[0x1d];
10234 
10235 	u8         reserved_at_20[0xc];
10236 	u8         max_bw_units[0x4];
10237 	u8         reserved_at_30[0x8];
10238 	u8         max_bw_value[0x8];
10239 };
10240 
10241 struct mlx5_ifc_qetc_reg_bits {
10242 	u8                                         reserved_at_0[0x8];
10243 	u8                                         port_number[0x8];
10244 	u8                                         reserved_at_10[0x30];
10245 
10246 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
10247 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10248 };
10249 
10250 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10251 	u8         e[0x1];
10252 	u8         reserved_at_01[0x0b];
10253 	u8         prio[0x04];
10254 };
10255 
10256 struct mlx5_ifc_qpdpm_reg_bits {
10257 	u8                                     reserved_at_0[0x8];
10258 	u8                                     local_port[0x8];
10259 	u8                                     reserved_at_10[0x10];
10260 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10261 };
10262 
10263 struct mlx5_ifc_qpts_reg_bits {
10264 	u8         reserved_at_0[0x8];
10265 	u8         local_port[0x8];
10266 	u8         reserved_at_10[0x2d];
10267 	u8         trust_state[0x3];
10268 };
10269 
10270 struct mlx5_ifc_pptb_reg_bits {
10271 	u8         reserved_at_0[0x2];
10272 	u8         mm[0x2];
10273 	u8         reserved_at_4[0x4];
10274 	u8         local_port[0x8];
10275 	u8         reserved_at_10[0x6];
10276 	u8         cm[0x1];
10277 	u8         um[0x1];
10278 	u8         pm[0x8];
10279 
10280 	u8         prio_x_buff[0x20];
10281 
10282 	u8         pm_msb[0x8];
10283 	u8         reserved_at_48[0x10];
10284 	u8         ctrl_buff[0x4];
10285 	u8         untagged_buff[0x4];
10286 };
10287 
10288 struct mlx5_ifc_sbcam_reg_bits {
10289 	u8         reserved_at_0[0x8];
10290 	u8         feature_group[0x8];
10291 	u8         reserved_at_10[0x8];
10292 	u8         access_reg_group[0x8];
10293 
10294 	u8         reserved_at_20[0x20];
10295 
10296 	u8         sb_access_reg_cap_mask[4][0x20];
10297 
10298 	u8         reserved_at_c0[0x80];
10299 
10300 	u8         sb_feature_cap_mask[4][0x20];
10301 
10302 	u8         reserved_at_1c0[0x40];
10303 
10304 	u8         cap_total_buffer_size[0x20];
10305 
10306 	u8         cap_cell_size[0x10];
10307 	u8         cap_max_pg_buffers[0x8];
10308 	u8         cap_num_pool_supported[0x8];
10309 
10310 	u8         reserved_at_240[0x8];
10311 	u8         cap_sbsr_stat_size[0x8];
10312 	u8         cap_max_tclass_data[0x8];
10313 	u8         cap_max_cpu_ingress_tclass_sb[0x8];
10314 };
10315 
10316 struct mlx5_ifc_pbmc_reg_bits {
10317 	u8         reserved_at_0[0x8];
10318 	u8         local_port[0x8];
10319 	u8         reserved_at_10[0x10];
10320 
10321 	u8         xoff_timer_value[0x10];
10322 	u8         xoff_refresh[0x10];
10323 
10324 	u8         reserved_at_40[0x9];
10325 	u8         fullness_threshold[0x7];
10326 	u8         port_buffer_size[0x10];
10327 
10328 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
10329 
10330 	u8         reserved_at_2e0[0x80];
10331 };
10332 
10333 struct mlx5_ifc_qtct_reg_bits {
10334 	u8         reserved_at_0[0x8];
10335 	u8         port_number[0x8];
10336 	u8         reserved_at_10[0xd];
10337 	u8         prio[0x3];
10338 
10339 	u8         reserved_at_20[0x1d];
10340 	u8         tclass[0x3];
10341 };
10342 
10343 struct mlx5_ifc_mcia_reg_bits {
10344 	u8         l[0x1];
10345 	u8         reserved_at_1[0x7];
10346 	u8         module[0x8];
10347 	u8         reserved_at_10[0x8];
10348 	u8         status[0x8];
10349 
10350 	u8         i2c_device_address[0x8];
10351 	u8         page_number[0x8];
10352 	u8         device_address[0x10];
10353 
10354 	u8         reserved_at_40[0x10];
10355 	u8         size[0x10];
10356 
10357 	u8         reserved_at_60[0x20];
10358 
10359 	u8         dword_0[0x20];
10360 	u8         dword_1[0x20];
10361 	u8         dword_2[0x20];
10362 	u8         dword_3[0x20];
10363 	u8         dword_4[0x20];
10364 	u8         dword_5[0x20];
10365 	u8         dword_6[0x20];
10366 	u8         dword_7[0x20];
10367 	u8         dword_8[0x20];
10368 	u8         dword_9[0x20];
10369 	u8         dword_10[0x20];
10370 	u8         dword_11[0x20];
10371 };
10372 
10373 struct mlx5_ifc_dcbx_param_bits {
10374 	u8         dcbx_cee_cap[0x1];
10375 	u8         dcbx_ieee_cap[0x1];
10376 	u8         dcbx_standby_cap[0x1];
10377 	u8         reserved_at_3[0x5];
10378 	u8         port_number[0x8];
10379 	u8         reserved_at_10[0xa];
10380 	u8         max_application_table_size[6];
10381 	u8         reserved_at_20[0x15];
10382 	u8         version_oper[0x3];
10383 	u8         reserved_at_38[5];
10384 	u8         version_admin[0x3];
10385 	u8         willing_admin[0x1];
10386 	u8         reserved_at_41[0x3];
10387 	u8         pfc_cap_oper[0x4];
10388 	u8         reserved_at_48[0x4];
10389 	u8         pfc_cap_admin[0x4];
10390 	u8         reserved_at_50[0x4];
10391 	u8         num_of_tc_oper[0x4];
10392 	u8         reserved_at_58[0x4];
10393 	u8         num_of_tc_admin[0x4];
10394 	u8         remote_willing[0x1];
10395 	u8         reserved_at_61[3];
10396 	u8         remote_pfc_cap[4];
10397 	u8         reserved_at_68[0x14];
10398 	u8         remote_num_of_tc[0x4];
10399 	u8         reserved_at_80[0x18];
10400 	u8         error[0x8];
10401 	u8         reserved_at_a0[0x160];
10402 };
10403 
10404 struct mlx5_ifc_lagc_bits {
10405 	u8         fdb_selection_mode[0x1];
10406 	u8         reserved_at_1[0x1c];
10407 	u8         lag_state[0x3];
10408 
10409 	u8         reserved_at_20[0x14];
10410 	u8         tx_remap_affinity_2[0x4];
10411 	u8         reserved_at_38[0x4];
10412 	u8         tx_remap_affinity_1[0x4];
10413 };
10414 
10415 struct mlx5_ifc_create_lag_out_bits {
10416 	u8         status[0x8];
10417 	u8         reserved_at_8[0x18];
10418 
10419 	u8         syndrome[0x20];
10420 
10421 	u8         reserved_at_40[0x40];
10422 };
10423 
10424 struct mlx5_ifc_create_lag_in_bits {
10425 	u8         opcode[0x10];
10426 	u8         reserved_at_10[0x10];
10427 
10428 	u8         reserved_at_20[0x10];
10429 	u8         op_mod[0x10];
10430 
10431 	struct mlx5_ifc_lagc_bits ctx;
10432 };
10433 
10434 struct mlx5_ifc_modify_lag_out_bits {
10435 	u8         status[0x8];
10436 	u8         reserved_at_8[0x18];
10437 
10438 	u8         syndrome[0x20];
10439 
10440 	u8         reserved_at_40[0x40];
10441 };
10442 
10443 struct mlx5_ifc_modify_lag_in_bits {
10444 	u8         opcode[0x10];
10445 	u8         reserved_at_10[0x10];
10446 
10447 	u8         reserved_at_20[0x10];
10448 	u8         op_mod[0x10];
10449 
10450 	u8         reserved_at_40[0x20];
10451 	u8         field_select[0x20];
10452 
10453 	struct mlx5_ifc_lagc_bits ctx;
10454 };
10455 
10456 struct mlx5_ifc_query_lag_out_bits {
10457 	u8         status[0x8];
10458 	u8         reserved_at_8[0x18];
10459 
10460 	u8         syndrome[0x20];
10461 
10462 	struct mlx5_ifc_lagc_bits ctx;
10463 };
10464 
10465 struct mlx5_ifc_query_lag_in_bits {
10466 	u8         opcode[0x10];
10467 	u8         reserved_at_10[0x10];
10468 
10469 	u8         reserved_at_20[0x10];
10470 	u8         op_mod[0x10];
10471 
10472 	u8         reserved_at_40[0x40];
10473 };
10474 
10475 struct mlx5_ifc_destroy_lag_out_bits {
10476 	u8         status[0x8];
10477 	u8         reserved_at_8[0x18];
10478 
10479 	u8         syndrome[0x20];
10480 
10481 	u8         reserved_at_40[0x40];
10482 };
10483 
10484 struct mlx5_ifc_destroy_lag_in_bits {
10485 	u8         opcode[0x10];
10486 	u8         reserved_at_10[0x10];
10487 
10488 	u8         reserved_at_20[0x10];
10489 	u8         op_mod[0x10];
10490 
10491 	u8         reserved_at_40[0x40];
10492 };
10493 
10494 struct mlx5_ifc_create_vport_lag_out_bits {
10495 	u8         status[0x8];
10496 	u8         reserved_at_8[0x18];
10497 
10498 	u8         syndrome[0x20];
10499 
10500 	u8         reserved_at_40[0x40];
10501 };
10502 
10503 struct mlx5_ifc_create_vport_lag_in_bits {
10504 	u8         opcode[0x10];
10505 	u8         reserved_at_10[0x10];
10506 
10507 	u8         reserved_at_20[0x10];
10508 	u8         op_mod[0x10];
10509 
10510 	u8         reserved_at_40[0x40];
10511 };
10512 
10513 struct mlx5_ifc_destroy_vport_lag_out_bits {
10514 	u8         status[0x8];
10515 	u8         reserved_at_8[0x18];
10516 
10517 	u8         syndrome[0x20];
10518 
10519 	u8         reserved_at_40[0x40];
10520 };
10521 
10522 struct mlx5_ifc_destroy_vport_lag_in_bits {
10523 	u8         opcode[0x10];
10524 	u8         reserved_at_10[0x10];
10525 
10526 	u8         reserved_at_20[0x10];
10527 	u8         op_mod[0x10];
10528 
10529 	u8         reserved_at_40[0x40];
10530 };
10531 
10532 enum {
10533 	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
10534 	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
10535 };
10536 
10537 struct mlx5_ifc_modify_memic_in_bits {
10538 	u8         opcode[0x10];
10539 	u8         uid[0x10];
10540 
10541 	u8         reserved_at_20[0x10];
10542 	u8         op_mod[0x10];
10543 
10544 	u8         reserved_at_40[0x20];
10545 
10546 	u8         reserved_at_60[0x18];
10547 	u8         memic_operation_type[0x8];
10548 
10549 	u8         memic_start_addr[0x40];
10550 
10551 	u8         reserved_at_c0[0x140];
10552 };
10553 
10554 struct mlx5_ifc_modify_memic_out_bits {
10555 	u8         status[0x8];
10556 	u8         reserved_at_8[0x18];
10557 
10558 	u8         syndrome[0x20];
10559 
10560 	u8         reserved_at_40[0x40];
10561 
10562 	u8         memic_operation_addr[0x40];
10563 
10564 	u8         reserved_at_c0[0x140];
10565 };
10566 
10567 struct mlx5_ifc_alloc_memic_in_bits {
10568 	u8         opcode[0x10];
10569 	u8         reserved_at_10[0x10];
10570 
10571 	u8         reserved_at_20[0x10];
10572 	u8         op_mod[0x10];
10573 
10574 	u8         reserved_at_30[0x20];
10575 
10576 	u8	   reserved_at_40[0x18];
10577 	u8	   log_memic_addr_alignment[0x8];
10578 
10579 	u8         range_start_addr[0x40];
10580 
10581 	u8         range_size[0x20];
10582 
10583 	u8         memic_size[0x20];
10584 };
10585 
10586 struct mlx5_ifc_alloc_memic_out_bits {
10587 	u8         status[0x8];
10588 	u8         reserved_at_8[0x18];
10589 
10590 	u8         syndrome[0x20];
10591 
10592 	u8         memic_start_addr[0x40];
10593 };
10594 
10595 struct mlx5_ifc_dealloc_memic_in_bits {
10596 	u8         opcode[0x10];
10597 	u8         reserved_at_10[0x10];
10598 
10599 	u8         reserved_at_20[0x10];
10600 	u8         op_mod[0x10];
10601 
10602 	u8         reserved_at_40[0x40];
10603 
10604 	u8         memic_start_addr[0x40];
10605 
10606 	u8         memic_size[0x20];
10607 
10608 	u8         reserved_at_e0[0x20];
10609 };
10610 
10611 struct mlx5_ifc_dealloc_memic_out_bits {
10612 	u8         status[0x8];
10613 	u8         reserved_at_8[0x18];
10614 
10615 	u8         syndrome[0x20];
10616 
10617 	u8         reserved_at_40[0x40];
10618 };
10619 
10620 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10621 	u8         opcode[0x10];
10622 	u8         uid[0x10];
10623 
10624 	u8         vhca_tunnel_id[0x10];
10625 	u8         obj_type[0x10];
10626 
10627 	u8         obj_id[0x20];
10628 
10629 	u8         reserved_at_60[0x20];
10630 };
10631 
10632 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10633 	u8         status[0x8];
10634 	u8         reserved_at_8[0x18];
10635 
10636 	u8         syndrome[0x20];
10637 
10638 	u8         obj_id[0x20];
10639 
10640 	u8         reserved_at_60[0x20];
10641 };
10642 
10643 struct mlx5_ifc_umem_bits {
10644 	u8         reserved_at_0[0x80];
10645 
10646 	u8         reserved_at_80[0x1b];
10647 	u8         log_page_size[0x5];
10648 
10649 	u8         page_offset[0x20];
10650 
10651 	u8         num_of_mtt[0x40];
10652 
10653 	struct mlx5_ifc_mtt_bits  mtt[];
10654 };
10655 
10656 struct mlx5_ifc_uctx_bits {
10657 	u8         cap[0x20];
10658 
10659 	u8         reserved_at_20[0x160];
10660 };
10661 
10662 struct mlx5_ifc_sw_icm_bits {
10663 	u8         modify_field_select[0x40];
10664 
10665 	u8	   reserved_at_40[0x18];
10666 	u8         log_sw_icm_size[0x8];
10667 
10668 	u8         reserved_at_60[0x20];
10669 
10670 	u8         sw_icm_start_addr[0x40];
10671 
10672 	u8         reserved_at_c0[0x140];
10673 };
10674 
10675 struct mlx5_ifc_geneve_tlv_option_bits {
10676 	u8         modify_field_select[0x40];
10677 
10678 	u8         reserved_at_40[0x18];
10679 	u8         geneve_option_fte_index[0x8];
10680 
10681 	u8         option_class[0x10];
10682 	u8         option_type[0x8];
10683 	u8         reserved_at_78[0x3];
10684 	u8         option_data_length[0x5];
10685 
10686 	u8         reserved_at_80[0x180];
10687 };
10688 
10689 struct mlx5_ifc_create_umem_in_bits {
10690 	u8         opcode[0x10];
10691 	u8         uid[0x10];
10692 
10693 	u8         reserved_at_20[0x10];
10694 	u8         op_mod[0x10];
10695 
10696 	u8         reserved_at_40[0x40];
10697 
10698 	struct mlx5_ifc_umem_bits  umem;
10699 };
10700 
10701 struct mlx5_ifc_create_umem_out_bits {
10702 	u8         status[0x8];
10703 	u8         reserved_at_8[0x18];
10704 
10705 	u8         syndrome[0x20];
10706 
10707 	u8         reserved_at_40[0x8];
10708 	u8         umem_id[0x18];
10709 
10710 	u8         reserved_at_60[0x20];
10711 };
10712 
10713 struct mlx5_ifc_destroy_umem_in_bits {
10714 	u8        opcode[0x10];
10715 	u8        uid[0x10];
10716 
10717 	u8        reserved_at_20[0x10];
10718 	u8        op_mod[0x10];
10719 
10720 	u8        reserved_at_40[0x8];
10721 	u8        umem_id[0x18];
10722 
10723 	u8        reserved_at_60[0x20];
10724 };
10725 
10726 struct mlx5_ifc_destroy_umem_out_bits {
10727 	u8        status[0x8];
10728 	u8        reserved_at_8[0x18];
10729 
10730 	u8        syndrome[0x20];
10731 
10732 	u8        reserved_at_40[0x40];
10733 };
10734 
10735 struct mlx5_ifc_create_uctx_in_bits {
10736 	u8         opcode[0x10];
10737 	u8         reserved_at_10[0x10];
10738 
10739 	u8         reserved_at_20[0x10];
10740 	u8         op_mod[0x10];
10741 
10742 	u8         reserved_at_40[0x40];
10743 
10744 	struct mlx5_ifc_uctx_bits  uctx;
10745 };
10746 
10747 struct mlx5_ifc_create_uctx_out_bits {
10748 	u8         status[0x8];
10749 	u8         reserved_at_8[0x18];
10750 
10751 	u8         syndrome[0x20];
10752 
10753 	u8         reserved_at_40[0x10];
10754 	u8         uid[0x10];
10755 
10756 	u8         reserved_at_60[0x20];
10757 };
10758 
10759 struct mlx5_ifc_destroy_uctx_in_bits {
10760 	u8         opcode[0x10];
10761 	u8         reserved_at_10[0x10];
10762 
10763 	u8         reserved_at_20[0x10];
10764 	u8         op_mod[0x10];
10765 
10766 	u8         reserved_at_40[0x10];
10767 	u8         uid[0x10];
10768 
10769 	u8         reserved_at_60[0x20];
10770 };
10771 
10772 struct mlx5_ifc_destroy_uctx_out_bits {
10773 	u8         status[0x8];
10774 	u8         reserved_at_8[0x18];
10775 
10776 	u8         syndrome[0x20];
10777 
10778 	u8          reserved_at_40[0x40];
10779 };
10780 
10781 struct mlx5_ifc_create_sw_icm_in_bits {
10782 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10783 	struct mlx5_ifc_sw_icm_bits		      sw_icm;
10784 };
10785 
10786 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10787 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10788 	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
10789 };
10790 
10791 struct mlx5_ifc_mtrc_string_db_param_bits {
10792 	u8         string_db_base_address[0x20];
10793 
10794 	u8         reserved_at_20[0x8];
10795 	u8         string_db_size[0x18];
10796 };
10797 
10798 struct mlx5_ifc_mtrc_cap_bits {
10799 	u8         trace_owner[0x1];
10800 	u8         trace_to_memory[0x1];
10801 	u8         reserved_at_2[0x4];
10802 	u8         trc_ver[0x2];
10803 	u8         reserved_at_8[0x14];
10804 	u8         num_string_db[0x4];
10805 
10806 	u8         first_string_trace[0x8];
10807 	u8         num_string_trace[0x8];
10808 	u8         reserved_at_30[0x28];
10809 
10810 	u8         log_max_trace_buffer_size[0x8];
10811 
10812 	u8         reserved_at_60[0x20];
10813 
10814 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10815 
10816 	u8         reserved_at_280[0x180];
10817 };
10818 
10819 struct mlx5_ifc_mtrc_conf_bits {
10820 	u8         reserved_at_0[0x1c];
10821 	u8         trace_mode[0x4];
10822 	u8         reserved_at_20[0x18];
10823 	u8         log_trace_buffer_size[0x8];
10824 	u8         trace_mkey[0x20];
10825 	u8         reserved_at_60[0x3a0];
10826 };
10827 
10828 struct mlx5_ifc_mtrc_stdb_bits {
10829 	u8         string_db_index[0x4];
10830 	u8         reserved_at_4[0x4];
10831 	u8         read_size[0x18];
10832 	u8         start_offset[0x20];
10833 	u8         string_db_data[];
10834 };
10835 
10836 struct mlx5_ifc_mtrc_ctrl_bits {
10837 	u8         trace_status[0x2];
10838 	u8         reserved_at_2[0x2];
10839 	u8         arm_event[0x1];
10840 	u8         reserved_at_5[0xb];
10841 	u8         modify_field_select[0x10];
10842 	u8         reserved_at_20[0x2b];
10843 	u8         current_timestamp52_32[0x15];
10844 	u8         current_timestamp31_0[0x20];
10845 	u8         reserved_at_80[0x180];
10846 };
10847 
10848 struct mlx5_ifc_host_params_context_bits {
10849 	u8         host_number[0x8];
10850 	u8         reserved_at_8[0x7];
10851 	u8         host_pf_disabled[0x1];
10852 	u8         host_num_of_vfs[0x10];
10853 
10854 	u8         host_total_vfs[0x10];
10855 	u8         host_pci_bus[0x10];
10856 
10857 	u8         reserved_at_40[0x10];
10858 	u8         host_pci_device[0x10];
10859 
10860 	u8         reserved_at_60[0x10];
10861 	u8         host_pci_function[0x10];
10862 
10863 	u8         reserved_at_80[0x180];
10864 };
10865 
10866 struct mlx5_ifc_query_esw_functions_in_bits {
10867 	u8         opcode[0x10];
10868 	u8         reserved_at_10[0x10];
10869 
10870 	u8         reserved_at_20[0x10];
10871 	u8         op_mod[0x10];
10872 
10873 	u8         reserved_at_40[0x40];
10874 };
10875 
10876 struct mlx5_ifc_query_esw_functions_out_bits {
10877 	u8         status[0x8];
10878 	u8         reserved_at_8[0x18];
10879 
10880 	u8         syndrome[0x20];
10881 
10882 	u8         reserved_at_40[0x40];
10883 
10884 	struct mlx5_ifc_host_params_context_bits host_params_context;
10885 
10886 	u8         reserved_at_280[0x180];
10887 	u8         host_sf_enable[][0x40];
10888 };
10889 
10890 struct mlx5_ifc_sf_partition_bits {
10891 	u8         reserved_at_0[0x10];
10892 	u8         log_num_sf[0x8];
10893 	u8         log_sf_bar_size[0x8];
10894 };
10895 
10896 struct mlx5_ifc_query_sf_partitions_out_bits {
10897 	u8         status[0x8];
10898 	u8         reserved_at_8[0x18];
10899 
10900 	u8         syndrome[0x20];
10901 
10902 	u8         reserved_at_40[0x18];
10903 	u8         num_sf_partitions[0x8];
10904 
10905 	u8         reserved_at_60[0x20];
10906 
10907 	struct mlx5_ifc_sf_partition_bits sf_partition[];
10908 };
10909 
10910 struct mlx5_ifc_query_sf_partitions_in_bits {
10911 	u8         opcode[0x10];
10912 	u8         reserved_at_10[0x10];
10913 
10914 	u8         reserved_at_20[0x10];
10915 	u8         op_mod[0x10];
10916 
10917 	u8         reserved_at_40[0x40];
10918 };
10919 
10920 struct mlx5_ifc_dealloc_sf_out_bits {
10921 	u8         status[0x8];
10922 	u8         reserved_at_8[0x18];
10923 
10924 	u8         syndrome[0x20];
10925 
10926 	u8         reserved_at_40[0x40];
10927 };
10928 
10929 struct mlx5_ifc_dealloc_sf_in_bits {
10930 	u8         opcode[0x10];
10931 	u8         reserved_at_10[0x10];
10932 
10933 	u8         reserved_at_20[0x10];
10934 	u8         op_mod[0x10];
10935 
10936 	u8         reserved_at_40[0x10];
10937 	u8         function_id[0x10];
10938 
10939 	u8         reserved_at_60[0x20];
10940 };
10941 
10942 struct mlx5_ifc_alloc_sf_out_bits {
10943 	u8         status[0x8];
10944 	u8         reserved_at_8[0x18];
10945 
10946 	u8         syndrome[0x20];
10947 
10948 	u8         reserved_at_40[0x40];
10949 };
10950 
10951 struct mlx5_ifc_alloc_sf_in_bits {
10952 	u8         opcode[0x10];
10953 	u8         reserved_at_10[0x10];
10954 
10955 	u8         reserved_at_20[0x10];
10956 	u8         op_mod[0x10];
10957 
10958 	u8         reserved_at_40[0x10];
10959 	u8         function_id[0x10];
10960 
10961 	u8         reserved_at_60[0x20];
10962 };
10963 
10964 struct mlx5_ifc_affiliated_event_header_bits {
10965 	u8         reserved_at_0[0x10];
10966 	u8         obj_type[0x10];
10967 
10968 	u8         obj_id[0x20];
10969 };
10970 
10971 enum {
10972 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
10973 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
10974 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
10975 };
10976 
10977 enum {
10978 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10979 	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
10980 	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
10981 };
10982 
10983 enum {
10984 	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
10985 	MLX5_IPSEC_OBJECT_ICV_LEN_12B,
10986 	MLX5_IPSEC_OBJECT_ICV_LEN_8B,
10987 };
10988 
10989 struct mlx5_ifc_ipsec_obj_bits {
10990 	u8         modify_field_select[0x40];
10991 	u8         full_offload[0x1];
10992 	u8         reserved_at_41[0x1];
10993 	u8         esn_en[0x1];
10994 	u8         esn_overlap[0x1];
10995 	u8         reserved_at_44[0x2];
10996 	u8         icv_length[0x2];
10997 	u8         reserved_at_48[0x4];
10998 	u8         aso_return_reg[0x4];
10999 	u8         reserved_at_50[0x10];
11000 
11001 	u8         esn_msb[0x20];
11002 
11003 	u8         reserved_at_80[0x8];
11004 	u8         dekn[0x18];
11005 
11006 	u8         salt[0x20];
11007 
11008 	u8         implicit_iv[0x40];
11009 
11010 	u8         reserved_at_100[0x700];
11011 };
11012 
11013 struct mlx5_ifc_create_ipsec_obj_in_bits {
11014 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11015 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11016 };
11017 
11018 enum {
11019 	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11020 	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11021 };
11022 
11023 struct mlx5_ifc_query_ipsec_obj_out_bits {
11024 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11025 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11026 };
11027 
11028 struct mlx5_ifc_modify_ipsec_obj_in_bits {
11029 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11030 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11031 };
11032 
11033 struct mlx5_ifc_encryption_key_obj_bits {
11034 	u8         modify_field_select[0x40];
11035 
11036 	u8         reserved_at_40[0x14];
11037 	u8         key_size[0x4];
11038 	u8         reserved_at_58[0x4];
11039 	u8         key_type[0x4];
11040 
11041 	u8         reserved_at_60[0x8];
11042 	u8         pd[0x18];
11043 
11044 	u8         reserved_at_80[0x180];
11045 	u8         key[8][0x20];
11046 
11047 	u8         reserved_at_300[0x500];
11048 };
11049 
11050 struct mlx5_ifc_create_encryption_key_in_bits {
11051 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11052 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11053 };
11054 
11055 struct mlx5_ifc_sampler_obj_bits {
11056 	u8         modify_field_select[0x40];
11057 
11058 	u8         table_type[0x8];
11059 	u8         level[0x8];
11060 	u8         reserved_at_50[0xf];
11061 	u8         ignore_flow_level[0x1];
11062 
11063 	u8         sample_ratio[0x20];
11064 
11065 	u8         reserved_at_80[0x8];
11066 	u8         sample_table_id[0x18];
11067 
11068 	u8         reserved_at_a0[0x8];
11069 	u8         default_table_id[0x18];
11070 
11071 	u8         sw_steering_icm_address_rx[0x40];
11072 	u8         sw_steering_icm_address_tx[0x40];
11073 
11074 	u8         reserved_at_140[0xa0];
11075 };
11076 
11077 struct mlx5_ifc_create_sampler_obj_in_bits {
11078 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11079 	struct mlx5_ifc_sampler_obj_bits sampler_object;
11080 };
11081 
11082 struct mlx5_ifc_query_sampler_obj_out_bits {
11083 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11084 	struct mlx5_ifc_sampler_obj_bits sampler_object;
11085 };
11086 
11087 enum {
11088 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11089 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11090 };
11091 
11092 enum {
11093 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11094 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
11095 };
11096 
11097 struct mlx5_ifc_tls_static_params_bits {
11098 	u8         const_2[0x2];
11099 	u8         tls_version[0x4];
11100 	u8         const_1[0x2];
11101 	u8         reserved_at_8[0x14];
11102 	u8         encryption_standard[0x4];
11103 
11104 	u8         reserved_at_20[0x20];
11105 
11106 	u8         initial_record_number[0x40];
11107 
11108 	u8         resync_tcp_sn[0x20];
11109 
11110 	u8         gcm_iv[0x20];
11111 
11112 	u8         implicit_iv[0x40];
11113 
11114 	u8         reserved_at_100[0x8];
11115 	u8         dek_index[0x18];
11116 
11117 	u8         reserved_at_120[0xe0];
11118 };
11119 
11120 struct mlx5_ifc_tls_progress_params_bits {
11121 	u8         next_record_tcp_sn[0x20];
11122 
11123 	u8         hw_resync_tcp_sn[0x20];
11124 
11125 	u8         record_tracker_state[0x2];
11126 	u8         auth_state[0x2];
11127 	u8         reserved_at_44[0x4];
11128 	u8         hw_offset_record_number[0x18];
11129 };
11130 
11131 enum {
11132 	MLX5_MTT_PERM_READ	= 1 << 0,
11133 	MLX5_MTT_PERM_WRITE	= 1 << 1,
11134 	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11135 };
11136 
11137 #endif /* MLX5_IFC_H */
11138