1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2021, Collabora 4 * 5 * Author: Benjamin Gaignard <benjamin.gaignard@collabora.com> 6 */ 7 8 #ifndef HANTRO_G2_REGS_H_ 9 #define HANTRO_G2_REGS_H_ 10 11 #include "hantro.h" 12 13 #define G2_SWREG(nr) ((nr) * 4) 14 15 #define G2_DEC_REG(b, s, m) \ 16 ((const struct hantro_reg) { \ 17 .base = G2_SWREG(b), \ 18 .shift = s, \ 19 .mask = m, \ 20 }) 21 22 #define G2_REG_VERSION G2_SWREG(0) 23 24 #define G2_REG_INTERRUPT G2_SWREG(1) 25 #define G2_REG_INTERRUPT_DEC_RDY_INT BIT(12) 26 #define G2_REG_INTERRUPT_DEC_ABORT_E BIT(5) 27 #define G2_REG_INTERRUPT_DEC_IRQ_DIS BIT(4) 28 #define G2_REG_INTERRUPT_DEC_E BIT(0) 29 30 #define g2_strm_swap G2_DEC_REG(2, 28, 0xf) 31 #define g2_dirmv_swap G2_DEC_REG(2, 20, 0xf) 32 33 #define g2_mode G2_DEC_REG(3, 27, 0x1f) 34 #define g2_compress_swap G2_DEC_REG(3, 20, 0xf) 35 #define g2_ref_compress_bypass G2_DEC_REG(3, 17, 0x1) 36 #define g2_out_rs_e G2_DEC_REG(3, 16, 0x1) 37 #define g2_out_dis G2_DEC_REG(3, 15, 0x1) 38 #define g2_out_filtering_dis G2_DEC_REG(3, 14, 0x1) 39 #define g2_write_mvs_e G2_DEC_REG(3, 12, 0x1) 40 41 #define g2_pic_width_in_cbs G2_DEC_REG(4, 19, 0x1fff) 42 #define g2_pic_height_in_cbs G2_DEC_REG(4, 6, 0x1fff) 43 #define g2_num_ref_frames G2_DEC_REG(4, 0, 0x1f) 44 45 #define g2_scaling_list_e G2_DEC_REG(5, 24, 0x1) 46 #define g2_cb_qp_offset G2_DEC_REG(5, 19, 0x1f) 47 #define g2_cr_qp_offset G2_DEC_REG(5, 14, 0x1f) 48 #define g2_sign_data_hide G2_DEC_REG(5, 12, 0x1) 49 #define g2_tempor_mvp_e G2_DEC_REG(5, 11, 0x1) 50 #define g2_max_cu_qpd_depth G2_DEC_REG(5, 5, 0x3f) 51 #define g2_cu_qpd_e G2_DEC_REG(5, 4, 0x1) 52 53 #define g2_stream_len G2_DEC_REG(6, 0, 0xffffffff) 54 55 #define g2_cabac_init_present G2_DEC_REG(7, 31, 0x1) 56 #define g2_weight_pred_e G2_DEC_REG(7, 28, 0x1) 57 #define g2_weight_bipr_idc G2_DEC_REG(7, 26, 0x3) 58 #define g2_filter_over_slices G2_DEC_REG(7, 25, 0x1) 59 #define g2_filter_over_tiles G2_DEC_REG(7, 24, 0x1) 60 #define g2_asym_pred_e G2_DEC_REG(7, 23, 0x1) 61 #define g2_sao_e G2_DEC_REG(7, 22, 0x1) 62 #define g2_pcm_filt_d G2_DEC_REG(7, 21, 0x1) 63 #define g2_slice_chqp_present G2_DEC_REG(7, 20, 0x1) 64 #define g2_dependent_slice G2_DEC_REG(7, 19, 0x1) 65 #define g2_filter_override G2_DEC_REG(7, 18, 0x1) 66 #define g2_strong_smooth_e G2_DEC_REG(7, 17, 0x1) 67 #define g2_filt_offset_beta G2_DEC_REG(7, 12, 0x1f) 68 #define g2_filt_offset_tc G2_DEC_REG(7, 7, 0x1f) 69 #define g2_slice_hdr_ext_e G2_DEC_REG(7, 6, 0x1) 70 #define g2_slice_hdr_ext_bits G2_DEC_REG(7, 3, 0x7) 71 72 #define g2_const_intra_e G2_DEC_REG(8, 31, 0x1) 73 #define g2_filt_ctrl_pres G2_DEC_REG(8, 30, 0x1) 74 #define g2_idr_pic_e G2_DEC_REG(8, 16, 0x1) 75 #define g2_bit_depth_pcm_y G2_DEC_REG(8, 12, 0xf) 76 #define g2_bit_depth_pcm_c G2_DEC_REG(8, 8, 0xf) 77 #define g2_bit_depth_y_minus8 G2_DEC_REG(8, 6, 0x3) 78 #define g2_bit_depth_c_minus8 G2_DEC_REG(8, 4, 0x3) 79 #define g2_output_8_bits G2_DEC_REG(8, 3, 0x1) 80 81 #define g2_refidx1_active G2_DEC_REG(9, 19, 0x1f) 82 #define g2_refidx0_active G2_DEC_REG(9, 14, 0x1f) 83 #define g2_hdr_skip_length G2_DEC_REG(9, 0, 0x3fff) 84 85 #define g2_start_code_e G2_DEC_REG(10, 31, 0x1) 86 #define g2_init_qp G2_DEC_REG(10, 24, 0x3f) 87 #define g2_num_tile_cols G2_DEC_REG(10, 19, 0x1f) 88 #define g2_num_tile_rows G2_DEC_REG(10, 14, 0x1f) 89 #define g2_tile_e G2_DEC_REG(10, 1, 0x1) 90 #define g2_entropy_sync_e G2_DEC_REG(10, 0, 0x1) 91 92 #define g2_refer_lterm_e G2_DEC_REG(12, 16, 0xffff) 93 #define g2_min_cb_size G2_DEC_REG(12, 13, 0x7) 94 #define g2_max_cb_size G2_DEC_REG(12, 10, 0x7) 95 #define g2_min_pcm_size G2_DEC_REG(12, 7, 0x7) 96 #define g2_max_pcm_size G2_DEC_REG(12, 4, 0x7) 97 #define g2_pcm_e G2_DEC_REG(12, 3, 0x1) 98 #define g2_transform_skip G2_DEC_REG(12, 2, 0x1) 99 #define g2_transq_bypass G2_DEC_REG(12, 1, 0x1) 100 #define g2_list_mod_e G2_DEC_REG(12, 0, 0x1) 101 102 #define hevc_min_trb_size G2_DEC_REG(13, 13, 0x7) 103 #define hevc_max_trb_size G2_DEC_REG(13, 10, 0x7) 104 #define hevc_max_intra_hierdepth G2_DEC_REG(13, 7, 0x7) 105 #define hevc_max_inter_hierdepth G2_DEC_REG(13, 4, 0x7) 106 #define hevc_parallel_merge G2_DEC_REG(13, 0, 0xf) 107 108 #define hevc_rlist_f0 G2_DEC_REG(14, 0, 0x1f) 109 #define hevc_rlist_f1 G2_DEC_REG(14, 10, 0x1f) 110 #define hevc_rlist_f2 G2_DEC_REG(14, 20, 0x1f) 111 #define hevc_rlist_b0 G2_DEC_REG(14, 5, 0x1f) 112 #define hevc_rlist_b1 G2_DEC_REG(14, 15, 0x1f) 113 #define hevc_rlist_b2 G2_DEC_REG(14, 25, 0x1f) 114 115 #define hevc_rlist_f3 G2_DEC_REG(15, 0, 0x1f) 116 #define hevc_rlist_f4 G2_DEC_REG(15, 10, 0x1f) 117 #define hevc_rlist_f5 G2_DEC_REG(15, 20, 0x1f) 118 #define hevc_rlist_b3 G2_DEC_REG(15, 5, 0x1f) 119 #define hevc_rlist_b4 G2_DEC_REG(15, 15, 0x1f) 120 #define hevc_rlist_b5 G2_DEC_REG(15, 25, 0x1f) 121 122 #define hevc_rlist_f6 G2_DEC_REG(16, 0, 0x1f) 123 #define hevc_rlist_f7 G2_DEC_REG(16, 10, 0x1f) 124 #define hevc_rlist_f8 G2_DEC_REG(16, 20, 0x1f) 125 #define hevc_rlist_b6 G2_DEC_REG(16, 5, 0x1f) 126 #define hevc_rlist_b7 G2_DEC_REG(16, 15, 0x1f) 127 #define hevc_rlist_b8 G2_DEC_REG(16, 25, 0x1f) 128 129 #define hevc_rlist_f9 G2_DEC_REG(17, 0, 0x1f) 130 #define hevc_rlist_f10 G2_DEC_REG(17, 10, 0x1f) 131 #define hevc_rlist_f11 G2_DEC_REG(17, 20, 0x1f) 132 #define hevc_rlist_b9 G2_DEC_REG(17, 5, 0x1f) 133 #define hevc_rlist_b10 G2_DEC_REG(17, 15, 0x1f) 134 #define hevc_rlist_b11 G2_DEC_REG(17, 25, 0x1f) 135 136 #define hevc_rlist_f12 G2_DEC_REG(18, 0, 0x1f) 137 #define hevc_rlist_f13 G2_DEC_REG(18, 10, 0x1f) 138 #define hevc_rlist_f14 G2_DEC_REG(18, 20, 0x1f) 139 #define hevc_rlist_b12 G2_DEC_REG(18, 5, 0x1f) 140 #define hevc_rlist_b13 G2_DEC_REG(18, 15, 0x1f) 141 #define hevc_rlist_b14 G2_DEC_REG(18, 25, 0x1f) 142 143 #define hevc_rlist_f15 G2_DEC_REG(19, 0, 0x1f) 144 #define hevc_rlist_b15 G2_DEC_REG(19, 5, 0x1f) 145 146 #define g2_partial_ctb_x G2_DEC_REG(20, 31, 0x1) 147 #define g2_partial_ctb_y G2_DEC_REG(20, 30, 0x1) 148 #define g2_pic_width_4x4 G2_DEC_REG(20, 16, 0xfff) 149 #define g2_pic_height_4x4 G2_DEC_REG(20, 0, 0xfff) 150 #define hevc_cur_poc_00 G2_DEC_REG(46, 24, 0xff) 151 #define hevc_cur_poc_01 G2_DEC_REG(46, 16, 0xff) 152 #define hevc_cur_poc_02 G2_DEC_REG(46, 8, 0xff) 153 #define hevc_cur_poc_03 G2_DEC_REG(46, 0, 0xff) 154 155 #define hevc_cur_poc_04 G2_DEC_REG(47, 24, 0xff) 156 #define hevc_cur_poc_05 G2_DEC_REG(47, 16, 0xff) 157 #define hevc_cur_poc_06 G2_DEC_REG(47, 8, 0xff) 158 #define hevc_cur_poc_07 G2_DEC_REG(47, 0, 0xff) 159 160 #define hevc_cur_poc_08 G2_DEC_REG(48, 24, 0xff) 161 #define hevc_cur_poc_09 G2_DEC_REG(48, 16, 0xff) 162 #define hevc_cur_poc_10 G2_DEC_REG(48, 8, 0xff) 163 #define hevc_cur_poc_11 G2_DEC_REG(48, 0, 0xff) 164 165 #define hevc_cur_poc_12 G2_DEC_REG(49, 24, 0xff) 166 #define hevc_cur_poc_13 G2_DEC_REG(49, 16, 0xff) 167 #define hevc_cur_poc_14 G2_DEC_REG(49, 8, 0xff) 168 #define hevc_cur_poc_15 G2_DEC_REG(49, 0, 0xff) 169 170 #define g2_apf_threshold G2_DEC_REG(55, 0, 0xffff) 171 172 #define g2_clk_gate_e G2_DEC_REG(58, 16, 0x1) 173 #define g2_buswidth G2_DEC_REG(58, 8, 0x7) 174 #define g2_max_burst G2_DEC_REG(58, 0, 0xff) 175 176 #define G2_REG_CONFIG G2_SWREG(58) 177 #define G2_REG_CONFIG_DEC_CLK_GATE_E BIT(16) 178 #define G2_REG_CONFIG_DEC_CLK_GATE_IDLE_E BIT(17) 179 180 #define G2_ADDR_DST (G2_SWREG(65)) 181 #define G2_REG_ADDR_REF(i) (G2_SWREG(67) + ((i) * 0x8)) 182 #define G2_ADDR_DST_CHR (G2_SWREG(99)) 183 #define G2_REG_CHR_REF(i) (G2_SWREG(101) + ((i) * 0x8)) 184 #define G2_ADDR_DST_MV (G2_SWREG(133)) 185 #define G2_REG_DMV_REF(i) (G2_SWREG(135) + ((i) * 0x8)) 186 #define G2_ADDR_TILE_SIZE (G2_SWREG(167)) 187 #define G2_ADDR_STR (G2_SWREG(169)) 188 #define HEVC_SCALING_LIST (G2_SWREG(171)) 189 #define G2_RASTER_SCAN (G2_SWREG(175)) 190 #define G2_RASTER_SCAN_CHR (G2_SWREG(177)) 191 #define G2_TILE_FILTER (G2_SWREG(179)) 192 #define G2_TILE_SAO (G2_SWREG(181)) 193 #define G2_TILE_BSD (G2_SWREG(183)) 194 195 #define g2_strm_buffer_len G2_DEC_REG(258, 0, 0xffffffff) 196 #define g2_strm_start_offset G2_DEC_REG(259, 0, 0xffffffff) 197 198 #endif 199