1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
3 #include <linux/dma-mapping.h>
4 #include <linux/module.h>
5 #include <linux/slab.h>
6 #include "qm.h"
7
8 #define HISI_ACC_SGL_SGE_NR_MIN 1
9 #define HISI_ACC_SGL_NR_MAX 256
10 #define HISI_ACC_SGL_ALIGN_SIZE 64
11 #define HISI_ACC_MEM_BLOCK_NR 5
12
13 struct acc_hw_sge {
14 dma_addr_t buf;
15 void *page_ctrl;
16 __le32 len;
17 __le32 pad;
18 __le32 pad0;
19 __le32 pad1;
20 };
21
22 /* use default sgl head size 64B */
23 struct hisi_acc_hw_sgl {
24 dma_addr_t next_dma;
25 __le16 entry_sum_in_chain;
26 __le16 entry_sum_in_sgl;
27 __le16 entry_length_in_sgl;
28 __le16 pad0;
29 __le64 pad1[5];
30 struct hisi_acc_hw_sgl *next;
31 struct acc_hw_sge sge_entries[];
32 } __aligned(1);
33
34 struct hisi_acc_sgl_pool {
35 struct mem_block {
36 struct hisi_acc_hw_sgl *sgl;
37 dma_addr_t sgl_dma;
38 size_t size;
39 } mem_block[HISI_ACC_MEM_BLOCK_NR];
40 u32 sgl_num_per_block;
41 u32 block_num;
42 u32 count;
43 u32 sge_nr;
44 size_t sgl_size;
45 };
46
47 /**
48 * hisi_acc_create_sgl_pool() - Create a hw sgl pool.
49 * @dev: The device which hw sgl pool belongs to.
50 * @count: Count of hisi_acc_hw_sgl in pool.
51 * @sge_nr: The count of sge in hw_sgl
52 *
53 * This function creates a hw sgl pool, after this user can get hw sgl memory
54 * from it.
55 */
hisi_acc_create_sgl_pool(struct device * dev,u32 count,u32 sge_nr)56 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
57 u32 count, u32 sge_nr)
58 {
59 u32 sgl_size, block_size, sgl_num_per_block, block_num, remain_sgl;
60 struct hisi_acc_sgl_pool *pool;
61 struct mem_block *block;
62 u32 i, j;
63
64 if (!dev || !count || !sge_nr || sge_nr > HISI_ACC_SGL_SGE_NR_MAX)
65 return ERR_PTR(-EINVAL);
66
67 sgl_size = sizeof(struct acc_hw_sge) * sge_nr +
68 sizeof(struct hisi_acc_hw_sgl);
69
70 /*
71 * the pool may allocate a block of memory of size PAGE_SIZE * 2^(MAX_ORDER - 1),
72 * block size may exceed 2^31 on ia64, so the max of block size is 2^31
73 */
74 block_size = 1 << (PAGE_SHIFT + MAX_ORDER <= 32 ?
75 PAGE_SHIFT + MAX_ORDER - 1 : 31);
76 sgl_num_per_block = block_size / sgl_size;
77 block_num = count / sgl_num_per_block;
78 remain_sgl = count % sgl_num_per_block;
79
80 if ((!remain_sgl && block_num > HISI_ACC_MEM_BLOCK_NR) ||
81 (remain_sgl > 0 && block_num > HISI_ACC_MEM_BLOCK_NR - 1))
82 return ERR_PTR(-EINVAL);
83
84 pool = kzalloc(sizeof(*pool), GFP_KERNEL);
85 if (!pool)
86 return ERR_PTR(-ENOMEM);
87 block = pool->mem_block;
88
89 for (i = 0; i < block_num; i++) {
90 block[i].sgl = dma_alloc_coherent(dev, block_size,
91 &block[i].sgl_dma,
92 GFP_KERNEL);
93 if (!block[i].sgl) {
94 dev_err(dev, "Fail to allocate hw SG buffer!\n");
95 goto err_free_mem;
96 }
97
98 block[i].size = block_size;
99 }
100
101 if (remain_sgl > 0) {
102 block[i].sgl = dma_alloc_coherent(dev, remain_sgl * sgl_size,
103 &block[i].sgl_dma,
104 GFP_KERNEL);
105 if (!block[i].sgl) {
106 dev_err(dev, "Fail to allocate remained hw SG buffer!\n");
107 goto err_free_mem;
108 }
109
110 block[i].size = remain_sgl * sgl_size;
111 }
112
113 pool->sgl_num_per_block = sgl_num_per_block;
114 pool->block_num = remain_sgl ? block_num + 1 : block_num;
115 pool->count = count;
116 pool->sgl_size = sgl_size;
117 pool->sge_nr = sge_nr;
118
119 return pool;
120
121 err_free_mem:
122 for (j = 0; j < i; j++) {
123 dma_free_coherent(dev, block_size, block[j].sgl,
124 block[j].sgl_dma);
125 }
126 kfree_sensitive(pool);
127 return ERR_PTR(-ENOMEM);
128 }
129 EXPORT_SYMBOL_GPL(hisi_acc_create_sgl_pool);
130
131 /**
132 * hisi_acc_free_sgl_pool() - Free a hw sgl pool.
133 * @dev: The device which hw sgl pool belongs to.
134 * @pool: Pointer of pool.
135 *
136 * This function frees memory of a hw sgl pool.
137 */
hisi_acc_free_sgl_pool(struct device * dev,struct hisi_acc_sgl_pool * pool)138 void hisi_acc_free_sgl_pool(struct device *dev, struct hisi_acc_sgl_pool *pool)
139 {
140 struct mem_block *block;
141 int i;
142
143 if (!dev || !pool)
144 return;
145
146 block = pool->mem_block;
147
148 for (i = 0; i < pool->block_num; i++)
149 dma_free_coherent(dev, block[i].size, block[i].sgl,
150 block[i].sgl_dma);
151
152 kfree(pool);
153 }
154 EXPORT_SYMBOL_GPL(hisi_acc_free_sgl_pool);
155
acc_get_sgl(struct hisi_acc_sgl_pool * pool,u32 index,dma_addr_t * hw_sgl_dma)156 static struct hisi_acc_hw_sgl *acc_get_sgl(struct hisi_acc_sgl_pool *pool,
157 u32 index, dma_addr_t *hw_sgl_dma)
158 {
159 struct mem_block *block;
160 u32 block_index, offset;
161
162 if (!pool || !hw_sgl_dma || index >= pool->count)
163 return ERR_PTR(-EINVAL);
164
165 block = pool->mem_block;
166 block_index = index / pool->sgl_num_per_block;
167 offset = index % pool->sgl_num_per_block;
168
169 *hw_sgl_dma = block[block_index].sgl_dma + pool->sgl_size * offset;
170 return (void *)block[block_index].sgl + pool->sgl_size * offset;
171 }
172
sg_map_to_hw_sg(struct scatterlist * sgl,struct acc_hw_sge * hw_sge)173 static void sg_map_to_hw_sg(struct scatterlist *sgl,
174 struct acc_hw_sge *hw_sge)
175 {
176 hw_sge->buf = sg_dma_address(sgl);
177 hw_sge->len = cpu_to_le32(sg_dma_len(sgl));
178 hw_sge->page_ctrl = sg_virt(sgl);
179 }
180
inc_hw_sgl_sge(struct hisi_acc_hw_sgl * hw_sgl)181 static void inc_hw_sgl_sge(struct hisi_acc_hw_sgl *hw_sgl)
182 {
183 u16 var = le16_to_cpu(hw_sgl->entry_sum_in_sgl);
184
185 var++;
186 hw_sgl->entry_sum_in_sgl = cpu_to_le16(var);
187 }
188
update_hw_sgl_sum_sge(struct hisi_acc_hw_sgl * hw_sgl,u16 sum)189 static void update_hw_sgl_sum_sge(struct hisi_acc_hw_sgl *hw_sgl, u16 sum)
190 {
191 hw_sgl->entry_sum_in_chain = cpu_to_le16(sum);
192 }
193
clear_hw_sgl_sge(struct hisi_acc_hw_sgl * hw_sgl)194 static void clear_hw_sgl_sge(struct hisi_acc_hw_sgl *hw_sgl)
195 {
196 struct acc_hw_sge *hw_sge = hw_sgl->sge_entries;
197 int i;
198
199 for (i = 0; i < le16_to_cpu(hw_sgl->entry_sum_in_sgl); i++) {
200 hw_sge[i].page_ctrl = NULL;
201 hw_sge[i].buf = 0;
202 hw_sge[i].len = 0;
203 }
204 }
205
206 /**
207 * hisi_acc_sg_buf_map_to_hw_sgl - Map a scatterlist to a hw sgl.
208 * @dev: The device which hw sgl belongs to.
209 * @sgl: Scatterlist which will be mapped to hw sgl.
210 * @pool: Pool which hw sgl memory will be allocated in.
211 * @index: Index of hisi_acc_hw_sgl in pool.
212 * @hw_sgl_dma: The dma address of allocated hw sgl.
213 *
214 * This function builds hw sgl according input sgl, user can use hw_sgl_dma
215 * as src/dst in its BD. Only support single hw sgl currently.
216 */
217 struct hisi_acc_hw_sgl *
hisi_acc_sg_buf_map_to_hw_sgl(struct device * dev,struct scatterlist * sgl,struct hisi_acc_sgl_pool * pool,u32 index,dma_addr_t * hw_sgl_dma)218 hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
219 struct scatterlist *sgl,
220 struct hisi_acc_sgl_pool *pool,
221 u32 index, dma_addr_t *hw_sgl_dma)
222 {
223 struct hisi_acc_hw_sgl *curr_hw_sgl;
224 dma_addr_t curr_sgl_dma = 0;
225 struct acc_hw_sge *curr_hw_sge;
226 struct scatterlist *sg;
227 int i, sg_n, sg_n_mapped;
228
229 if (!dev || !sgl || !pool || !hw_sgl_dma)
230 return ERR_PTR(-EINVAL);
231
232 sg_n = sg_nents(sgl);
233
234 sg_n_mapped = dma_map_sg(dev, sgl, sg_n, DMA_BIDIRECTIONAL);
235 if (!sg_n_mapped) {
236 dev_err(dev, "DMA mapping for SG error!\n");
237 return ERR_PTR(-EINVAL);
238 }
239
240 if (sg_n_mapped > pool->sge_nr) {
241 dev_err(dev, "the number of entries in input scatterlist is bigger than SGL pool setting.\n");
242 return ERR_PTR(-EINVAL);
243 }
244
245 curr_hw_sgl = acc_get_sgl(pool, index, &curr_sgl_dma);
246 if (IS_ERR(curr_hw_sgl)) {
247 dev_err(dev, "Get SGL error!\n");
248 dma_unmap_sg(dev, sgl, sg_n, DMA_BIDIRECTIONAL);
249 return ERR_PTR(-ENOMEM);
250
251 }
252 curr_hw_sgl->entry_length_in_sgl = cpu_to_le16(pool->sge_nr);
253 curr_hw_sge = curr_hw_sgl->sge_entries;
254
255 for_each_sg(sgl, sg, sg_n_mapped, i) {
256 sg_map_to_hw_sg(sg, curr_hw_sge);
257 inc_hw_sgl_sge(curr_hw_sgl);
258 curr_hw_sge++;
259 }
260
261 update_hw_sgl_sum_sge(curr_hw_sgl, pool->sge_nr);
262 *hw_sgl_dma = curr_sgl_dma;
263
264 return curr_hw_sgl;
265 }
266 EXPORT_SYMBOL_GPL(hisi_acc_sg_buf_map_to_hw_sgl);
267
268 /**
269 * hisi_acc_sg_buf_unmap() - Unmap allocated hw sgl.
270 * @dev: The device which hw sgl belongs to.
271 * @sgl: Related scatterlist.
272 * @hw_sgl: Virtual address of hw sgl.
273 *
274 * This function unmaps allocated hw sgl.
275 */
hisi_acc_sg_buf_unmap(struct device * dev,struct scatterlist * sgl,struct hisi_acc_hw_sgl * hw_sgl)276 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
277 struct hisi_acc_hw_sgl *hw_sgl)
278 {
279 if (!dev || !sgl || !hw_sgl)
280 return;
281
282 dma_unmap_sg(dev, sgl, sg_nents(sgl), DMA_BIDIRECTIONAL);
283 clear_hw_sgl_sge(hw_sgl);
284 hw_sgl->entry_sum_in_chain = 0;
285 hw_sgl->entry_sum_in_sgl = 0;
286 hw_sgl->entry_length_in_sgl = 0;
287 }
288 EXPORT_SYMBOL_GPL(hisi_acc_sg_buf_unmap);
289