1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "reg_helper.h"
28
29 #include "core_types.h"
30 #include "link_encoder.h"
31 #include "dcn31_dio_link_encoder.h"
32 #include "stream_encoder.h"
33 #include "i2caux_interface.h"
34 #include "dc_bios_types.h"
35
36 #include "gpio_service_interface.h"
37
38 #include "link_enc_cfg.h"
39 #include "dc_dmub_srv.h"
40 #include "dal_asic_id.h"
41
42 #define CTX \
43 enc10->base.ctx
44 #define DC_LOGGER \
45 enc10->base.ctx->logger
46
47 #define REG(reg)\
48 (enc10->link_regs->reg)
49
50 #undef FN
51 #define FN(reg_name, field_name) \
52 enc10->link_shift->field_name, enc10->link_mask->field_name
53
54 #define IND_REG(index) \
55 (enc10->link_regs->index)
56
57 #define AUX_REG(reg)\
58 (enc10->aux_regs->reg)
59
60 #define AUX_REG_READ(reg_name) \
61 dm_read_reg(CTX, AUX_REG(reg_name))
62
63 #define AUX_REG_WRITE(reg_name, val) \
64 dm_write_reg(CTX, AUX_REG(reg_name), val)
65
66 #ifndef MIN
67 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
68 #endif
69
dcn31_link_encoder_set_dio_phy_mux(struct link_encoder * enc,enum encoder_type_select sel,uint32_t hpo_inst)70 void dcn31_link_encoder_set_dio_phy_mux(
71 struct link_encoder *enc,
72 enum encoder_type_select sel,
73 uint32_t hpo_inst)
74 {
75 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
76
77 switch (enc->transmitter) {
78 case TRANSMITTER_UNIPHY_A:
79 if (sel == ENCODER_TYPE_HDMI_FRL)
80 REG_UPDATE(DIO_LINKA_CNTL,
81 HPO_HDMI_ENC_SEL, hpo_inst);
82 else if (sel == ENCODER_TYPE_DP_128B132B)
83 REG_UPDATE(DIO_LINKA_CNTL,
84 HPO_DP_ENC_SEL, hpo_inst);
85 REG_UPDATE(DIO_LINKA_CNTL,
86 ENC_TYPE_SEL, sel);
87 break;
88 case TRANSMITTER_UNIPHY_B:
89 if (sel == ENCODER_TYPE_HDMI_FRL)
90 REG_UPDATE(DIO_LINKB_CNTL,
91 HPO_HDMI_ENC_SEL, hpo_inst);
92 else if (sel == ENCODER_TYPE_DP_128B132B)
93 REG_UPDATE(DIO_LINKB_CNTL,
94 HPO_DP_ENC_SEL, hpo_inst);
95 REG_UPDATE(DIO_LINKB_CNTL,
96 ENC_TYPE_SEL, sel);
97 break;
98 case TRANSMITTER_UNIPHY_C:
99 if (sel == ENCODER_TYPE_HDMI_FRL)
100 REG_UPDATE(DIO_LINKC_CNTL,
101 HPO_HDMI_ENC_SEL, hpo_inst);
102 else if (sel == ENCODER_TYPE_DP_128B132B)
103 REG_UPDATE(DIO_LINKC_CNTL,
104 HPO_DP_ENC_SEL, hpo_inst);
105 REG_UPDATE(DIO_LINKC_CNTL,
106 ENC_TYPE_SEL, sel);
107 break;
108 case TRANSMITTER_UNIPHY_D:
109 if (sel == ENCODER_TYPE_HDMI_FRL)
110 REG_UPDATE(DIO_LINKD_CNTL,
111 HPO_HDMI_ENC_SEL, hpo_inst);
112 else if (sel == ENCODER_TYPE_DP_128B132B)
113 REG_UPDATE(DIO_LINKD_CNTL,
114 HPO_DP_ENC_SEL, hpo_inst);
115 REG_UPDATE(DIO_LINKD_CNTL,
116 ENC_TYPE_SEL, sel);
117 break;
118 case TRANSMITTER_UNIPHY_E:
119 if (sel == ENCODER_TYPE_HDMI_FRL)
120 REG_UPDATE(DIO_LINKE_CNTL,
121 HPO_HDMI_ENC_SEL, hpo_inst);
122 else if (sel == ENCODER_TYPE_DP_128B132B)
123 REG_UPDATE(DIO_LINKE_CNTL,
124 HPO_DP_ENC_SEL, hpo_inst);
125 REG_UPDATE(DIO_LINKE_CNTL,
126 ENC_TYPE_SEL, sel);
127 break;
128 case TRANSMITTER_UNIPHY_F:
129 if (sel == ENCODER_TYPE_HDMI_FRL)
130 REG_UPDATE(DIO_LINKF_CNTL,
131 HPO_HDMI_ENC_SEL, hpo_inst);
132 else if (sel == ENCODER_TYPE_DP_128B132B)
133 REG_UPDATE(DIO_LINKF_CNTL,
134 HPO_DP_ENC_SEL, hpo_inst);
135 REG_UPDATE(DIO_LINKF_CNTL,
136 ENC_TYPE_SEL, sel);
137 break;
138 default:
139 /* Do nothing */
140 break;
141 }
142 }
143
enc31_hw_init(struct link_encoder * enc)144 void enc31_hw_init(struct link_encoder *enc)
145 {
146 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
147
148 /*
149 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
150 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
151 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
152 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
153 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
154 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
155 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
156 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
157 */
158
159 /*
160 AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
161 AUX_RX_START_WINDOW = 1 [6:4]
162 AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
163 AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1
164 AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
165 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0
166 AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1
167 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1
168 AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3
169 AUX_RX_DETECTION_THRESHOLD [30:28] = 1
170 */
171 // dmub will read AUX_DPHY_RX_CONTROL0/AUX_DPHY_TX_CONTROL from vbios table in dp_aux_init
172
173 //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
174 // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
175 // 27MHz -> 0xd
176 // 100MHz -> 0x32
177 // 48MHz -> 0x18
178
179 #ifdef CLEANUP_FIXME
180 /*from display_init*/
181 REG_WRITE(RDPCSTX_DEBUG_CONFIG, 0);
182 #endif
183
184 // Set TMDS_CTL0 to 1. This is a legacy setting.
185 REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
186
187 /*HW default is 5*/
188 REG_UPDATE(RDPCSTX_CNTL,
189 RDPCS_TX_FIFO_RD_START_DELAY, 4);
190
191 dcn10_aux_initialize(enc10);
192 }
193
194 static const struct link_encoder_funcs dcn31_link_enc_funcs = {
195 .read_state = link_enc2_read_state,
196 .validate_output_with_stream =
197 dcn30_link_encoder_validate_output_with_stream,
198 .hw_init = enc31_hw_init,
199 .setup = dcn10_link_encoder_setup,
200 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
201 .enable_dp_output = dcn31_link_encoder_enable_dp_output,
202 .enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output,
203 .disable_output = dcn31_link_encoder_disable_output,
204 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
205 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
206 .update_mst_stream_allocation_table =
207 dcn10_link_encoder_update_mst_stream_allocation_table,
208 .psr_program_dp_dphy_fast_training =
209 dcn10_psr_program_dp_dphy_fast_training,
210 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
211 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
212 .enable_hpd = dcn10_link_encoder_enable_hpd,
213 .disable_hpd = dcn10_link_encoder_disable_hpd,
214 .is_dig_enabled = dcn10_is_dig_enabled,
215 .destroy = dcn10_link_encoder_destroy,
216 .fec_set_enable = enc2_fec_set_enable,
217 .fec_set_ready = enc2_fec_set_ready,
218 .fec_is_active = enc2_fec_is_active,
219 .get_dig_frontend = dcn10_get_dig_frontend,
220 .get_dig_mode = dcn10_get_dig_mode,
221 .is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,
222 .get_max_link_cap = dcn31_link_encoder_get_max_link_cap,
223 .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
224 };
225
dcn31_link_encoder_construct(struct dcn20_link_encoder * enc20,const struct encoder_init_data * init_data,const struct encoder_feature_support * enc_features,const struct dcn10_link_enc_registers * link_regs,const struct dcn10_link_enc_aux_registers * aux_regs,const struct dcn10_link_enc_hpd_registers * hpd_regs,const struct dcn10_link_enc_shift * link_shift,const struct dcn10_link_enc_mask * link_mask)226 void dcn31_link_encoder_construct(
227 struct dcn20_link_encoder *enc20,
228 const struct encoder_init_data *init_data,
229 const struct encoder_feature_support *enc_features,
230 const struct dcn10_link_enc_registers *link_regs,
231 const struct dcn10_link_enc_aux_registers *aux_regs,
232 const struct dcn10_link_enc_hpd_registers *hpd_regs,
233 const struct dcn10_link_enc_shift *link_shift,
234 const struct dcn10_link_enc_mask *link_mask)
235 {
236 struct bp_encoder_cap_info bp_cap_info = {0};
237 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
238 enum bp_result result = BP_RESULT_OK;
239 struct dcn10_link_encoder *enc10 = &enc20->enc10;
240
241 enc10->base.funcs = &dcn31_link_enc_funcs;
242 enc10->base.ctx = init_data->ctx;
243 enc10->base.id = init_data->encoder;
244
245 enc10->base.hpd_source = init_data->hpd_source;
246 enc10->base.connector = init_data->connector;
247
248 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
249
250 enc10->base.features = *enc_features;
251
252 enc10->base.transmitter = init_data->transmitter;
253
254 /* set the flag to indicate whether driver poll the I2C data pin
255 * while doing the DP sink detect
256 */
257
258 /* if (dal_adapter_service_is_feature_supported(as,
259 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
260 enc10->base.features.flags.bits.
261 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
262
263 enc10->base.output_signals =
264 SIGNAL_TYPE_DVI_SINGLE_LINK |
265 SIGNAL_TYPE_DVI_DUAL_LINK |
266 SIGNAL_TYPE_LVDS |
267 SIGNAL_TYPE_DISPLAY_PORT |
268 SIGNAL_TYPE_DISPLAY_PORT_MST |
269 SIGNAL_TYPE_EDP |
270 SIGNAL_TYPE_HDMI_TYPE_A;
271
272 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
273 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
274 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
275 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
276 * Prefer DIG assignment is decided by board design.
277 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
278 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
279 * By this, adding DIGG should not hurt DCE 8.0.
280 * This will let DCE 8.1 share DCE 8.0 as much as possible
281 */
282
283 enc10->link_regs = link_regs;
284 enc10->aux_regs = aux_regs;
285 enc10->hpd_regs = hpd_regs;
286 enc10->link_shift = link_shift;
287 enc10->link_mask = link_mask;
288
289 switch (enc10->base.transmitter) {
290 case TRANSMITTER_UNIPHY_A:
291 enc10->base.preferred_engine = ENGINE_ID_DIGA;
292 break;
293 case TRANSMITTER_UNIPHY_B:
294 enc10->base.preferred_engine = ENGINE_ID_DIGB;
295 break;
296 case TRANSMITTER_UNIPHY_C:
297 enc10->base.preferred_engine = ENGINE_ID_DIGC;
298 break;
299 case TRANSMITTER_UNIPHY_D:
300 enc10->base.preferred_engine = ENGINE_ID_DIGD;
301 break;
302 case TRANSMITTER_UNIPHY_E:
303 enc10->base.preferred_engine = ENGINE_ID_DIGE;
304 break;
305 case TRANSMITTER_UNIPHY_F:
306 enc10->base.preferred_engine = ENGINE_ID_DIGF;
307 break;
308 default:
309 ASSERT_CRITICAL(false);
310 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
311 }
312
313 /* default to one to mirror Windows behavior */
314 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
315
316 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
317 enc10->base.id, &bp_cap_info);
318
319 /* Override features with DCE-specific values */
320 if (result == BP_RESULT_OK) {
321 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
322 bp_cap_info.DP_HBR2_EN;
323 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
324 bp_cap_info.DP_HBR3_EN;
325 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
326 enc10->base.features.flags.bits.DP_IS_USB_C =
327 bp_cap_info.DP_IS_USB_C;
328 } else {
329 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
330 __func__,
331 result);
332 }
333 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
334 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
335 }
336 }
337
dcn31_link_encoder_construct_minimal(struct dcn20_link_encoder * enc20,struct dc_context * ctx,const struct encoder_feature_support * enc_features,const struct dcn10_link_enc_registers * link_regs,enum engine_id eng_id)338 void dcn31_link_encoder_construct_minimal(
339 struct dcn20_link_encoder *enc20,
340 struct dc_context *ctx,
341 const struct encoder_feature_support *enc_features,
342 const struct dcn10_link_enc_registers *link_regs,
343 enum engine_id eng_id)
344 {
345 struct dcn10_link_encoder *enc10 = &enc20->enc10;
346
347 enc10->base.funcs = &dcn31_link_enc_funcs;
348 enc10->base.ctx = ctx;
349 enc10->base.id.type = OBJECT_TYPE_ENCODER;
350 enc10->base.hpd_source = HPD_SOURCEID_UNKNOWN;
351 enc10->base.connector.type = OBJECT_TYPE_CONNECTOR;
352 enc10->base.preferred_engine = eng_id;
353 enc10->base.features = *enc_features;
354 enc10->base.transmitter = TRANSMITTER_UNKNOWN;
355 enc10->link_regs = link_regs;
356
357 enc10->base.output_signals =
358 SIGNAL_TYPE_DISPLAY_PORT |
359 SIGNAL_TYPE_DISPLAY_PORT_MST |
360 SIGNAL_TYPE_EDP;
361 }
362
dcn31_link_encoder_enable_dp_output(struct link_encoder * enc,const struct dc_link_settings * link_settings,enum clock_source_id clock_source)363 void dcn31_link_encoder_enable_dp_output(
364 struct link_encoder *enc,
365 const struct dc_link_settings *link_settings,
366 enum clock_source_id clock_source)
367 {
368 /* Enable transmitter and encoder. */
369 if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
370
371 dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source);
372
373 } else {
374
375 /** @todo Handle transmitter with programmable mapping to link encoder. */
376 }
377 }
378
dcn31_link_encoder_enable_dp_mst_output(struct link_encoder * enc,const struct dc_link_settings * link_settings,enum clock_source_id clock_source)379 void dcn31_link_encoder_enable_dp_mst_output(
380 struct link_encoder *enc,
381 const struct dc_link_settings *link_settings,
382 enum clock_source_id clock_source)
383 {
384 /* Enable transmitter and encoder. */
385 if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
386
387 dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
388
389 } else {
390
391 /** @todo Handle transmitter with programmable mapping to link encoder. */
392 }
393 }
394
dcn31_link_encoder_disable_output(struct link_encoder * enc,enum signal_type signal)395 void dcn31_link_encoder_disable_output(
396 struct link_encoder *enc,
397 enum signal_type signal)
398 {
399 /* Disable transmitter and encoder. */
400 if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
401
402 dcn10_link_encoder_disable_output(enc, signal);
403
404 } else {
405
406 /** @todo Handle transmitter with programmable mapping to link encoder. */
407 }
408 }
409
dcn31_link_encoder_is_in_alt_mode(struct link_encoder * enc)410 bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc)
411 {
412 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
413 uint32_t dp_alt_mode_disable;
414 bool is_usb_c_alt_mode = false;
415
416 if (enc->features.flags.bits.DP_IS_USB_C) {
417 if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
418 // [Note] no need to check hw_internal_rev once phy mux selection is ready
419 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
420 } else {
421 /*
422 * B0 phys use a new set of registers to check whether alt mode is disabled.
423 * if value == 1 alt mode is disabled, otherwise it is enabled.
424 */
425 if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
426 || (enc10->base.transmitter == TRANSMITTER_UNIPHY_B)
427 || (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
428 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
429 } else {
430 // [Note] need to change TRANSMITTER_UNIPHY_C/D to F/G once phy mux selection is ready
431 REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
432 }
433 }
434
435 is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
436 }
437
438 return is_usb_c_alt_mode;
439 }
440
dcn31_link_encoder_get_max_link_cap(struct link_encoder * enc,struct dc_link_settings * link_settings)441 void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,
442 struct dc_link_settings *link_settings)
443 {
444 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
445 uint32_t is_in_usb_c_dp4_mode = 0;
446
447 dcn10_link_encoder_get_max_link_cap(enc, link_settings);
448
449 /* in usb c dp2 mode, max lane count is 2 */
450 if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
451 if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
452 // [Note] no need to check hw_internal_rev once phy mux selection is ready
453 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
454 } else {
455 if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
456 || (enc10->base.transmitter == TRANSMITTER_UNIPHY_B)
457 || (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
458 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
459 } else {
460 REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
461 }
462 }
463 if (!is_in_usb_c_dp4_mode)
464 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
465 }
466 }
467