1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Cell Internal Interrupt Controller
4 *
5 * Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
6 * IBM, Corp.
7 *
8 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
9 *
10 * Author: Arnd Bergmann <arndb@de.ibm.com>
11 *
12 * TODO:
13 * - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
14 * vs node numbers in the setup code
15 * - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
16 * a non-active node to the active node)
17 */
18
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/export.h>
22 #include <linux/percpu.h>
23 #include <linux/types.h>
24 #include <linux/ioport.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/pgtable.h>
27
28 #include <asm/io.h>
29 #include <asm/prom.h>
30 #include <asm/ptrace.h>
31 #include <asm/machdep.h>
32 #include <asm/cell-regs.h>
33
34 #include "interrupt.h"
35
36 struct iic {
37 struct cbe_iic_thread_regs __iomem *regs;
38 u8 target_id;
39 u8 eoi_stack[16];
40 int eoi_ptr;
41 struct device_node *node;
42 };
43
44 static DEFINE_PER_CPU(struct iic, cpu_iic);
45 #define IIC_NODE_COUNT 2
46 static struct irq_domain *iic_host;
47
48 /* Convert between "pending" bits and hw irq number */
iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)49 static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
50 {
51 unsigned char unit = bits.source & 0xf;
52 unsigned char node = bits.source >> 4;
53 unsigned char class = bits.class & 3;
54
55 /* Decode IPIs */
56 if (bits.flags & CBE_IIC_IRQ_IPI)
57 return IIC_IRQ_TYPE_IPI | (bits.prio >> 4);
58 else
59 return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit;
60 }
61
iic_mask(struct irq_data * d)62 static void iic_mask(struct irq_data *d)
63 {
64 }
65
iic_unmask(struct irq_data * d)66 static void iic_unmask(struct irq_data *d)
67 {
68 }
69
iic_eoi(struct irq_data * d)70 static void iic_eoi(struct irq_data *d)
71 {
72 struct iic *iic = this_cpu_ptr(&cpu_iic);
73 out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
74 BUG_ON(iic->eoi_ptr < 0);
75 }
76
77 static struct irq_chip iic_chip = {
78 .name = "CELL-IIC",
79 .irq_mask = iic_mask,
80 .irq_unmask = iic_unmask,
81 .irq_eoi = iic_eoi,
82 };
83
84
iic_ioexc_eoi(struct irq_data * d)85 static void iic_ioexc_eoi(struct irq_data *d)
86 {
87 }
88
iic_ioexc_cascade(struct irq_desc * desc)89 static void iic_ioexc_cascade(struct irq_desc *desc)
90 {
91 struct irq_chip *chip = irq_desc_get_chip(desc);
92 struct cbe_iic_regs __iomem *node_iic =
93 (void __iomem *)irq_desc_get_handler_data(desc);
94 unsigned int irq = irq_desc_get_irq(desc);
95 unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC;
96 unsigned long bits, ack;
97 int cascade;
98
99 for (;;) {
100 bits = in_be64(&node_iic->iic_is);
101 if (bits == 0)
102 break;
103 /* pre-ack edge interrupts */
104 ack = bits & IIC_ISR_EDGE_MASK;
105 if (ack)
106 out_be64(&node_iic->iic_is, ack);
107 /* handle them */
108 for (cascade = 63; cascade >= 0; cascade--)
109 if (bits & (0x8000000000000000UL >> cascade))
110 generic_handle_domain_irq(iic_host,
111 base | cascade);
112 /* post-ack level interrupts */
113 ack = bits & ~IIC_ISR_EDGE_MASK;
114 if (ack)
115 out_be64(&node_iic->iic_is, ack);
116 }
117 chip->irq_eoi(&desc->irq_data);
118 }
119
120
121 static struct irq_chip iic_ioexc_chip = {
122 .name = "CELL-IOEX",
123 .irq_mask = iic_mask,
124 .irq_unmask = iic_unmask,
125 .irq_eoi = iic_ioexc_eoi,
126 };
127
128 /* Get an IRQ number from the pending state register of the IIC */
iic_get_irq(void)129 static unsigned int iic_get_irq(void)
130 {
131 struct cbe_iic_pending_bits pending;
132 struct iic *iic;
133 unsigned int virq;
134
135 iic = this_cpu_ptr(&cpu_iic);
136 *(unsigned long *) &pending =
137 in_be64((u64 __iomem *) &iic->regs->pending_destr);
138 if (!(pending.flags & CBE_IIC_IRQ_VALID))
139 return 0;
140 virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
141 if (!virq)
142 return 0;
143 iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
144 BUG_ON(iic->eoi_ptr > 15);
145 return virq;
146 }
147
iic_setup_cpu(void)148 void iic_setup_cpu(void)
149 {
150 out_be64(&this_cpu_ptr(&cpu_iic)->regs->prio, 0xff);
151 }
152
iic_get_target_id(int cpu)153 u8 iic_get_target_id(int cpu)
154 {
155 return per_cpu(cpu_iic, cpu).target_id;
156 }
157
158 EXPORT_SYMBOL_GPL(iic_get_target_id);
159
160 #ifdef CONFIG_SMP
161
162 /* Use the highest interrupt priorities for IPI */
iic_msg_to_irq(int msg)163 static inline int iic_msg_to_irq(int msg)
164 {
165 return IIC_IRQ_TYPE_IPI + 0xf - msg;
166 }
167
iic_message_pass(int cpu,int msg)168 void iic_message_pass(int cpu, int msg)
169 {
170 out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - msg) << 4);
171 }
172
iic_request_ipi(int msg)173 static void iic_request_ipi(int msg)
174 {
175 int virq;
176
177 virq = irq_create_mapping(iic_host, iic_msg_to_irq(msg));
178 if (!virq) {
179 printk(KERN_ERR
180 "iic: failed to map IPI %s\n", smp_ipi_name[msg]);
181 return;
182 }
183
184 /*
185 * If smp_request_message_ipi encounters an error it will notify
186 * the error. If a message is not needed it will return non-zero.
187 */
188 if (smp_request_message_ipi(virq, msg))
189 irq_dispose_mapping(virq);
190 }
191
iic_request_IPIs(void)192 void iic_request_IPIs(void)
193 {
194 iic_request_ipi(PPC_MSG_CALL_FUNCTION);
195 iic_request_ipi(PPC_MSG_RESCHEDULE);
196 iic_request_ipi(PPC_MSG_TICK_BROADCAST);
197 iic_request_ipi(PPC_MSG_NMI_IPI);
198 }
199
200 #endif /* CONFIG_SMP */
201
202
iic_host_match(struct irq_domain * h,struct device_node * node,enum irq_domain_bus_token bus_token)203 static int iic_host_match(struct irq_domain *h, struct device_node *node,
204 enum irq_domain_bus_token bus_token)
205 {
206 return of_device_is_compatible(node,
207 "IBM,CBEA-Internal-Interrupt-Controller");
208 }
209
iic_host_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)210 static int iic_host_map(struct irq_domain *h, unsigned int virq,
211 irq_hw_number_t hw)
212 {
213 switch (hw & IIC_IRQ_TYPE_MASK) {
214 case IIC_IRQ_TYPE_IPI:
215 irq_set_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
216 break;
217 case IIC_IRQ_TYPE_IOEXC:
218 irq_set_chip_and_handler(virq, &iic_ioexc_chip,
219 handle_edge_eoi_irq);
220 break;
221 default:
222 irq_set_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq);
223 }
224 return 0;
225 }
226
iic_host_xlate(struct irq_domain * h,struct device_node * ct,const u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_flags)227 static int iic_host_xlate(struct irq_domain *h, struct device_node *ct,
228 const u32 *intspec, unsigned int intsize,
229 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
230
231 {
232 unsigned int node, ext, unit, class;
233 const u32 *val;
234
235 if (!of_device_is_compatible(ct,
236 "IBM,CBEA-Internal-Interrupt-Controller"))
237 return -ENODEV;
238 if (intsize != 1)
239 return -ENODEV;
240 val = of_get_property(ct, "#interrupt-cells", NULL);
241 if (val == NULL || *val != 1)
242 return -ENODEV;
243
244 node = intspec[0] >> 24;
245 ext = (intspec[0] >> 16) & 0xff;
246 class = (intspec[0] >> 8) & 0xff;
247 unit = intspec[0] & 0xff;
248
249 /* Check if node is in supported range */
250 if (node > 1)
251 return -EINVAL;
252
253 /* Build up interrupt number, special case for IO exceptions */
254 *out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
255 if (unit == IIC_UNIT_IIC && class == 1)
256 *out_hwirq |= IIC_IRQ_TYPE_IOEXC | ext;
257 else
258 *out_hwirq |= IIC_IRQ_TYPE_NORMAL |
259 (class << IIC_IRQ_CLASS_SHIFT) | unit;
260
261 /* Dummy flags, ignored by iic code */
262 *out_flags = IRQ_TYPE_EDGE_RISING;
263
264 return 0;
265 }
266
267 static const struct irq_domain_ops iic_host_ops = {
268 .match = iic_host_match,
269 .map = iic_host_map,
270 .xlate = iic_host_xlate,
271 };
272
init_one_iic(unsigned int hw_cpu,unsigned long addr,struct device_node * node)273 static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
274 struct device_node *node)
275 {
276 /* XXX FIXME: should locate the linux CPU number from the HW cpu
277 * number properly. We are lucky for now
278 */
279 struct iic *iic = &per_cpu(cpu_iic, hw_cpu);
280
281 iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs));
282 BUG_ON(iic->regs == NULL);
283
284 iic->target_id = ((hw_cpu & 2) << 3) | ((hw_cpu & 1) ? 0xf : 0xe);
285 iic->eoi_stack[0] = 0xff;
286 iic->node = of_node_get(node);
287 out_be64(&iic->regs->prio, 0);
288
289 printk(KERN_INFO "IIC for CPU %d target id 0x%x : %pOF\n",
290 hw_cpu, iic->target_id, node);
291 }
292
setup_iic(void)293 static int __init setup_iic(void)
294 {
295 struct device_node *dn;
296 struct resource r0, r1;
297 unsigned int node, cascade, found = 0;
298 struct cbe_iic_regs __iomem *node_iic;
299 const u32 *np;
300
301 for_each_node_by_name(dn, "interrupt-controller") {
302 if (!of_device_is_compatible(dn,
303 "IBM,CBEA-Internal-Interrupt-Controller"))
304 continue;
305 np = of_get_property(dn, "ibm,interrupt-server-ranges", NULL);
306 if (np == NULL) {
307 printk(KERN_WARNING "IIC: CPU association not found\n");
308 of_node_put(dn);
309 return -ENODEV;
310 }
311 if (of_address_to_resource(dn, 0, &r0) ||
312 of_address_to_resource(dn, 1, &r1)) {
313 printk(KERN_WARNING "IIC: Can't resolve addresses\n");
314 of_node_put(dn);
315 return -ENODEV;
316 }
317 found++;
318 init_one_iic(np[0], r0.start, dn);
319 init_one_iic(np[1], r1.start, dn);
320
321 /* Setup cascade for IO exceptions. XXX cleanup tricks to get
322 * node vs CPU etc...
323 * Note that we configure the IIC_IRR here with a hard coded
324 * priority of 1. We might want to improve that later.
325 */
326 node = np[0] >> 1;
327 node_iic = cbe_get_cpu_iic_regs(np[0]);
328 cascade = node << IIC_IRQ_NODE_SHIFT;
329 cascade |= 1 << IIC_IRQ_CLASS_SHIFT;
330 cascade |= IIC_UNIT_IIC;
331 cascade = irq_create_mapping(iic_host, cascade);
332 if (!cascade)
333 continue;
334 /*
335 * irq_data is a generic pointer that gets passed back
336 * to us later, so the forced cast is fine.
337 */
338 irq_set_handler_data(cascade, (void __force *)node_iic);
339 irq_set_chained_handler(cascade, iic_ioexc_cascade);
340 out_be64(&node_iic->iic_ir,
341 (1 << 12) /* priority */ |
342 (node << 4) /* dest node */ |
343 IIC_UNIT_THREAD_0 /* route them to thread 0 */);
344 /* Flush pending (make sure it triggers if there is
345 * anything pending
346 */
347 out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
348 }
349
350 if (found)
351 return 0;
352 else
353 return -ENODEV;
354 }
355
iic_init_IRQ(void)356 void __init iic_init_IRQ(void)
357 {
358 /* Setup an irq host data structure */
359 iic_host = irq_domain_add_linear(NULL, IIC_SOURCE_COUNT, &iic_host_ops,
360 NULL);
361 BUG_ON(iic_host == NULL);
362 irq_set_default_host(iic_host);
363
364 /* Discover and initialize iics */
365 if (setup_iic() < 0)
366 panic("IIC: Failed to initialize !\n");
367
368 /* Set master interrupt handling function */
369 ppc_md.get_irq = iic_get_irq;
370
371 /* Enable on current CPU */
372 iic_setup_cpu();
373 }
374
iic_set_interrupt_routing(int cpu,int thread,int priority)375 void iic_set_interrupt_routing(int cpu, int thread, int priority)
376 {
377 struct cbe_iic_regs __iomem *iic_regs = cbe_get_cpu_iic_regs(cpu);
378 u64 iic_ir = 0;
379 int node = cpu >> 1;
380
381 /* Set which node and thread will handle the next interrupt */
382 iic_ir |= CBE_IIC_IR_PRIO(priority) |
383 CBE_IIC_IR_DEST_NODE(node);
384 if (thread == 0)
385 iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_0);
386 else
387 iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_1);
388 out_be64(&iic_regs->iic_ir, iic_ir);
389 }
390