1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Zhi Wang <zhi.a.wang@intel.com>
26 *
27 * Contributors:
28 * Min he <min.he@intel.com>
29 *
30 */
31
32 #include "i915_drv.h"
33 #include "gvt.h"
34 #include "trace.h"
35
36 /* common offset among interrupt control registers */
37 #define regbase_to_isr(base) (base)
38 #define regbase_to_imr(base) (base + 0x4)
39 #define regbase_to_iir(base) (base + 0x8)
40 #define regbase_to_ier(base) (base + 0xC)
41
42 #define iir_to_regbase(iir) (iir - 0x8)
43 #define ier_to_regbase(ier) (ier - 0xC)
44
45 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler)
46 #define get_irq_info(irq, e) (irq->events[e].info)
47
48 #define irq_to_gvt(irq) \
49 container_of(irq, struct intel_gvt, irq)
50
51 static void update_upstream_irq(struct intel_vgpu *vgpu,
52 struct intel_gvt_irq_info *info);
53
54 static const char * const irq_name[INTEL_GVT_EVENT_MAX] = {
55 [RCS_MI_USER_INTERRUPT] = "Render CS MI USER INTERRUPT",
56 [RCS_DEBUG] = "Render EU debug from SVG",
57 [RCS_MMIO_SYNC_FLUSH] = "Render MMIO sync flush status",
58 [RCS_CMD_STREAMER_ERR] = "Render CS error interrupt",
59 [RCS_PIPE_CONTROL] = "Render PIPE CONTROL notify",
60 [RCS_WATCHDOG_EXCEEDED] = "Render CS Watchdog counter exceeded",
61 [RCS_PAGE_DIRECTORY_FAULT] = "Render page directory faults",
62 [RCS_AS_CONTEXT_SWITCH] = "Render AS Context Switch Interrupt",
63
64 [VCS_MI_USER_INTERRUPT] = "Video CS MI USER INTERRUPT",
65 [VCS_MMIO_SYNC_FLUSH] = "Video MMIO sync flush status",
66 [VCS_CMD_STREAMER_ERR] = "Video CS error interrupt",
67 [VCS_MI_FLUSH_DW] = "Video MI FLUSH DW notify",
68 [VCS_WATCHDOG_EXCEEDED] = "Video CS Watchdog counter exceeded",
69 [VCS_PAGE_DIRECTORY_FAULT] = "Video page directory faults",
70 [VCS_AS_CONTEXT_SWITCH] = "Video AS Context Switch Interrupt",
71 [VCS2_MI_USER_INTERRUPT] = "VCS2 Video CS MI USER INTERRUPT",
72 [VCS2_MI_FLUSH_DW] = "VCS2 Video MI FLUSH DW notify",
73 [VCS2_AS_CONTEXT_SWITCH] = "VCS2 Context Switch Interrupt",
74
75 [BCS_MI_USER_INTERRUPT] = "Blitter CS MI USER INTERRUPT",
76 [BCS_MMIO_SYNC_FLUSH] = "Billter MMIO sync flush status",
77 [BCS_CMD_STREAMER_ERR] = "Blitter CS error interrupt",
78 [BCS_MI_FLUSH_DW] = "Blitter MI FLUSH DW notify",
79 [BCS_PAGE_DIRECTORY_FAULT] = "Blitter page directory faults",
80 [BCS_AS_CONTEXT_SWITCH] = "Blitter AS Context Switch Interrupt",
81
82 [VECS_MI_FLUSH_DW] = "Video Enhanced Streamer MI FLUSH DW notify",
83 [VECS_AS_CONTEXT_SWITCH] = "VECS Context Switch Interrupt",
84
85 [PIPE_A_FIFO_UNDERRUN] = "Pipe A FIFO underrun",
86 [PIPE_A_CRC_ERR] = "Pipe A CRC error",
87 [PIPE_A_CRC_DONE] = "Pipe A CRC done",
88 [PIPE_A_VSYNC] = "Pipe A vsync",
89 [PIPE_A_LINE_COMPARE] = "Pipe A line compare",
90 [PIPE_A_ODD_FIELD] = "Pipe A odd field",
91 [PIPE_A_EVEN_FIELD] = "Pipe A even field",
92 [PIPE_A_VBLANK] = "Pipe A vblank",
93 [PIPE_B_FIFO_UNDERRUN] = "Pipe B FIFO underrun",
94 [PIPE_B_CRC_ERR] = "Pipe B CRC error",
95 [PIPE_B_CRC_DONE] = "Pipe B CRC done",
96 [PIPE_B_VSYNC] = "Pipe B vsync",
97 [PIPE_B_LINE_COMPARE] = "Pipe B line compare",
98 [PIPE_B_ODD_FIELD] = "Pipe B odd field",
99 [PIPE_B_EVEN_FIELD] = "Pipe B even field",
100 [PIPE_B_VBLANK] = "Pipe B vblank",
101 [PIPE_C_VBLANK] = "Pipe C vblank",
102 [DPST_PHASE_IN] = "DPST phase in event",
103 [DPST_HISTOGRAM] = "DPST histogram event",
104 [GSE] = "GSE",
105 [DP_A_HOTPLUG] = "DP A Hotplug",
106 [AUX_CHANNEL_A] = "AUX Channel A",
107 [PERF_COUNTER] = "Performance counter",
108 [POISON] = "Poison",
109 [GTT_FAULT] = "GTT fault",
110 [PRIMARY_A_FLIP_DONE] = "Primary Plane A flip done",
111 [PRIMARY_B_FLIP_DONE] = "Primary Plane B flip done",
112 [PRIMARY_C_FLIP_DONE] = "Primary Plane C flip done",
113 [SPRITE_A_FLIP_DONE] = "Sprite Plane A flip done",
114 [SPRITE_B_FLIP_DONE] = "Sprite Plane B flip done",
115 [SPRITE_C_FLIP_DONE] = "Sprite Plane C flip done",
116
117 [PCU_THERMAL] = "PCU Thermal Event",
118 [PCU_PCODE2DRIVER_MAILBOX] = "PCU pcode2driver mailbox event",
119
120 [FDI_RX_INTERRUPTS_TRANSCODER_A] = "FDI RX Interrupts Combined A",
121 [AUDIO_CP_CHANGE_TRANSCODER_A] = "Audio CP Change Transcoder A",
122 [AUDIO_CP_REQUEST_TRANSCODER_A] = "Audio CP Request Transcoder A",
123 [FDI_RX_INTERRUPTS_TRANSCODER_B] = "FDI RX Interrupts Combined B",
124 [AUDIO_CP_CHANGE_TRANSCODER_B] = "Audio CP Change Transcoder B",
125 [AUDIO_CP_REQUEST_TRANSCODER_B] = "Audio CP Request Transcoder B",
126 [FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C",
127 [AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C",
128 [AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C",
129 [ERR_AND_DBG] = "South Error and Debug Interrupts Combined",
130 [GMBUS] = "Gmbus",
131 [SDVO_B_HOTPLUG] = "SDVO B hotplug",
132 [CRT_HOTPLUG] = "CRT Hotplug",
133 [DP_B_HOTPLUG] = "DisplayPort/HDMI/DVI B Hotplug",
134 [DP_C_HOTPLUG] = "DisplayPort/HDMI/DVI C Hotplug",
135 [DP_D_HOTPLUG] = "DisplayPort/HDMI/DVI D Hotplug",
136 [AUX_CHANNEL_B] = "AUX Channel B",
137 [AUX_CHANNEL_C] = "AUX Channel C",
138 [AUX_CHANNEL_D] = "AUX Channel D",
139 [AUDIO_POWER_STATE_CHANGE_B] = "Audio Power State change Port B",
140 [AUDIO_POWER_STATE_CHANGE_C] = "Audio Power State change Port C",
141 [AUDIO_POWER_STATE_CHANGE_D] = "Audio Power State change Port D",
142
143 [INTEL_GVT_EVENT_RESERVED] = "RESERVED EVENTS!!!",
144 };
145
regbase_to_irq_info(struct intel_gvt * gvt,unsigned int reg)146 static inline struct intel_gvt_irq_info *regbase_to_irq_info(
147 struct intel_gvt *gvt,
148 unsigned int reg)
149 {
150 struct intel_gvt_irq *irq = &gvt->irq;
151 int i;
152
153 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
154 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)
155 return irq->info[i];
156 }
157
158 return NULL;
159 }
160
161 /**
162 * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler
163 * @vgpu: a vGPU
164 * @reg: register offset written by guest
165 * @p_data: register data written by guest
166 * @bytes: register data length
167 *
168 * This function is used to emulate the generic IMR register bit change
169 * behavior.
170 *
171 * Returns:
172 * Zero on success, negative error code if failed.
173 *
174 */
intel_vgpu_reg_imr_handler(struct intel_vgpu * vgpu,unsigned int reg,void * p_data,unsigned int bytes)175 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
176 unsigned int reg, void *p_data, unsigned int bytes)
177 {
178 struct intel_gvt *gvt = vgpu->gvt;
179 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
180 u32 imr = *(u32 *)p_data;
181
182 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
183 (vgpu_vreg(vgpu, reg) ^ imr));
184
185 vgpu_vreg(vgpu, reg) = imr;
186
187 ops->check_pending_irq(vgpu);
188
189 return 0;
190 }
191
192 /**
193 * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler
194 * @vgpu: a vGPU
195 * @reg: register offset written by guest
196 * @p_data: register data written by guest
197 * @bytes: register data length
198 *
199 * This function is used to emulate the master IRQ register on gen8+.
200 *
201 * Returns:
202 * Zero on success, negative error code if failed.
203 *
204 */
intel_vgpu_reg_master_irq_handler(struct intel_vgpu * vgpu,unsigned int reg,void * p_data,unsigned int bytes)205 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
206 unsigned int reg, void *p_data, unsigned int bytes)
207 {
208 struct intel_gvt *gvt = vgpu->gvt;
209 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
210 u32 ier = *(u32 *)p_data;
211 u32 virtual_ier = vgpu_vreg(vgpu, reg);
212
213 trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier,
214 (virtual_ier ^ ier));
215
216 /*
217 * GEN8_MASTER_IRQ is a special irq register,
218 * only bit 31 is allowed to be modified
219 * and treated as an IER bit.
220 */
221 ier &= GEN8_MASTER_IRQ_CONTROL;
222 virtual_ier &= GEN8_MASTER_IRQ_CONTROL;
223 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
224 vgpu_vreg(vgpu, reg) |= ier;
225
226 ops->check_pending_irq(vgpu);
227
228 return 0;
229 }
230
231 /**
232 * intel_vgpu_reg_ier_handler - Generic IER write emulation handler
233 * @vgpu: a vGPU
234 * @reg: register offset written by guest
235 * @p_data: register data written by guest
236 * @bytes: register data length
237 *
238 * This function is used to emulate the generic IER register behavior.
239 *
240 * Returns:
241 * Zero on success, negative error code if failed.
242 *
243 */
intel_vgpu_reg_ier_handler(struct intel_vgpu * vgpu,unsigned int reg,void * p_data,unsigned int bytes)244 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
245 unsigned int reg, void *p_data, unsigned int bytes)
246 {
247 struct intel_gvt *gvt = vgpu->gvt;
248 struct drm_i915_private *i915 = gvt->gt->i915;
249 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
250 struct intel_gvt_irq_info *info;
251 u32 ier = *(u32 *)p_data;
252
253 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
254 (vgpu_vreg(vgpu, reg) ^ ier));
255
256 vgpu_vreg(vgpu, reg) = ier;
257
258 info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
259 if (drm_WARN_ON(&i915->drm, !info))
260 return -EINVAL;
261
262 if (info->has_upstream_irq)
263 update_upstream_irq(vgpu, info);
264
265 ops->check_pending_irq(vgpu);
266
267 return 0;
268 }
269
270 /**
271 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler
272 * @vgpu: a vGPU
273 * @reg: register offset written by guest
274 * @p_data: register data written by guest
275 * @bytes: register data length
276 *
277 * This function is used to emulate the generic IIR register behavior.
278 *
279 * Returns:
280 * Zero on success, negative error code if failed.
281 *
282 */
intel_vgpu_reg_iir_handler(struct intel_vgpu * vgpu,unsigned int reg,void * p_data,unsigned int bytes)283 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
284 void *p_data, unsigned int bytes)
285 {
286 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
287 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
288 iir_to_regbase(reg));
289 u32 iir = *(u32 *)p_data;
290
291 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
292 (vgpu_vreg(vgpu, reg) ^ iir));
293
294 if (drm_WARN_ON(&i915->drm, !info))
295 return -EINVAL;
296
297 vgpu_vreg(vgpu, reg) &= ~iir;
298
299 if (info->has_upstream_irq)
300 update_upstream_irq(vgpu, info);
301 return 0;
302 }
303
304 static struct intel_gvt_irq_map gen8_irq_map[] = {
305 { INTEL_GVT_IRQ_INFO_MASTER, 0, INTEL_GVT_IRQ_INFO_GT0, 0xffff },
306 { INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 },
307 { INTEL_GVT_IRQ_INFO_MASTER, 2, INTEL_GVT_IRQ_INFO_GT1, 0xffff },
308 { INTEL_GVT_IRQ_INFO_MASTER, 3, INTEL_GVT_IRQ_INFO_GT1, 0xffff0000 },
309 { INTEL_GVT_IRQ_INFO_MASTER, 4, INTEL_GVT_IRQ_INFO_GT2, 0xffff },
310 { INTEL_GVT_IRQ_INFO_MASTER, 6, INTEL_GVT_IRQ_INFO_GT3, 0xffff },
311 { INTEL_GVT_IRQ_INFO_MASTER, 16, INTEL_GVT_IRQ_INFO_DE_PIPE_A, ~0 },
312 { INTEL_GVT_IRQ_INFO_MASTER, 17, INTEL_GVT_IRQ_INFO_DE_PIPE_B, ~0 },
313 { INTEL_GVT_IRQ_INFO_MASTER, 18, INTEL_GVT_IRQ_INFO_DE_PIPE_C, ~0 },
314 { INTEL_GVT_IRQ_INFO_MASTER, 20, INTEL_GVT_IRQ_INFO_DE_PORT, ~0 },
315 { INTEL_GVT_IRQ_INFO_MASTER, 22, INTEL_GVT_IRQ_INFO_DE_MISC, ~0 },
316 { INTEL_GVT_IRQ_INFO_MASTER, 23, INTEL_GVT_IRQ_INFO_PCH, ~0 },
317 { INTEL_GVT_IRQ_INFO_MASTER, 30, INTEL_GVT_IRQ_INFO_PCU, ~0 },
318 { -1, -1, ~0 },
319 };
320
update_upstream_irq(struct intel_vgpu * vgpu,struct intel_gvt_irq_info * info)321 static void update_upstream_irq(struct intel_vgpu *vgpu,
322 struct intel_gvt_irq_info *info)
323 {
324 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
325 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
326 struct intel_gvt_irq_map *map = irq->irq_map;
327 struct intel_gvt_irq_info *up_irq_info = NULL;
328 u32 set_bits = 0;
329 u32 clear_bits = 0;
330 int bit;
331 u32 val = vgpu_vreg(vgpu,
332 regbase_to_iir(i915_mmio_reg_offset(info->reg_base)))
333 & vgpu_vreg(vgpu,
334 regbase_to_ier(i915_mmio_reg_offset(info->reg_base)));
335
336 if (!info->has_upstream_irq)
337 return;
338
339 for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
340 if (info->group != map->down_irq_group)
341 continue;
342
343 if (!up_irq_info)
344 up_irq_info = irq->info[map->up_irq_group];
345 else
346 drm_WARN_ON(&i915->drm, up_irq_info !=
347 irq->info[map->up_irq_group]);
348
349 bit = map->up_irq_bit;
350
351 if (val & map->down_irq_bitmask)
352 set_bits |= (1 << bit);
353 else
354 clear_bits |= (1 << bit);
355 }
356
357 if (drm_WARN_ON(&i915->drm, !up_irq_info))
358 return;
359
360 if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {
361 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);
362
363 vgpu_vreg(vgpu, isr) &= ~clear_bits;
364 vgpu_vreg(vgpu, isr) |= set_bits;
365 } else {
366 u32 iir = regbase_to_iir(
367 i915_mmio_reg_offset(up_irq_info->reg_base));
368 u32 imr = regbase_to_imr(
369 i915_mmio_reg_offset(up_irq_info->reg_base));
370
371 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
372 }
373
374 if (up_irq_info->has_upstream_irq)
375 update_upstream_irq(vgpu, up_irq_info);
376 }
377
init_irq_map(struct intel_gvt_irq * irq)378 static void init_irq_map(struct intel_gvt_irq *irq)
379 {
380 struct intel_gvt_irq_map *map;
381 struct intel_gvt_irq_info *up_info, *down_info;
382 int up_bit;
383
384 for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
385 up_info = irq->info[map->up_irq_group];
386 up_bit = map->up_irq_bit;
387 down_info = irq->info[map->down_irq_group];
388
389 set_bit(up_bit, up_info->downstream_irq_bitmap);
390 down_info->has_upstream_irq = true;
391
392 gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n",
393 up_info->group, up_bit,
394 down_info->group, map->down_irq_bitmask);
395 }
396 }
397
398 /* =======================vEvent injection===================== */
inject_virtual_interrupt(struct intel_vgpu * vgpu)399 static int inject_virtual_interrupt(struct intel_vgpu *vgpu)
400 {
401 return intel_gvt_hypervisor_inject_msi(vgpu);
402 }
403
propagate_event(struct intel_gvt_irq * irq,enum intel_gvt_event_type event,struct intel_vgpu * vgpu)404 static void propagate_event(struct intel_gvt_irq *irq,
405 enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
406 {
407 struct intel_gvt_irq_info *info;
408 unsigned int reg_base;
409 int bit;
410
411 info = get_irq_info(irq, event);
412 if (WARN_ON(!info))
413 return;
414
415 reg_base = i915_mmio_reg_offset(info->reg_base);
416 bit = irq->events[event].bit;
417
418 if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,
419 regbase_to_imr(reg_base)))) {
420 trace_propagate_event(vgpu->id, irq_name[event], bit);
421 set_bit(bit, (void *)&vgpu_vreg(vgpu,
422 regbase_to_iir(reg_base)));
423 }
424 }
425
426 /* =======================vEvent Handlers===================== */
handle_default_event_virt(struct intel_gvt_irq * irq,enum intel_gvt_event_type event,struct intel_vgpu * vgpu)427 static void handle_default_event_virt(struct intel_gvt_irq *irq,
428 enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
429 {
430 if (!vgpu->irq.irq_warn_once[event]) {
431 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n",
432 vgpu->id, event, irq_name[event]);
433 vgpu->irq.irq_warn_once[event] = true;
434 }
435 propagate_event(irq, event, vgpu);
436 }
437
438 /* =====================GEN specific logic======================= */
439 /* GEN8 interrupt routines. */
440
441 #define DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(regname, regbase) \
442 static struct intel_gvt_irq_info gen8_##regname##_info = { \
443 .name = #regname"-IRQ", \
444 .reg_base = (regbase), \
445 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \
446 INTEL_GVT_EVENT_RESERVED}, \
447 }
448
449 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt0, GEN8_GT_ISR(0));
450 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1));
451 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt2, GEN8_GT_ISR(2));
452 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt3, GEN8_GT_ISR(3));
453 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A));
454 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));
455 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C));
456 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_port, GEN8_DE_PORT_ISR);
457 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_misc, GEN8_DE_MISC_ISR);
458 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(pcu, GEN8_PCU_ISR);
459 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ);
460
461 static struct intel_gvt_irq_info gvt_base_pch_info = {
462 .name = "PCH-IRQ",
463 .reg_base = SDEISR,
464 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] =
465 INTEL_GVT_EVENT_RESERVED},
466 };
467
gen8_check_pending_irq(struct intel_vgpu * vgpu)468 static void gen8_check_pending_irq(struct intel_vgpu *vgpu)
469 {
470 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
471 int i;
472
473 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
474 GEN8_MASTER_IRQ_CONTROL))
475 return;
476
477 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
478 struct intel_gvt_irq_info *info = irq->info[i];
479 u32 reg_base;
480
481 if (!info->has_upstream_irq)
482 continue;
483
484 reg_base = i915_mmio_reg_offset(info->reg_base);
485 if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))
486 & vgpu_vreg(vgpu, regbase_to_ier(reg_base))))
487 update_upstream_irq(vgpu, info);
488 }
489
490 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
491 & ~GEN8_MASTER_IRQ_CONTROL)
492 inject_virtual_interrupt(vgpu);
493 }
494
gen8_init_irq(struct intel_gvt_irq * irq)495 static void gen8_init_irq(
496 struct intel_gvt_irq *irq)
497 {
498 struct intel_gvt *gvt = irq_to_gvt(irq);
499
500 #define SET_BIT_INFO(s, b, e, i) \
501 do { \
502 s->events[e].bit = b; \
503 s->events[e].info = s->info[i]; \
504 s->info[i]->bit_to_event[b] = e;\
505 } while (0)
506
507 #define SET_IRQ_GROUP(s, g, i) \
508 do { \
509 s->info[g] = i; \
510 (i)->group = g; \
511 set_bit(g, s->irq_info_bitmap); \
512 } while (0)
513
514 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info);
515 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info);
516 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info);
517 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info);
518 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info);
519 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info);
520 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info);
521 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info);
522 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info);
523 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info);
524 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info);
525 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info);
526
527 /* GEN8 level 2 interrupts. */
528
529 /* GEN8 interrupt GT0 events */
530 SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
531 SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0);
532 SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
533
534 SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
535 SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0);
536 SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
537
538 /* GEN8 interrupt GT1 events */
539 SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1);
540 SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
541 SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
542
543 if (HAS_ENGINE(gvt->gt, VCS1)) {
544 SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
545 INTEL_GVT_IRQ_INFO_GT1);
546 SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
547 INTEL_GVT_IRQ_INFO_GT1);
548 SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH,
549 INTEL_GVT_IRQ_INFO_GT1);
550 }
551
552 /* GEN8 interrupt GT3 events */
553 SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3);
554 SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3);
555 SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3);
556
557 SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
558 SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
559 SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
560
561 /* GEN8 interrupt DE PORT events */
562 SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT);
563 SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT);
564
565 /* GEN8 interrupt DE MISC events */
566 SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC);
567
568 /* PCH events */
569 SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH);
570 SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
571 SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
572 SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
573 SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
574
575 if (IS_BROADWELL(gvt->gt->i915)) {
576 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);
577 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);
578 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);
579
580 SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
581 SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
582
583 SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
584 SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
585
586 SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
587 SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
588 } else if (GRAPHICS_VER(gvt->gt->i915) >= 9) {
589 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
590 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
591 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
592
593 SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
594 SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
595 SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
596
597 SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
598 SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
599 SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
600 }
601
602 /* GEN8 interrupt PCU events */
603 SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU);
604 SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU);
605 }
606
607 static struct intel_gvt_irq_ops gen8_irq_ops = {
608 .init_irq = gen8_init_irq,
609 .check_pending_irq = gen8_check_pending_irq,
610 };
611
612 /**
613 * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU
614 * @vgpu: a vGPU
615 * @event: interrupt event
616 *
617 * This function is used to trigger a virtual interrupt event for vGPU.
618 * The caller provides the event to be triggered, the framework itself
619 * will emulate the IRQ register bit change.
620 *
621 */
intel_vgpu_trigger_virtual_event(struct intel_vgpu * vgpu,enum intel_gvt_event_type event)622 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
623 enum intel_gvt_event_type event)
624 {
625 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
626 struct intel_gvt *gvt = vgpu->gvt;
627 struct intel_gvt_irq *irq = &gvt->irq;
628 gvt_event_virt_handler_t handler;
629 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
630
631 handler = get_event_virt_handler(irq, event);
632 drm_WARN_ON(&i915->drm, !handler);
633
634 handler(irq, event, vgpu);
635
636 ops->check_pending_irq(vgpu);
637 }
638
init_events(struct intel_gvt_irq * irq)639 static void init_events(
640 struct intel_gvt_irq *irq)
641 {
642 int i;
643
644 for (i = 0; i < INTEL_GVT_EVENT_MAX; i++) {
645 irq->events[i].info = NULL;
646 irq->events[i].v_handler = handle_default_event_virt;
647 }
648 }
649
650 /**
651 * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem
652 * @gvt: a GVT device
653 *
654 * This function is called at driver loading stage, to initialize the GVT-g IRQ
655 * emulation subsystem.
656 *
657 * Returns:
658 * Zero on success, negative error code if failed.
659 */
intel_gvt_init_irq(struct intel_gvt * gvt)660 int intel_gvt_init_irq(struct intel_gvt *gvt)
661 {
662 struct intel_gvt_irq *irq = &gvt->irq;
663
664 gvt_dbg_core("init irq framework\n");
665
666 irq->ops = &gen8_irq_ops;
667 irq->irq_map = gen8_irq_map;
668
669 /* common event initialization */
670 init_events(irq);
671
672 /* gen specific initialization */
673 irq->ops->init_irq(irq);
674
675 init_irq_map(irq);
676
677 return 0;
678 }
679