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1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Copyright (C) 2021 Linaro Ltd. */
4 
5 #include <linux/log2.h>
6 
7 #include "gsi.h"
8 #include "ipa_data.h"
9 #include "ipa_endpoint.h"
10 #include "ipa_mem.h"
11 
12 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.5 */
13 enum ipa_resource_type {
14 	/* Source resource types; first must have value 0 */
15 	IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS		= 0,
16 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
17 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
18 	IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
19 	IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
20 
21 	/* Destination resource types; first must have value 0 */
22 	IPA_RESOURCE_TYPE_DST_DATA_SECTORS		= 0,
23 	IPA_RESOURCE_TYPE_DST_DPS_DMARS,
24 };
25 
26 /* Resource groups used for an SoC having IPA v4.5 */
27 enum ipa_rsrc_group_id {
28 	/* Source resource group identifiers */
29 	IPA_RSRC_GROUP_SRC_UNUSED_0		= 0,
30 	IPA_RSRC_GROUP_SRC_UL_DL,
31 	IPA_RSRC_GROUP_SRC_UNUSED_2,
32 	IPA_RSRC_GROUP_SRC_UNUSED_3,
33 	IPA_RSRC_GROUP_SRC_UC_RX_Q,
34 	IPA_RSRC_GROUP_SRC_COUNT,	/* Last in set; not a source group */
35 
36 	/* Destination resource group identifiers */
37 	IPA_RSRC_GROUP_DST_UNUSED_0		= 0,
38 	IPA_RSRC_GROUP_DST_UL_DL_DPL,
39 	IPA_RSRC_GROUP_DST_UNUSED_2,
40 	IPA_RSRC_GROUP_DST_UNUSED_3,
41 	IPA_RSRC_GROUP_DST_UC,
42 	IPA_RSRC_GROUP_DST_COUNT,	/* Last; not a destination group */
43 };
44 
45 /* QSB configuration data for an SoC having IPA v4.5 */
46 static const struct ipa_qsb_data ipa_qsb_data[] = {
47 	[IPA_QSB_MASTER_DDR] = {
48 		.max_writes		= 8,
49 		.max_reads		= 0,	/* no limit (hardware max) */
50 		.max_reads_beats	= 120,
51 	},
52 	[IPA_QSB_MASTER_PCIE] = {
53 		.max_writes		= 8,
54 		.max_reads		= 12,
55 		/* no outstanding read byte (beat) limit */
56 	},
57 };
58 
59 /* Endpoint configuration data for an SoC having IPA v4.5 */
60 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
61 	[IPA_ENDPOINT_AP_COMMAND_TX] = {
62 		.ee_id		= GSI_EE_AP,
63 		.channel_id	= 9,
64 		.endpoint_id	= 7,
65 		.toward_ipa	= true,
66 		.channel = {
67 			.tre_count	= 256,
68 			.event_count	= 256,
69 			.tlv_count	= 20,
70 		},
71 		.endpoint = {
72 			.config = {
73 				.resource_group	= IPA_RSRC_GROUP_SRC_UL_DL,
74 				.dma_mode	= true,
75 				.dma_endpoint	= IPA_ENDPOINT_AP_LAN_RX,
76 				.tx = {
77 					.seq_type = IPA_SEQ_DMA,
78 				},
79 			},
80 		},
81 	},
82 	[IPA_ENDPOINT_AP_LAN_RX] = {
83 		.ee_id		= GSI_EE_AP,
84 		.channel_id	= 10,
85 		.endpoint_id	= 16,
86 		.toward_ipa	= false,
87 		.channel = {
88 			.tre_count	= 256,
89 			.event_count	= 256,
90 			.tlv_count	= 9,
91 		},
92 		.endpoint = {
93 			.config = {
94 				.resource_group	= IPA_RSRC_GROUP_DST_UL_DL_DPL,
95 				.aggregation	= true,
96 				.status_enable	= true,
97 				.rx = {
98 					.pad_align	= ilog2(sizeof(u32)),
99 				},
100 			},
101 		},
102 	},
103 	[IPA_ENDPOINT_AP_MODEM_TX] = {
104 		.ee_id		= GSI_EE_AP,
105 		.channel_id	= 7,
106 		.endpoint_id	= 2,
107 		.toward_ipa	= true,
108 		.channel = {
109 			.tre_count	= 512,
110 			.event_count	= 512,
111 			.tlv_count	= 16,
112 		},
113 		.endpoint = {
114 			.filter_support	= true,
115 			.config = {
116 				.resource_group	= IPA_RSRC_GROUP_SRC_UL_DL,
117 				.checksum       = true,
118 				.qmap		= true,
119 				.status_enable	= true,
120 				.tx = {
121 					.seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
122 					.status_endpoint =
123 						IPA_ENDPOINT_MODEM_AP_RX,
124 				},
125 			},
126 		},
127 	},
128 	[IPA_ENDPOINT_AP_MODEM_RX] = {
129 		.ee_id		= GSI_EE_AP,
130 		.channel_id	= 1,
131 		.endpoint_id	= 14,
132 		.toward_ipa	= false,
133 		.channel = {
134 			.tre_count	= 256,
135 			.event_count	= 256,
136 			.tlv_count	= 9,
137 		},
138 		.endpoint = {
139 			.config = {
140 				.resource_group	= IPA_RSRC_GROUP_DST_UL_DL_DPL,
141 				.checksum       = true,
142 				.qmap		= true,
143 				.aggregation	= true,
144 				.rx = {
145 					.aggr_close_eof	= true,
146 				},
147 			},
148 		},
149 	},
150 	[IPA_ENDPOINT_MODEM_AP_TX] = {
151 		.ee_id		= GSI_EE_MODEM,
152 		.channel_id	= 0,
153 		.endpoint_id	= 5,
154 		.toward_ipa	= true,
155 		.endpoint = {
156 			.filter_support	= true,
157 		},
158 	},
159 	[IPA_ENDPOINT_MODEM_AP_RX] = {
160 		.ee_id		= GSI_EE_MODEM,
161 		.channel_id	= 7,
162 		.endpoint_id	= 21,
163 		.toward_ipa	= false,
164 	},
165 	[IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
166 		.ee_id		= GSI_EE_MODEM,
167 		.channel_id	= 2,
168 		.endpoint_id	= 8,
169 		.toward_ipa	= true,
170 		.endpoint = {
171 			.filter_support	= true,
172 		},
173 	},
174 };
175 
176 /* Source resource configuration data for an SoC having IPA v4.5 */
177 static const struct ipa_resource ipa_resource_src[] = {
178 	[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
179 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
180 			.min = 1,	.max = 11,
181 		},
182 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
183 			.min = 1,	.max = 63,
184 		},
185 	},
186 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
187 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
188 			.min = 14,	.max = 14,
189 		},
190 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
191 			.min = 3,	.max = 3,
192 		},
193 	},
194 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
195 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
196 			.min = 18,	.max = 18,
197 		},
198 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
199 			.min = 8,	.max = 8,
200 		},
201 	},
202 	[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
203 		.limits[IPA_RSRC_GROUP_SRC_UNUSED_0] = {
204 			.min = 0,	.max = 63,
205 		},
206 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
207 			.min = 0,	.max = 63,
208 		},
209 		.limits[IPA_RSRC_GROUP_SRC_UNUSED_2] = {
210 			.min = 0,	.max = 63,
211 		},
212 		.limits[IPA_RSRC_GROUP_SRC_UNUSED_3] = {
213 			.min = 0,	.max = 63,
214 		},
215 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
216 			.min = 0,	.max = 63,
217 		},
218 	},
219 	[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
220 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
221 			.min = 24,	.max = 24,
222 		},
223 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
224 			.min = 8,	.max = 8,
225 		},
226 	},
227 };
228 
229 /* Destination resource configuration data for an SoC having IPA v4.5 */
230 static const struct ipa_resource ipa_resource_dst[] = {
231 	[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
232 		.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
233 			.min = 16,	.max = 16,
234 		},
235 		.limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
236 			.min = 2,	.max = 2,
237 		},
238 		.limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {
239 			.min = 2,	.max = 2,
240 		},
241 	},
242 	[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
243 		.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
244 			.min = 2,	.max = 63,
245 		},
246 		.limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
247 			.min = 1,	.max = 2,
248 		},
249 		.limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {
250 			.min = 1,	.max = 2,
251 		},
252 		.limits[IPA_RSRC_GROUP_DST_UC] = {
253 			.min = 0,	.max = 2,
254 		},
255 	},
256 };
257 
258 /* Resource configuration data for an SoC having IPA v4.5 */
259 static const struct ipa_resource_data ipa_resource_data = {
260 	.rsrc_group_src_count	= IPA_RSRC_GROUP_SRC_COUNT,
261 	.rsrc_group_dst_count	= IPA_RSRC_GROUP_DST_COUNT,
262 	.resource_src_count	= ARRAY_SIZE(ipa_resource_src),
263 	.resource_src		= ipa_resource_src,
264 	.resource_dst_count	= ARRAY_SIZE(ipa_resource_dst),
265 	.resource_dst		= ipa_resource_dst,
266 };
267 
268 /* IPA-resident memory region data for an SoC having IPA v4.5 */
269 static const struct ipa_mem ipa_mem_local_data[] = {
270 	{
271 		.id		= IPA_MEM_UC_SHARED,
272 		.offset		= 0x0000,
273 		.size		= 0x0080,
274 		.canary_count	= 0,
275 	},
276 	{
277 		.id		= IPA_MEM_UC_INFO,
278 		.offset		= 0x0080,
279 		.size		= 0x0200,
280 		.canary_count	= 0,
281 	},
282 	{
283 		.id		= IPA_MEM_V4_FILTER_HASHED,
284 		.offset		= 0x0288,
285 		.size		= 0x0078,
286 		.canary_count	= 2,
287 	},
288 	{
289 		.id		= IPA_MEM_V4_FILTER,
290 		.offset		= 0x0308,
291 		.size		= 0x0078,
292 		.canary_count	= 2,
293 	},
294 	{
295 		.id		= IPA_MEM_V6_FILTER_HASHED,
296 		.offset		= 0x0388,
297 		.size		= 0x0078,
298 		.canary_count	= 2,
299 	},
300 	{
301 		.id		= IPA_MEM_V6_FILTER,
302 		.offset		= 0x0408,
303 		.size		= 0x0078,
304 		.canary_count	= 2,
305 	},
306 	{
307 		.id		= IPA_MEM_V4_ROUTE_HASHED,
308 		.offset		= 0x0488,
309 		.size		= 0x0078,
310 		.canary_count	= 2,
311 	},
312 	{
313 		.id		= IPA_MEM_V4_ROUTE,
314 		.offset		= 0x0508,
315 		.size		= 0x0078,
316 		.canary_count	= 2,
317 	},
318 	{
319 		.id		= IPA_MEM_V6_ROUTE_HASHED,
320 		.offset		= 0x0588,
321 		.size		= 0x0078,
322 		.canary_count	= 2,
323 	},
324 	{
325 		.id		= IPA_MEM_V6_ROUTE,
326 		.offset		= 0x0608,
327 		.size		= 0x0078,
328 		.canary_count	= 2,
329 	},
330 	{
331 		.id		= IPA_MEM_MODEM_HEADER,
332 		.offset		= 0x0688,
333 		.size		= 0x0240,
334 		.canary_count	= 2,
335 	},
336 	{
337 		.id		= IPA_MEM_AP_HEADER,
338 		.offset		= 0x08c8,
339 		.size		= 0x0200,
340 		.canary_count	= 0,
341 	},
342 	{
343 		.id		= IPA_MEM_MODEM_PROC_CTX,
344 		.offset		= 0x0ad0,
345 		.size		= 0x0b20,
346 		.canary_count	= 2,
347 	},
348 	{
349 		.id		= IPA_MEM_AP_PROC_CTX,
350 		.offset		= 0x15f0,
351 		.size		= 0x0200,
352 		.canary_count	= 0,
353 	},
354 	{
355 		.id		= IPA_MEM_NAT_TABLE,
356 		.offset		= 0x1800,
357 		.size		= 0x0d00,
358 		.canary_count	= 4,
359 	},
360 	{
361 		.id		= IPA_MEM_STATS_QUOTA_MODEM,
362 		.offset		= 0x2510,
363 		.size		= 0x0030,
364 		.canary_count	= 4,
365 	},
366 	{
367 		.id		= IPA_MEM_STATS_QUOTA_AP,
368 		.offset		= 0x2540,
369 		.size		= 0x0048,
370 		.canary_count	= 0,
371 	},
372 	{
373 		.id		= IPA_MEM_STATS_TETHERING,
374 		.offset		= 0x2588,
375 		.size		= 0x0238,
376 		.canary_count	= 0,
377 	},
378 	{
379 		.id		= IPA_MEM_STATS_FILTER_ROUTE,
380 		.offset		= 0x27c0,
381 		.size		= 0x0800,
382 		.canary_count	= 0,
383 	},
384 	{
385 		.id		= IPA_MEM_STATS_DROP,
386 		.offset		= 0x2fc0,
387 		.size		= 0x0020,
388 		.canary_count	= 0,
389 	},
390 	{
391 		.id		= IPA_MEM_MODEM,
392 		.offset		= 0x2fe8,
393 		.size		= 0x0800,
394 		.canary_count	= 2,
395 	},
396 	{
397 		.id		= IPA_MEM_UC_EVENT_RING,
398 		.offset		= 0x3800,
399 		.size		= 0x1000,
400 		.canary_count	= 1,
401 	},
402 	{
403 		.id		= IPA_MEM_PDN_CONFIG,
404 		.offset		= 0x4800,
405 		.size		= 0x0050,
406 		.canary_count	= 0,
407 	},
408 };
409 
410 /* Memory configuration data for an SoC having IPA v4.5 */
411 static const struct ipa_mem_data ipa_mem_data = {
412 	.local_count	= ARRAY_SIZE(ipa_mem_local_data),
413 	.local		= ipa_mem_local_data,
414 	.imem_addr	= 0x14688000,
415 	.imem_size	= 0x00003000,
416 	.smem_id	= 497,
417 	.smem_size	= 0x00009000,
418 };
419 
420 /* Interconnect rates are in 1000 byte/second units */
421 static const struct ipa_interconnect_data ipa_interconnect_data[] = {
422 	{
423 		.name			= "memory-a",
424 		.peak_bandwidth		= 600000,	/* 600 MBps */
425 		.average_bandwidth	= 150000,	/* 150 MBps */
426 	},
427 	{
428 		.name			= "memory-b",
429 		.peak_bandwidth		= 1804000,	/* 1.804 GBps */
430 		.average_bandwidth	= 150000,	/* 150 MBps */
431 	},
432 	/* Average rate is unused for the next two interconnects */
433 	{
434 		.name			= "imem",
435 		.peak_bandwidth		= 450000,	/* 450 MBps */
436 		.average_bandwidth	= 75000,	/* 75 MBps (unused?) */
437 	},
438 	{
439 		.name			= "config",
440 		.peak_bandwidth		= 171400,	/* 171.4 MBps */
441 		.average_bandwidth	= 0,		/* unused */
442 	},
443 };
444 
445 /* Clock and interconnect configuration data for an SoC having IPA v4.5 */
446 static const struct ipa_power_data ipa_power_data = {
447 	.core_clock_rate	= 150 * 1000 * 1000,	/* Hz (150?  60?) */
448 	.interconnect_count	= ARRAY_SIZE(ipa_interconnect_data),
449 	.interconnect_data	= ipa_interconnect_data,
450 };
451 
452 /* Configuration data for an SoC having IPA v4.5 */
453 const struct ipa_data ipa_data_v4_5 = {
454 	.version	= IPA_VERSION_4_5,
455 	.qsb_count	= ARRAY_SIZE(ipa_qsb_data),
456 	.qsb_data	= ipa_qsb_data,
457 	.endpoint_count	= ARRAY_SIZE(ipa_gsi_endpoint_data),
458 	.endpoint_data	= ipa_gsi_endpoint_data,
459 	.resource_data	= &ipa_resource_data,
460 	.mem_data	= &ipa_mem_data,
461 	.power_data	= &ipa_power_data,
462 };
463