1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
6 */
7 #include <linux/devcoredump.h>
8 #include "iwl-drv.h"
9 #include "runtime.h"
10 #include "dbg.h"
11 #include "debugfs.h"
12 #include "iwl-io.h"
13 #include "iwl-prph.h"
14 #include "iwl-csr.h"
15
16 /**
17 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump
18 *
19 * @fwrt_ptr: pointer to the buffer coming from fwrt
20 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the
21 * transport's data.
22 * @trans_len: length of the valid data in trans_ptr
23 * @fwrt_len: length of the valid data in fwrt_ptr
24 */
25 struct iwl_fw_dump_ptrs {
26 struct iwl_trans_dump_data *trans_ptr;
27 void *fwrt_ptr;
28 u32 fwrt_len;
29 };
30
31 #define RADIO_REG_MAX_READ 0x2ad
iwl_read_radio_regs(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data)32 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,
33 struct iwl_fw_error_dump_data **dump_data)
34 {
35 u8 *pos = (void *)(*dump_data)->data;
36 int i;
37
38 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n");
39
40 if (!iwl_trans_grab_nic_access(fwrt->trans))
41 return;
42
43 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG);
44 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ);
45
46 for (i = 0; i < RADIO_REG_MAX_READ; i++) {
47 u32 rd_cmd = RADIO_RSP_RD_CMD;
48
49 rd_cmd |= i << RADIO_RSP_ADDR_POS;
50 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd);
51 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT);
52
53 pos++;
54 }
55
56 *dump_data = iwl_fw_error_next_data(*dump_data);
57
58 iwl_trans_release_nic_access(fwrt->trans);
59 }
60
iwl_fwrt_dump_rxf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data,int size,u32 offset,int fifo_num)61 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt,
62 struct iwl_fw_error_dump_data **dump_data,
63 int size, u32 offset, int fifo_num)
64 {
65 struct iwl_fw_error_dump_fifo *fifo_hdr;
66 u32 *fifo_data;
67 u32 fifo_len;
68 int i;
69
70 fifo_hdr = (void *)(*dump_data)->data;
71 fifo_data = (void *)fifo_hdr->data;
72 fifo_len = size;
73
74 /* No need to try to read the data if the length is 0 */
75 if (fifo_len == 0)
76 return;
77
78 /* Add a TLV for the RXF */
79 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF);
80 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
81
82 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
83 fifo_hdr->available_bytes =
84 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
85 RXF_RD_D_SPACE + offset));
86 fifo_hdr->wr_ptr =
87 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
88 RXF_RD_WR_PTR + offset));
89 fifo_hdr->rd_ptr =
90 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
91 RXF_RD_RD_PTR + offset));
92 fifo_hdr->fence_ptr =
93 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
94 RXF_RD_FENCE_PTR + offset));
95 fifo_hdr->fence_mode =
96 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
97 RXF_SET_FENCE_MODE + offset));
98
99 /* Lock fence */
100 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1);
101 /* Set fence pointer to the same place like WR pointer */
102 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1);
103 /* Set fence offset */
104 iwl_trans_write_prph(fwrt->trans,
105 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);
106
107 /* Read FIFO */
108 fifo_len /= sizeof(u32); /* Size in DWORDS */
109 for (i = 0; i < fifo_len; i++)
110 fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
111 RXF_FIFO_RD_FENCE_INC +
112 offset);
113 *dump_data = iwl_fw_error_next_data(*dump_data);
114 }
115
iwl_fwrt_dump_txf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data,int size,u32 offset,int fifo_num)116 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt,
117 struct iwl_fw_error_dump_data **dump_data,
118 int size, u32 offset, int fifo_num)
119 {
120 struct iwl_fw_error_dump_fifo *fifo_hdr;
121 u32 *fifo_data;
122 u32 fifo_len;
123 int i;
124
125 fifo_hdr = (void *)(*dump_data)->data;
126 fifo_data = (void *)fifo_hdr->data;
127 fifo_len = size;
128
129 /* No need to try to read the data if the length is 0 */
130 if (fifo_len == 0)
131 return;
132
133 /* Add a TLV for the FIFO */
134 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF);
135 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
136
137 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
138 fifo_hdr->available_bytes =
139 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
140 TXF_FIFO_ITEM_CNT + offset));
141 fifo_hdr->wr_ptr =
142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
143 TXF_WR_PTR + offset));
144 fifo_hdr->rd_ptr =
145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
146 TXF_RD_PTR + offset));
147 fifo_hdr->fence_ptr =
148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
149 TXF_FENCE_PTR + offset));
150 fifo_hdr->fence_mode =
151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
152 TXF_LOCK_FENCE + offset));
153
154 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
155 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset,
156 TXF_WR_PTR + offset);
157
158 /* Dummy-read to advance the read pointer to the head */
159 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset);
160
161 /* Read FIFO */
162 fifo_len /= sizeof(u32); /* Size in DWORDS */
163 for (i = 0; i < fifo_len; i++)
164 fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
165 TXF_READ_MODIFY_DATA +
166 offset);
167 *dump_data = iwl_fw_error_next_data(*dump_data);
168 }
169
iwl_fw_dump_rxf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data)170 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt,
171 struct iwl_fw_error_dump_data **dump_data)
172 {
173 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
174
175 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n");
176
177 if (!iwl_trans_grab_nic_access(fwrt->trans))
178 return;
179
180 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) {
181 /* Pull RXF1 */
182 iwl_fwrt_dump_rxf(fwrt, dump_data,
183 cfg->lmac[0].rxfifo1_size, 0, 0);
184 /* Pull RXF2 */
185 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size,
186 RXF_DIFF_FROM_PREV +
187 fwrt->trans->trans_cfg->umac_prph_offset, 1);
188 /* Pull LMAC2 RXF1 */
189 if (fwrt->smem_cfg.num_lmacs > 1)
190 iwl_fwrt_dump_rxf(fwrt, dump_data,
191 cfg->lmac[1].rxfifo1_size,
192 LMAC2_PRPH_OFFSET, 2);
193 }
194
195 iwl_trans_release_nic_access(fwrt->trans);
196 }
197
iwl_fw_dump_txf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data)198 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
199 struct iwl_fw_error_dump_data **dump_data)
200 {
201 struct iwl_fw_error_dump_fifo *fifo_hdr;
202 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
203 u32 *fifo_data;
204 u32 fifo_len;
205 int i, j;
206
207 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n");
208
209 if (!iwl_trans_grab_nic_access(fwrt->trans))
210 return;
211
212 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) {
213 /* Pull TXF data from LMAC1 */
214 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) {
215 /* Mark the number of TXF we're pulling now */
216 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i);
217 iwl_fwrt_dump_txf(fwrt, dump_data,
218 cfg->lmac[0].txfifo_size[i], 0, i);
219 }
220
221 /* Pull TXF data from LMAC2 */
222 if (fwrt->smem_cfg.num_lmacs > 1) {
223 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries;
224 i++) {
225 /* Mark the number of TXF we're pulling now */
226 iwl_trans_write_prph(fwrt->trans,
227 TXF_LARC_NUM +
228 LMAC2_PRPH_OFFSET, i);
229 iwl_fwrt_dump_txf(fwrt, dump_data,
230 cfg->lmac[1].txfifo_size[i],
231 LMAC2_PRPH_OFFSET,
232 i + cfg->num_txfifo_entries);
233 }
234 }
235 }
236
237 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
238 fw_has_capa(&fwrt->fw->ucode_capa,
239 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
240 /* Pull UMAC internal TXF data from all TXFs */
241 for (i = 0;
242 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size);
243 i++) {
244 fifo_hdr = (void *)(*dump_data)->data;
245 fifo_data = (void *)fifo_hdr->data;
246 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i];
247
248 /* No need to try to read the data if the length is 0 */
249 if (fifo_len == 0)
250 continue;
251
252 /* Add a TLV for the internal FIFOs */
253 (*dump_data)->type =
254 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF);
255 (*dump_data)->len =
256 cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
257
258 fifo_hdr->fifo_num = cpu_to_le32(i);
259
260 /* Mark the number of TXF we're pulling now */
261 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i +
262 fwrt->smem_cfg.num_txfifo_entries);
263
264 fifo_hdr->available_bytes =
265 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
266 TXF_CPU2_FIFO_ITEM_CNT));
267 fifo_hdr->wr_ptr =
268 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
269 TXF_CPU2_WR_PTR));
270 fifo_hdr->rd_ptr =
271 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
272 TXF_CPU2_RD_PTR));
273 fifo_hdr->fence_ptr =
274 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
275 TXF_CPU2_FENCE_PTR));
276 fifo_hdr->fence_mode =
277 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
278 TXF_CPU2_LOCK_FENCE));
279
280 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */
281 iwl_trans_write_prph(fwrt->trans,
282 TXF_CPU2_READ_MODIFY_ADDR,
283 TXF_CPU2_WR_PTR);
284
285 /* Dummy-read to advance the read pointer to head */
286 iwl_trans_read_prph(fwrt->trans,
287 TXF_CPU2_READ_MODIFY_DATA);
288
289 /* Read FIFO */
290 fifo_len /= sizeof(u32); /* Size in DWORDS */
291 for (j = 0; j < fifo_len; j++)
292 fifo_data[j] =
293 iwl_trans_read_prph(fwrt->trans,
294 TXF_CPU2_READ_MODIFY_DATA);
295 *dump_data = iwl_fw_error_next_data(*dump_data);
296 }
297 }
298
299 iwl_trans_release_nic_access(fwrt->trans);
300 }
301
302 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */
303 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */
304
305 struct iwl_prph_range {
306 u32 start, end;
307 };
308
309 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = {
310 { .start = 0x00a00000, .end = 0x00a00000 },
311 { .start = 0x00a0000c, .end = 0x00a00024 },
312 { .start = 0x00a0002c, .end = 0x00a0003c },
313 { .start = 0x00a00410, .end = 0x00a00418 },
314 { .start = 0x00a00420, .end = 0x00a00420 },
315 { .start = 0x00a00428, .end = 0x00a00428 },
316 { .start = 0x00a00430, .end = 0x00a0043c },
317 { .start = 0x00a00444, .end = 0x00a00444 },
318 { .start = 0x00a004c0, .end = 0x00a004cc },
319 { .start = 0x00a004d8, .end = 0x00a004d8 },
320 { .start = 0x00a004e0, .end = 0x00a004f0 },
321 { .start = 0x00a00840, .end = 0x00a00840 },
322 { .start = 0x00a00850, .end = 0x00a00858 },
323 { .start = 0x00a01004, .end = 0x00a01008 },
324 { .start = 0x00a01010, .end = 0x00a01010 },
325 { .start = 0x00a01018, .end = 0x00a01018 },
326 { .start = 0x00a01024, .end = 0x00a01024 },
327 { .start = 0x00a0102c, .end = 0x00a01034 },
328 { .start = 0x00a0103c, .end = 0x00a01040 },
329 { .start = 0x00a01048, .end = 0x00a01094 },
330 { .start = 0x00a01c00, .end = 0x00a01c20 },
331 { .start = 0x00a01c58, .end = 0x00a01c58 },
332 { .start = 0x00a01c7c, .end = 0x00a01c7c },
333 { .start = 0x00a01c28, .end = 0x00a01c54 },
334 { .start = 0x00a01c5c, .end = 0x00a01c5c },
335 { .start = 0x00a01c60, .end = 0x00a01cdc },
336 { .start = 0x00a01ce0, .end = 0x00a01d0c },
337 { .start = 0x00a01d18, .end = 0x00a01d20 },
338 { .start = 0x00a01d2c, .end = 0x00a01d30 },
339 { .start = 0x00a01d40, .end = 0x00a01d5c },
340 { .start = 0x00a01d80, .end = 0x00a01d80 },
341 { .start = 0x00a01d98, .end = 0x00a01d9c },
342 { .start = 0x00a01da8, .end = 0x00a01da8 },
343 { .start = 0x00a01db8, .end = 0x00a01df4 },
344 { .start = 0x00a01dc0, .end = 0x00a01dfc },
345 { .start = 0x00a01e00, .end = 0x00a01e2c },
346 { .start = 0x00a01e40, .end = 0x00a01e60 },
347 { .start = 0x00a01e68, .end = 0x00a01e6c },
348 { .start = 0x00a01e74, .end = 0x00a01e74 },
349 { .start = 0x00a01e84, .end = 0x00a01e90 },
350 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
351 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
352 { .start = 0x00a01f00, .end = 0x00a01f1c },
353 { .start = 0x00a01f44, .end = 0x00a01ffc },
354 { .start = 0x00a02000, .end = 0x00a02048 },
355 { .start = 0x00a02068, .end = 0x00a020f0 },
356 { .start = 0x00a02100, .end = 0x00a02118 },
357 { .start = 0x00a02140, .end = 0x00a0214c },
358 { .start = 0x00a02168, .end = 0x00a0218c },
359 { .start = 0x00a021c0, .end = 0x00a021c0 },
360 { .start = 0x00a02400, .end = 0x00a02410 },
361 { .start = 0x00a02418, .end = 0x00a02420 },
362 { .start = 0x00a02428, .end = 0x00a0242c },
363 { .start = 0x00a02434, .end = 0x00a02434 },
364 { .start = 0x00a02440, .end = 0x00a02460 },
365 { .start = 0x00a02468, .end = 0x00a024b0 },
366 { .start = 0x00a024c8, .end = 0x00a024cc },
367 { .start = 0x00a02500, .end = 0x00a02504 },
368 { .start = 0x00a0250c, .end = 0x00a02510 },
369 { .start = 0x00a02540, .end = 0x00a02554 },
370 { .start = 0x00a02580, .end = 0x00a025f4 },
371 { .start = 0x00a02600, .end = 0x00a0260c },
372 { .start = 0x00a02648, .end = 0x00a02650 },
373 { .start = 0x00a02680, .end = 0x00a02680 },
374 { .start = 0x00a026c0, .end = 0x00a026d0 },
375 { .start = 0x00a02700, .end = 0x00a0270c },
376 { .start = 0x00a02804, .end = 0x00a02804 },
377 { .start = 0x00a02818, .end = 0x00a0281c },
378 { .start = 0x00a02c00, .end = 0x00a02db4 },
379 { .start = 0x00a02df4, .end = 0x00a02fb0 },
380 { .start = 0x00a03000, .end = 0x00a03014 },
381 { .start = 0x00a0301c, .end = 0x00a0302c },
382 { .start = 0x00a03034, .end = 0x00a03038 },
383 { .start = 0x00a03040, .end = 0x00a03048 },
384 { .start = 0x00a03060, .end = 0x00a03068 },
385 { .start = 0x00a03070, .end = 0x00a03074 },
386 { .start = 0x00a0307c, .end = 0x00a0307c },
387 { .start = 0x00a03080, .end = 0x00a03084 },
388 { .start = 0x00a0308c, .end = 0x00a03090 },
389 { .start = 0x00a03098, .end = 0x00a03098 },
390 { .start = 0x00a030a0, .end = 0x00a030a0 },
391 { .start = 0x00a030a8, .end = 0x00a030b4 },
392 { .start = 0x00a030bc, .end = 0x00a030bc },
393 { .start = 0x00a030c0, .end = 0x00a0312c },
394 { .start = 0x00a03c00, .end = 0x00a03c5c },
395 { .start = 0x00a04400, .end = 0x00a04454 },
396 { .start = 0x00a04460, .end = 0x00a04474 },
397 { .start = 0x00a044c0, .end = 0x00a044ec },
398 { .start = 0x00a04500, .end = 0x00a04504 },
399 { .start = 0x00a04510, .end = 0x00a04538 },
400 { .start = 0x00a04540, .end = 0x00a04548 },
401 { .start = 0x00a04560, .end = 0x00a0457c },
402 { .start = 0x00a04590, .end = 0x00a04598 },
403 { .start = 0x00a045c0, .end = 0x00a045f4 },
404 };
405
406 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = {
407 { .start = 0x00a05c00, .end = 0x00a05c18 },
408 { .start = 0x00a05400, .end = 0x00a056e8 },
409 { .start = 0x00a08000, .end = 0x00a098bc },
410 { .start = 0x00a02400, .end = 0x00a02758 },
411 { .start = 0x00a04764, .end = 0x00a0476c },
412 { .start = 0x00a04770, .end = 0x00a04774 },
413 { .start = 0x00a04620, .end = 0x00a04624 },
414 };
415
416 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = {
417 { .start = 0x00a00000, .end = 0x00a00000 },
418 { .start = 0x00a0000c, .end = 0x00a00024 },
419 { .start = 0x00a0002c, .end = 0x00a00034 },
420 { .start = 0x00a0003c, .end = 0x00a0003c },
421 { .start = 0x00a00410, .end = 0x00a00418 },
422 { .start = 0x00a00420, .end = 0x00a00420 },
423 { .start = 0x00a00428, .end = 0x00a00428 },
424 { .start = 0x00a00430, .end = 0x00a0043c },
425 { .start = 0x00a00444, .end = 0x00a00444 },
426 { .start = 0x00a00840, .end = 0x00a00840 },
427 { .start = 0x00a00850, .end = 0x00a00858 },
428 { .start = 0x00a01004, .end = 0x00a01008 },
429 { .start = 0x00a01010, .end = 0x00a01010 },
430 { .start = 0x00a01018, .end = 0x00a01018 },
431 { .start = 0x00a01024, .end = 0x00a01024 },
432 { .start = 0x00a0102c, .end = 0x00a01034 },
433 { .start = 0x00a0103c, .end = 0x00a01040 },
434 { .start = 0x00a01048, .end = 0x00a01050 },
435 { .start = 0x00a01058, .end = 0x00a01058 },
436 { .start = 0x00a01060, .end = 0x00a01070 },
437 { .start = 0x00a0108c, .end = 0x00a0108c },
438 { .start = 0x00a01c20, .end = 0x00a01c28 },
439 { .start = 0x00a01d10, .end = 0x00a01d10 },
440 { .start = 0x00a01e28, .end = 0x00a01e2c },
441 { .start = 0x00a01e60, .end = 0x00a01e60 },
442 { .start = 0x00a01e80, .end = 0x00a01e80 },
443 { .start = 0x00a01ea0, .end = 0x00a01ea0 },
444 { .start = 0x00a02000, .end = 0x00a0201c },
445 { .start = 0x00a02024, .end = 0x00a02024 },
446 { .start = 0x00a02040, .end = 0x00a02048 },
447 { .start = 0x00a020c0, .end = 0x00a020e0 },
448 { .start = 0x00a02400, .end = 0x00a02404 },
449 { .start = 0x00a0240c, .end = 0x00a02414 },
450 { .start = 0x00a0241c, .end = 0x00a0243c },
451 { .start = 0x00a02448, .end = 0x00a024bc },
452 { .start = 0x00a024c4, .end = 0x00a024cc },
453 { .start = 0x00a02508, .end = 0x00a02508 },
454 { .start = 0x00a02510, .end = 0x00a02514 },
455 { .start = 0x00a0251c, .end = 0x00a0251c },
456 { .start = 0x00a0252c, .end = 0x00a0255c },
457 { .start = 0x00a02564, .end = 0x00a025a0 },
458 { .start = 0x00a025a8, .end = 0x00a025b4 },
459 { .start = 0x00a025c0, .end = 0x00a025c0 },
460 { .start = 0x00a025e8, .end = 0x00a025f4 },
461 { .start = 0x00a02c08, .end = 0x00a02c18 },
462 { .start = 0x00a02c2c, .end = 0x00a02c38 },
463 { .start = 0x00a02c68, .end = 0x00a02c78 },
464 { .start = 0x00a03000, .end = 0x00a03000 },
465 { .start = 0x00a03010, .end = 0x00a03014 },
466 { .start = 0x00a0301c, .end = 0x00a0302c },
467 { .start = 0x00a03034, .end = 0x00a03038 },
468 { .start = 0x00a03040, .end = 0x00a03044 },
469 { .start = 0x00a03060, .end = 0x00a03068 },
470 { .start = 0x00a03070, .end = 0x00a03070 },
471 { .start = 0x00a0307c, .end = 0x00a03084 },
472 { .start = 0x00a0308c, .end = 0x00a03090 },
473 { .start = 0x00a03098, .end = 0x00a03098 },
474 { .start = 0x00a030a0, .end = 0x00a030a0 },
475 { .start = 0x00a030a8, .end = 0x00a030b4 },
476 { .start = 0x00a030bc, .end = 0x00a030c0 },
477 { .start = 0x00a030c8, .end = 0x00a030f4 },
478 { .start = 0x00a03100, .end = 0x00a0312c },
479 { .start = 0x00a03c00, .end = 0x00a03c5c },
480 { .start = 0x00a04400, .end = 0x00a04454 },
481 { .start = 0x00a04460, .end = 0x00a04474 },
482 { .start = 0x00a044c0, .end = 0x00a044ec },
483 { .start = 0x00a04500, .end = 0x00a04504 },
484 { .start = 0x00a04510, .end = 0x00a04538 },
485 { .start = 0x00a04540, .end = 0x00a04548 },
486 { .start = 0x00a04560, .end = 0x00a04560 },
487 { .start = 0x00a04570, .end = 0x00a0457c },
488 { .start = 0x00a04590, .end = 0x00a04590 },
489 { .start = 0x00a04598, .end = 0x00a04598 },
490 { .start = 0x00a045c0, .end = 0x00a045f4 },
491 { .start = 0x00a05c18, .end = 0x00a05c1c },
492 { .start = 0x00a0c000, .end = 0x00a0c018 },
493 { .start = 0x00a0c020, .end = 0x00a0c028 },
494 { .start = 0x00a0c038, .end = 0x00a0c094 },
495 { .start = 0x00a0c0c0, .end = 0x00a0c104 },
496 { .start = 0x00a0c10c, .end = 0x00a0c118 },
497 { .start = 0x00a0c150, .end = 0x00a0c174 },
498 { .start = 0x00a0c17c, .end = 0x00a0c188 },
499 { .start = 0x00a0c190, .end = 0x00a0c198 },
500 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 },
501 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 },
502 };
503
504 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = {
505 { .start = 0x00d03c00, .end = 0x00d03c64 },
506 { .start = 0x00d05c18, .end = 0x00d05c1c },
507 { .start = 0x00d0c000, .end = 0x00d0c174 },
508 };
509
iwl_read_prph_block(struct iwl_trans * trans,u32 start,u32 len_bytes,__le32 * data)510 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start,
511 u32 len_bytes, __le32 *data)
512 {
513 u32 i;
514
515 for (i = 0; i < len_bytes; i += 4)
516 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i));
517 }
518
iwl_dump_prph(struct iwl_fw_runtime * fwrt,const struct iwl_prph_range * iwl_prph_dump_addr,u32 range_len,void * ptr)519 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
520 const struct iwl_prph_range *iwl_prph_dump_addr,
521 u32 range_len, void *ptr)
522 {
523 struct iwl_fw_error_dump_prph *prph;
524 struct iwl_trans *trans = fwrt->trans;
525 struct iwl_fw_error_dump_data **data =
526 (struct iwl_fw_error_dump_data **)ptr;
527 u32 i;
528
529 if (!data)
530 return;
531
532 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n");
533
534 if (!iwl_trans_grab_nic_access(trans))
535 return;
536
537 for (i = 0; i < range_len; i++) {
538 /* The range includes both boundaries */
539 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
540 iwl_prph_dump_addr[i].start + 4;
541
542 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
543 (*data)->len = cpu_to_le32(sizeof(*prph) +
544 num_bytes_in_chunk);
545 prph = (void *)(*data)->data;
546 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
547
548 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start,
549 /* our range is inclusive, hence + 4 */
550 iwl_prph_dump_addr[i].end -
551 iwl_prph_dump_addr[i].start + 4,
552 (void *)prph->data);
553
554 *data = iwl_fw_error_next_data(*data);
555 }
556
557 iwl_trans_release_nic_access(trans);
558 }
559
560 /*
561 * alloc_sgtable - allocates scallerlist table in the given size,
562 * fills it with pages and returns it
563 * @size: the size (in bytes) of the table
564 */
alloc_sgtable(int size)565 static struct scatterlist *alloc_sgtable(int size)
566 {
567 int alloc_size, nents, i;
568 struct page *new_page;
569 struct scatterlist *iter;
570 struct scatterlist *table;
571
572 nents = DIV_ROUND_UP(size, PAGE_SIZE);
573 table = kcalloc(nents, sizeof(*table), GFP_KERNEL);
574 if (!table)
575 return NULL;
576 sg_init_table(table, nents);
577 iter = table;
578 for_each_sg(table, iter, sg_nents(table), i) {
579 new_page = alloc_page(GFP_KERNEL);
580 if (!new_page) {
581 /* release all previous allocated pages in the table */
582 iter = table;
583 for_each_sg(table, iter, sg_nents(table), i) {
584 new_page = sg_page(iter);
585 if (new_page)
586 __free_page(new_page);
587 }
588 kfree(table);
589 return NULL;
590 }
591 alloc_size = min_t(int, size, PAGE_SIZE);
592 size -= PAGE_SIZE;
593 sg_set_page(iter, new_page, alloc_size, 0);
594 }
595 return table;
596 }
597
iwl_fw_get_prph_len(struct iwl_fw_runtime * fwrt,const struct iwl_prph_range * iwl_prph_dump_addr,u32 range_len,void * ptr)598 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt,
599 const struct iwl_prph_range *iwl_prph_dump_addr,
600 u32 range_len, void *ptr)
601 {
602 u32 *prph_len = (u32 *)ptr;
603 int i, num_bytes_in_chunk;
604
605 if (!prph_len)
606 return;
607
608 for (i = 0; i < range_len; i++) {
609 /* The range includes both boundaries */
610 num_bytes_in_chunk =
611 iwl_prph_dump_addr[i].end -
612 iwl_prph_dump_addr[i].start + 4;
613
614 *prph_len += sizeof(struct iwl_fw_error_dump_data) +
615 sizeof(struct iwl_fw_error_dump_prph) +
616 num_bytes_in_chunk;
617 }
618 }
619
iwl_fw_prph_handler(struct iwl_fw_runtime * fwrt,void * ptr,void (* handler)(struct iwl_fw_runtime *,const struct iwl_prph_range *,u32,void *))620 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr,
621 void (*handler)(struct iwl_fw_runtime *,
622 const struct iwl_prph_range *,
623 u32, void *))
624 {
625 u32 range_len;
626
627 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
628 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210);
629 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr);
630 } else if (fwrt->trans->trans_cfg->device_family >=
631 IWL_DEVICE_FAMILY_22000) {
632 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000);
633 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr);
634 } else {
635 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm);
636 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr);
637
638 if (fwrt->trans->trans_cfg->mq_rx_supported) {
639 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000);
640 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr);
641 }
642 }
643 }
644
iwl_fw_dump_mem(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data,u32 len,u32 ofs,u32 type)645 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt,
646 struct iwl_fw_error_dump_data **dump_data,
647 u32 len, u32 ofs, u32 type)
648 {
649 struct iwl_fw_error_dump_mem *dump_mem;
650
651 if (!len)
652 return;
653
654 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
655 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem));
656 dump_mem = (void *)(*dump_data)->data;
657 dump_mem->type = cpu_to_le32(type);
658 dump_mem->offset = cpu_to_le32(ofs);
659 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len);
660 *dump_data = iwl_fw_error_next_data(*dump_data);
661
662 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type);
663 }
664
665 #define ADD_LEN(len, item_len, const_len) \
666 do {size_t item = item_len; len += (!!item) * const_len + item; } \
667 while (0)
668
iwl_fw_rxf_len(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_shared_mem_cfg * mem_cfg)669 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt,
670 struct iwl_fwrt_shared_mem_cfg *mem_cfg)
671 {
672 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
673 sizeof(struct iwl_fw_error_dump_fifo);
674 u32 fifo_len = 0;
675 int i;
676
677 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF))
678 return 0;
679
680 /* Count RXF2 size */
681 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len);
682
683 /* Count RXF1 sizes */
684 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
685 mem_cfg->num_lmacs = MAX_NUM_LMAC;
686
687 for (i = 0; i < mem_cfg->num_lmacs; i++)
688 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len);
689
690 return fifo_len;
691 }
692
iwl_fw_txf_len(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_shared_mem_cfg * mem_cfg)693 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt,
694 struct iwl_fwrt_shared_mem_cfg *mem_cfg)
695 {
696 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
697 sizeof(struct iwl_fw_error_dump_fifo);
698 u32 fifo_len = 0;
699 int i;
700
701 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF))
702 goto dump_internal_txf;
703
704 /* Count TXF sizes */
705 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
706 mem_cfg->num_lmacs = MAX_NUM_LMAC;
707
708 for (i = 0; i < mem_cfg->num_lmacs; i++) {
709 int j;
710
711 for (j = 0; j < mem_cfg->num_txfifo_entries; j++)
712 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j],
713 hdr_len);
714 }
715
716 dump_internal_txf:
717 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
718 fw_has_capa(&fwrt->fw->ucode_capa,
719 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)))
720 goto out;
721
722 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++)
723 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len);
724
725 out:
726 return fifo_len;
727 }
728
iwl_dump_paging(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** data)729 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt,
730 struct iwl_fw_error_dump_data **data)
731 {
732 int i;
733
734 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n");
735 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) {
736 struct iwl_fw_error_dump_paging *paging;
737 struct page *pages =
738 fwrt->fw_paging_db[i].fw_paging_block;
739 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys;
740
741 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
742 (*data)->len = cpu_to_le32(sizeof(*paging) +
743 PAGING_BLOCK_SIZE);
744 paging = (void *)(*data)->data;
745 paging->index = cpu_to_le32(i);
746 dma_sync_single_for_cpu(fwrt->trans->dev, addr,
747 PAGING_BLOCK_SIZE,
748 DMA_BIDIRECTIONAL);
749 memcpy(paging->data, page_address(pages),
750 PAGING_BLOCK_SIZE);
751 dma_sync_single_for_device(fwrt->trans->dev, addr,
752 PAGING_BLOCK_SIZE,
753 DMA_BIDIRECTIONAL);
754 (*data) = iwl_fw_error_next_data(*data);
755 }
756 }
757
758 static struct iwl_fw_error_dump_file *
iwl_fw_error_dump_file(struct iwl_fw_runtime * fwrt,struct iwl_fw_dump_ptrs * fw_error_dump,struct iwl_fwrt_dump_data * data)759 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt,
760 struct iwl_fw_dump_ptrs *fw_error_dump,
761 struct iwl_fwrt_dump_data *data)
762 {
763 struct iwl_fw_error_dump_file *dump_file;
764 struct iwl_fw_error_dump_data *dump_data;
765 struct iwl_fw_error_dump_info *dump_info;
766 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg;
767 struct iwl_fw_error_dump_trigger_desc *dump_trig;
768 u32 sram_len, sram_ofs;
769 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv;
770 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg;
771 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0;
772 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len;
773 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ?
774 0 : fwrt->trans->cfg->dccm2_len;
775 int i;
776
777 /* SRAM - include stack CCM if driver knows the values for it */
778 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) {
779 const struct fw_img *img;
780
781 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX)
782 return NULL;
783 img = &fwrt->fw->img[fwrt->cur_fw_img];
784 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset;
785 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len;
786 } else {
787 sram_ofs = fwrt->trans->cfg->dccm_offset;
788 sram_len = fwrt->trans->cfg->dccm_len;
789 }
790
791 /* reading RXF/TXF sizes */
792 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) {
793 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg);
794 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg);
795
796 /* Make room for PRPH registers */
797 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH))
798 iwl_fw_prph_handler(fwrt, &prph_len,
799 iwl_fw_get_prph_len);
800
801 if (fwrt->trans->trans_cfg->device_family ==
802 IWL_DEVICE_FAMILY_7000 &&
803 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG))
804 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ;
805 }
806
807 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len;
808
809 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO))
810 file_len += sizeof(*dump_data) + sizeof(*dump_info);
811 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG))
812 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg);
813
814 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
815 size_t hdr_len = sizeof(*dump_data) +
816 sizeof(struct iwl_fw_error_dump_mem);
817
818 /* Dump SRAM only if no mem_tlvs */
819 if (!fwrt->fw->dbg.n_mem_tlv)
820 ADD_LEN(file_len, sram_len, hdr_len);
821
822 /* Make room for all mem types that exist */
823 ADD_LEN(file_len, smem_len, hdr_len);
824 ADD_LEN(file_len, sram2_len, hdr_len);
825
826 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++)
827 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len);
828 }
829
830 /* Make room for fw's virtual image pages, if it exists */
831 if (iwl_fw_dbg_is_paging_enabled(fwrt))
832 file_len += fwrt->num_of_paging_blk *
833 (sizeof(*dump_data) +
834 sizeof(struct iwl_fw_error_dump_paging) +
835 PAGING_BLOCK_SIZE);
836
837 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
838 file_len += sizeof(*dump_data) +
839 fwrt->trans->cfg->d3_debug_data_length * 2;
840 }
841
842 /* If we only want a monitor dump, reset the file length */
843 if (data->monitor_only) {
844 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 +
845 sizeof(*dump_info) + sizeof(*dump_smem_cfg);
846 }
847
848 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
849 data->desc)
850 file_len += sizeof(*dump_data) + sizeof(*dump_trig) +
851 data->desc->len;
852
853 dump_file = vzalloc(file_len);
854 if (!dump_file)
855 return NULL;
856
857 fw_error_dump->fwrt_ptr = dump_file;
858
859 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
860 dump_data = (void *)dump_file->data;
861
862 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) {
863 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO);
864 dump_data->len = cpu_to_le32(sizeof(*dump_info));
865 dump_info = (void *)dump_data->data;
866 dump_info->hw_type =
867 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev));
868 dump_info->hw_step =
869 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev));
870 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable,
871 sizeof(dump_info->fw_human_readable));
872 strncpy(dump_info->dev_human_readable, fwrt->trans->name,
873 sizeof(dump_info->dev_human_readable) - 1);
874 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name,
875 sizeof(dump_info->bus_human_readable) - 1);
876 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs;
877 dump_info->lmac_err_id[0] =
878 cpu_to_le32(fwrt->dump.lmac_err_id[0]);
879 if (fwrt->smem_cfg.num_lmacs > 1)
880 dump_info->lmac_err_id[1] =
881 cpu_to_le32(fwrt->dump.lmac_err_id[1]);
882 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id);
883
884 dump_data = iwl_fw_error_next_data(dump_data);
885 }
886
887 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) {
888 /* Dump shared memory configuration */
889 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG);
890 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg));
891 dump_smem_cfg = (void *)dump_data->data;
892 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs);
893 dump_smem_cfg->num_txfifo_entries =
894 cpu_to_le32(mem_cfg->num_txfifo_entries);
895 for (i = 0; i < MAX_NUM_LMAC; i++) {
896 int j;
897 u32 *txf_size = mem_cfg->lmac[i].txfifo_size;
898
899 for (j = 0; j < TX_FIFO_MAX_NUM; j++)
900 dump_smem_cfg->lmac[i].txfifo_size[j] =
901 cpu_to_le32(txf_size[j]);
902 dump_smem_cfg->lmac[i].rxfifo1_size =
903 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size);
904 }
905 dump_smem_cfg->rxfifo2_size =
906 cpu_to_le32(mem_cfg->rxfifo2_size);
907 dump_smem_cfg->internal_txfifo_addr =
908 cpu_to_le32(mem_cfg->internal_txfifo_addr);
909 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) {
910 dump_smem_cfg->internal_txfifo_size[i] =
911 cpu_to_le32(mem_cfg->internal_txfifo_size[i]);
912 }
913
914 dump_data = iwl_fw_error_next_data(dump_data);
915 }
916
917 /* We only dump the FIFOs if the FW is in error state */
918 if (fifo_len) {
919 iwl_fw_dump_rxf(fwrt, &dump_data);
920 iwl_fw_dump_txf(fwrt, &dump_data);
921 }
922
923 if (radio_len)
924 iwl_read_radio_regs(fwrt, &dump_data);
925
926 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
927 data->desc) {
928 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO);
929 dump_data->len = cpu_to_le32(sizeof(*dump_trig) +
930 data->desc->len);
931 dump_trig = (void *)dump_data->data;
932 memcpy(dump_trig, &data->desc->trig_desc,
933 sizeof(*dump_trig) + data->desc->len);
934
935 dump_data = iwl_fw_error_next_data(dump_data);
936 }
937
938 /* In case we only want monitor dump, skip to dump trasport data */
939 if (data->monitor_only)
940 goto out;
941
942 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
943 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem =
944 fwrt->fw->dbg.mem_tlv;
945
946 if (!fwrt->fw->dbg.n_mem_tlv)
947 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs,
948 IWL_FW_ERROR_DUMP_MEM_SRAM);
949
950 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) {
951 u32 len = le32_to_cpu(fw_dbg_mem[i].len);
952 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs);
953
954 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs,
955 le32_to_cpu(fw_dbg_mem[i].data_type));
956 }
957
958 iwl_fw_dump_mem(fwrt, &dump_data, smem_len,
959 fwrt->trans->cfg->smem_offset,
960 IWL_FW_ERROR_DUMP_MEM_SMEM);
961
962 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len,
963 fwrt->trans->cfg->dccm2_offset,
964 IWL_FW_ERROR_DUMP_MEM_SRAM);
965 }
966
967 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
968 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr;
969 size_t data_size = fwrt->trans->cfg->d3_debug_data_length;
970
971 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA);
972 dump_data->len = cpu_to_le32(data_size * 2);
973
974 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size);
975
976 kfree(fwrt->dump.d3_debug_data);
977 fwrt->dump.d3_debug_data = NULL;
978
979 iwl_trans_read_mem_bytes(fwrt->trans, addr,
980 dump_data->data + data_size,
981 data_size);
982
983 dump_data = iwl_fw_error_next_data(dump_data);
984 }
985
986 /* Dump fw's virtual image */
987 if (iwl_fw_dbg_is_paging_enabled(fwrt))
988 iwl_dump_paging(fwrt, &dump_data);
989
990 if (prph_len)
991 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph);
992
993 out:
994 dump_file->file_len = cpu_to_le32(file_len);
995 return dump_file;
996 }
997
998 /**
999 * struct iwl_dump_ini_region_data - region data
1000 * @reg_tlv: region TLV
1001 * @dump_data: dump data
1002 */
1003 struct iwl_dump_ini_region_data {
1004 struct iwl_ucode_tlv *reg_tlv;
1005 struct iwl_fwrt_dump_data *dump_data;
1006 };
1007
1008 static int
iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1009 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt,
1010 struct iwl_dump_ini_region_data *reg_data,
1011 void *range_ptr, int idx)
1012 {
1013 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1014 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1015 __le32 *val = range->data;
1016 u32 prph_val;
1017 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1018 le32_to_cpu(reg->dev_addr.offset);
1019 int i;
1020
1021 range->internal_base_addr = cpu_to_le32(addr);
1022 range->range_data_size = reg->dev_addr.size;
1023 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1024 prph_val = iwl_read_prph(fwrt->trans, addr + i);
1025 if ((prph_val & ~0xf) == 0xa5a5a5a0)
1026 return -EBUSY;
1027 *val++ = cpu_to_le32(prph_val);
1028 }
1029
1030 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1031 }
1032
1033 static int
iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1034 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt,
1035 struct iwl_dump_ini_region_data *reg_data,
1036 void *range_ptr, int idx)
1037 {
1038 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1039 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1040 __le32 *val = range->data;
1041 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1;
1042 u32 indirect_rd_addr = WMAL_MRSPF_1;
1043 u32 prph_val;
1044 u32 addr = le32_to_cpu(reg->addrs[idx]);
1045 u32 dphy_state;
1046 u32 dphy_addr;
1047 int i;
1048
1049 range->internal_base_addr = cpu_to_le32(addr);
1050 range->range_data_size = reg->dev_addr.size;
1051
1052 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
1053 indirect_wr_addr = WMAL_INDRCT_CMD1;
1054
1055 indirect_wr_addr += le32_to_cpu(reg->dev_addr.offset);
1056 indirect_rd_addr += le32_to_cpu(reg->dev_addr.offset);
1057
1058 if (!iwl_trans_grab_nic_access(fwrt->trans))
1059 return -EBUSY;
1060
1061 dphy_addr = (reg->dev_addr.offset) ? WFPM_LMAC2_PS_CTL_RW :
1062 WFPM_LMAC1_PS_CTL_RW;
1063 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr);
1064
1065 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1066 if (dphy_state == HBUS_TIMEOUT ||
1067 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) !=
1068 WFPM_PHYRF_STATE_ON) {
1069 *val++ = cpu_to_le32(WFPM_DPHY_OFF);
1070 continue;
1071 }
1072
1073 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr,
1074 WMAL_INDRCT_CMD(addr + i));
1075 prph_val = iwl_read_prph_no_grab(fwrt->trans,
1076 indirect_rd_addr);
1077 *val++ = cpu_to_le32(prph_val);
1078 }
1079
1080 iwl_trans_release_nic_access(fwrt->trans);
1081 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1082 }
1083
iwl_dump_ini_csr_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1084 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt,
1085 struct iwl_dump_ini_region_data *reg_data,
1086 void *range_ptr, int idx)
1087 {
1088 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1089 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1090 __le32 *val = range->data;
1091 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1092 le32_to_cpu(reg->dev_addr.offset);
1093 int i;
1094
1095 range->internal_base_addr = cpu_to_le32(addr);
1096 range->range_data_size = reg->dev_addr.size;
1097 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4)
1098 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i));
1099
1100 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1101 }
1102
iwl_dump_ini_config_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1103 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt,
1104 struct iwl_dump_ini_region_data *reg_data,
1105 void *range_ptr, int idx)
1106 {
1107 struct iwl_trans *trans = fwrt->trans;
1108 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1109 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1110 __le32 *val = range->data;
1111 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1112 le32_to_cpu(reg->dev_addr.offset);
1113 int i;
1114
1115 /* we shouldn't get here if the trans doesn't have read_config32 */
1116 if (WARN_ON_ONCE(!trans->ops->read_config32))
1117 return -EOPNOTSUPP;
1118
1119 range->internal_base_addr = cpu_to_le32(addr);
1120 range->range_data_size = reg->dev_addr.size;
1121 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1122 int ret;
1123 u32 tmp;
1124
1125 ret = trans->ops->read_config32(trans, addr + i, &tmp);
1126 if (ret < 0)
1127 return ret;
1128
1129 *val++ = cpu_to_le32(tmp);
1130 }
1131
1132 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1133 }
1134
iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1135 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt,
1136 struct iwl_dump_ini_region_data *reg_data,
1137 void *range_ptr, int idx)
1138 {
1139 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1140 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1141 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1142 le32_to_cpu(reg->dev_addr.offset);
1143
1144 range->internal_base_addr = cpu_to_le32(addr);
1145 range->range_data_size = reg->dev_addr.size;
1146 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1147 le32_to_cpu(reg->dev_addr.size));
1148
1149 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1150 }
1151
_iwl_dump_ini_paging_iter(struct iwl_fw_runtime * fwrt,void * range_ptr,int idx)1152 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt,
1153 void *range_ptr, int idx)
1154 {
1155 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block;
1156 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1157 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys;
1158 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size;
1159
1160 range->page_num = cpu_to_le32(idx);
1161 range->range_data_size = cpu_to_le32(page_size);
1162 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size,
1163 DMA_BIDIRECTIONAL);
1164 memcpy(range->data, page_address(page), page_size);
1165 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size,
1166 DMA_BIDIRECTIONAL);
1167
1168 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1169 }
1170
iwl_dump_ini_paging_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1171 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt,
1172 struct iwl_dump_ini_region_data *reg_data,
1173 void *range_ptr, int idx)
1174 {
1175 struct iwl_fw_ini_error_dump_range *range;
1176 u32 page_size;
1177
1178 /* all paged index start from 1 to skip CSS section */
1179 idx++;
1180
1181 if (!fwrt->trans->trans_cfg->gen2)
1182 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, idx);
1183
1184 range = range_ptr;
1185 page_size = fwrt->trans->init_dram.paging[idx].size;
1186
1187 range->page_num = cpu_to_le32(idx);
1188 range->range_data_size = cpu_to_le32(page_size);
1189 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block,
1190 page_size);
1191
1192 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1193 }
1194
1195 static int
iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1196 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt,
1197 struct iwl_dump_ini_region_data *reg_data,
1198 void *range_ptr, int idx)
1199 {
1200 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1201 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1202 struct iwl_dram_data *frag;
1203 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
1204
1205 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx];
1206
1207 range->dram_base_addr = cpu_to_le64(frag->physical);
1208 range->range_data_size = cpu_to_le32(frag->size);
1209
1210 memcpy(range->data, frag->block, frag->size);
1211
1212 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1213 }
1214
iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1215 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt,
1216 struct iwl_dump_ini_region_data *reg_data,
1217 void *range_ptr, int idx)
1218 {
1219 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1220 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1221 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr);
1222
1223 range->internal_base_addr = cpu_to_le32(addr);
1224 range->range_data_size = reg->internal_buffer.size;
1225 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1226 le32_to_cpu(reg->internal_buffer.size));
1227
1228 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1229 }
1230
iwl_ini_txf_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,int idx)1231 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1232 struct iwl_dump_ini_region_data *reg_data, int idx)
1233 {
1234 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1235 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1236 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
1237 int txf_num = cfg->num_txfifo_entries;
1238 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size);
1239 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]);
1240
1241 if (!idx) {
1242 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) {
1243 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n",
1244 le32_to_cpu(reg->fifos.offset));
1245 return false;
1246 }
1247
1248 iter->internal_txf = 0;
1249 iter->fifo_size = 0;
1250 iter->fifo = -1;
1251 if (le32_to_cpu(reg->fifos.offset))
1252 iter->lmac = 1;
1253 else
1254 iter->lmac = 0;
1255 }
1256
1257 if (!iter->internal_txf) {
1258 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) {
1259 iter->fifo_size =
1260 cfg->lmac[iter->lmac].txfifo_size[iter->fifo];
1261 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1262 return true;
1263 }
1264 iter->fifo--;
1265 }
1266
1267 iter->internal_txf = 1;
1268
1269 if (!fw_has_capa(&fwrt->fw->ucode_capa,
1270 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))
1271 return false;
1272
1273 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) {
1274 iter->fifo_size =
1275 cfg->internal_txfifo_size[iter->fifo - txf_num];
1276 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1277 return true;
1278 }
1279
1280 return false;
1281 }
1282
iwl_dump_ini_txf_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1283 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1284 struct iwl_dump_ini_region_data *reg_data,
1285 void *range_ptr, int idx)
1286 {
1287 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1288 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1289 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1290 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1291 u32 offs = le32_to_cpu(reg->fifos.offset), addr;
1292 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1293 u32 registers_size = registers_num * sizeof(*reg_dump);
1294 __le32 *data;
1295 int i;
1296
1297 if (!iwl_ini_txf_iter(fwrt, reg_data, idx))
1298 return -EIO;
1299
1300 if (!iwl_trans_grab_nic_access(fwrt->trans))
1301 return -EBUSY;
1302
1303 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo);
1304 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num);
1305 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size);
1306
1307 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo);
1308
1309 /*
1310 * read txf registers. for each register, write to the dump the
1311 * register address and its value
1312 */
1313 for (i = 0; i < registers_num; i++) {
1314 addr = le32_to_cpu(reg->addrs[i]) + offs;
1315
1316 reg_dump->addr = cpu_to_le32(addr);
1317 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1318 addr));
1319
1320 reg_dump++;
1321 }
1322
1323 if (reg->fifos.hdr_only) {
1324 range->range_data_size = cpu_to_le32(registers_size);
1325 goto out;
1326 }
1327
1328 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
1329 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs,
1330 TXF_WR_PTR + offs);
1331
1332 /* Dummy-read to advance the read pointer to the head */
1333 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs);
1334
1335 /* Read FIFO */
1336 addr = TXF_READ_MODIFY_DATA + offs;
1337 data = (void *)reg_dump;
1338 for (i = 0; i < iter->fifo_size; i += sizeof(*data))
1339 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1340
1341 out:
1342 iwl_trans_release_nic_access(fwrt->trans);
1343
1344 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1345 }
1346
1347 struct iwl_ini_rxf_data {
1348 u32 fifo_num;
1349 u32 size;
1350 u32 offset;
1351 };
1352
iwl_ini_get_rxf_data(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,struct iwl_ini_rxf_data * data)1353 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt,
1354 struct iwl_dump_ini_region_data *reg_data,
1355 struct iwl_ini_rxf_data *data)
1356 {
1357 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1358 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]);
1359 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]);
1360 u8 fifo_idx;
1361
1362 if (!data)
1363 return;
1364
1365 memset(data, 0, sizeof(*data));
1366
1367 /* make sure only one bit is set in only one fid */
1368 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1,
1369 "fid1=%x, fid2=%x\n", fid1, fid2))
1370 return;
1371
1372 if (fid1) {
1373 fifo_idx = ffs(fid1) - 1;
1374 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n",
1375 fifo_idx))
1376 return;
1377
1378 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size;
1379 data->fifo_num = fifo_idx;
1380 } else {
1381 u8 max_idx;
1382
1383 fifo_idx = ffs(fid2) - 1;
1384 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP,
1385 SHARED_MEM_CFG_CMD, 0) <= 3)
1386 max_idx = 0;
1387 else
1388 max_idx = 1;
1389
1390 if (WARN_ONCE(fifo_idx > max_idx,
1391 "invalid umac fifo idx %d", fifo_idx))
1392 return;
1393
1394 /* use bit 31 to distinguish between umac and lmac rxf while
1395 * parsing the dump
1396 */
1397 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT;
1398
1399 switch (fifo_idx) {
1400 case 0:
1401 data->size = fwrt->smem_cfg.rxfifo2_size;
1402 data->offset = iwl_umac_prph(fwrt->trans,
1403 RXF_DIFF_FROM_PREV);
1404 break;
1405 case 1:
1406 data->size = fwrt->smem_cfg.rxfifo2_control_size;
1407 data->offset = iwl_umac_prph(fwrt->trans,
1408 RXF2C_DIFF_FROM_PREV);
1409 break;
1410 }
1411 }
1412 }
1413
iwl_dump_ini_rxf_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1414 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,
1415 struct iwl_dump_ini_region_data *reg_data,
1416 void *range_ptr, int idx)
1417 {
1418 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1419 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1420 struct iwl_ini_rxf_data rxf_data;
1421 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1422 u32 offs = le32_to_cpu(reg->fifos.offset), addr;
1423 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1424 u32 registers_size = registers_num * sizeof(*reg_dump);
1425 __le32 *data;
1426 int i;
1427
1428 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data);
1429 if (!rxf_data.size)
1430 return -EIO;
1431
1432 if (!iwl_trans_grab_nic_access(fwrt->trans))
1433 return -EBUSY;
1434
1435 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num);
1436 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num);
1437 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size);
1438
1439 /*
1440 * read rxf registers. for each register, write to the dump the
1441 * register address and its value
1442 */
1443 for (i = 0; i < registers_num; i++) {
1444 addr = le32_to_cpu(reg->addrs[i]) + offs;
1445
1446 reg_dump->addr = cpu_to_le32(addr);
1447 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1448 addr));
1449
1450 reg_dump++;
1451 }
1452
1453 if (reg->fifos.hdr_only) {
1454 range->range_data_size = cpu_to_le32(registers_size);
1455 goto out;
1456 }
1457
1458 offs = rxf_data.offset;
1459
1460 /* Lock fence */
1461 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1);
1462 /* Set fence pointer to the same place like WR pointer */
1463 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1);
1464 /* Set fence offset */
1465 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs,
1466 0x0);
1467
1468 /* Read FIFO */
1469 addr = RXF_FIFO_RD_FENCE_INC + offs;
1470 data = (void *)reg_dump;
1471 for (i = 0; i < rxf_data.size; i += sizeof(*data))
1472 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1473
1474 out:
1475 iwl_trans_release_nic_access(fwrt->trans);
1476
1477 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1478 }
1479
1480 static int
iwl_dump_ini_err_table_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1481 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt,
1482 struct iwl_dump_ini_region_data *reg_data,
1483 void *range_ptr, int idx)
1484 {
1485 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1486 struct iwl_fw_ini_region_err_table *err_table = ®->err_table;
1487 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1488 u32 addr = le32_to_cpu(err_table->base_addr) +
1489 le32_to_cpu(err_table->offset);
1490
1491 range->internal_base_addr = cpu_to_le32(addr);
1492 range->range_data_size = err_table->size;
1493 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1494 le32_to_cpu(err_table->size));
1495
1496 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1497 }
1498
1499 static int
iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1500 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt,
1501 struct iwl_dump_ini_region_data *reg_data,
1502 void *range_ptr, int idx)
1503 {
1504 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1505 struct iwl_fw_ini_region_special_device_memory *special_mem =
1506 ®->special_mem;
1507
1508 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1509 u32 addr = le32_to_cpu(special_mem->base_addr) +
1510 le32_to_cpu(special_mem->offset);
1511
1512 range->internal_base_addr = cpu_to_le32(addr);
1513 range->range_data_size = special_mem->size;
1514 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1515 le32_to_cpu(special_mem->size));
1516
1517 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1518 }
1519
1520 static int
iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1521 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt,
1522 struct iwl_dump_ini_region_data *reg_data,
1523 void *range_ptr, int idx)
1524 {
1525 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1526 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1527 __le32 *val = range->data;
1528 u32 prph_data;
1529 int i;
1530
1531 if (!iwl_trans_grab_nic_access(fwrt->trans))
1532 return -EBUSY;
1533
1534 range->range_data_size = reg->dev_addr.size;
1535 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) {
1536 prph_data = iwl_read_prph(fwrt->trans, (i % 2) ?
1537 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB :
1538 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB);
1539 if ((prph_data & ~0xf) == 0xa5a5a5a0) {
1540 iwl_trans_release_nic_access(fwrt->trans);
1541 return -EBUSY;
1542 }
1543 *val++ = cpu_to_le32(prph_data);
1544 }
1545 iwl_trans_release_nic_access(fwrt->trans);
1546 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1547 }
1548
iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,int idx)1549 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt,
1550 struct iwl_dump_ini_region_data *reg_data,
1551 void *range_ptr, int idx)
1552 {
1553 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1554 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt;
1555 u32 pkt_len;
1556
1557 if (!pkt)
1558 return -EIO;
1559
1560 pkt_len = iwl_rx_packet_payload_len(pkt);
1561
1562 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr));
1563 range->range_data_size = cpu_to_le32(pkt_len);
1564
1565 memcpy(range->data, pkt->data, pkt_len);
1566
1567 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1568 }
1569
1570 static void *
iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data)1571 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt,
1572 struct iwl_dump_ini_region_data *reg_data,
1573 void *data)
1574 {
1575 struct iwl_fw_ini_error_dump *dump = data;
1576
1577 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1578
1579 return dump->data;
1580 }
1581
1582 /**
1583 * mask_apply_and_normalize - applies mask on val and normalize the result
1584 *
1585 * The normalization is based on the first set bit in the mask
1586 *
1587 * @val: value
1588 * @mask: mask to apply and to normalize with
1589 */
mask_apply_and_normalize(u32 val,u32 mask)1590 static u32 mask_apply_and_normalize(u32 val, u32 mask)
1591 {
1592 return (val & mask) >> (ffs(mask) - 1);
1593 }
1594
iwl_get_mon_reg(struct iwl_fw_runtime * fwrt,u32 alloc_id,const struct iwl_fw_mon_reg * reg_info)1595 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id,
1596 const struct iwl_fw_mon_reg *reg_info)
1597 {
1598 u32 val, offs;
1599
1600 /* The header addresses of DBGCi is calculate as follows:
1601 * DBGC1 address + (0x100 * i)
1602 */
1603 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100;
1604
1605 if (!reg_info || !reg_info->addr || !reg_info->mask)
1606 return 0;
1607
1608 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs);
1609
1610 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask));
1611 }
1612
1613 static void *
iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,struct iwl_fw_ini_monitor_dump * data,const struct iwl_fw_mon_regs * addrs)1614 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt,
1615 struct iwl_dump_ini_region_data *reg_data,
1616 struct iwl_fw_ini_monitor_dump *data,
1617 const struct iwl_fw_mon_regs *addrs)
1618 {
1619 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1620 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
1621
1622 if (!iwl_trans_grab_nic_access(fwrt->trans)) {
1623 IWL_ERR(fwrt, "Failed to get monitor header\n");
1624 return NULL;
1625 }
1626
1627 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id,
1628 &addrs->write_ptr);
1629 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1630 u32 wrt_ptr = le32_to_cpu(data->write_ptr);
1631
1632 data->write_ptr = cpu_to_le32(wrt_ptr >> 2);
1633 }
1634 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id,
1635 &addrs->cycle_cnt);
1636 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id,
1637 &addrs->cur_frag);
1638
1639 iwl_trans_release_nic_access(fwrt->trans);
1640
1641 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1642
1643 return data->data;
1644 }
1645
1646 static void *
iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data)1647 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt,
1648 struct iwl_dump_ini_region_data *reg_data,
1649 void *data)
1650 {
1651 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1652
1653 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump,
1654 &fwrt->trans->cfg->mon_dram_regs);
1655 }
1656
1657 static void *
iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data)1658 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt,
1659 struct iwl_dump_ini_region_data *reg_data,
1660 void *data)
1661 {
1662 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1663
1664 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump,
1665 &fwrt->trans->cfg->mon_smem_regs);
1666 }
1667
1668 static void *
iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data)1669 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt,
1670 struct iwl_dump_ini_region_data *reg_data,
1671 void *data)
1672 {
1673 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1674 struct iwl_fw_ini_err_table_dump *dump = data;
1675
1676 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1677 dump->version = reg->err_table.version;
1678
1679 return dump->data;
1680 }
1681
1682 static void *
iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data)1683 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt,
1684 struct iwl_dump_ini_region_data *reg_data,
1685 void *data)
1686 {
1687 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1688 struct iwl_fw_ini_special_device_memory *dump = data;
1689
1690 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1691 dump->type = reg->special_mem.type;
1692 dump->version = reg->special_mem.version;
1693
1694 return dump->data;
1695 }
1696
iwl_dump_ini_mem_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1697 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt,
1698 struct iwl_dump_ini_region_data *reg_data)
1699 {
1700 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1701
1702 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1703 }
1704
iwl_dump_ini_paging_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1705 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt,
1706 struct iwl_dump_ini_region_data *reg_data)
1707 {
1708 if (fwrt->trans->trans_cfg->gen2) {
1709 if (fwrt->trans->init_dram.paging_cnt)
1710 return fwrt->trans->init_dram.paging_cnt - 1;
1711 else
1712 return 0;
1713 }
1714
1715 return fwrt->num_of_paging_blk;
1716 }
1717
1718 static u32
iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1719 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt,
1720 struct iwl_dump_ini_region_data *reg_data)
1721 {
1722 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1723 struct iwl_fw_mon *fw_mon;
1724 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
1725 int i;
1726
1727 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
1728
1729 for (i = 0; i < fw_mon->num_frags; i++) {
1730 if (!fw_mon->frags[i].size)
1731 break;
1732
1733 ranges++;
1734 }
1735
1736 return ranges;
1737 }
1738
iwl_dump_ini_txf_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1739 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt,
1740 struct iwl_dump_ini_region_data *reg_data)
1741 {
1742 u32 num_of_fifos = 0;
1743
1744 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos))
1745 num_of_fifos++;
1746
1747 return num_of_fifos;
1748 }
1749
iwl_dump_ini_single_range(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1750 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt,
1751 struct iwl_dump_ini_region_data *reg_data)
1752 {
1753 return 1;
1754 }
1755
iwl_dump_ini_mem_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1756 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt,
1757 struct iwl_dump_ini_region_data *reg_data)
1758 {
1759 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1760 u32 size = le32_to_cpu(reg->dev_addr.size);
1761 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data);
1762
1763 if (!size || !ranges)
1764 return 0;
1765
1766 return sizeof(struct iwl_fw_ini_error_dump) + ranges *
1767 (size + sizeof(struct iwl_fw_ini_error_dump_range));
1768 }
1769
1770 static u32
iwl_dump_ini_paging_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1771 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt,
1772 struct iwl_dump_ini_region_data *reg_data)
1773 {
1774 int i;
1775 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range);
1776 u32 size = sizeof(struct iwl_fw_ini_error_dump);
1777
1778 /* start from 1 to skip CSS section */
1779 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) {
1780 size += range_header_len;
1781 if (fwrt->trans->trans_cfg->gen2)
1782 size += fwrt->trans->init_dram.paging[i].size;
1783 else
1784 size += fwrt->fw_paging_db[i].fw_paging_size;
1785 }
1786
1787 return size;
1788 }
1789
1790 static u32
iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1791 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt,
1792 struct iwl_dump_ini_region_data *reg_data)
1793 {
1794 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1795 struct iwl_fw_mon *fw_mon;
1796 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
1797 int i;
1798
1799 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
1800
1801 for (i = 0; i < fw_mon->num_frags; i++) {
1802 struct iwl_dram_data *frag = &fw_mon->frags[i];
1803
1804 if (!frag->size)
1805 break;
1806
1807 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size;
1808 }
1809
1810 if (size)
1811 size += sizeof(struct iwl_fw_ini_monitor_dump);
1812
1813 return size;
1814 }
1815
1816 static u32
iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1817 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt,
1818 struct iwl_dump_ini_region_data *reg_data)
1819 {
1820 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1821 u32 size;
1822
1823 size = le32_to_cpu(reg->internal_buffer.size);
1824 if (!size)
1825 return 0;
1826
1827 size += sizeof(struct iwl_fw_ini_monitor_dump) +
1828 sizeof(struct iwl_fw_ini_error_dump_range);
1829
1830 return size;
1831 }
1832
iwl_dump_ini_txf_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1833 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt,
1834 struct iwl_dump_ini_region_data *reg_data)
1835 {
1836 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1837 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1838 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1839 u32 size = 0;
1840 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) +
1841 registers_num *
1842 sizeof(struct iwl_fw_ini_error_dump_register);
1843
1844 while (iwl_ini_txf_iter(fwrt, reg_data, size)) {
1845 size += fifo_hdr;
1846 if (!reg->fifos.hdr_only)
1847 size += iter->fifo_size;
1848 }
1849
1850 if (!size)
1851 return 0;
1852
1853 return size + sizeof(struct iwl_fw_ini_error_dump);
1854 }
1855
iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1856 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt,
1857 struct iwl_dump_ini_region_data *reg_data)
1858 {
1859 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1860 struct iwl_ini_rxf_data rx_data;
1861 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1862 u32 size = sizeof(struct iwl_fw_ini_error_dump) +
1863 sizeof(struct iwl_fw_ini_error_dump_range) +
1864 registers_num * sizeof(struct iwl_fw_ini_error_dump_register);
1865
1866 if (reg->fifos.hdr_only)
1867 return size;
1868
1869 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data);
1870 size += rx_data.size;
1871
1872 return size;
1873 }
1874
1875 static u32
iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1876 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt,
1877 struct iwl_dump_ini_region_data *reg_data)
1878 {
1879 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1880 u32 size = le32_to_cpu(reg->err_table.size);
1881
1882 if (size)
1883 size += sizeof(struct iwl_fw_ini_err_table_dump) +
1884 sizeof(struct iwl_fw_ini_error_dump_range);
1885
1886 return size;
1887 }
1888
1889 static u32
iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1890 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt,
1891 struct iwl_dump_ini_region_data *reg_data)
1892 {
1893 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1894 u32 size = le32_to_cpu(reg->special_mem.size);
1895
1896 if (size)
1897 size += sizeof(struct iwl_fw_ini_special_device_memory) +
1898 sizeof(struct iwl_fw_ini_error_dump_range);
1899
1900 return size;
1901 }
1902
1903 static u32
iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1904 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt,
1905 struct iwl_dump_ini_region_data *reg_data)
1906 {
1907 u32 size = 0;
1908
1909 if (!reg_data->dump_data->fw_pkt)
1910 return 0;
1911
1912 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt);
1913 if (size)
1914 size += sizeof(struct iwl_fw_ini_error_dump) +
1915 sizeof(struct iwl_fw_ini_error_dump_range);
1916
1917 return size;
1918 }
1919
1920 /**
1921 * struct iwl_dump_ini_mem_ops - ini memory dump operations
1922 * @get_num_of_ranges: returns the number of memory ranges in the region.
1923 * @get_size: returns the total size of the region.
1924 * @fill_mem_hdr: fills region type specific headers and returns pointer to
1925 * the first range or NULL if failed to fill headers.
1926 * @fill_range: copies a given memory range into the dump.
1927 * Returns the size of the range or negative error value otherwise.
1928 */
1929 struct iwl_dump_ini_mem_ops {
1930 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt,
1931 struct iwl_dump_ini_region_data *reg_data);
1932 u32 (*get_size)(struct iwl_fw_runtime *fwrt,
1933 struct iwl_dump_ini_region_data *reg_data);
1934 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt,
1935 struct iwl_dump_ini_region_data *reg_data,
1936 void *data);
1937 int (*fill_range)(struct iwl_fw_runtime *fwrt,
1938 struct iwl_dump_ini_region_data *reg_data,
1939 void *range, int idx);
1940 };
1941
1942 /**
1943 * iwl_dump_ini_mem
1944 *
1945 * Creates a dump tlv and copy a memory region into it.
1946 * Returns the size of the current dump tlv or 0 if failed
1947 *
1948 * @fwrt: fw runtime struct
1949 * @list: list to add the dump tlv to
1950 * @reg_data: memory region
1951 * @ops: memory dump operations
1952 */
iwl_dump_ini_mem(struct iwl_fw_runtime * fwrt,struct list_head * list,struct iwl_dump_ini_region_data * reg_data,const struct iwl_dump_ini_mem_ops * ops)1953 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list,
1954 struct iwl_dump_ini_region_data *reg_data,
1955 const struct iwl_dump_ini_mem_ops *ops)
1956 {
1957 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1958 struct iwl_fw_ini_dump_entry *entry;
1959 struct iwl_fw_error_dump_data *tlv;
1960 struct iwl_fw_ini_error_dump_header *header;
1961 u32 type = le32_to_cpu(reg->type), id = le32_to_cpu(reg->id);
1962 u32 num_of_ranges, i, size;
1963 u8 *range;
1964
1965 /*
1966 * The higher part of the ID in version 2 is irrelevant for
1967 * us, so mask it out.
1968 */
1969 if (le32_to_cpu(reg->hdr.version) == 2)
1970 id &= IWL_FW_INI_REGION_V2_MASK;
1971
1972 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr ||
1973 !ops->fill_range)
1974 return 0;
1975
1976 size = ops->get_size(fwrt, reg_data);
1977 if (!size)
1978 return 0;
1979
1980 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size);
1981 if (!entry)
1982 return 0;
1983
1984 entry->size = sizeof(*tlv) + size;
1985
1986 tlv = (void *)entry->data;
1987 tlv->type = reg->type;
1988 tlv->len = cpu_to_le32(size);
1989
1990 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: id=%d, type=%d\n", id,
1991 type);
1992
1993 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data);
1994
1995 header = (void *)tlv->data;
1996 header->region_id = cpu_to_le32(id);
1997 header->num_of_ranges = cpu_to_le32(num_of_ranges);
1998 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME);
1999 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME);
2000
2001 range = ops->fill_mem_hdr(fwrt, reg_data, header);
2002 if (!range) {
2003 IWL_ERR(fwrt,
2004 "WRT: Failed to fill region header: id=%d, type=%d\n",
2005 id, type);
2006 goto out_err;
2007 }
2008
2009 for (i = 0; i < num_of_ranges; i++) {
2010 int range_size = ops->fill_range(fwrt, reg_data, range, i);
2011
2012 if (range_size < 0) {
2013 IWL_ERR(fwrt,
2014 "WRT: Failed to dump region: id=%d, type=%d\n",
2015 id, type);
2016 goto out_err;
2017 }
2018 range = range + range_size;
2019 }
2020
2021 list_add_tail(&entry->list, list);
2022
2023 return entry->size;
2024
2025 out_err:
2026 vfree(entry);
2027
2028 return 0;
2029 }
2030
iwl_dump_ini_info(struct iwl_fw_runtime * fwrt,struct iwl_fw_ini_trigger_tlv * trigger,struct list_head * list)2031 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt,
2032 struct iwl_fw_ini_trigger_tlv *trigger,
2033 struct list_head *list)
2034 {
2035 struct iwl_fw_ini_dump_entry *entry;
2036 struct iwl_fw_error_dump_data *tlv;
2037 struct iwl_fw_ini_dump_info *dump;
2038 struct iwl_dbg_tlv_node *node;
2039 struct iwl_fw_ini_dump_cfg_name *cfg_name;
2040 u32 size = sizeof(*tlv) + sizeof(*dump);
2041 u32 num_of_cfg_names = 0;
2042 u32 hw_type;
2043
2044 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) {
2045 size += sizeof(*cfg_name);
2046 num_of_cfg_names++;
2047 }
2048
2049 entry = vzalloc(sizeof(*entry) + size);
2050 if (!entry)
2051 return 0;
2052
2053 entry->size = size;
2054
2055 tlv = (void *)entry->data;
2056 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE);
2057 tlv->len = cpu_to_le32(size - sizeof(*tlv));
2058
2059 dump = (void *)tlv->data;
2060
2061 dump->version = cpu_to_le32(IWL_INI_DUMP_VER);
2062 dump->time_point = trigger->time_point;
2063 dump->trigger_reason = trigger->trigger_reason;
2064 dump->external_cfg_state =
2065 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg);
2066
2067 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type);
2068 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype);
2069
2070 dump->hw_step = cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev));
2071
2072 /*
2073 * Several HWs all have type == 0x42, so we'll override this value
2074 * according to the detected HW
2075 */
2076 hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev);
2077 if (hw_type == IWL_AX210_HW_TYPE) {
2078 u32 prph_val = iwl_read_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR);
2079 u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT);
2080 u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT);
2081 u32 masked_bits = is_jacket | (is_cdb << 1);
2082
2083 /*
2084 * The HW type depends on certain bits in this case, so add
2085 * these bits to the HW type. We won't have collisions since we
2086 * add these bits after the highest possible bit in the mask.
2087 */
2088 hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT;
2089 }
2090 dump->hw_type = cpu_to_le32(hw_type);
2091
2092 dump->rf_id_flavor =
2093 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id));
2094 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id));
2095 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id));
2096 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id));
2097
2098 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major);
2099 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor);
2100 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major);
2101 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor);
2102
2103 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest);
2104 dump->regions_mask = trigger->regions_mask &
2105 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk);
2106
2107 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag));
2108 memcpy(dump->build_tag, fwrt->fw->human_readable,
2109 sizeof(dump->build_tag));
2110
2111 cfg_name = dump->cfg_names;
2112 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names);
2113 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) {
2114 struct iwl_fw_ini_debug_info_tlv *debug_info =
2115 (void *)node->tlv.data;
2116
2117 cfg_name->image_type = debug_info->image_type;
2118 cfg_name->cfg_name_len =
2119 cpu_to_le32(IWL_FW_INI_MAX_CFG_NAME);
2120 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name,
2121 sizeof(cfg_name->cfg_name));
2122 cfg_name++;
2123 }
2124
2125 /* add dump info TLV to the beginning of the list since it needs to be
2126 * the first TLV in the dump
2127 */
2128 list_add(&entry->list, list);
2129
2130 return entry->size;
2131 }
2132
2133 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = {
2134 [IWL_FW_INI_REGION_INVALID] = {},
2135 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = {
2136 .get_num_of_ranges = iwl_dump_ini_single_range,
2137 .get_size = iwl_dump_ini_mon_smem_get_size,
2138 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header,
2139 .fill_range = iwl_dump_ini_mon_smem_iter,
2140 },
2141 [IWL_FW_INI_REGION_DRAM_BUFFER] = {
2142 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges,
2143 .get_size = iwl_dump_ini_mon_dram_get_size,
2144 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header,
2145 .fill_range = iwl_dump_ini_mon_dram_iter,
2146 },
2147 [IWL_FW_INI_REGION_TXF] = {
2148 .get_num_of_ranges = iwl_dump_ini_txf_ranges,
2149 .get_size = iwl_dump_ini_txf_get_size,
2150 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2151 .fill_range = iwl_dump_ini_txf_iter,
2152 },
2153 [IWL_FW_INI_REGION_RXF] = {
2154 .get_num_of_ranges = iwl_dump_ini_single_range,
2155 .get_size = iwl_dump_ini_rxf_get_size,
2156 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2157 .fill_range = iwl_dump_ini_rxf_iter,
2158 },
2159 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = {
2160 .get_num_of_ranges = iwl_dump_ini_single_range,
2161 .get_size = iwl_dump_ini_err_table_get_size,
2162 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header,
2163 .fill_range = iwl_dump_ini_err_table_iter,
2164 },
2165 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = {
2166 .get_num_of_ranges = iwl_dump_ini_single_range,
2167 .get_size = iwl_dump_ini_err_table_get_size,
2168 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header,
2169 .fill_range = iwl_dump_ini_err_table_iter,
2170 },
2171 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = {
2172 .get_num_of_ranges = iwl_dump_ini_single_range,
2173 .get_size = iwl_dump_ini_fw_pkt_get_size,
2174 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2175 .fill_range = iwl_dump_ini_fw_pkt_iter,
2176 },
2177 [IWL_FW_INI_REGION_DEVICE_MEMORY] = {
2178 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2179 .get_size = iwl_dump_ini_mem_get_size,
2180 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2181 .fill_range = iwl_dump_ini_dev_mem_iter,
2182 },
2183 [IWL_FW_INI_REGION_PERIPHERY_MAC] = {
2184 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2185 .get_size = iwl_dump_ini_mem_get_size,
2186 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2187 .fill_range = iwl_dump_ini_prph_mac_iter,
2188 },
2189 [IWL_FW_INI_REGION_PERIPHERY_PHY] = {
2190 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2191 .get_size = iwl_dump_ini_mem_get_size,
2192 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2193 .fill_range = iwl_dump_ini_prph_phy_iter,
2194 },
2195 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {},
2196 [IWL_FW_INI_REGION_PAGING] = {
2197 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2198 .get_num_of_ranges = iwl_dump_ini_paging_ranges,
2199 .get_size = iwl_dump_ini_paging_get_size,
2200 .fill_range = iwl_dump_ini_paging_iter,
2201 },
2202 [IWL_FW_INI_REGION_CSR] = {
2203 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2204 .get_size = iwl_dump_ini_mem_get_size,
2205 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2206 .fill_range = iwl_dump_ini_csr_iter,
2207 },
2208 [IWL_FW_INI_REGION_DRAM_IMR] = {},
2209 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = {
2210 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2211 .get_size = iwl_dump_ini_mem_get_size,
2212 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2213 .fill_range = iwl_dump_ini_config_iter,
2214 },
2215 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = {
2216 .get_num_of_ranges = iwl_dump_ini_single_range,
2217 .get_size = iwl_dump_ini_special_mem_get_size,
2218 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header,
2219 .fill_range = iwl_dump_ini_special_mem_iter,
2220 },
2221 [IWL_FW_INI_REGION_DBGI_SRAM] = {
2222 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2223 .get_size = iwl_dump_ini_mem_get_size,
2224 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2225 .fill_range = iwl_dump_ini_dbgi_sram_iter,
2226 },
2227 };
2228
iwl_dump_ini_trigger(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,struct list_head * list)2229 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,
2230 struct iwl_fwrt_dump_data *dump_data,
2231 struct list_head *list)
2232 {
2233 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig;
2234 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point);
2235 struct iwl_dump_ini_region_data reg_data = {
2236 .dump_data = dump_data,
2237 };
2238 int i;
2239 u32 size = 0;
2240 u64 regions_mask = le64_to_cpu(trigger->regions_mask) &
2241 ~(fwrt->trans->dbg.unsupported_region_msk);
2242
2243 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask));
2244 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) <
2245 ARRAY_SIZE(fwrt->trans->dbg.active_regions));
2246
2247 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) {
2248 u32 reg_type;
2249 struct iwl_fw_ini_region_tlv *reg;
2250
2251 if (!(BIT_ULL(i) & regions_mask))
2252 continue;
2253
2254 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i];
2255 if (!reg_data.reg_tlv) {
2256 IWL_WARN(fwrt,
2257 "WRT: Unassigned region id %d, skipping\n", i);
2258 continue;
2259 }
2260
2261 reg = (void *)reg_data.reg_tlv->data;
2262 reg_type = le32_to_cpu(reg->type);
2263 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops))
2264 continue;
2265
2266 if (reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY &&
2267 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) {
2268 IWL_WARN(fwrt,
2269 "WRT: trying to collect phy prph at time point: %d, skipping\n",
2270 tp_id);
2271 continue;
2272 }
2273
2274 size += iwl_dump_ini_mem(fwrt, list, ®_data,
2275 &iwl_dump_ini_region_ops[reg_type]);
2276 }
2277
2278 if (size)
2279 size += iwl_dump_ini_info(fwrt, trigger, list);
2280
2281 return size;
2282 }
2283
iwl_fw_ini_trigger_on(struct iwl_fw_runtime * fwrt,struct iwl_fw_ini_trigger_tlv * trig)2284 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt,
2285 struct iwl_fw_ini_trigger_tlv *trig)
2286 {
2287 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point);
2288 u32 usec = le32_to_cpu(trig->ignore_consec);
2289
2290 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
2291 tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
2292 tp_id >= IWL_FW_INI_TIME_POINT_NUM ||
2293 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec))
2294 return false;
2295
2296 return true;
2297 }
2298
iwl_dump_ini_file_gen(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,struct list_head * list)2299 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt,
2300 struct iwl_fwrt_dump_data *dump_data,
2301 struct list_head *list)
2302 {
2303 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig;
2304 struct iwl_fw_ini_dump_entry *entry;
2305 struct iwl_fw_ini_dump_file_hdr *hdr;
2306 u32 size;
2307
2308 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) ||
2309 !le64_to_cpu(trigger->regions_mask))
2310 return 0;
2311
2312 entry = vzalloc(sizeof(*entry) + sizeof(*hdr));
2313 if (!entry)
2314 return 0;
2315
2316 entry->size = sizeof(*hdr);
2317
2318 size = iwl_dump_ini_trigger(fwrt, dump_data, list);
2319 if (!size) {
2320 vfree(entry);
2321 return 0;
2322 }
2323
2324 hdr = (void *)entry->data;
2325 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER);
2326 hdr->file_len = cpu_to_le32(size + entry->size);
2327
2328 list_add(&entry->list, list);
2329
2330 return le32_to_cpu(hdr->file_len);
2331 }
2332
iwl_fw_free_dump_desc(struct iwl_fw_runtime * fwrt,const struct iwl_fw_dump_desc * desc)2333 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt,
2334 const struct iwl_fw_dump_desc *desc)
2335 {
2336 if (desc && desc != &iwl_dump_desc_assert)
2337 kfree(desc);
2338
2339 fwrt->dump.lmac_err_id[0] = 0;
2340 if (fwrt->smem_cfg.num_lmacs > 1)
2341 fwrt->dump.lmac_err_id[1] = 0;
2342 fwrt->dump.umac_err_id = 0;
2343 }
2344
iwl_fw_error_dump(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data)2345 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt,
2346 struct iwl_fwrt_dump_data *dump_data)
2347 {
2348 struct iwl_fw_dump_ptrs fw_error_dump = {};
2349 struct iwl_fw_error_dump_file *dump_file;
2350 struct scatterlist *sg_dump_data;
2351 u32 file_len;
2352 u32 dump_mask = fwrt->fw->dbg.dump_mask;
2353
2354 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data);
2355 if (!dump_file)
2356 return;
2357
2358 if (dump_data->monitor_only)
2359 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR);
2360
2361 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask);
2362 file_len = le32_to_cpu(dump_file->file_len);
2363 fw_error_dump.fwrt_len = file_len;
2364
2365 if (fw_error_dump.trans_ptr) {
2366 file_len += fw_error_dump.trans_ptr->len;
2367 dump_file->file_len = cpu_to_le32(file_len);
2368 }
2369
2370 sg_dump_data = alloc_sgtable(file_len);
2371 if (sg_dump_data) {
2372 sg_pcopy_from_buffer(sg_dump_data,
2373 sg_nents(sg_dump_data),
2374 fw_error_dump.fwrt_ptr,
2375 fw_error_dump.fwrt_len, 0);
2376 if (fw_error_dump.trans_ptr)
2377 sg_pcopy_from_buffer(sg_dump_data,
2378 sg_nents(sg_dump_data),
2379 fw_error_dump.trans_ptr->data,
2380 fw_error_dump.trans_ptr->len,
2381 fw_error_dump.fwrt_len);
2382 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2383 GFP_KERNEL);
2384 }
2385 vfree(fw_error_dump.fwrt_ptr);
2386 vfree(fw_error_dump.trans_ptr);
2387 }
2388
iwl_dump_ini_list_free(struct list_head * list)2389 static void iwl_dump_ini_list_free(struct list_head *list)
2390 {
2391 while (!list_empty(list)) {
2392 struct iwl_fw_ini_dump_entry *entry =
2393 list_entry(list->next, typeof(*entry), list);
2394
2395 list_del(&entry->list);
2396 vfree(entry);
2397 }
2398 }
2399
iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data * dump_data)2400 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data)
2401 {
2402 dump_data->trig = NULL;
2403 kfree(dump_data->fw_pkt);
2404 dump_data->fw_pkt = NULL;
2405 }
2406
iwl_fw_error_ini_dump(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data)2407 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt,
2408 struct iwl_fwrt_dump_data *dump_data)
2409 {
2410 struct list_head dump_list = LIST_HEAD_INIT(dump_list);
2411 struct scatterlist *sg_dump_data;
2412 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list);
2413
2414 if (!file_len)
2415 return;
2416
2417 sg_dump_data = alloc_sgtable(file_len);
2418 if (sg_dump_data) {
2419 struct iwl_fw_ini_dump_entry *entry;
2420 int sg_entries = sg_nents(sg_dump_data);
2421 u32 offs = 0;
2422
2423 list_for_each_entry(entry, &dump_list, list) {
2424 sg_pcopy_from_buffer(sg_dump_data, sg_entries,
2425 entry->data, entry->size, offs);
2426 offs += entry->size;
2427 }
2428 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2429 GFP_KERNEL);
2430 }
2431 iwl_dump_ini_list_free(&dump_list);
2432 }
2433
2434 const struct iwl_fw_dump_desc iwl_dump_desc_assert = {
2435 .trig_desc = {
2436 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT),
2437 },
2438 };
2439 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert);
2440
iwl_fw_dbg_collect_desc(struct iwl_fw_runtime * fwrt,const struct iwl_fw_dump_desc * desc,bool monitor_only,unsigned int delay)2441 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt,
2442 const struct iwl_fw_dump_desc *desc,
2443 bool monitor_only,
2444 unsigned int delay)
2445 {
2446 struct iwl_fwrt_wk_data *wk_data;
2447 unsigned long idx;
2448
2449 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2450 iwl_fw_free_dump_desc(fwrt, desc);
2451 return 0;
2452 }
2453
2454 /*
2455 * Check there is an available worker.
2456 * ffz return value is undefined if no zero exists,
2457 * so check against ~0UL first.
2458 */
2459 if (fwrt->dump.active_wks == ~0UL)
2460 return -EBUSY;
2461
2462 idx = ffz(fwrt->dump.active_wks);
2463
2464 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM ||
2465 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks))
2466 return -EBUSY;
2467
2468 wk_data = &fwrt->dump.wks[idx];
2469
2470 if (WARN_ON(wk_data->dump_data.desc))
2471 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc);
2472
2473 wk_data->dump_data.desc = desc;
2474 wk_data->dump_data.monitor_only = monitor_only;
2475
2476 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n",
2477 le32_to_cpu(desc->trig_desc.type));
2478
2479 schedule_delayed_work(&wk_data->wk, usecs_to_jiffies(delay));
2480
2481 return 0;
2482 }
2483 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc);
2484
iwl_fw_dbg_error_collect(struct iwl_fw_runtime * fwrt,enum iwl_fw_dbg_trigger trig_type)2485 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt,
2486 enum iwl_fw_dbg_trigger trig_type)
2487 {
2488 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status))
2489 return -EIO;
2490
2491 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2492 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT &&
2493 trig_type != FW_DBG_TRIGGER_DRIVER)
2494 return -EIO;
2495
2496 iwl_dbg_tlv_time_point(fwrt,
2497 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT,
2498 NULL);
2499 } else {
2500 struct iwl_fw_dump_desc *iwl_dump_error_desc;
2501 int ret;
2502
2503 iwl_dump_error_desc =
2504 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL);
2505
2506 if (!iwl_dump_error_desc)
2507 return -ENOMEM;
2508
2509 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type);
2510 iwl_dump_error_desc->len = 0;
2511
2512 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc,
2513 false, 0);
2514 if (ret) {
2515 kfree(iwl_dump_error_desc);
2516 return ret;
2517 }
2518 }
2519
2520 iwl_trans_sync_nmi(fwrt->trans);
2521
2522 return 0;
2523 }
2524 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect);
2525
iwl_fw_dbg_collect(struct iwl_fw_runtime * fwrt,enum iwl_fw_dbg_trigger trig,const char * str,size_t len,struct iwl_fw_dbg_trigger_tlv * trigger)2526 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt,
2527 enum iwl_fw_dbg_trigger trig,
2528 const char *str, size_t len,
2529 struct iwl_fw_dbg_trigger_tlv *trigger)
2530 {
2531 struct iwl_fw_dump_desc *desc;
2532 unsigned int delay = 0;
2533 bool monitor_only = false;
2534
2535 if (trigger) {
2536 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1;
2537
2538 if (!le16_to_cpu(trigger->occurrences))
2539 return 0;
2540
2541 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) {
2542 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n",
2543 trig);
2544 iwl_force_nmi(fwrt->trans);
2545 return 0;
2546 }
2547
2548 trigger->occurrences = cpu_to_le16(occurrences);
2549 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY;
2550
2551 /* convert msec to usec */
2552 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC;
2553 }
2554
2555 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC);
2556 if (!desc)
2557 return -ENOMEM;
2558
2559
2560 desc->len = len;
2561 desc->trig_desc.type = cpu_to_le32(trig);
2562 memcpy(desc->trig_desc.data, str, len);
2563
2564 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay);
2565 }
2566 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect);
2567
iwl_fw_dbg_collect_trig(struct iwl_fw_runtime * fwrt,struct iwl_fw_dbg_trigger_tlv * trigger,const char * fmt,...)2568 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt,
2569 struct iwl_fw_dbg_trigger_tlv *trigger,
2570 const char *fmt, ...)
2571 {
2572 int ret, len = 0;
2573 char buf[64];
2574
2575 if (iwl_trans_dbg_ini_valid(fwrt->trans))
2576 return 0;
2577
2578 if (fmt) {
2579 va_list ap;
2580
2581 buf[sizeof(buf) - 1] = '\0';
2582
2583 va_start(ap, fmt);
2584 vsnprintf(buf, sizeof(buf), fmt, ap);
2585 va_end(ap);
2586
2587 /* check for truncation */
2588 if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
2589 buf[sizeof(buf) - 1] = '\0';
2590
2591 len = strlen(buf) + 1;
2592 }
2593
2594 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len,
2595 trigger);
2596
2597 if (ret)
2598 return ret;
2599
2600 return 0;
2601 }
2602 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig);
2603
iwl_fw_start_dbg_conf(struct iwl_fw_runtime * fwrt,u8 conf_id)2604 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id)
2605 {
2606 u8 *ptr;
2607 int ret;
2608 int i;
2609
2610 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv),
2611 "Invalid configuration %d\n", conf_id))
2612 return -EINVAL;
2613
2614 /* EARLY START - firmware's configuration is hard coded */
2615 if ((!fwrt->fw->dbg.conf_tlv[conf_id] ||
2616 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) &&
2617 conf_id == FW_DBG_START_FROM_ALIVE)
2618 return 0;
2619
2620 if (!fwrt->fw->dbg.conf_tlv[conf_id])
2621 return -EINVAL;
2622
2623 if (fwrt->dump.conf != FW_DBG_INVALID)
2624 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n",
2625 fwrt->dump.conf);
2626
2627 /* Send all HCMDs for configuring the FW debug */
2628 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd;
2629 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) {
2630 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
2631 struct iwl_host_cmd hcmd = {
2632 .id = cmd->id,
2633 .len = { le16_to_cpu(cmd->len), },
2634 .data = { cmd->data, },
2635 };
2636
2637 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
2638 if (ret)
2639 return ret;
2640
2641 ptr += sizeof(*cmd);
2642 ptr += le16_to_cpu(cmd->len);
2643 }
2644
2645 fwrt->dump.conf = conf_id;
2646
2647 return 0;
2648 }
2649 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf);
2650
2651 /* this function assumes dump_start was called beforehand and dump_end will be
2652 * called afterwards
2653 */
iwl_fw_dbg_collect_sync(struct iwl_fw_runtime * fwrt,u8 wk_idx)2654 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx)
2655 {
2656 struct iwl_fw_dbg_params params = {0};
2657 struct iwl_fwrt_dump_data *dump_data =
2658 &fwrt->dump.wks[wk_idx].dump_data;
2659
2660 if (!test_bit(wk_idx, &fwrt->dump.active_wks))
2661 return;
2662
2663 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) {
2664 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n");
2665 goto out;
2666 }
2667
2668 /* there's no point in fw dump if the bus is dead */
2669 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) {
2670 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n");
2671 goto out;
2672 }
2673
2674 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true);
2675
2676 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n");
2677 if (iwl_trans_dbg_ini_valid(fwrt->trans))
2678 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data);
2679 else
2680 iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data);
2681 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n");
2682
2683 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false);
2684
2685 out:
2686 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2687 iwl_fw_error_dump_data_free(dump_data);
2688 } else {
2689 iwl_fw_free_dump_desc(fwrt, dump_data->desc);
2690 dump_data->desc = NULL;
2691 }
2692
2693 clear_bit(wk_idx, &fwrt->dump.active_wks);
2694 }
2695
iwl_fw_dbg_ini_collect(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,bool sync)2696 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt,
2697 struct iwl_fwrt_dump_data *dump_data,
2698 bool sync)
2699 {
2700 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig;
2701 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point);
2702 u32 occur, delay;
2703 unsigned long idx;
2704
2705 if (!iwl_fw_ini_trigger_on(fwrt, trig)) {
2706 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n",
2707 tp_id);
2708 return -EINVAL;
2709 }
2710
2711 delay = le32_to_cpu(trig->dump_delay);
2712 occur = le32_to_cpu(trig->occurrences);
2713 if (!occur)
2714 return 0;
2715
2716 trig->occurrences = cpu_to_le32(--occur);
2717
2718 /* Check there is an available worker.
2719 * ffz return value is undefined if no zero exists,
2720 * so check against ~0UL first.
2721 */
2722 if (fwrt->dump.active_wks == ~0UL)
2723 return -EBUSY;
2724
2725 idx = ffz(fwrt->dump.active_wks);
2726
2727 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM ||
2728 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks))
2729 return -EBUSY;
2730
2731 fwrt->dump.wks[idx].dump_data = *dump_data;
2732
2733 if (sync)
2734 delay = 0;
2735
2736 IWL_WARN(fwrt,
2737 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n",
2738 tp_id, (u32)(delay / USEC_PER_MSEC));
2739
2740 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay));
2741
2742 if (sync)
2743 iwl_fw_dbg_collect_sync(fwrt, idx);
2744
2745 return 0;
2746 }
2747
iwl_fw_error_dump_wk(struct work_struct * work)2748 void iwl_fw_error_dump_wk(struct work_struct *work)
2749 {
2750 struct iwl_fwrt_wk_data *wks =
2751 container_of(work, typeof(*wks), wk.work);
2752 struct iwl_fw_runtime *fwrt =
2753 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]);
2754
2755 /* assumes the op mode mutex is locked in dump_start since
2756 * iwl_fw_dbg_collect_sync can't run in parallel
2757 */
2758 if (fwrt->ops && fwrt->ops->dump_start &&
2759 fwrt->ops->dump_start(fwrt->ops_ctx))
2760 return;
2761
2762 iwl_fw_dbg_collect_sync(fwrt, wks->idx);
2763
2764 if (fwrt->ops && fwrt->ops->dump_end)
2765 fwrt->ops->dump_end(fwrt->ops_ctx);
2766 }
2767
iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime * fwrt)2768 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt)
2769 {
2770 const struct iwl_cfg *cfg = fwrt->trans->cfg;
2771
2772 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt))
2773 return;
2774
2775 if (!fwrt->dump.d3_debug_data) {
2776 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length,
2777 GFP_KERNEL);
2778 if (!fwrt->dump.d3_debug_data) {
2779 IWL_ERR(fwrt,
2780 "failed to allocate memory for D3 debug data\n");
2781 return;
2782 }
2783 }
2784
2785 /* if the buffer holds previous debug data it is overwritten */
2786 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr,
2787 fwrt->dump.d3_debug_data,
2788 cfg->d3_debug_data_length);
2789 }
2790 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data);
2791
iwl_fw_dbg_stop_sync(struct iwl_fw_runtime * fwrt)2792 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt)
2793 {
2794 int i;
2795
2796 iwl_dbg_tlv_del_timers(fwrt->trans);
2797 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++)
2798 iwl_fw_dbg_collect_sync(fwrt, i);
2799
2800 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true);
2801 }
2802 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync);
2803
iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans * trans,bool suspend)2804 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend)
2805 {
2806 struct iwl_dbg_suspend_resume_cmd cmd = {
2807 .operation = suspend ?
2808 cpu_to_le32(DBGC_SUSPEND_CMD) :
2809 cpu_to_le32(DBGC_RESUME_CMD),
2810 };
2811 struct iwl_host_cmd hcmd = {
2812 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME),
2813 .data[0] = &cmd,
2814 .len[0] = sizeof(cmd),
2815 };
2816
2817 return iwl_trans_send_cmd(trans, &hcmd);
2818 }
2819
iwl_fw_dbg_stop_recording(struct iwl_trans * trans,struct iwl_fw_dbg_params * params)2820 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans,
2821 struct iwl_fw_dbg_params *params)
2822 {
2823 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
2824 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
2825 return;
2826 }
2827
2828 if (params) {
2829 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE);
2830 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL);
2831 }
2832
2833 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);
2834 /* wait for the DBGC to finish writing the internal buffer to DRAM to
2835 * avoid halting the HW while writing
2836 */
2837 usleep_range(700, 1000);
2838 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0);
2839 }
2840
iwl_fw_dbg_restart_recording(struct iwl_trans * trans,struct iwl_fw_dbg_params * params)2841 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans,
2842 struct iwl_fw_dbg_params *params)
2843 {
2844 if (!params)
2845 return -EIO;
2846
2847 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
2848 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
2849 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
2850 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
2851 } else {
2852 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample);
2853 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl);
2854 }
2855
2856 return 0;
2857 }
2858
iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime * fwrt,struct iwl_fw_dbg_params * params,bool stop)2859 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt,
2860 struct iwl_fw_dbg_params *params,
2861 bool stop)
2862 {
2863 int ret __maybe_unused = 0;
2864
2865 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status))
2866 return;
2867
2868 if (fw_has_capa(&fwrt->fw->ucode_capa,
2869 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP))
2870 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop);
2871 else if (stop)
2872 iwl_fw_dbg_stop_recording(fwrt->trans, params);
2873 else
2874 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params);
2875 #ifdef CONFIG_IWLWIFI_DEBUGFS
2876 if (!ret) {
2877 if (stop)
2878 fwrt->trans->dbg.rec_on = false;
2879 else
2880 iwl_fw_set_dbg_rec_on(fwrt);
2881 }
2882 #endif
2883 }
2884 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording);
2885