1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7 #include <linux/types.h>
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/etherdevice.h>
11 #include <linux/pci.h>
12 #include <linux/firmware.h>
13
14 #include "iwl-drv.h"
15 #include "iwl-modparams.h"
16 #include "iwl-nvm-parse.h"
17 #include "iwl-prph.h"
18 #include "iwl-io.h"
19 #include "iwl-csr.h"
20 #include "fw/acpi.h"
21 #include "fw/api/nvm-reg.h"
22 #include "fw/api/commands.h"
23 #include "fw/api/cmdhdr.h"
24 #include "fw/img.h"
25
26 /* NVM offsets (in words) definitions */
27 enum nvm_offsets {
28 /* NVM HW-Section offset (in words) definitions */
29 SUBSYSTEM_ID = 0x0A,
30 HW_ADDR = 0x15,
31
32 /* NVM SW-Section offset (in words) definitions */
33 NVM_SW_SECTION = 0x1C0,
34 NVM_VERSION = 0,
35 RADIO_CFG = 1,
36 SKU = 2,
37 N_HW_ADDRS = 3,
38 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
39
40 /* NVM calibration section offset (in words) definitions */
41 NVM_CALIB_SECTION = 0x2B8,
42 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION,
43
44 /* NVM REGULATORY -Section offset (in words) definitions */
45 NVM_CHANNELS_SDP = 0,
46 };
47
48 enum ext_nvm_offsets {
49 /* NVM HW-Section offset (in words) definitions */
50 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
51
52 /* NVM SW-Section offset (in words) definitions */
53 NVM_VERSION_EXT_NVM = 0,
54 N_HW_ADDRS_FAMILY_8000 = 3,
55
56 /* NVM PHY_SKU-Section offset (in words) definitions */
57 RADIO_CFG_FAMILY_EXT_NVM = 0,
58 SKU_FAMILY_8000 = 2,
59
60 /* NVM REGULATORY -Section offset (in words) definitions */
61 NVM_CHANNELS_EXTENDED = 0,
62 NVM_LAR_OFFSET_OLD = 0x4C7,
63 NVM_LAR_OFFSET = 0x507,
64 NVM_LAR_ENABLED = 0x7,
65 };
66
67 /* SKU Capabilities (actual values from NVM definition) */
68 enum nvm_sku_bits {
69 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
70 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
71 NVM_SKU_CAP_11N_ENABLE = BIT(2),
72 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
73 NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
74 };
75
76 /*
77 * These are the channel numbers in the order that they are stored in the NVM
78 */
79 static const u16 iwl_nvm_channels[] = {
80 /* 2.4 GHz */
81 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
82 /* 5 GHz */
83 36, 40, 44 , 48, 52, 56, 60, 64,
84 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
85 149, 153, 157, 161, 165
86 };
87
88 static const u16 iwl_ext_nvm_channels[] = {
89 /* 2.4 GHz */
90 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
91 /* 5 GHz */
92 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
93 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
94 149, 153, 157, 161, 165, 169, 173, 177, 181
95 };
96
97 static const u16 iwl_uhb_nvm_channels[] = {
98 /* 2.4 GHz */
99 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
100 /* 5 GHz */
101 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
102 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
103 149, 153, 157, 161, 165, 169, 173, 177, 181,
104 /* 6-7 GHz */
105 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69,
106 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129,
107 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185,
108 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233
109 };
110
111 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
112 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels)
113 #define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels)
114 #define NUM_2GHZ_CHANNELS 14
115 #define NUM_5GHZ_CHANNELS 37
116 #define FIRST_2GHZ_HT_MINUS 5
117 #define LAST_2GHZ_HT_PLUS 9
118 #define N_HW_ADDR_MASK 0xF
119
120 /* rate data (static) */
121 static struct ieee80211_rate iwl_cfg80211_rates[] = {
122 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
123 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
124 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
125 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
126 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
127 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
128 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
129 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
130 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
131 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
132 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
133 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
134 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
135 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
136 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
137 };
138 #define RATES_24_OFFS 0
139 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
140 #define RATES_52_OFFS 4
141 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
142
143 /**
144 * enum iwl_nvm_channel_flags - channel flags in NVM
145 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
146 * @NVM_CHANNEL_IBSS: usable as an IBSS channel
147 * @NVM_CHANNEL_ACTIVE: active scanning allowed
148 * @NVM_CHANNEL_RADAR: radar detection required
149 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
150 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
151 * on same channel on 2.4 or same UNII band on 5.2
152 * @NVM_CHANNEL_UNIFORM: uniform spreading required
153 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
154 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
155 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
156 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
157 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
158 */
159 enum iwl_nvm_channel_flags {
160 NVM_CHANNEL_VALID = BIT(0),
161 NVM_CHANNEL_IBSS = BIT(1),
162 NVM_CHANNEL_ACTIVE = BIT(3),
163 NVM_CHANNEL_RADAR = BIT(4),
164 NVM_CHANNEL_INDOOR_ONLY = BIT(5),
165 NVM_CHANNEL_GO_CONCURRENT = BIT(6),
166 NVM_CHANNEL_UNIFORM = BIT(7),
167 NVM_CHANNEL_20MHZ = BIT(8),
168 NVM_CHANNEL_40MHZ = BIT(9),
169 NVM_CHANNEL_80MHZ = BIT(10),
170 NVM_CHANNEL_160MHZ = BIT(11),
171 NVM_CHANNEL_DC_HIGH = BIT(12),
172 };
173
174 /**
175 * enum iwl_reg_capa_flags - global flags applied for the whole regulatory
176 * domain.
177 * @REG_CAPA_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
178 * 2.4Ghz band is allowed.
179 * @REG_CAPA_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
180 * 5Ghz band is allowed.
181 * @REG_CAPA_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
182 * for this regulatory domain (valid only in 5Ghz).
183 * @REG_CAPA_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
184 * for this regulatory domain (valid only in 5Ghz).
185 * @REG_CAPA_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
186 * @REG_CAPA_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
187 * @REG_CAPA_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
188 * for this regulatory domain (valid only in 5Ghz).
189 * @REG_CAPA_DC_HIGH_ENABLED: DC HIGH allowed.
190 * @REG_CAPA_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
191 */
192 enum iwl_reg_capa_flags {
193 REG_CAPA_BF_CCD_LOW_BAND = BIT(0),
194 REG_CAPA_BF_CCD_HIGH_BAND = BIT(1),
195 REG_CAPA_160MHZ_ALLOWED = BIT(2),
196 REG_CAPA_80MHZ_ALLOWED = BIT(3),
197 REG_CAPA_MCS_8_ALLOWED = BIT(4),
198 REG_CAPA_MCS_9_ALLOWED = BIT(5),
199 REG_CAPA_40MHZ_FORBIDDEN = BIT(7),
200 REG_CAPA_DC_HIGH_ENABLED = BIT(9),
201 REG_CAPA_11AX_DISABLED = BIT(10),
202 };
203
204 /**
205 * enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory
206 * domain (version 2).
207 * @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are
208 * disabled.
209 * @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
210 * 2.4Ghz band is allowed.
211 * @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
212 * 5Ghz band is allowed.
213 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
214 * for this regulatory domain (valid only in 5Ghz).
215 * @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
216 * for this regulatory domain (valid only in 5Ghz).
217 * @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
218 * @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
219 * @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118,
220 * 126, 122) are disabled.
221 * @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed
222 * for this regulatory domain (uvalid only in 5Ghz).
223 * @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
224 */
225 enum iwl_reg_capa_flags_v2 {
226 REG_CAPA_V2_STRADDLE_DISABLED = BIT(0),
227 REG_CAPA_V2_BF_CCD_LOW_BAND = BIT(1),
228 REG_CAPA_V2_BF_CCD_HIGH_BAND = BIT(2),
229 REG_CAPA_V2_160MHZ_ALLOWED = BIT(3),
230 REG_CAPA_V2_80MHZ_ALLOWED = BIT(4),
231 REG_CAPA_V2_MCS_8_ALLOWED = BIT(5),
232 REG_CAPA_V2_MCS_9_ALLOWED = BIT(6),
233 REG_CAPA_V2_WEATHER_DISABLED = BIT(7),
234 REG_CAPA_V2_40MHZ_ALLOWED = BIT(8),
235 REG_CAPA_V2_11AX_DISABLED = BIT(10),
236 };
237
238 /*
239 * API v2 for reg_capa_flags is relevant from version 6 and onwards of the
240 * MCC update command response.
241 */
242 #define REG_CAPA_V2_RESP_VER 6
243
244 /**
245 * struct iwl_reg_capa - struct for global regulatory capabilities, Used for
246 * handling the different APIs of reg_capa_flags.
247 *
248 * @allow_40mhz: 11n channel with a width of 40Mhz is allowed
249 * for this regulatory domain (valid only in 5Ghz).
250 * @allow_80mhz: 11ac channel with a width of 80Mhz is allowed
251 * for this regulatory domain (valid only in 5Ghz).
252 * @allow_160mhz: 11ac channel with a width of 160Mhz is allowed
253 * for this regulatory domain (valid only in 5Ghz).
254 * @disable_11ax: 11ax is forbidden for this regulatory domain.
255 */
256 struct iwl_reg_capa {
257 u16 allow_40mhz;
258 u16 allow_80mhz;
259 u16 allow_160mhz;
260 u16 disable_11ax;
261 };
262
iwl_nvm_print_channel_flags(struct device * dev,u32 level,int chan,u32 flags)263 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
264 int chan, u32 flags)
265 {
266 #define CHECK_AND_PRINT_I(x) \
267 ((flags & NVM_CHANNEL_##x) ? " " #x : "")
268
269 if (!(flags & NVM_CHANNEL_VALID)) {
270 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
271 chan, flags);
272 return;
273 }
274
275 /* Note: already can print up to 101 characters, 110 is the limit! */
276 IWL_DEBUG_DEV(dev, level,
277 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n",
278 chan, flags,
279 CHECK_AND_PRINT_I(VALID),
280 CHECK_AND_PRINT_I(IBSS),
281 CHECK_AND_PRINT_I(ACTIVE),
282 CHECK_AND_PRINT_I(RADAR),
283 CHECK_AND_PRINT_I(INDOOR_ONLY),
284 CHECK_AND_PRINT_I(GO_CONCURRENT),
285 CHECK_AND_PRINT_I(UNIFORM),
286 CHECK_AND_PRINT_I(20MHZ),
287 CHECK_AND_PRINT_I(40MHZ),
288 CHECK_AND_PRINT_I(80MHZ),
289 CHECK_AND_PRINT_I(160MHZ),
290 CHECK_AND_PRINT_I(DC_HIGH));
291 #undef CHECK_AND_PRINT_I
292 }
293
iwl_get_channel_flags(u8 ch_num,int ch_idx,enum nl80211_band band,u32 nvm_flags,const struct iwl_cfg * cfg)294 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band,
295 u32 nvm_flags, const struct iwl_cfg *cfg)
296 {
297 u32 flags = IEEE80211_CHAN_NO_HT40;
298
299 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) {
300 if (ch_num <= LAST_2GHZ_HT_PLUS)
301 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
302 if (ch_num >= FIRST_2GHZ_HT_MINUS)
303 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
304 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
305 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
306 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
307 else
308 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
309 }
310 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
311 flags |= IEEE80211_CHAN_NO_80MHZ;
312 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
313 flags |= IEEE80211_CHAN_NO_160MHZ;
314
315 if (!(nvm_flags & NVM_CHANNEL_IBSS))
316 flags |= IEEE80211_CHAN_NO_IR;
317
318 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
319 flags |= IEEE80211_CHAN_NO_IR;
320
321 if (nvm_flags & NVM_CHANNEL_RADAR)
322 flags |= IEEE80211_CHAN_RADAR;
323
324 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
325 flags |= IEEE80211_CHAN_INDOOR_ONLY;
326
327 /* Set the GO concurrent flag only in case that NO_IR is set.
328 * Otherwise it is meaningless
329 */
330 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
331 (flags & IEEE80211_CHAN_NO_IR))
332 flags |= IEEE80211_CHAN_IR_CONCURRENT;
333
334 return flags;
335 }
336
iwl_nl80211_band_from_channel_idx(int ch_idx)337 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx)
338 {
339 if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) {
340 return NL80211_BAND_6GHZ;
341 }
342
343 if (ch_idx >= NUM_2GHZ_CHANNELS)
344 return NL80211_BAND_5GHZ;
345 return NL80211_BAND_2GHZ;
346 }
347
iwl_init_channel_map(struct device * dev,const struct iwl_cfg * cfg,struct iwl_nvm_data * data,const void * const nvm_ch_flags,u32 sbands_flags,bool v4)348 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
349 struct iwl_nvm_data *data,
350 const void * const nvm_ch_flags,
351 u32 sbands_flags, bool v4)
352 {
353 int ch_idx;
354 int n_channels = 0;
355 struct ieee80211_channel *channel;
356 u32 ch_flags;
357 int num_of_ch;
358 const u16 *nvm_chan;
359
360 if (cfg->uhb_supported) {
361 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB;
362 nvm_chan = iwl_uhb_nvm_channels;
363 } else if (cfg->nvm_type == IWL_NVM_EXT) {
364 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
365 nvm_chan = iwl_ext_nvm_channels;
366 } else {
367 num_of_ch = IWL_NVM_NUM_CHANNELS;
368 nvm_chan = iwl_nvm_channels;
369 }
370
371 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
372 enum nl80211_band band =
373 iwl_nl80211_band_from_channel_idx(ch_idx);
374
375 if (v4)
376 ch_flags =
377 __le32_to_cpup((__le32 *)nvm_ch_flags + ch_idx);
378 else
379 ch_flags =
380 __le16_to_cpup((__le16 *)nvm_ch_flags + ch_idx);
381
382 if (band == NL80211_BAND_5GHZ &&
383 !data->sku_cap_band_52ghz_enable)
384 continue;
385
386 /* workaround to disable wide channels in 5GHz */
387 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
388 band == NL80211_BAND_5GHZ) {
389 ch_flags &= ~(NVM_CHANNEL_40MHZ |
390 NVM_CHANNEL_80MHZ |
391 NVM_CHANNEL_160MHZ);
392 }
393
394 if (ch_flags & NVM_CHANNEL_160MHZ)
395 data->vht160_supported = true;
396
397 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
398 !(ch_flags & NVM_CHANNEL_VALID)) {
399 /*
400 * Channels might become valid later if lar is
401 * supported, hence we still want to add them to
402 * the list of supported channels to cfg80211.
403 */
404 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
405 nvm_chan[ch_idx], ch_flags);
406 continue;
407 }
408
409 channel = &data->channels[n_channels];
410 n_channels++;
411
412 channel->hw_value = nvm_chan[ch_idx];
413 channel->band = band;
414 channel->center_freq =
415 ieee80211_channel_to_frequency(
416 channel->hw_value, channel->band);
417
418 /* Initialize regulatory-based run-time data */
419
420 /*
421 * Default value - highest tx power value. max_power
422 * is not used in mvm, and is used for backwards compatibility
423 */
424 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
425
426 /* don't put limitations in case we're using LAR */
427 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
428 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
429 ch_idx, band,
430 ch_flags, cfg);
431 else
432 channel->flags = 0;
433
434 /* TODO: Don't put limitations on UHB devices as we still don't
435 * have NVM for them
436 */
437 if (cfg->uhb_supported)
438 channel->flags = 0;
439 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
440 channel->hw_value, ch_flags);
441 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
442 channel->hw_value, channel->max_power);
443 }
444
445 return n_channels;
446 }
447
iwl_init_vht_hw_capab(struct iwl_trans * trans,struct iwl_nvm_data * data,struct ieee80211_sta_vht_cap * vht_cap,u8 tx_chains,u8 rx_chains)448 static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
449 struct iwl_nvm_data *data,
450 struct ieee80211_sta_vht_cap *vht_cap,
451 u8 tx_chains, u8 rx_chains)
452 {
453 const struct iwl_cfg *cfg = trans->cfg;
454 int num_rx_ants = num_of_ant(rx_chains);
455 int num_tx_ants = num_of_ant(tx_chains);
456
457 vht_cap->vht_supported = true;
458
459 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
460 IEEE80211_VHT_CAP_RXSTBC_1 |
461 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
462 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
463 IEEE80211_VHT_MAX_AMPDU_1024K <<
464 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
465
466 if (data->vht160_supported)
467 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
468 IEEE80211_VHT_CAP_SHORT_GI_160;
469
470 if (cfg->vht_mu_mimo_supported)
471 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
472
473 if (cfg->ht_params->ldpc)
474 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
475
476 if (data->sku_cap_mimo_disabled) {
477 num_rx_ants = 1;
478 num_tx_ants = 1;
479 }
480
481 if (num_tx_ants > 1)
482 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
483 else
484 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
485
486 switch (iwlwifi_mod_params.amsdu_size) {
487 case IWL_AMSDU_DEF:
488 if (trans->trans_cfg->mq_rx_supported)
489 vht_cap->cap |=
490 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
491 else
492 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
493 break;
494 case IWL_AMSDU_2K:
495 if (trans->trans_cfg->mq_rx_supported)
496 vht_cap->cap |=
497 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
498 else
499 WARN(1, "RB size of 2K is not supported by this device\n");
500 break;
501 case IWL_AMSDU_4K:
502 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
503 break;
504 case IWL_AMSDU_8K:
505 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
506 break;
507 case IWL_AMSDU_12K:
508 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
509 break;
510 default:
511 break;
512 }
513
514 vht_cap->vht_mcs.rx_mcs_map =
515 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
516 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
517 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
518 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
519 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
520 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
521 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
522 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
523
524 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
525 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
526 /* this works because NOT_SUPPORTED == 3 */
527 vht_cap->vht_mcs.rx_mcs_map |=
528 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
529 }
530
531 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
532
533 vht_cap->vht_mcs.tx_highest |=
534 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
535 }
536
537 static const struct ieee80211_sband_iftype_data iwl_he_capa[] = {
538 {
539 .types_mask = BIT(NL80211_IFTYPE_STATION),
540 .he_cap = {
541 .has_he = true,
542 .he_cap_elem = {
543 .mac_cap_info[0] =
544 IEEE80211_HE_MAC_CAP0_HTC_HE,
545 .mac_cap_info[1] =
546 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
547 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
548 .mac_cap_info[2] =
549 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP,
550 .mac_cap_info[3] =
551 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
552 IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS,
553 .mac_cap_info[4] =
554 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU |
555 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39,
556 .mac_cap_info[5] =
557 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 |
558 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 |
559 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU |
560 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS |
561 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
562 .phy_cap_info[0] =
563 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
564 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
565 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
566 .phy_cap_info[1] =
567 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK |
568 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
569 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
570 .phy_cap_info[2] =
571 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
572 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ,
573 .phy_cap_info[3] =
574 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
575 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
576 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
577 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
578 .phy_cap_info[4] =
579 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
580 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
581 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
582 .phy_cap_info[6] =
583 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
584 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB |
585 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
586 .phy_cap_info[7] =
587 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
588 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI,
589 .phy_cap_info[8] =
590 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
591 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
592 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
593 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
594 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242,
595 .phy_cap_info[9] =
596 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
597 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
598 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
599 .phy_cap_info[10] =
600 IEEE80211_HE_PHY_CAP10_HE_MU_M1RU_MAX_LTF,
601 },
602 /*
603 * Set default Tx/Rx HE MCS NSS Support field.
604 * Indicate support for up to 2 spatial streams and all
605 * MCS, without any special cases
606 */
607 .he_mcs_nss_supp = {
608 .rx_mcs_80 = cpu_to_le16(0xfffa),
609 .tx_mcs_80 = cpu_to_le16(0xfffa),
610 .rx_mcs_160 = cpu_to_le16(0xfffa),
611 .tx_mcs_160 = cpu_to_le16(0xfffa),
612 .rx_mcs_80p80 = cpu_to_le16(0xffff),
613 .tx_mcs_80p80 = cpu_to_le16(0xffff),
614 },
615 /*
616 * Set default PPE thresholds, with PPET16 set to 0,
617 * PPET8 set to 7
618 */
619 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
620 },
621 },
622 {
623 .types_mask = BIT(NL80211_IFTYPE_AP),
624 .he_cap = {
625 .has_he = true,
626 .he_cap_elem = {
627 .mac_cap_info[0] =
628 IEEE80211_HE_MAC_CAP0_HTC_HE,
629 .mac_cap_info[1] =
630 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
631 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
632 .mac_cap_info[3] =
633 IEEE80211_HE_MAC_CAP3_OMI_CONTROL,
634 .phy_cap_info[0] =
635 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
636 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G,
637 .phy_cap_info[1] =
638 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
639 .phy_cap_info[2] =
640 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
641 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
642 .phy_cap_info[3] =
643 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
644 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
645 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
646 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
647 .phy_cap_info[6] =
648 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
649 .phy_cap_info[7] =
650 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI,
651 .phy_cap_info[8] =
652 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
653 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242,
654 .phy_cap_info[9] =
655 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
656 },
657 /*
658 * Set default Tx/Rx HE MCS NSS Support field.
659 * Indicate support for up to 2 spatial streams and all
660 * MCS, without any special cases
661 */
662 .he_mcs_nss_supp = {
663 .rx_mcs_80 = cpu_to_le16(0xfffa),
664 .tx_mcs_80 = cpu_to_le16(0xfffa),
665 .rx_mcs_160 = cpu_to_le16(0xfffa),
666 .tx_mcs_160 = cpu_to_le16(0xfffa),
667 .rx_mcs_80p80 = cpu_to_le16(0xffff),
668 .tx_mcs_80p80 = cpu_to_le16(0xffff),
669 },
670 /*
671 * Set default PPE thresholds, with PPET16 set to 0,
672 * PPET8 set to 7
673 */
674 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
675 },
676 },
677 };
678
iwl_init_he_6ghz_capa(struct iwl_trans * trans,struct iwl_nvm_data * data,struct ieee80211_supported_band * sband,u8 tx_chains,u8 rx_chains)679 static void iwl_init_he_6ghz_capa(struct iwl_trans *trans,
680 struct iwl_nvm_data *data,
681 struct ieee80211_supported_band *sband,
682 u8 tx_chains, u8 rx_chains)
683 {
684 struct ieee80211_sta_ht_cap ht_cap;
685 struct ieee80211_sta_vht_cap vht_cap = {};
686 struct ieee80211_sband_iftype_data *iftype_data;
687 u16 he_6ghz_capa = 0;
688 u32 exp;
689 int i;
690
691 if (sband->band != NL80211_BAND_6GHZ)
692 return;
693
694 /* grab HT/VHT capabilities and calculate HE 6 GHz capabilities */
695 iwl_init_ht_hw_capab(trans, data, &ht_cap, NL80211_BAND_5GHZ,
696 tx_chains, rx_chains);
697 WARN_ON(!ht_cap.ht_supported);
698 iwl_init_vht_hw_capab(trans, data, &vht_cap, tx_chains, rx_chains);
699 WARN_ON(!vht_cap.vht_supported);
700
701 he_6ghz_capa |=
702 u16_encode_bits(ht_cap.ampdu_density,
703 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START);
704 exp = u32_get_bits(vht_cap.cap,
705 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK);
706 he_6ghz_capa |=
707 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP);
708 exp = u32_get_bits(vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK);
709 he_6ghz_capa |=
710 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
711 /* we don't support extended_ht_cap_info anywhere, so no RD_RESPONDER */
712 if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN)
713 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS;
714 if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN)
715 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
716
717 IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa);
718
719 /* we know it's writable - we set it before ourselves */
720 iftype_data = (void *)sband->iftype_data;
721 for (i = 0; i < sband->n_iftype_data; i++)
722 iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa);
723 }
724
725 static void
iwl_nvm_fixup_sband_iftd(struct iwl_trans * trans,struct ieee80211_supported_band * sband,struct ieee80211_sband_iftype_data * iftype_data,u8 tx_chains,u8 rx_chains,const struct iwl_fw * fw)726 iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans,
727 struct ieee80211_supported_band *sband,
728 struct ieee80211_sband_iftype_data *iftype_data,
729 u8 tx_chains, u8 rx_chains,
730 const struct iwl_fw *fw)
731 {
732 bool is_ap = iftype_data->types_mask & BIT(NL80211_IFTYPE_AP);
733
734 /* Advertise an A-MPDU exponent extension based on
735 * operating band
736 */
737 if (sband->band != NL80211_BAND_2GHZ)
738 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
739 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_1;
740 else
741 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
742 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
743
744 if (is_ap && iwlwifi_mod_params.nvm_file)
745 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |=
746 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
747
748 if ((tx_chains & rx_chains) == ANT_AB) {
749 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |=
750 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ;
751 iftype_data->he_cap.he_cap_elem.phy_cap_info[5] |=
752 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
753 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2;
754 if (!is_ap)
755 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |=
756 IEEE80211_HE_PHY_CAP7_MAX_NC_2;
757 } else if (!is_ap) {
758 /* If not 2x2, we need to indicate 1x1 in the
759 * Midamble RX Max NSTS - but not for AP mode
760 */
761 iftype_data->he_cap.he_cap_elem.phy_cap_info[1] &=
762 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS;
763 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &=
764 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS;
765 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |=
766 IEEE80211_HE_PHY_CAP7_MAX_NC_1;
767 }
768
769 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
770 case IWL_CFG_RF_TYPE_GF:
771 case IWL_CFG_RF_TYPE_MR:
772 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |=
773 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
774 if (!is_ap)
775 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |=
776 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
777 break;
778 }
779
780 if (fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_BROADCAST_TWT))
781 iftype_data->he_cap.he_cap_elem.mac_cap_info[2] |=
782 IEEE80211_HE_MAC_CAP2_BCAST_TWT;
783 }
784
iwl_init_he_hw_capab(struct iwl_trans * trans,struct iwl_nvm_data * data,struct ieee80211_supported_band * sband,u8 tx_chains,u8 rx_chains,const struct iwl_fw * fw)785 static void iwl_init_he_hw_capab(struct iwl_trans *trans,
786 struct iwl_nvm_data *data,
787 struct ieee80211_supported_band *sband,
788 u8 tx_chains, u8 rx_chains,
789 const struct iwl_fw *fw)
790 {
791 struct ieee80211_sband_iftype_data *iftype_data;
792 int i;
793
794 /* should only initialize once */
795 if (WARN_ON(sband->iftype_data))
796 return;
797
798 BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_capa));
799 BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_capa));
800
801 switch (sband->band) {
802 case NL80211_BAND_2GHZ:
803 iftype_data = data->iftd.low;
804 break;
805 case NL80211_BAND_5GHZ:
806 case NL80211_BAND_6GHZ:
807 iftype_data = data->iftd.high;
808 break;
809 default:
810 WARN_ON(1);
811 return;
812 }
813
814 memcpy(iftype_data, iwl_he_capa, sizeof(iwl_he_capa));
815
816 sband->iftype_data = iftype_data;
817 sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa);
818
819 for (i = 0; i < sband->n_iftype_data; i++)
820 iwl_nvm_fixup_sband_iftd(trans, sband, &iftype_data[i],
821 tx_chains, rx_chains, fw);
822
823 iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains);
824 }
825
iwl_init_sbands(struct iwl_trans * trans,struct iwl_nvm_data * data,const void * nvm_ch_flags,u8 tx_chains,u8 rx_chains,u32 sbands_flags,bool v4,const struct iwl_fw * fw)826 static void iwl_init_sbands(struct iwl_trans *trans,
827 struct iwl_nvm_data *data,
828 const void *nvm_ch_flags, u8 tx_chains,
829 u8 rx_chains, u32 sbands_flags, bool v4,
830 const struct iwl_fw *fw)
831 {
832 struct device *dev = trans->dev;
833 const struct iwl_cfg *cfg = trans->cfg;
834 int n_channels;
835 int n_used = 0;
836 struct ieee80211_supported_band *sband;
837
838 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
839 sbands_flags, v4);
840 sband = &data->bands[NL80211_BAND_2GHZ];
841 sband->band = NL80211_BAND_2GHZ;
842 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
843 sband->n_bitrates = N_RATES_24;
844 n_used += iwl_init_sband_channels(data, sband, n_channels,
845 NL80211_BAND_2GHZ);
846 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
847 tx_chains, rx_chains);
848
849 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
850 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
851 fw);
852
853 sband = &data->bands[NL80211_BAND_5GHZ];
854 sband->band = NL80211_BAND_5GHZ;
855 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
856 sband->n_bitrates = N_RATES_52;
857 n_used += iwl_init_sband_channels(data, sband, n_channels,
858 NL80211_BAND_5GHZ);
859 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
860 tx_chains, rx_chains);
861 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
862 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
863 tx_chains, rx_chains);
864
865 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
866 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
867 fw);
868
869 /* 6GHz band. */
870 sband = &data->bands[NL80211_BAND_6GHZ];
871 sband->band = NL80211_BAND_6GHZ;
872 /* use the same rates as 5GHz band */
873 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
874 sband->n_bitrates = N_RATES_52;
875 n_used += iwl_init_sband_channels(data, sband, n_channels,
876 NL80211_BAND_6GHZ);
877
878 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
879 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
880 fw);
881 else
882 sband->n_channels = 0;
883 if (n_channels != n_used)
884 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
885 n_used, n_channels);
886 }
887
iwl_get_sku(const struct iwl_cfg * cfg,const __le16 * nvm_sw,const __le16 * phy_sku)888 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
889 const __le16 *phy_sku)
890 {
891 if (cfg->nvm_type != IWL_NVM_EXT)
892 return le16_to_cpup(nvm_sw + SKU);
893
894 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
895 }
896
iwl_get_nvm_version(const struct iwl_cfg * cfg,const __le16 * nvm_sw)897 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
898 {
899 if (cfg->nvm_type != IWL_NVM_EXT)
900 return le16_to_cpup(nvm_sw + NVM_VERSION);
901 else
902 return le32_to_cpup((__le32 *)(nvm_sw +
903 NVM_VERSION_EXT_NVM));
904 }
905
iwl_get_radio_cfg(const struct iwl_cfg * cfg,const __le16 * nvm_sw,const __le16 * phy_sku)906 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
907 const __le16 *phy_sku)
908 {
909 if (cfg->nvm_type != IWL_NVM_EXT)
910 return le16_to_cpup(nvm_sw + RADIO_CFG);
911
912 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
913
914 }
915
iwl_get_n_hw_addrs(const struct iwl_cfg * cfg,const __le16 * nvm_sw)916 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
917 {
918 int n_hw_addr;
919
920 if (cfg->nvm_type != IWL_NVM_EXT)
921 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
922
923 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
924
925 return n_hw_addr & N_HW_ADDR_MASK;
926 }
927
iwl_set_radio_cfg(const struct iwl_cfg * cfg,struct iwl_nvm_data * data,u32 radio_cfg)928 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
929 struct iwl_nvm_data *data,
930 u32 radio_cfg)
931 {
932 if (cfg->nvm_type != IWL_NVM_EXT) {
933 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
934 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
935 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
936 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
937 return;
938 }
939
940 /* set the radio configuration for family 8000 */
941 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
942 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
943 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
944 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
945 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
946 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
947 }
948
iwl_flip_hw_address(__le32 mac_addr0,__le32 mac_addr1,u8 * dest)949 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
950 {
951 const u8 *hw_addr;
952
953 hw_addr = (const u8 *)&mac_addr0;
954 dest[0] = hw_addr[3];
955 dest[1] = hw_addr[2];
956 dest[2] = hw_addr[1];
957 dest[3] = hw_addr[0];
958
959 hw_addr = (const u8 *)&mac_addr1;
960 dest[4] = hw_addr[1];
961 dest[5] = hw_addr[0];
962 }
963
iwl_set_hw_address_from_csr(struct iwl_trans * trans,struct iwl_nvm_data * data)964 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
965 struct iwl_nvm_data *data)
966 {
967 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans,
968 CSR_MAC_ADDR0_STRAP(trans)));
969 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans,
970 CSR_MAC_ADDR1_STRAP(trans)));
971
972 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
973 /*
974 * If the OEM fused a valid address, use it instead of the one in the
975 * OTP
976 */
977 if (is_valid_ether_addr(data->hw_addr))
978 return;
979
980 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans)));
981 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans)));
982
983 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
984 }
985
iwl_set_hw_address_family_8000(struct iwl_trans * trans,const struct iwl_cfg * cfg,struct iwl_nvm_data * data,const __le16 * mac_override,const __be16 * nvm_hw)986 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
987 const struct iwl_cfg *cfg,
988 struct iwl_nvm_data *data,
989 const __le16 *mac_override,
990 const __be16 *nvm_hw)
991 {
992 const u8 *hw_addr;
993
994 if (mac_override) {
995 static const u8 reserved_mac[] = {
996 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
997 };
998
999 hw_addr = (const u8 *)(mac_override +
1000 MAC_ADDRESS_OVERRIDE_EXT_NVM);
1001
1002 /*
1003 * Store the MAC address from MAO section.
1004 * No byte swapping is required in MAO section
1005 */
1006 memcpy(data->hw_addr, hw_addr, ETH_ALEN);
1007
1008 /*
1009 * Force the use of the OTP MAC address in case of reserved MAC
1010 * address in the NVM, or if address is given but invalid.
1011 */
1012 if (is_valid_ether_addr(data->hw_addr) &&
1013 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
1014 return;
1015
1016 IWL_ERR(trans,
1017 "mac address from nvm override section is not valid\n");
1018 }
1019
1020 if (nvm_hw) {
1021 /* read the mac address from WFMP registers */
1022 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
1023 WFMP_MAC_ADDR_0));
1024 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
1025 WFMP_MAC_ADDR_1));
1026
1027 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
1028
1029 return;
1030 }
1031
1032 IWL_ERR(trans, "mac address is not found\n");
1033 }
1034
iwl_set_hw_address(struct iwl_trans * trans,const struct iwl_cfg * cfg,struct iwl_nvm_data * data,const __be16 * nvm_hw,const __le16 * mac_override)1035 static int iwl_set_hw_address(struct iwl_trans *trans,
1036 const struct iwl_cfg *cfg,
1037 struct iwl_nvm_data *data, const __be16 *nvm_hw,
1038 const __le16 *mac_override)
1039 {
1040 if (cfg->mac_addr_from_csr) {
1041 iwl_set_hw_address_from_csr(trans, data);
1042 } else if (cfg->nvm_type != IWL_NVM_EXT) {
1043 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
1044
1045 /* The byte order is little endian 16 bit, meaning 214365 */
1046 data->hw_addr[0] = hw_addr[1];
1047 data->hw_addr[1] = hw_addr[0];
1048 data->hw_addr[2] = hw_addr[3];
1049 data->hw_addr[3] = hw_addr[2];
1050 data->hw_addr[4] = hw_addr[5];
1051 data->hw_addr[5] = hw_addr[4];
1052 } else {
1053 iwl_set_hw_address_family_8000(trans, cfg, data,
1054 mac_override, nvm_hw);
1055 }
1056
1057 if (!is_valid_ether_addr(data->hw_addr)) {
1058 IWL_ERR(trans, "no valid mac address was found\n");
1059 return -EINVAL;
1060 }
1061
1062 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr);
1063
1064 return 0;
1065 }
1066
1067 static bool
iwl_nvm_no_wide_in_5ghz(struct iwl_trans * trans,const struct iwl_cfg * cfg,const __be16 * nvm_hw)1068 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1069 const __be16 *nvm_hw)
1070 {
1071 /*
1072 * Workaround a bug in Indonesia SKUs where the regulatory in
1073 * some 7000-family OTPs erroneously allow wide channels in
1074 * 5GHz. To check for Indonesia, we take the SKU value from
1075 * bits 1-4 in the subsystem ID and check if it is either 5 or
1076 * 9. In those cases, we need to force-disable wide channels
1077 * in 5GHz otherwise the FW will throw a sysassert when we try
1078 * to use them.
1079 */
1080 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1081 /*
1082 * Unlike the other sections in the NVM, the hw
1083 * section uses big-endian.
1084 */
1085 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
1086 u8 sku = (subsystem_id & 0x1e) >> 1;
1087
1088 if (sku == 5 || sku == 9) {
1089 IWL_DEBUG_EEPROM(trans->dev,
1090 "disabling wide channels in 5GHz (0x%0x %d)\n",
1091 subsystem_id, sku);
1092 return true;
1093 }
1094 }
1095
1096 return false;
1097 }
1098
1099 struct iwl_nvm_data *
iwl_parse_nvm_data(struct iwl_trans * trans,const struct iwl_cfg * cfg,const struct iwl_fw * fw,const __be16 * nvm_hw,const __le16 * nvm_sw,const __le16 * nvm_calib,const __le16 * regulatory,const __le16 * mac_override,const __le16 * phy_sku,u8 tx_chains,u8 rx_chains)1100 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1101 const struct iwl_fw *fw,
1102 const __be16 *nvm_hw, const __le16 *nvm_sw,
1103 const __le16 *nvm_calib, const __le16 *regulatory,
1104 const __le16 *mac_override, const __le16 *phy_sku,
1105 u8 tx_chains, u8 rx_chains)
1106 {
1107 struct iwl_nvm_data *data;
1108 bool lar_enabled;
1109 u32 sku, radio_cfg;
1110 u32 sbands_flags = 0;
1111 u16 lar_config;
1112 const __le16 *ch_section;
1113
1114 if (cfg->uhb_supported)
1115 data = kzalloc(struct_size(data, channels,
1116 IWL_NVM_NUM_CHANNELS_UHB),
1117 GFP_KERNEL);
1118 else if (cfg->nvm_type != IWL_NVM_EXT)
1119 data = kzalloc(struct_size(data, channels,
1120 IWL_NVM_NUM_CHANNELS),
1121 GFP_KERNEL);
1122 else
1123 data = kzalloc(struct_size(data, channels,
1124 IWL_NVM_NUM_CHANNELS_EXT),
1125 GFP_KERNEL);
1126 if (!data)
1127 return NULL;
1128
1129 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
1130
1131 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
1132 iwl_set_radio_cfg(cfg, data, radio_cfg);
1133 if (data->valid_tx_ant)
1134 tx_chains &= data->valid_tx_ant;
1135 if (data->valid_rx_ant)
1136 rx_chains &= data->valid_rx_ant;
1137
1138 sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
1139 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
1140 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
1141 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
1142 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
1143 data->sku_cap_11n_enable = false;
1144 data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
1145 (sku & NVM_SKU_CAP_11AC_ENABLE);
1146 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
1147
1148 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
1149
1150 if (cfg->nvm_type != IWL_NVM_EXT) {
1151 /* Checking for required sections */
1152 if (!nvm_calib) {
1153 IWL_ERR(trans,
1154 "Can't parse empty Calib NVM sections\n");
1155 kfree(data);
1156 return NULL;
1157 }
1158
1159 ch_section = cfg->nvm_type == IWL_NVM_SDP ?
1160 ®ulatory[NVM_CHANNELS_SDP] :
1161 &nvm_sw[NVM_CHANNELS];
1162
1163 /* in family 8000 Xtal calibration values moved to OTP */
1164 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
1165 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
1166 lar_enabled = true;
1167 } else {
1168 u16 lar_offset = data->nvm_version < 0xE39 ?
1169 NVM_LAR_OFFSET_OLD :
1170 NVM_LAR_OFFSET;
1171
1172 lar_config = le16_to_cpup(regulatory + lar_offset);
1173 data->lar_enabled = !!(lar_config &
1174 NVM_LAR_ENABLED);
1175 lar_enabled = data->lar_enabled;
1176 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED];
1177 }
1178
1179 /* If no valid mac address was found - bail out */
1180 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
1181 kfree(data);
1182 return NULL;
1183 }
1184
1185 if (lar_enabled &&
1186 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1187 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1188
1189 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw))
1190 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
1191
1192 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains,
1193 sbands_flags, false, fw);
1194 data->calib_version = 255;
1195
1196 return data;
1197 }
1198 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
1199
iwl_nvm_get_regdom_bw_flags(const u16 * nvm_chan,int ch_idx,u16 nvm_flags,struct iwl_reg_capa reg_capa,const struct iwl_cfg * cfg)1200 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan,
1201 int ch_idx, u16 nvm_flags,
1202 struct iwl_reg_capa reg_capa,
1203 const struct iwl_cfg *cfg)
1204 {
1205 u32 flags = NL80211_RRF_NO_HT40;
1206
1207 if (ch_idx < NUM_2GHZ_CHANNELS &&
1208 (nvm_flags & NVM_CHANNEL_40MHZ)) {
1209 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
1210 flags &= ~NL80211_RRF_NO_HT40PLUS;
1211 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
1212 flags &= ~NL80211_RRF_NO_HT40MINUS;
1213 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
1214 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
1215 flags &= ~NL80211_RRF_NO_HT40PLUS;
1216 else
1217 flags &= ~NL80211_RRF_NO_HT40MINUS;
1218 }
1219
1220 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
1221 flags |= NL80211_RRF_NO_80MHZ;
1222 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
1223 flags |= NL80211_RRF_NO_160MHZ;
1224
1225 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
1226 flags |= NL80211_RRF_NO_IR;
1227
1228 if (nvm_flags & NVM_CHANNEL_RADAR)
1229 flags |= NL80211_RRF_DFS;
1230
1231 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
1232 flags |= NL80211_RRF_NO_OUTDOOR;
1233
1234 /* Set the GO concurrent flag only in case that NO_IR is set.
1235 * Otherwise it is meaningless
1236 */
1237 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
1238 (flags & NL80211_RRF_NO_IR))
1239 flags |= NL80211_RRF_GO_CONCURRENT;
1240
1241 /*
1242 * reg_capa is per regulatory domain so apply it for every channel
1243 */
1244 if (ch_idx >= NUM_2GHZ_CHANNELS) {
1245 if (!reg_capa.allow_40mhz)
1246 flags |= NL80211_RRF_NO_HT40;
1247
1248 if (!reg_capa.allow_80mhz)
1249 flags |= NL80211_RRF_NO_80MHZ;
1250
1251 if (!reg_capa.allow_160mhz)
1252 flags |= NL80211_RRF_NO_160MHZ;
1253 }
1254 if (reg_capa.disable_11ax)
1255 flags |= NL80211_RRF_NO_HE;
1256
1257 return flags;
1258 }
1259
iwl_get_reg_capa(u16 flags,u8 resp_ver)1260 static struct iwl_reg_capa iwl_get_reg_capa(u16 flags, u8 resp_ver)
1261 {
1262 struct iwl_reg_capa reg_capa;
1263
1264 if (resp_ver >= REG_CAPA_V2_RESP_VER) {
1265 reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED;
1266 reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED;
1267 reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED;
1268 reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED;
1269 } else {
1270 reg_capa.allow_40mhz = !(flags & REG_CAPA_40MHZ_FORBIDDEN);
1271 reg_capa.allow_80mhz = flags & REG_CAPA_80MHZ_ALLOWED;
1272 reg_capa.allow_160mhz = flags & REG_CAPA_160MHZ_ALLOWED;
1273 reg_capa.disable_11ax = flags & REG_CAPA_11AX_DISABLED;
1274 }
1275 return reg_capa;
1276 }
1277
1278 struct ieee80211_regdomain *
iwl_parse_nvm_mcc_info(struct device * dev,const struct iwl_cfg * cfg,int num_of_ch,__le32 * channels,u16 fw_mcc,u16 geo_info,u16 cap,u8 resp_ver)1279 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1280 int num_of_ch, __le32 *channels, u16 fw_mcc,
1281 u16 geo_info, u16 cap, u8 resp_ver)
1282 {
1283 int ch_idx;
1284 u16 ch_flags;
1285 u32 reg_rule_flags, prev_reg_rule_flags = 0;
1286 const u16 *nvm_chan;
1287 struct ieee80211_regdomain *regd, *copy_rd;
1288 struct ieee80211_reg_rule *rule;
1289 enum nl80211_band band;
1290 int center_freq, prev_center_freq = 0;
1291 int valid_rules = 0;
1292 bool new_rule;
1293 int max_num_ch;
1294 struct iwl_reg_capa reg_capa;
1295
1296 if (cfg->uhb_supported) {
1297 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB;
1298 nvm_chan = iwl_uhb_nvm_channels;
1299 } else if (cfg->nvm_type == IWL_NVM_EXT) {
1300 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT;
1301 nvm_chan = iwl_ext_nvm_channels;
1302 } else {
1303 max_num_ch = IWL_NVM_NUM_CHANNELS;
1304 nvm_chan = iwl_nvm_channels;
1305 }
1306
1307 if (WARN_ON(num_of_ch > max_num_ch))
1308 num_of_ch = max_num_ch;
1309
1310 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1311 return ERR_PTR(-EINVAL);
1312
1313 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1314 num_of_ch);
1315
1316 /* build a regdomain rule for every valid channel */
1317 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL);
1318 if (!regd)
1319 return ERR_PTR(-ENOMEM);
1320
1321 /* set alpha2 from FW. */
1322 regd->alpha2[0] = fw_mcc >> 8;
1323 regd->alpha2[1] = fw_mcc & 0xff;
1324
1325 /* parse regulatory capability flags */
1326 reg_capa = iwl_get_reg_capa(cap, resp_ver);
1327
1328 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1329 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
1330 band = iwl_nl80211_band_from_channel_idx(ch_idx);
1331 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
1332 band);
1333 new_rule = false;
1334
1335 if (!(ch_flags & NVM_CHANNEL_VALID)) {
1336 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1337 nvm_chan[ch_idx], ch_flags);
1338 continue;
1339 }
1340
1341 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1342 ch_flags, reg_capa,
1343 cfg);
1344
1345 /* we can't continue the same rule */
1346 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1347 center_freq - prev_center_freq > 20) {
1348 valid_rules++;
1349 new_rule = true;
1350 }
1351
1352 rule = ®d->reg_rules[valid_rules - 1];
1353
1354 if (new_rule)
1355 rule->freq_range.start_freq_khz =
1356 MHZ_TO_KHZ(center_freq - 10);
1357
1358 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1359
1360 /* this doesn't matter - not used by FW */
1361 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1362 rule->power_rule.max_eirp =
1363 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1364
1365 rule->flags = reg_rule_flags;
1366
1367 /* rely on auto-calculation to merge BW of contiguous chans */
1368 rule->flags |= NL80211_RRF_AUTO_BW;
1369 rule->freq_range.max_bandwidth_khz = 0;
1370
1371 prev_center_freq = center_freq;
1372 prev_reg_rule_flags = reg_rule_flags;
1373
1374 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1375 nvm_chan[ch_idx], ch_flags);
1376
1377 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1378 band == NL80211_BAND_2GHZ)
1379 continue;
1380
1381 reg_query_regdb_wmm(regd->alpha2, center_freq, rule);
1382 }
1383
1384 /*
1385 * Certain firmware versions might report no valid channels
1386 * if booted in RF-kill, i.e. not all calibrations etc. are
1387 * running. We'll get out of this situation later when the
1388 * rfkill is removed and we update the regdomain again, but
1389 * since cfg80211 doesn't accept an empty regdomain, add a
1390 * dummy (unusable) rule here in this case so we can init.
1391 */
1392 if (!valid_rules) {
1393 valid_rules = 1;
1394 rule = ®d->reg_rules[valid_rules - 1];
1395 rule->freq_range.start_freq_khz = MHZ_TO_KHZ(2412);
1396 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(2413);
1397 rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(1);
1398 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1399 rule->power_rule.max_eirp =
1400 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1401 }
1402
1403 regd->n_reg_rules = valid_rules;
1404
1405 /*
1406 * Narrow down regdom for unused regulatory rules to prevent hole
1407 * between reg rules to wmm rules.
1408 */
1409 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules),
1410 GFP_KERNEL);
1411 if (!copy_rd)
1412 copy_rd = ERR_PTR(-ENOMEM);
1413
1414 kfree(regd);
1415 return copy_rd;
1416 }
1417 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1418
1419 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58
1420 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc
1421 #define MAX_NVM_FILE_LEN 16384
1422
iwl_nvm_fixups(u32 hw_id,unsigned int section,u8 * data,unsigned int len)1423 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1424 unsigned int len)
1425 {
1426 #define IWL_4165_DEVICE_ID 0x5501
1427 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1428
1429 if (section == NVM_SECTION_TYPE_PHY_SKU &&
1430 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1431 (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1432 /* OTP 0x52 bug work around: it's a 1x1 device */
1433 data[3] = ANT_B | (ANT_B << 4);
1434 }
1435 IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1436
1437 /*
1438 * Reads external NVM from a file into mvm->nvm_sections
1439 *
1440 * HOW TO CREATE THE NVM FILE FORMAT:
1441 * ------------------------------
1442 * 1. create hex file, format:
1443 * 3800 -> header
1444 * 0000 -> header
1445 * 5a40 -> data
1446 *
1447 * rev - 6 bit (word1)
1448 * len - 10 bit (word1)
1449 * id - 4 bit (word2)
1450 * rsv - 12 bit (word2)
1451 *
1452 * 2. flip 8bits with 8 bits per line to get the right NVM file format
1453 *
1454 * 3. create binary file from the hex file
1455 *
1456 * 4. save as "iNVM_xxx.bin" under /lib/firmware
1457 */
iwl_read_external_nvm(struct iwl_trans * trans,const char * nvm_file_name,struct iwl_nvm_section * nvm_sections)1458 int iwl_read_external_nvm(struct iwl_trans *trans,
1459 const char *nvm_file_name,
1460 struct iwl_nvm_section *nvm_sections)
1461 {
1462 int ret, section_size;
1463 u16 section_id;
1464 const struct firmware *fw_entry;
1465 const struct {
1466 __le16 word1;
1467 __le16 word2;
1468 u8 data[];
1469 } *file_sec;
1470 const u8 *eof;
1471 u8 *temp;
1472 int max_section_size;
1473 const __le32 *dword_buff;
1474
1475 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1476 #define NVM_WORD2_ID(x) (x >> 12)
1477 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1478 #define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1479 #define NVM_HEADER_0 (0x2A504C54)
1480 #define NVM_HEADER_1 (0x4E564D2A)
1481 #define NVM_HEADER_SIZE (4 * sizeof(u32))
1482
1483 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1484
1485 /* Maximal size depends on NVM version */
1486 if (trans->cfg->nvm_type != IWL_NVM_EXT)
1487 max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1488 else
1489 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1490
1491 /*
1492 * Obtain NVM image via request_firmware. Since we already used
1493 * request_firmware_nowait() for the firmware binary load and only
1494 * get here after that we assume the NVM request can be satisfied
1495 * synchronously.
1496 */
1497 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
1498 if (ret) {
1499 IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1500 nvm_file_name, ret);
1501 return ret;
1502 }
1503
1504 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1505 nvm_file_name, fw_entry->size);
1506
1507 if (fw_entry->size > MAX_NVM_FILE_LEN) {
1508 IWL_ERR(trans, "NVM file too large\n");
1509 ret = -EINVAL;
1510 goto out;
1511 }
1512
1513 eof = fw_entry->data + fw_entry->size;
1514 dword_buff = (__le32 *)fw_entry->data;
1515
1516 /* some NVM file will contain a header.
1517 * The header is identified by 2 dwords header as follow:
1518 * dword[0] = 0x2A504C54
1519 * dword[1] = 0x4E564D2A
1520 *
1521 * This header must be skipped when providing the NVM data to the FW.
1522 */
1523 if (fw_entry->size > NVM_HEADER_SIZE &&
1524 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1525 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1526 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
1527 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1528 IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1529 le32_to_cpu(dword_buff[3]));
1530
1531 /* nvm file validation, dword_buff[2] holds the file version */
1532 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1533 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP &&
1534 le32_to_cpu(dword_buff[2]) < 0xE4A) {
1535 ret = -EFAULT;
1536 goto out;
1537 }
1538 } else {
1539 file_sec = (void *)fw_entry->data;
1540 }
1541
1542 while (true) {
1543 if (file_sec->data > eof) {
1544 IWL_ERR(trans,
1545 "ERROR - NVM file too short for section header\n");
1546 ret = -EINVAL;
1547 break;
1548 }
1549
1550 /* check for EOF marker */
1551 if (!file_sec->word1 && !file_sec->word2) {
1552 ret = 0;
1553 break;
1554 }
1555
1556 if (trans->cfg->nvm_type != IWL_NVM_EXT) {
1557 section_size =
1558 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
1559 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
1560 } else {
1561 section_size = 2 * EXT_NVM_WORD2_LEN(
1562 le16_to_cpu(file_sec->word2));
1563 section_id = EXT_NVM_WORD1_ID(
1564 le16_to_cpu(file_sec->word1));
1565 }
1566
1567 if (section_size > max_section_size) {
1568 IWL_ERR(trans, "ERROR - section too large (%d)\n",
1569 section_size);
1570 ret = -EINVAL;
1571 break;
1572 }
1573
1574 if (!section_size) {
1575 IWL_ERR(trans, "ERROR - section empty\n");
1576 ret = -EINVAL;
1577 break;
1578 }
1579
1580 if (file_sec->data + section_size > eof) {
1581 IWL_ERR(trans,
1582 "ERROR - NVM file too short for section (%d bytes)\n",
1583 section_size);
1584 ret = -EINVAL;
1585 break;
1586 }
1587
1588 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
1589 "Invalid NVM section ID %d\n", section_id)) {
1590 ret = -EINVAL;
1591 break;
1592 }
1593
1594 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
1595 if (!temp) {
1596 ret = -ENOMEM;
1597 break;
1598 }
1599
1600 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
1601
1602 kfree(nvm_sections[section_id].data);
1603 nvm_sections[section_id].data = temp;
1604 nvm_sections[section_id].length = section_size;
1605
1606 /* advance to the next section */
1607 file_sec = (void *)(file_sec->data + section_size);
1608 }
1609 out:
1610 release_firmware(fw_entry);
1611 return ret;
1612 }
1613 IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
1614
iwl_get_nvm(struct iwl_trans * trans,const struct iwl_fw * fw)1615 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
1616 const struct iwl_fw *fw)
1617 {
1618 struct iwl_nvm_get_info cmd = {};
1619 struct iwl_nvm_data *nvm;
1620 struct iwl_host_cmd hcmd = {
1621 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
1622 .data = { &cmd, },
1623 .len = { sizeof(cmd) },
1624 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
1625 };
1626 int ret;
1627 bool empty_otp;
1628 u32 mac_flags;
1629 u32 sbands_flags = 0;
1630 /*
1631 * All the values in iwl_nvm_get_info_rsp v4 are the same as
1632 * in v3, except for the channel profile part of the
1633 * regulatory. So we can just access the new struct, with the
1634 * exception of the latter.
1635 */
1636 struct iwl_nvm_get_info_rsp *rsp;
1637 struct iwl_nvm_get_info_rsp_v3 *rsp_v3;
1638 bool v4 = fw_has_api(&fw->ucode_capa,
1639 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO);
1640 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3);
1641 void *channel_profile;
1642
1643 ret = iwl_trans_send_cmd(trans, &hcmd);
1644 if (ret)
1645 return ERR_PTR(ret);
1646
1647 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size,
1648 "Invalid payload len in NVM response from FW %d",
1649 iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
1650 ret = -EINVAL;
1651 goto out;
1652 }
1653
1654 rsp = (void *)hcmd.resp_pkt->data;
1655 empty_otp = !!(le32_to_cpu(rsp->general.flags) &
1656 NVM_GENERAL_FLAGS_EMPTY_OTP);
1657 if (empty_otp)
1658 IWL_INFO(trans, "OTP is empty\n");
1659
1660 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL);
1661 if (!nvm) {
1662 ret = -ENOMEM;
1663 goto out;
1664 }
1665
1666 iwl_set_hw_address_from_csr(trans, nvm);
1667 /* TODO: if platform NVM has MAC address - override it here */
1668
1669 if (!is_valid_ether_addr(nvm->hw_addr)) {
1670 IWL_ERR(trans, "no valid mac address was found\n");
1671 ret = -EINVAL;
1672 goto err_free;
1673 }
1674
1675 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
1676
1677 /* Initialize general data */
1678 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
1679 nvm->n_hw_addrs = rsp->general.n_hw_addrs;
1680 if (nvm->n_hw_addrs == 0)
1681 IWL_WARN(trans,
1682 "Firmware declares no reserved mac addresses. OTP is empty: %d\n",
1683 empty_otp);
1684
1685 /* Initialize MAC sku data */
1686 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
1687 nvm->sku_cap_11ac_enable =
1688 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
1689 nvm->sku_cap_11n_enable =
1690 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
1691 nvm->sku_cap_11ax_enable =
1692 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
1693 nvm->sku_cap_band_24ghz_enable =
1694 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
1695 nvm->sku_cap_band_52ghz_enable =
1696 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
1697 nvm->sku_cap_mimo_disabled =
1698 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
1699
1700 /* Initialize PHY sku data */
1701 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
1702 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
1703
1704 if (le32_to_cpu(rsp->regulatory.lar_enabled) &&
1705 fw_has_capa(&fw->ucode_capa,
1706 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) {
1707 nvm->lar_enabled = true;
1708 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1709 }
1710
1711 rsp_v3 = (void *)rsp;
1712 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile :
1713 (void *)rsp_v3->regulatory.channel_profile;
1714
1715 iwl_init_sbands(trans, nvm,
1716 channel_profile,
1717 nvm->valid_tx_ant & fw->valid_tx_ant,
1718 nvm->valid_rx_ant & fw->valid_rx_ant,
1719 sbands_flags, v4, fw);
1720
1721 iwl_free_resp(&hcmd);
1722 return nvm;
1723
1724 err_free:
1725 kfree(nvm);
1726 out:
1727 iwl_free_resp(&hcmd);
1728 return ERR_PTR(ret);
1729 }
1730 IWL_EXPORT_SYMBOL(iwl_get_nvm);
1731